1 // SPDX-License-Identifier: MIT 2 /* Copyright © 2024 Intel Corporation */ 3 4 #include <drm/display/drm_dp.h> 5 #include <drm/display/drm_dp_helper.h> 6 #include <drm/drm_edid.h> 7 8 #include "i915_drv.h" 9 #include "i915_reg.h" 10 #include "intel_ddi.h" 11 #include "intel_de.h" 12 #include "intel_display_types.h" 13 #include "intel_dp.h" 14 #include "intel_dp_link_training.h" 15 #include "intel_dp_mst.h" 16 #include "intel_dp_test.h" 17 18 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev) 19 20 /* Adjust link config limits based on compliance test requests. */ 21 void 22 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, 23 struct intel_crtc_state *pipe_config, 24 struct link_config_limits *limits) 25 { 26 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 27 28 /* For DP Compliance we override the computed bpp for the pipe */ 29 if (intel_dp->compliance.test_data.bpc != 0) { 30 int bpp = 3 * intel_dp->compliance.test_data.bpc; 31 32 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp; 33 pipe_config->dither_force_disable = bpp == 6 * 3; 34 35 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp); 36 } 37 38 /* Use values requested by Compliance Test Request */ 39 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { 40 int index; 41 42 /* Validate the compliance test data since max values 43 * might have changed due to link train fallback. 44 */ 45 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, 46 intel_dp->compliance.test_lane_count)) { 47 index = intel_dp_rate_index(intel_dp->common_rates, 48 intel_dp->num_common_rates, 49 intel_dp->compliance.test_link_rate); 50 if (index >= 0) 51 limits->min_rate = limits->max_rate = 52 intel_dp->compliance.test_link_rate; 53 limits->min_lane_count = limits->max_lane_count = 54 intel_dp->compliance.test_lane_count; 55 } 56 } 57 } 58 59 /* Compliance test status bits */ 60 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 61 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) 62 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) 63 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) 64 65 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) 66 { 67 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 68 int status = 0; 69 int test_link_rate; 70 u8 test_lane_count, test_link_bw; 71 /* (DP CTS 1.2) 72 * 4.3.1.11 73 */ 74 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ 75 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, 76 &test_lane_count); 77 78 if (status <= 0) { 79 drm_dbg_kms(&i915->drm, "Lane count read failed\n"); 80 return DP_TEST_NAK; 81 } 82 test_lane_count &= DP_MAX_LANE_COUNT_MASK; 83 84 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, 85 &test_link_bw); 86 if (status <= 0) { 87 drm_dbg_kms(&i915->drm, "Link Rate read failed\n"); 88 return DP_TEST_NAK; 89 } 90 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); 91 92 /* Validate the requested link rate and lane count */ 93 if (!intel_dp_link_params_valid(intel_dp, test_link_rate, 94 test_lane_count)) 95 return DP_TEST_NAK; 96 97 intel_dp->compliance.test_lane_count = test_lane_count; 98 intel_dp->compliance.test_link_rate = test_link_rate; 99 100 return DP_TEST_ACK; 101 } 102 103 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) 104 { 105 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 106 u8 test_pattern; 107 u8 test_misc; 108 __be16 h_width, v_height; 109 int status = 0; 110 111 /* Read the TEST_PATTERN (DP CTS 3.1.5) */ 112 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, 113 &test_pattern); 114 if (status <= 0) { 115 drm_dbg_kms(&i915->drm, "Test pattern read failed\n"); 116 return DP_TEST_NAK; 117 } 118 if (test_pattern != DP_COLOR_RAMP) 119 return DP_TEST_NAK; 120 121 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, 122 &h_width, 2); 123 if (status <= 0) { 124 drm_dbg_kms(&i915->drm, "H Width read failed\n"); 125 return DP_TEST_NAK; 126 } 127 128 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, 129 &v_height, 2); 130 if (status <= 0) { 131 drm_dbg_kms(&i915->drm, "V Height read failed\n"); 132 return DP_TEST_NAK; 133 } 134 135 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, 136 &test_misc); 137 if (status <= 0) { 138 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n"); 139 return DP_TEST_NAK; 140 } 141 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) 142 return DP_TEST_NAK; 143 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) 144 return DP_TEST_NAK; 145 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { 146 case DP_TEST_BIT_DEPTH_6: 147 intel_dp->compliance.test_data.bpc = 6; 148 break; 149 case DP_TEST_BIT_DEPTH_8: 150 intel_dp->compliance.test_data.bpc = 8; 151 break; 152 default: 153 return DP_TEST_NAK; 154 } 155 156 intel_dp->compliance.test_data.video_pattern = test_pattern; 157 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); 158 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); 159 /* Set test active flag here so userspace doesn't interrupt things */ 160 intel_dp->compliance.test_active = true; 161 162 return DP_TEST_ACK; 163 } 164 165 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) 166 { 167 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 168 u8 test_result = DP_TEST_ACK; 169 struct intel_connector *intel_connector = intel_dp->attached_connector; 170 struct drm_connector *connector = &intel_connector->base; 171 172 if (intel_connector->detect_edid == NULL || 173 connector->edid_corrupt || 174 intel_dp->aux.i2c_defer_count > 6) { 175 /* Check EDID read for NACKs, DEFERs and corruption 176 * (DP CTS 1.2 Core r1.1) 177 * 4.2.2.4 : Failed EDID read, I2C_NAK 178 * 4.2.2.5 : Failed EDID read, I2C_DEFER 179 * 4.2.2.6 : EDID corruption detected 180 * Use failsafe mode for all cases 181 */ 182 if (intel_dp->aux.i2c_nack_count > 0 || 183 intel_dp->aux.i2c_defer_count > 0) 184 drm_dbg_kms(&i915->drm, 185 "EDID read had %d NACKs, %d DEFERs\n", 186 intel_dp->aux.i2c_nack_count, 187 intel_dp->aux.i2c_defer_count); 188 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; 189 } else { 190 /* FIXME: Get rid of drm_edid_raw() */ 191 const struct edid *block = drm_edid_raw(intel_connector->detect_edid); 192 193 /* We have to write the checksum of the last block read */ 194 block += block->extensions; 195 196 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, 197 block->checksum) <= 0) 198 drm_dbg_kms(&i915->drm, 199 "Failed to write EDID checksum\n"); 200 201 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; 202 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; 203 } 204 205 /* Set test active flag here so userspace doesn't interrupt things */ 206 intel_dp->compliance.test_active = true; 207 208 return test_result; 209 } 210 211 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, 212 const struct intel_crtc_state *crtc_state) 213 { 214 struct drm_i915_private *dev_priv = 215 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 216 struct drm_dp_phy_test_params *data = 217 &intel_dp->compliance.test_data.phytest; 218 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 219 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 220 enum pipe pipe = crtc->pipe; 221 u32 pattern_val; 222 223 switch (data->phy_pattern) { 224 case DP_LINK_QUAL_PATTERN_DISABLE: 225 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n"); 226 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); 227 if (DISPLAY_VER(dev_priv) >= 10) 228 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 229 DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK, 230 DP_TP_CTL_LINK_TRAIN_NORMAL); 231 break; 232 case DP_LINK_QUAL_PATTERN_D10_2: 233 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n"); 234 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 235 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); 236 break; 237 case DP_LINK_QUAL_PATTERN_ERROR_RATE: 238 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n"); 239 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 240 DDI_DP_COMP_CTL_ENABLE | 241 DDI_DP_COMP_CTL_SCRAMBLED_0); 242 break; 243 case DP_LINK_QUAL_PATTERN_PRBS7: 244 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n"); 245 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 246 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); 247 break; 248 case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM: 249 /* 250 * FIXME: Ideally pattern should come from DPCD 0x250. As 251 * current firmware of DPR-100 could not set it, so hardcoding 252 * now for complaince test. 253 */ 254 drm_dbg_kms(&dev_priv->drm, 255 "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); 256 pattern_val = 0x3e0f83e0; 257 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); 258 pattern_val = 0x0f83e0f8; 259 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); 260 pattern_val = 0x0000f83e; 261 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); 262 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 263 DDI_DP_COMP_CTL_ENABLE | 264 DDI_DP_COMP_CTL_CUSTOM80); 265 break; 266 case DP_LINK_QUAL_PATTERN_CP2520_PAT_1: 267 /* 268 * FIXME: Ideally pattern should come from DPCD 0x24A. As 269 * current firmware of DPR-100 could not set it, so hardcoding 270 * now for complaince test. 271 */ 272 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n"); 273 pattern_val = 0xFB; 274 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 275 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | 276 pattern_val); 277 break; 278 case DP_LINK_QUAL_PATTERN_CP2520_PAT_3: 279 if (DISPLAY_VER(dev_priv) < 10) { 280 drm_warn(&dev_priv->drm, "Platform does not support TPS4\n"); 281 break; 282 } 283 drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n"); 284 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); 285 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 286 DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK, 287 DP_TP_CTL_TRAIN_PAT4_SEL_TP4A | DP_TP_CTL_LINK_TRAIN_PAT4); 288 break; 289 default: 290 drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n"); 291 } 292 } 293 294 static void intel_dp_process_phy_request(struct intel_dp *intel_dp, 295 const struct intel_crtc_state *crtc_state) 296 { 297 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 298 struct drm_dp_phy_test_params *data = 299 &intel_dp->compliance.test_data.phytest; 300 u8 link_status[DP_LINK_STATUS_SIZE]; 301 302 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 303 link_status) < 0) { 304 drm_dbg_kms(&i915->drm, "failed to get link status\n"); 305 return; 306 } 307 308 /* retrieve vswing & pre-emphasis setting */ 309 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, 310 link_status); 311 312 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX); 313 314 intel_dp_phy_pattern_update(intel_dp, crtc_state); 315 316 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 317 intel_dp->train_set, crtc_state->lane_count); 318 319 drm_dp_set_phy_test_pattern(&intel_dp->aux, data, 320 intel_dp->dpcd[DP_DPCD_REV]); 321 } 322 323 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) 324 { 325 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 326 struct drm_dp_phy_test_params *data = 327 &intel_dp->compliance.test_data.phytest; 328 329 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) { 330 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n"); 331 return DP_TEST_NAK; 332 } 333 334 /* Set test active flag here so userspace doesn't interrupt things */ 335 intel_dp->compliance.test_active = true; 336 337 return DP_TEST_ACK; 338 } 339 340 void intel_dp_handle_test_request(struct intel_dp *intel_dp) 341 { 342 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 343 u8 response = DP_TEST_NAK; 344 u8 request = 0; 345 int status; 346 347 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); 348 if (status <= 0) { 349 drm_dbg_kms(&i915->drm, 350 "Could not read test request from sink\n"); 351 goto update_status; 352 } 353 354 switch (request) { 355 case DP_TEST_LINK_TRAINING: 356 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n"); 357 response = intel_dp_autotest_link_training(intel_dp); 358 break; 359 case DP_TEST_LINK_VIDEO_PATTERN: 360 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n"); 361 response = intel_dp_autotest_video_pattern(intel_dp); 362 break; 363 case DP_TEST_LINK_EDID_READ: 364 drm_dbg_kms(&i915->drm, "EDID test requested\n"); 365 response = intel_dp_autotest_edid(intel_dp); 366 break; 367 case DP_TEST_LINK_PHY_TEST_PATTERN: 368 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); 369 response = intel_dp_autotest_phy_pattern(intel_dp); 370 break; 371 default: 372 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n", 373 request); 374 break; 375 } 376 377 if (response & DP_TEST_ACK) 378 intel_dp->compliance.test_type = request; 379 380 update_status: 381 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); 382 if (status <= 0) 383 drm_dbg_kms(&i915->drm, 384 "Could not write test response to sink\n"); 385 } 386 387 /* phy test */ 388 389 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, 390 struct drm_modeset_acquire_ctx *ctx, 391 u8 *pipe_mask) 392 { 393 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 394 struct drm_connector_list_iter conn_iter; 395 struct intel_connector *connector; 396 int ret = 0; 397 398 *pipe_mask = 0; 399 400 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 401 for_each_intel_connector_iter(connector, &conn_iter) { 402 struct drm_connector_state *conn_state = 403 connector->base.state; 404 struct intel_crtc_state *crtc_state; 405 struct intel_crtc *crtc; 406 407 if (!intel_dp_has_connector(intel_dp, conn_state)) 408 continue; 409 410 crtc = to_intel_crtc(conn_state->crtc); 411 if (!crtc) 412 continue; 413 414 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 415 if (ret) 416 break; 417 418 crtc_state = to_intel_crtc_state(crtc->base.state); 419 420 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); 421 422 if (!crtc_state->hw.active) 423 continue; 424 425 if (conn_state->commit && 426 !try_wait_for_completion(&conn_state->commit->hw_done)) 427 continue; 428 429 *pipe_mask |= BIT(crtc->pipe); 430 } 431 drm_connector_list_iter_end(&conn_iter); 432 433 return ret; 434 } 435 436 static int intel_dp_do_phy_test(struct intel_encoder *encoder, 437 struct drm_modeset_acquire_ctx *ctx) 438 { 439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 440 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 441 struct intel_crtc *crtc; 442 u8 pipe_mask; 443 int ret; 444 445 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 446 ctx); 447 if (ret) 448 return ret; 449 450 ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask); 451 if (ret) 452 return ret; 453 454 if (pipe_mask == 0) 455 return 0; 456 457 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n", 458 encoder->base.base.id, encoder->base.name); 459 460 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { 461 const struct intel_crtc_state *crtc_state = 462 to_intel_crtc_state(crtc->base.state); 463 464 /* test on the MST master transcoder */ 465 if (DISPLAY_VER(dev_priv) >= 12 && 466 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 467 !intel_dp_mst_is_master_trans(crtc_state)) 468 continue; 469 470 intel_dp_process_phy_request(intel_dp, crtc_state); 471 break; 472 } 473 474 return 0; 475 } 476 477 void intel_dp_phy_test(struct intel_encoder *encoder) 478 { 479 struct drm_modeset_acquire_ctx ctx; 480 int ret; 481 482 drm_modeset_acquire_init(&ctx, 0); 483 484 for (;;) { 485 ret = intel_dp_do_phy_test(encoder, &ctx); 486 487 if (ret == -EDEADLK) { 488 drm_modeset_backoff(&ctx); 489 continue; 490 } 491 492 break; 493 } 494 495 drm_modeset_drop_locks(&ctx); 496 drm_modeset_acquire_fini(&ctx); 497 drm_WARN(encoder->base.dev, ret, 498 "Acquiring modeset locks failed with %i\n", ret); 499 } 500