1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 #include <linux/iopoll.h> 26 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_print.h> 29 30 #include "intel_display_core.h" 31 #include "intel_display_jiffies.h" 32 #include "intel_display_types.h" 33 #include "intel_display_utils.h" 34 #include "intel_dp.h" 35 #include "intel_dp_link_training.h" 36 #include "intel_encoder.h" 37 #include "intel_hdmi.h" 38 #include "intel_hotplug.h" 39 #include "intel_panel.h" 40 #include "intel_psr.h" 41 42 #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " 43 #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \ 44 (_intel_dp)->attached_connector->base.name, \ 45 dp_to_dig_port(_intel_dp)->base.base.base.id, \ 46 dp_to_dig_port(_intel_dp)->base.base.name, \ 47 drm_dp_phy_name(_dp_phy) 48 49 #define lt_dbg(_intel_dp, _dp_phy, _format, ...) \ 50 drm_dbg_kms(to_intel_display(_intel_dp)->drm, \ 51 LT_MSG_PREFIX _format, \ 52 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__) 53 54 #define lt_err(_intel_dp, _dp_phy, _format, ...) do { \ 55 if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \ 56 drm_err(to_intel_display(_intel_dp)->drm, \ 57 LT_MSG_PREFIX _format, \ 58 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \ 59 else \ 60 lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \ 61 } while (0) 62 63 #define MAX_SEQ_TRAIN_FAILURES 2 64 65 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) 66 { 67 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); 68 } 69 70 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 71 { 72 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 73 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 74 } 75 76 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 77 enum drm_dp_phy dp_phy) 78 { 79 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 80 } 81 82 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 83 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 84 enum drm_dp_phy dp_phy) 85 { 86 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 87 88 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { 89 lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n"); 90 return; 91 } 92 93 lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n", 94 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 95 phy_caps); 96 } 97 98 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, 99 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 100 { 101 int ret; 102 103 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, 104 intel_dp->lttpr_common_caps); 105 if (ret < 0) 106 goto reset_caps; 107 108 lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n", 109 (int)sizeof(intel_dp->lttpr_common_caps), 110 intel_dp->lttpr_common_caps); 111 112 /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ 113 if (intel_dp->lttpr_common_caps[0] < 0x14) 114 goto reset_caps; 115 116 return true; 117 118 reset_caps: 119 intel_dp_reset_lttpr_common_caps(intel_dp); 120 return false; 121 } 122 123 static bool 124 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 125 { 126 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 127 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 128 129 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 130 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val; 131 132 return true; 133 } 134 135 bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp) 136 { 137 return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 138 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] == 139 DP_PHY_REPEATER_MODE_TRANSPARENT; 140 } 141 142 /* 143 * Read the LTTPR common capabilities and switch the LTTPR PHYs to 144 * non-transparent mode if this is supported. Preserve the 145 * transparent/non-transparent mode on an active link. 146 * 147 * Return the number of detected LTTPRs in non-transparent mode or 0 if the 148 * LTTPRs are in transparent mode or the detection failed. 149 */ 150 static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 151 { 152 int lttpr_count; 153 int ret; 154 155 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) 156 return 0; 157 158 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 159 /* 160 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are 161 * detected as this breaks link training at least on the Dell WD19TB 162 * dock. 163 */ 164 if (lttpr_count == 0) 165 return 0; 166 167 /* 168 * Don't change the mode on an active link, to prevent a loss of link 169 * synchronization. See DP Standard v2.0 3.6.7. about the LTTPR 170 * resetting its internal state when the mode is changed from 171 * non-transparent to transparent. 172 */ 173 if (intel_dp->link.active) { 174 if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp)) 175 goto out_reset_lttpr_count; 176 177 return lttpr_count; 178 } 179 180 ret = drm_dp_lttpr_init(&intel_dp->aux, lttpr_count); 181 if (ret) { 182 lt_dbg(intel_dp, DP_PHY_DPRX, 183 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); 184 185 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 186 187 goto out_reset_lttpr_count; 188 } 189 190 intel_dp_set_lttpr_transparent_mode(intel_dp, false); 191 192 return lttpr_count; 193 194 out_reset_lttpr_count: 195 intel_dp_reset_lttpr_count(intel_dp); 196 197 return 0; 198 } 199 200 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 201 { 202 int lttpr_count; 203 int i; 204 205 lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd); 206 207 for (i = 0; i < lttpr_count; i++) { 208 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); 209 drm_dp_dump_lttpr_desc(&intel_dp->aux, DP_PHY_LTTPR(i)); 210 } 211 212 return lttpr_count; 213 } 214 215 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) 216 { 217 struct intel_display *display = to_intel_display(intel_dp); 218 219 if (intel_dp_is_edp(intel_dp)) 220 return 0; 221 222 /* 223 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 224 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 225 */ 226 if (DISPLAY_VER(display) >= 10 && !display->platform.geminilake) 227 if (drm_dp_dpcd_probe(&intel_dp->aux, 228 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV)) 229 return -EIO; 230 231 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) 232 return -EIO; 233 234 return 0; 235 } 236 237 /** 238 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode 239 * @intel_dp: Intel DP struct 240 * 241 * Read the LTTPR common and DPRX capabilities and switch to non-transparent 242 * link training mode if any is detected and read the PHY capabilities for all 243 * detected LTTPRs. In case of an LTTPR detection error or if the number of 244 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 245 * transparent mode link training mode. 246 * 247 * Returns: 248 * >0 if LTTPRs were detected and the non-transparent LT mode was set. The 249 * DPRX capabilities are read out. 250 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 251 * detection failure and the transparent LT mode was set. The DPRX 252 * capabilities are read out. 253 * <0 Reading out the DPRX capabilities failed. 254 */ 255 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) 256 { 257 struct intel_display *display = to_intel_display(intel_dp); 258 int lttpr_count = 0; 259 260 /* 261 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 262 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 263 */ 264 if (!intel_dp_is_edp(intel_dp) && 265 (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)) { 266 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 267 int err = intel_dp_read_dprx_caps(intel_dp, dpcd); 268 269 if (err != 0) 270 return err; 271 272 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); 273 } 274 275 /* 276 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read 277 * it here. 278 */ 279 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { 280 intel_dp_reset_lttpr_common_caps(intel_dp); 281 return -EIO; 282 } 283 284 return lttpr_count; 285 } 286 287 static u8 dp_voltage_max(u8 preemph) 288 { 289 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 290 case DP_TRAIN_PRE_EMPH_LEVEL_0: 291 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 292 case DP_TRAIN_PRE_EMPH_LEVEL_1: 293 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 294 case DP_TRAIN_PRE_EMPH_LEVEL_2: 295 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 296 case DP_TRAIN_PRE_EMPH_LEVEL_3: 297 default: 298 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 299 } 300 } 301 302 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 303 enum drm_dp_phy dp_phy) 304 { 305 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 306 307 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 308 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 309 else 310 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 311 } 312 313 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 314 enum drm_dp_phy dp_phy) 315 { 316 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 317 318 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 319 return DP_TRAIN_PRE_EMPH_LEVEL_3; 320 else 321 return DP_TRAIN_PRE_EMPH_LEVEL_2; 322 } 323 324 static bool 325 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 326 enum drm_dp_phy dp_phy) 327 { 328 struct intel_display *display = to_intel_display(intel_dp); 329 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 330 331 drm_WARN_ON_ONCE(display->drm, 332 lttpr_count <= 0 && dp_phy != DP_PHY_DPRX); 333 334 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 335 } 336 337 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 338 const struct intel_crtc_state *crtc_state, 339 enum drm_dp_phy dp_phy) 340 { 341 struct intel_display *display = to_intel_display(intel_dp); 342 u8 voltage_max; 343 344 /* 345 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 346 * the DPRX_PHY we train. 347 */ 348 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 349 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 350 else 351 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 352 353 drm_WARN_ON_ONCE(display->drm, 354 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 355 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 356 357 return voltage_max; 358 } 359 360 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 361 enum drm_dp_phy dp_phy) 362 { 363 struct intel_display *display = to_intel_display(intel_dp); 364 u8 preemph_max; 365 366 /* 367 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 368 * the DPRX_PHY we train. 369 */ 370 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 371 preemph_max = intel_dp->preemph_max(intel_dp); 372 else 373 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 374 375 drm_WARN_ON_ONCE(display->drm, 376 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 377 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 378 379 return preemph_max; 380 } 381 382 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, 383 enum drm_dp_phy dp_phy) 384 { 385 struct intel_display *display = to_intel_display(intel_dp); 386 387 return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) || 388 DISPLAY_VER(display) >= 10 || display->platform.broxton; 389 } 390 391 /* 128b/132b */ 392 static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp, 393 const struct intel_crtc_state *crtc_state, 394 enum drm_dp_phy dp_phy, 395 const u8 link_status[DP_LINK_STATUS_SIZE], 396 int lane) 397 { 398 u8 tx_ffe = 0; 399 400 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 401 lane = min(lane, crtc_state->lane_count - 1); 402 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); 403 } else { 404 for (lane = 0; lane < crtc_state->lane_count; lane++) 405 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); 406 } 407 408 return tx_ffe; 409 } 410 411 /* 8b/10b */ 412 static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp, 413 const struct intel_crtc_state *crtc_state, 414 enum drm_dp_phy dp_phy, 415 const u8 link_status[DP_LINK_STATUS_SIZE], 416 int lane) 417 { 418 u8 v = 0; 419 u8 p = 0; 420 u8 voltage_max; 421 u8 preemph_max; 422 423 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 424 lane = min(lane, crtc_state->lane_count - 1); 425 426 v = drm_dp_get_adjust_request_voltage(link_status, lane); 427 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 428 } else { 429 for (lane = 0; lane < crtc_state->lane_count; lane++) { 430 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 431 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 432 } 433 } 434 435 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 436 if (p >= preemph_max) 437 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 438 439 v = min(v, dp_voltage_max(p)); 440 441 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 442 if (v >= voltage_max) 443 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 444 445 return v | p; 446 } 447 448 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, 449 const struct intel_crtc_state *crtc_state, 450 enum drm_dp_phy dp_phy, 451 const u8 link_status[DP_LINK_STATUS_SIZE], 452 int lane) 453 { 454 if (intel_dp_is_uhbr(crtc_state)) 455 return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state, 456 dp_phy, link_status, lane); 457 else 458 return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state, 459 dp_phy, link_status, lane); 460 } 461 462 #define TRAIN_REQ_FMT "%d/%d/%d/%d" 463 #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \ 464 (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT) 465 #define TRAIN_REQ_VSWING_ARGS(link_status) \ 466 _TRAIN_REQ_VSWING_ARGS(link_status, 0), \ 467 _TRAIN_REQ_VSWING_ARGS(link_status, 1), \ 468 _TRAIN_REQ_VSWING_ARGS(link_status, 2), \ 469 _TRAIN_REQ_VSWING_ARGS(link_status, 3) 470 #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \ 471 (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT) 472 #define TRAIN_REQ_PREEMPH_ARGS(link_status) \ 473 _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \ 474 _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \ 475 _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \ 476 _TRAIN_REQ_PREEMPH_ARGS(link_status, 3) 477 #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \ 478 drm_dp_get_adjust_tx_ffe_preset((link_status), (lane)) 479 #define TRAIN_REQ_TX_FFE_ARGS(link_status) \ 480 _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \ 481 _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \ 482 _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \ 483 _TRAIN_REQ_TX_FFE_ARGS(link_status, 3) 484 485 bool 486 intel_dp_get_adjust_train(struct intel_dp *intel_dp, 487 const struct intel_crtc_state *crtc_state, 488 enum drm_dp_phy dp_phy, 489 const u8 link_status[DP_LINK_STATUS_SIZE]) 490 { 491 bool changed = false; 492 int lane; 493 494 if (intel_dp_is_uhbr(crtc_state)) { 495 lt_dbg(intel_dp, dp_phy, 496 "128b/132b, lanes: %d, " 497 "TX FFE request: " TRAIN_REQ_FMT "\n", 498 crtc_state->lane_count, 499 TRAIN_REQ_TX_FFE_ARGS(link_status)); 500 } else { 501 lt_dbg(intel_dp, dp_phy, 502 "8b/10b, lanes: %d, " 503 "vswing request: " TRAIN_REQ_FMT ", " 504 "pre-emphasis request: " TRAIN_REQ_FMT "\n", 505 crtc_state->lane_count, 506 TRAIN_REQ_VSWING_ARGS(link_status), 507 TRAIN_REQ_PREEMPH_ARGS(link_status)); 508 } 509 510 for (lane = 0; lane < 4; lane++) { 511 u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state, 512 dp_phy, link_status, lane); 513 if (intel_dp->train_set[lane] == new) 514 continue; 515 516 intel_dp->train_set[lane] = new; 517 changed = true; 518 } 519 520 return changed; 521 } 522 523 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 524 enum drm_dp_phy dp_phy) 525 { 526 return dp_phy == DP_PHY_DPRX ? 527 DP_TRAINING_PATTERN_SET : 528 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 529 } 530 531 static bool 532 intel_dp_set_link_train(struct intel_dp *intel_dp, 533 const struct intel_crtc_state *crtc_state, 534 enum drm_dp_phy dp_phy, 535 u8 dp_train_pat) 536 { 537 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 538 u8 buf[sizeof(intel_dp->train_set) + 1]; 539 int len; 540 541 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 542 dp_phy, dp_train_pat); 543 544 buf[0] = dp_train_pat; 545 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 546 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 547 len = crtc_state->lane_count + 1; 548 549 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 550 } 551 552 static char dp_training_pattern_name(u8 train_pat) 553 { 554 switch (train_pat) { 555 case DP_TRAINING_PATTERN_1: 556 case DP_TRAINING_PATTERN_2: 557 case DP_TRAINING_PATTERN_3: 558 return '0' + train_pat; 559 case DP_TRAINING_PATTERN_4: 560 return '4'; 561 default: 562 MISSING_CASE(train_pat); 563 return '?'; 564 } 565 } 566 567 void 568 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 569 const struct intel_crtc_state *crtc_state, 570 enum drm_dp_phy dp_phy, 571 u8 dp_train_pat) 572 { 573 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat); 574 575 if (train_pat != DP_TRAINING_PATTERN_DISABLE) 576 lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n", 577 dp_training_pattern_name(train_pat)); 578 579 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); 580 } 581 582 #define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" 583 #define _TRAIN_SET_VSWING_ARGS(train_set) \ 584 ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ 585 (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" 586 #define TRAIN_SET_VSWING_ARGS(train_set) \ 587 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ 588 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ 589 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ 590 _TRAIN_SET_VSWING_ARGS((train_set)[3]) 591 #define _TRAIN_SET_PREEMPH_ARGS(train_set) \ 592 ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ 593 (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" 594 #define TRAIN_SET_PREEMPH_ARGS(train_set) \ 595 _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ 596 _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ 597 _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ 598 _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) 599 #define _TRAIN_SET_TX_FFE_ARGS(train_set) \ 600 ((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), "" 601 #define TRAIN_SET_TX_FFE_ARGS(train_set) \ 602 _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \ 603 _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \ 604 _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \ 605 _TRAIN_SET_TX_FFE_ARGS((train_set)[3]) 606 607 void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 608 const struct intel_crtc_state *crtc_state, 609 enum drm_dp_phy dp_phy) 610 { 611 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 612 613 if (intel_dp_is_uhbr(crtc_state)) { 614 lt_dbg(intel_dp, dp_phy, 615 "128b/132b, lanes: %d, " 616 "TX FFE presets: " TRAIN_SET_FMT "\n", 617 crtc_state->lane_count, 618 TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set)); 619 } else { 620 lt_dbg(intel_dp, dp_phy, 621 "8b/10b, lanes: %d, " 622 "vswing levels: " TRAIN_SET_FMT ", " 623 "pre-emphasis levels: " TRAIN_SET_FMT "\n", 624 crtc_state->lane_count, 625 TRAIN_SET_VSWING_ARGS(intel_dp->train_set), 626 TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set)); 627 } 628 629 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 630 encoder->set_signal_levels(encoder, crtc_state); 631 } 632 633 static bool 634 intel_dp_reset_link_train(struct intel_dp *intel_dp, 635 const struct intel_crtc_state *crtc_state, 636 enum drm_dp_phy dp_phy, 637 u8 dp_train_pat) 638 { 639 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 640 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 641 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 642 } 643 644 static bool 645 intel_dp_update_link_train(struct intel_dp *intel_dp, 646 const struct intel_crtc_state *crtc_state, 647 enum drm_dp_phy dp_phy) 648 { 649 int reg = dp_phy == DP_PHY_DPRX ? 650 DP_TRAINING_LANE0_SET : 651 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 652 int ret; 653 654 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 655 656 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 657 intel_dp->train_set, crtc_state->lane_count); 658 659 return ret == crtc_state->lane_count; 660 } 661 662 /* 128b/132b */ 663 static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane) 664 { 665 return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) == 666 DP_TX_FFE_PRESET_VALUE_MASK; 667 } 668 669 /* 670 * 8b/10b 671 * 672 * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to 673 * have self contradicting tests around this area. 674 * 675 * In lieu of better ideas let's just stop when we've reached the max supported 676 * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on 677 * whether vswing level 3 is supported or not. 678 */ 679 static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane) 680 { 681 u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 682 DP_TRAIN_VOLTAGE_SWING_SHIFT; 683 u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 684 DP_TRAIN_PRE_EMPHASIS_SHIFT; 685 686 if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0) 687 return false; 688 689 if (v + p != 3) 690 return false; 691 692 return true; 693 } 694 695 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 696 const struct intel_crtc_state *crtc_state) 697 { 698 int lane; 699 700 for (lane = 0; lane < crtc_state->lane_count; lane++) { 701 u8 train_set_lane = intel_dp->train_set[lane]; 702 703 if (intel_dp_is_uhbr(crtc_state)) { 704 if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane)) 705 return false; 706 } else { 707 if (!intel_dp_lane_max_vswing_reached(train_set_lane)) 708 return false; 709 } 710 } 711 712 return true; 713 } 714 715 void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, 716 bool is_vrr, 717 bool pr_with_as_sdp_enable) 718 { 719 u8 link_config[2]; 720 721 link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 722 link_config[0] |= pr_with_as_sdp_enable ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0; 723 link_config[1] = drm_dp_is_uhbr_rate(link_rate) ? 724 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; 725 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 726 } 727 728 static bool 729 intel_dp_pr_with_as_sdp_enabled(struct intel_dp *intel_dp, 730 const struct intel_crtc_state *crtc_state) 731 { 732 return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) && 733 (crtc_state->infoframes.enable & 734 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)); 735 } 736 737 static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, 738 const struct intel_crtc_state *crtc_state) 739 { 740 /* 741 * Currently, we set the MSA ignore bit based on vrr.in_range. 742 * We can't really read that out during driver load since we don't have 743 * the connector information read in yet. So if we do end up doing a 744 * modeset during initial_commit() we'll clear the MSA ignore bit. 745 * GOP likely wouldn't have set this bit so after the initial commit, 746 * if there are no modesets and we enable VRR mode seamlessly 747 * (without a full modeset), the MSA ignore bit might never get set. 748 * 749 * #TODO: Implement readout of vrr.in_range. 750 * We need fastset support for setting the MSA ignore bit in DPCD, 751 * especially on the first real commit when clearing the inherited flag. 752 */ 753 intel_dp_link_training_set_mode(intel_dp, 754 crtc_state->port_clock, 755 crtc_state->vrr.in_range, 756 intel_dp_pr_with_as_sdp_enabled(intel_dp, crtc_state)); 757 } 758 759 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, 760 int link_bw, int rate_select, int lane_count, 761 bool enhanced_framing, bool post_lt_adj_req) 762 { 763 if (enhanced_framing) 764 lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 765 766 if (post_lt_adj_req) 767 lane_count |= DP_POST_LT_ADJ_REQ_GRANTED; 768 769 if (link_bw) { 770 /* DP and eDP v1.3 and earlier link bw set method. */ 771 u8 link_config[] = { link_bw, lane_count }; 772 773 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 774 ARRAY_SIZE(link_config)); 775 } else { 776 /* 777 * eDP v1.4 and later link rate set method. 778 * 779 * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if 780 * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET. 781 * 782 * eDP v1.5 sinks allow choosing either, and the last choice 783 * shall be active. 784 */ 785 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count); 786 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select); 787 } 788 } 789 790 /* 791 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 792 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or 793 * 1.2 devices that support it, TPS2 otherwise. 794 */ 795 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 796 const struct intel_crtc_state *crtc_state, 797 enum drm_dp_phy dp_phy) 798 { 799 struct intel_display *display = to_intel_display(intel_dp); 800 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 801 802 /* UHBR+ use separate 128b/132b TPS2 */ 803 if (intel_dp_is_uhbr(crtc_state)) 804 return DP_TRAINING_PATTERN_2; 805 806 /* 807 * TPS4 support is mandatory for all downstream devices that 808 * support HBR3. There are no known eDP panels that support 809 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification. 810 * LTTPRs must support TPS4. 811 */ 812 source_tps4 = intel_dp_source_supports_tps4(display); 813 sink_tps4 = dp_phy != DP_PHY_DPRX || 814 drm_dp_tps4_supported(intel_dp->dpcd); 815 if (source_tps4 && sink_tps4) { 816 return DP_TRAINING_PATTERN_4; 817 } else if (crtc_state->port_clock == 810000) { 818 if (!source_tps4) 819 lt_dbg(intel_dp, dp_phy, 820 "8.1 Gbps link rate without source TPS4 support\n"); 821 if (!sink_tps4) 822 lt_dbg(intel_dp, dp_phy, 823 "8.1 Gbps link rate without sink TPS4 support\n"); 824 } 825 826 /* 827 * TPS3 support is mandatory for downstream devices that 828 * support HBR2. However, not all sinks follow the spec. 829 */ 830 source_tps3 = intel_dp_source_supports_tps3(display); 831 sink_tps3 = dp_phy != DP_PHY_DPRX || 832 drm_dp_tps3_supported(intel_dp->dpcd); 833 if (source_tps3 && sink_tps3) { 834 return DP_TRAINING_PATTERN_3; 835 } else if (crtc_state->port_clock >= 540000) { 836 if (!source_tps3) 837 lt_dbg(intel_dp, dp_phy, 838 ">=5.4/6.48 Gbps link rate without source TPS3 support\n"); 839 if (!sink_tps3) 840 lt_dbg(intel_dp, dp_phy, 841 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 842 } 843 844 return DP_TRAINING_PATTERN_2; 845 } 846 847 static bool intel_dp_use_post_lt_adj_req(struct intel_dp *intel_dp, 848 const struct intel_crtc_state *crtc_state) 849 { 850 return intel_dp->set_idle_link_train && 851 drm_dp_post_lt_adj_req_supported(intel_dp->dpcd) && 852 intel_dp_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX) != DP_TRAINING_PATTERN_4; 853 } 854 855 static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp, 856 const struct intel_crtc_state *crtc_state, 857 u8 link_bw, u8 rate_select) 858 { 859 intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count, 860 crtc_state->enhanced_framing, 861 intel_dp_use_post_lt_adj_req(intel_dp, crtc_state)); 862 } 863 864 /* 865 * Prepare link training by configuring the link parameters. On DDI platforms 866 * also enable the port here. 867 */ 868 static bool 869 intel_dp_prepare_link_train(struct intel_dp *intel_dp, 870 const struct intel_crtc_state *crtc_state) 871 { 872 u8 link_bw, rate_select; 873 874 if (intel_dp->prepare_link_retrain) 875 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 876 877 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 878 &link_bw, &rate_select); 879 880 /* 881 * WaEdpLinkRateDataReload 882 * 883 * Parade PS8461E MUX (used on various TGL+ laptops) needs 884 * to snoop the link rates reported by the sink when we 885 * use LINK_RATE_SET in order to operate in jitter cleaning 886 * mode (as opposed to redriver mode). Unfortunately it 887 * loses track of the snooped link rates when powered down, 888 * so we need to make it re-snoop often. Without this high 889 * link rates are not stable. 890 */ 891 if (!link_bw) { 892 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 893 894 lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n"); 895 896 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 897 sink_rates, sizeof(sink_rates)); 898 } 899 900 if (link_bw) 901 lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n", 902 link_bw); 903 else 904 lt_dbg(intel_dp, DP_PHY_DPRX, 905 "Using LINK_RATE_SET value %02x\n", 906 rate_select); 907 /* 908 * Spec DP2.1 Section 3.5.2.16 909 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate 910 */ 911 intel_dp_update_downspread_ctrl(intel_dp, crtc_state); 912 intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw, 913 rate_select); 914 915 return true; 916 } 917 918 static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state, 919 const u8 old_link_status[DP_LINK_STATUS_SIZE], 920 const u8 new_link_status[DP_LINK_STATUS_SIZE]) 921 { 922 int lane; 923 924 for (lane = 0; lane < crtc_state->lane_count; lane++) { 925 u8 old, new; 926 927 if (intel_dp_is_uhbr(crtc_state)) { 928 old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane); 929 new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane); 930 } else { 931 old = drm_dp_get_adjust_request_voltage(old_link_status, lane) | 932 drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane); 933 new = drm_dp_get_adjust_request_voltage(new_link_status, lane) | 934 drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane); 935 } 936 937 if (old != new) 938 return true; 939 } 940 941 return false; 942 } 943 944 void 945 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy, 946 const u8 link_status[DP_LINK_STATUS_SIZE]) 947 { 948 lt_dbg(intel_dp, dp_phy, 949 "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n", 950 link_status[0], link_status[1], link_status[2], 951 link_status[3], link_status[4], link_status[5]); 952 } 953 954 /* 955 * Perform the link training clock recovery phase on the given DP PHY using 956 * training pattern 1. 957 */ 958 static bool 959 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 960 const struct intel_crtc_state *crtc_state, 961 enum drm_dp_phy dp_phy) 962 { 963 u8 old_link_status[DP_LINK_STATUS_SIZE] = {}; 964 int voltage_tries, cr_tries, max_cr_tries; 965 u8 link_status[DP_LINK_STATUS_SIZE]; 966 bool max_vswing_reached = false; 967 int delay_us; 968 969 delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux, 970 intel_dp->dpcd, dp_phy, 971 intel_dp_is_uhbr(crtc_state)); 972 973 /* clock recovery */ 974 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 975 DP_TRAINING_PATTERN_1 | 976 DP_LINK_SCRAMBLING_DISABLE)) { 977 lt_err(intel_dp, dp_phy, "Failed to enable link training\n"); 978 return false; 979 } 980 981 /* 982 * The DP 1.4 spec defines the max clock recovery retries value 983 * as 10 but for pre-DP 1.4 devices we set a very tolerant 984 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 985 * x 5 identical voltage retries). Since the previous specs didn't 986 * define a limit and created the possibility of an infinite loop 987 * we want to prevent any sync from triggering that corner case. 988 */ 989 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 990 max_cr_tries = 10; 991 else 992 max_cr_tries = 80; 993 994 voltage_tries = 1; 995 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 996 fsleep(delay_us); 997 998 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 999 link_status) < 0) { 1000 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 1001 return false; 1002 } 1003 1004 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 1005 lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n"); 1006 return true; 1007 } 1008 1009 if (voltage_tries == 5) { 1010 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1011 lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n"); 1012 return false; 1013 } 1014 1015 if (max_vswing_reached) { 1016 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1017 lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n"); 1018 return false; 1019 } 1020 1021 /* Update training set as requested by target */ 1022 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 1023 link_status); 1024 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 1025 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 1026 return false; 1027 } 1028 1029 if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status)) 1030 ++voltage_tries; 1031 else 1032 voltage_tries = 1; 1033 1034 memcpy(old_link_status, link_status, sizeof(link_status)); 1035 1036 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 1037 max_vswing_reached = true; 1038 } 1039 1040 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1041 lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n", 1042 max_cr_tries); 1043 1044 return false; 1045 } 1046 1047 /* 1048 * Perform the link training channel equalization phase on the given DP PHY 1049 * using one of training pattern 2, 3 or 4 depending on the source and 1050 * sink capabilities. 1051 */ 1052 static bool 1053 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 1054 const struct intel_crtc_state *crtc_state, 1055 enum drm_dp_phy dp_phy) 1056 { 1057 int tries; 1058 u32 training_pattern; 1059 u8 link_status[DP_LINK_STATUS_SIZE]; 1060 bool channel_eq = false; 1061 int delay_us; 1062 1063 delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux, 1064 intel_dp->dpcd, dp_phy, 1065 intel_dp_is_uhbr(crtc_state)); 1066 1067 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 1068 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 1069 if (training_pattern != DP_TRAINING_PATTERN_4) 1070 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 1071 1072 /* channel equalization */ 1073 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 1074 training_pattern)) { 1075 lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n"); 1076 return false; 1077 } 1078 1079 for (tries = 0; tries < 5; tries++) { 1080 fsleep(delay_us); 1081 1082 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 1083 link_status) < 0) { 1084 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 1085 break; 1086 } 1087 1088 /* Make sure clock is still ok */ 1089 if (!drm_dp_clock_recovery_ok(link_status, 1090 crtc_state->lane_count)) { 1091 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1092 lt_dbg(intel_dp, dp_phy, 1093 "Clock recovery check failed, cannot continue channel equalization\n"); 1094 break; 1095 } 1096 1097 if (drm_dp_channel_eq_ok(link_status, 1098 crtc_state->lane_count)) { 1099 channel_eq = true; 1100 lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n"); 1101 break; 1102 } 1103 1104 /* Update training set as requested by target */ 1105 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 1106 link_status); 1107 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 1108 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 1109 break; 1110 } 1111 } 1112 1113 /* Try 5 times, else fail and try at lower BW */ 1114 if (tries == 5) { 1115 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1116 lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n"); 1117 } 1118 1119 return channel_eq; 1120 } 1121 1122 static bool 1123 intel_dp_post_lt_adj_req(struct intel_dp *intel_dp, 1124 const struct intel_crtc_state *crtc_state) 1125 { 1126 u8 link_status[DP_LINK_STATUS_SIZE]; 1127 unsigned long deadline; 1128 bool timeout = false; 1129 bool success = false; 1130 int changes = 0; 1131 1132 if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state)) 1133 return true; 1134 1135 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 1136 link_status) < 0) { 1137 lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n"); 1138 return false; 1139 } 1140 1141 deadline = jiffies + msecs_to_jiffies_timeout(200); 1142 1143 for (;;) { 1144 /* Make sure clock is still ok */ 1145 if (!drm_dp_clock_recovery_ok(link_status, 1146 crtc_state->lane_count)) { 1147 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1148 lt_dbg(intel_dp, DP_PHY_DPRX, 1149 "Clock recovery check failed, cannot continue POST_LT_ADJ_REQ\n"); 1150 break; 1151 } 1152 1153 if (!drm_dp_channel_eq_ok(link_status, 1154 crtc_state->lane_count)) { 1155 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1156 lt_dbg(intel_dp, DP_PHY_DPRX, "Channel EQ check failed. cannot continue POST_LT_ADJ_REQ\n"); 1157 break; 1158 } 1159 1160 if (!drm_dp_post_lt_adj_req_in_progress(link_status)) { 1161 success = true; 1162 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1163 lt_dbg(intel_dp, DP_PHY_DPRX, 1164 "POST_LT_ADJ_REQ done (%d changes). DP Training successful\n", changes); 1165 break; 1166 } 1167 1168 if (changes == 6) { 1169 success = true; 1170 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1171 lt_dbg(intel_dp, DP_PHY_DPRX, 1172 "POST_LT_ADJ_REQ limit reached (%d changes). DP Training successful\n", changes); 1173 break; 1174 } 1175 1176 if (timeout) { 1177 success = true; 1178 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1179 lt_dbg(intel_dp, DP_PHY_DPRX, 1180 "POST_LT_ADJ_REQ timeout reached (%d changes). DP Training successful\n", changes); 1181 break; 1182 } 1183 1184 fsleep(5000); 1185 1186 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 1187 link_status) < 0) { 1188 lt_err(intel_dp, DP_PHY_DPRX, "Failed to get link status\n"); 1189 break; 1190 } 1191 1192 /* Update training set as requested by target */ 1193 if (intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status)) { 1194 deadline = jiffies + msecs_to_jiffies_timeout(200); 1195 changes++; 1196 1197 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1198 lt_err(intel_dp, DP_PHY_DPRX, "Failed to update link training\n"); 1199 break; 1200 } 1201 } else if (time_after(jiffies, deadline)) { 1202 timeout = true; 1203 } 1204 } 1205 1206 return success; 1207 } 1208 1209 static void intel_dp_stop_post_lt_adj_req(struct intel_dp *intel_dp, 1210 const struct intel_crtc_state *crtc_state) 1211 { 1212 u8 lane_count; 1213 1214 if (!intel_dp_use_post_lt_adj_req(intel_dp, crtc_state)) 1215 return; 1216 1217 /* clear DP_POST_LT_ADJ_REQ_GRANTED */ 1218 lane_count = crtc_state->lane_count; 1219 if (crtc_state->enhanced_framing) 1220 lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 1221 1222 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count); 1223 } 1224 1225 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 1226 enum drm_dp_phy dp_phy) 1227 { 1228 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 1229 u8 val = DP_TRAINING_PATTERN_DISABLE; 1230 1231 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 1232 } 1233 1234 static int 1235 intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp, 1236 const struct intel_crtc_state *crtc_state) 1237 { 1238 u8 sink_status; 1239 int ret; 1240 1241 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status); 1242 if (ret != 1) { 1243 lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n"); 1244 return ret < 0 ? ret : -EIO; 1245 } 1246 1247 return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0; 1248 } 1249 1250 /** 1251 * intel_dp_stop_link_train - stop link training 1252 * @intel_dp: DP struct 1253 * @crtc_state: state for CRTC attached to the encoder 1254 * 1255 * Stop the link training of the @intel_dp port, disabling the training 1256 * pattern in the sink's DPCD, and disabling the test pattern symbol 1257 * generation on the port. 1258 * 1259 * What symbols are output on the port after this point is 1260 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 1261 * with the pipe being disabled, on older platforms it's HW specific if/how an 1262 * idle pattern is generated, as the pipe is already enabled here for those. 1263 * 1264 * This function must be called after intel_dp_start_link_train(). 1265 */ 1266 void intel_dp_stop_link_train(struct intel_dp *intel_dp, 1267 const struct intel_crtc_state *crtc_state) 1268 { 1269 struct intel_display *display = to_intel_display(intel_dp); 1270 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1271 int ret; 1272 1273 intel_dp->link.active = true; 1274 1275 intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX, 1276 DP_TRAINING_PATTERN_DISABLE); 1277 1278 if (intel_dp_is_uhbr(crtc_state)) { 1279 ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state), 1280 ret == 0, 1281 500, 500 * 1000, false); 1282 if (ret) 1283 lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n"); 1284 } 1285 1286 intel_hpd_unblock(encoder); 1287 1288 if (!display->hotplug.ignore_long_hpd && 1289 intel_dp->link.seq_train_failures < MAX_SEQ_TRAIN_FAILURES) { 1290 int delay_ms = intel_dp->link.seq_train_failures ? 0 : 2000; 1291 1292 intel_encoder_link_check_queue_work(encoder, delay_ms); 1293 } 1294 } 1295 1296 static bool 1297 intel_dp_link_train_phy(struct intel_dp *intel_dp, 1298 const struct intel_crtc_state *crtc_state, 1299 enum drm_dp_phy dp_phy) 1300 { 1301 bool ret = false; 1302 1303 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 1304 goto out; 1305 1306 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 1307 goto out; 1308 1309 ret = true; 1310 1311 out: 1312 lt_dbg(intel_dp, dp_phy, 1313 "Link Training %s at link rate = %d, lane count = %d\n", 1314 ret ? "passed" : "failed", 1315 crtc_state->port_clock, crtc_state->lane_count); 1316 1317 return ret; 1318 } 1319 1320 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, 1321 int link_rate, 1322 u8 lane_count) 1323 { 1324 /* FIXME figure out what we actually want here */ 1325 const struct drm_display_mode *fixed_mode = 1326 intel_panel_preferred_fixed_mode(intel_dp->attached_connector); 1327 int mode_rate, max_rate; 1328 1329 mode_rate = intel_dp_link_required(link_rate, lane_count, 1330 fixed_mode->clock, fixed_mode->hdisplay, 1331 fxp_q4_from_int(18), 0); 1332 max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); 1333 if (mode_rate > max_rate) 1334 return false; 1335 1336 return true; 1337 } 1338 1339 static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp, 1340 const struct intel_crtc_state *crtc_state, 1341 int *new_link_rate, int *new_lane_count) 1342 { 1343 int link_rate; 1344 int lane_count; 1345 int i; 1346 1347 i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 1348 for (i--; i >= 0; i--) { 1349 intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count); 1350 1351 if ((intel_dp->link.force_rate && 1352 intel_dp->link.force_rate != link_rate) || 1353 (intel_dp->link.force_lane_count && 1354 intel_dp->link.force_lane_count != lane_count)) 1355 continue; 1356 1357 break; 1358 } 1359 1360 if (i < 0) 1361 return false; 1362 1363 *new_link_rate = link_rate; 1364 *new_lane_count = lane_count; 1365 1366 return true; 1367 } 1368 1369 static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) 1370 { 1371 int rate_index; 1372 int new_rate; 1373 1374 if (intel_dp->link.force_rate) 1375 return -1; 1376 1377 rate_index = intel_dp_rate_index(intel_dp->common_rates, 1378 intel_dp->num_common_rates, 1379 current_rate); 1380 1381 if (rate_index <= 0) 1382 return -1; 1383 1384 new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); 1385 1386 /* TODO: Make switching from UHBR to non-UHBR rates work. */ 1387 if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate)) 1388 return -1; 1389 1390 return new_rate; 1391 } 1392 1393 static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) 1394 { 1395 if (intel_dp->link.force_lane_count) 1396 return -1; 1397 1398 if (current_lane_count == 1) 1399 return -1; 1400 1401 return current_lane_count >> 1; 1402 } 1403 1404 static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp, 1405 const struct intel_crtc_state *crtc_state, 1406 int *new_link_rate, int *new_lane_count) 1407 { 1408 int link_rate; 1409 int lane_count; 1410 1411 lane_count = crtc_state->lane_count; 1412 link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); 1413 if (link_rate < 0) { 1414 lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); 1415 link_rate = intel_dp_max_common_rate(intel_dp); 1416 } 1417 1418 if (lane_count < 0) 1419 return false; 1420 1421 *new_link_rate = link_rate; 1422 *new_lane_count = lane_count; 1423 1424 return true; 1425 } 1426 1427 static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, 1428 int *new_link_rate, int *new_lane_count) 1429 { 1430 /* TODO: Use the same fallback logic on SST as on MST. */ 1431 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 1432 return reduce_link_params_in_bw_order(intel_dp, crtc_state, 1433 new_link_rate, new_lane_count); 1434 else 1435 return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state, 1436 new_link_rate, new_lane_count); 1437 } 1438 1439 static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 1440 const struct intel_crtc_state *crtc_state) 1441 { 1442 int new_link_rate; 1443 int new_lane_count; 1444 1445 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { 1446 lt_dbg(intel_dp, DP_PHY_DPRX, 1447 "Retrying Link training for eDP with max parameters\n"); 1448 intel_dp->use_max_params = true; 1449 return 0; 1450 } 1451 1452 if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count)) 1453 return -1; 1454 1455 if (intel_dp_is_edp(intel_dp) && 1456 !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { 1457 lt_dbg(intel_dp, DP_PHY_DPRX, 1458 "Retrying Link training for eDP with same parameters\n"); 1459 return 0; 1460 } 1461 1462 lt_dbg(intel_dp, DP_PHY_DPRX, 1463 "Reducing link parameters from %dx%d to %dx%d\n", 1464 crtc_state->lane_count, crtc_state->port_clock, 1465 new_lane_count, new_link_rate); 1466 1467 intel_dp->link.max_rate = new_link_rate; 1468 intel_dp->link.max_lane_count = new_lane_count; 1469 1470 return 0; 1471 } 1472 1473 static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, 1474 struct intel_dp *intel_dp, 1475 const struct intel_crtc_state *crtc_state) 1476 { 1477 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1478 1479 if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { 1480 lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); 1481 return true; 1482 } 1483 1484 if (intel_dp->hobl_active) { 1485 lt_dbg(intel_dp, DP_PHY_DPRX, 1486 "Link Training failed with HOBL active, not enabling it from now on\n"); 1487 intel_dp->hobl_failed = true; 1488 } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { 1489 return false; 1490 } 1491 1492 /* Schedule a Hotplug Uevent to userspace to start modeset */ 1493 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 1494 1495 return true; 1496 } 1497 1498 /* Perform the link training on all LTTPRs and the DPRX on a link. */ 1499 static bool 1500 intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 1501 const struct intel_crtc_state *crtc_state, 1502 int lttpr_count) 1503 { 1504 bool ret = true; 1505 int i; 1506 1507 for (i = lttpr_count - 1; i >= 0; i--) { 1508 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 1509 1510 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 1511 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 1512 1513 if (!ret) 1514 break; 1515 } 1516 1517 if (ret) 1518 ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 1519 1520 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 1521 intel_dp->set_idle_link_train(intel_dp, crtc_state); 1522 1523 if (ret) 1524 ret = intel_dp_post_lt_adj_req(intel_dp, crtc_state); 1525 1526 intel_dp_stop_post_lt_adj_req(intel_dp, crtc_state); 1527 1528 return ret; 1529 } 1530 1531 /* 1532 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1) 1533 */ 1534 static bool 1535 intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, 1536 const struct intel_crtc_state *crtc_state) 1537 { 1538 u8 link_status[DP_LINK_STATUS_SIZE]; 1539 int delay_us; 1540 int try, max_tries = 20; 1541 unsigned long deadline; 1542 bool timeout = false; 1543 1544 /* 1545 * Reset signal levels. Start transmitting 128b/132b TPS1. 1546 * 1547 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1 1548 * in DP_TRAINING_PATTERN_SET. 1549 */ 1550 if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1551 DP_TRAINING_PATTERN_1)) { 1552 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n"); 1553 return false; 1554 } 1555 1556 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1557 1558 /* Read the initial TX FFE settings. */ 1559 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1560 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n"); 1561 return false; 1562 } 1563 1564 /* Update signal levels and training set as requested. */ 1565 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1566 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1567 lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n"); 1568 return false; 1569 } 1570 1571 /* Start transmitting 128b/132b TPS2. */ 1572 if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1573 DP_TRAINING_PATTERN_2)) { 1574 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n"); 1575 return false; 1576 } 1577 1578 /* Time budget for the LANEx_EQ_DONE Sequence */ 1579 deadline = jiffies + msecs_to_jiffies_timeout(450); 1580 1581 for (try = 0; try < max_tries; try++) { 1582 fsleep(delay_us); 1583 1584 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1585 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1586 return false; 1587 } 1588 1589 if (drm_dp_128b132b_link_training_failed(link_status)) { 1590 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1591 lt_err(intel_dp, DP_PHY_DPRX, 1592 "Downstream link training failure\n"); 1593 return false; 1594 } 1595 1596 if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) { 1597 lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n"); 1598 break; 1599 } 1600 1601 if (timeout) { 1602 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1603 lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n"); 1604 return false; 1605 } 1606 1607 if (time_after(jiffies, deadline)) 1608 timeout = true; /* try one last time after deadline */ 1609 1610 /* 1611 * During LT, Tx shall read AUX_RD_INTERVAL just before writing the new FFE 1612 * presets. 1613 */ 1614 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1615 1616 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1617 1618 /* Update signal levels and training set as requested. */ 1619 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1620 lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n"); 1621 return false; 1622 } 1623 } 1624 1625 if (try == max_tries) { 1626 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1627 lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n"); 1628 return false; 1629 } 1630 1631 for (;;) { 1632 if (time_after(jiffies, deadline)) 1633 timeout = true; /* try one last time after deadline */ 1634 1635 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1636 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1637 return false; 1638 } 1639 1640 if (drm_dp_128b132b_link_training_failed(link_status)) { 1641 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1642 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1643 return false; 1644 } 1645 1646 if (drm_dp_128b132b_eq_interlane_align_done(link_status)) { 1647 lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n"); 1648 break; 1649 } 1650 1651 if (timeout) { 1652 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1653 lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n"); 1654 return false; 1655 } 1656 1657 usleep_range(2000, 3000); 1658 } 1659 1660 return true; 1661 } 1662 1663 /* 1664 * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2) 1665 */ 1666 static bool 1667 intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp, 1668 const struct intel_crtc_state *crtc_state, 1669 int lttpr_count) 1670 { 1671 u8 link_status[DP_LINK_STATUS_SIZE]; 1672 unsigned long deadline; 1673 1674 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 1675 DP_TRAINING_PATTERN_2_CDS) != 1) { 1676 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n"); 1677 return false; 1678 } 1679 1680 /* Time budget for the LANEx_CDS_DONE Sequence */ 1681 deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20); 1682 1683 for (;;) { 1684 bool timeout = false; 1685 1686 if (time_after(jiffies, deadline)) 1687 timeout = true; /* try one last time after deadline */ 1688 1689 usleep_range(2000, 3000); 1690 1691 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1692 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1693 return false; 1694 } 1695 1696 if (drm_dp_128b132b_eq_interlane_align_done(link_status) && 1697 drm_dp_128b132b_cds_interlane_align_done(link_status) && 1698 drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) { 1699 lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n"); 1700 break; 1701 } 1702 1703 if (drm_dp_128b132b_link_training_failed(link_status)) { 1704 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1705 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1706 return false; 1707 } 1708 1709 if (timeout) { 1710 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1711 lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n"); 1712 return false; 1713 } 1714 } 1715 1716 return true; 1717 } 1718 1719 /* 1720 * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.) 1721 */ 1722 static bool 1723 intel_dp_128b132b_link_train(struct intel_dp *intel_dp, 1724 const struct intel_crtc_state *crtc_state, 1725 int lttpr_count) 1726 { 1727 bool passed = false; 1728 int ret; 1729 1730 ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state), 1731 ret == 0, 1732 500, 500 * 1000, false); 1733 if (ret) { 1734 lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n"); 1735 goto out; 1736 } 1737 1738 if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) && 1739 intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count)) 1740 passed = true; 1741 1742 lt_dbg(intel_dp, DP_PHY_DPRX, 1743 "128b/132b Link Training %s at link rate = %d, lane count = %d\n", 1744 passed ? "passed" : "failed", 1745 crtc_state->port_clock, crtc_state->lane_count); 1746 1747 out: 1748 /* 1749 * Ensure that the training pattern does get set to TPS2 even in case 1750 * of a failure, as is the case at the end of a passing link training 1751 * and what is expected by the transcoder. Leaving TPS1 set (and 1752 * disabling the link train mode in DP_TP_CTL later from TPS1 directly) 1753 * would result in a stuck transcoder HW state and flip-done timeouts 1754 * later in the modeset sequence. 1755 */ 1756 if (!passed) 1757 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 1758 DP_PHY_DPRX, DP_TRAINING_PATTERN_2); 1759 1760 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 1761 1762 return passed; 1763 } 1764 1765 /** 1766 * intel_dp_start_link_train - start link training 1767 * @state: Atomic state 1768 * @intel_dp: DP struct 1769 * @crtc_state: state for CRTC attached to the encoder 1770 * 1771 * Start the link training of the @intel_dp port, scheduling a fallback 1772 * retraining with reduced link rate/lane parameters if the link training 1773 * fails. 1774 * After calling this function intel_dp_stop_link_train() must be called. 1775 */ 1776 void intel_dp_start_link_train(struct intel_atomic_state *state, 1777 struct intel_dp *intel_dp, 1778 const struct intel_crtc_state *crtc_state) 1779 { 1780 struct intel_display *display = to_intel_display(state); 1781 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1782 struct intel_encoder *encoder = &dig_port->base; 1783 bool passed; 1784 /* 1785 * Reinit the LTTPRs here to ensure that they are switched to 1786 * non-transparent mode. During an earlier LTTPR detection this 1787 * could've been prevented by an active link. 1788 */ 1789 int lttpr_count; 1790 1791 intel_hpd_block(encoder); 1792 1793 lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); 1794 1795 if (lttpr_count < 0) 1796 /* Still continue with enabling the port and link training. */ 1797 lttpr_count = 0; 1798 1799 intel_dp_prepare_link_train(intel_dp, crtc_state); 1800 1801 if (intel_dp_is_uhbr(crtc_state)) 1802 passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count); 1803 else 1804 passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); 1805 1806 if (intel_dp->link.force_train_failure) { 1807 intel_dp->link.force_train_failure--; 1808 lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n"); 1809 } else if (passed) { 1810 intel_dp->link.seq_train_failures = 0; 1811 return; 1812 } 1813 1814 intel_dp->link.seq_train_failures++; 1815 1816 /* 1817 * Ignore the link failure in CI 1818 * 1819 * In fixed environments like CI, sometimes unexpected long HPDs are 1820 * generated by the displays. If ignore_long_hpd flag is set, such long 1821 * HPDs are ignored. And probably as a consequence of these ignored 1822 * long HPDs, subsequent link trainings are failed resulting into CI 1823 * execution failures. 1824 * 1825 * For test cases which rely on the link training or processing of HPDs 1826 * ignore_long_hpd flag can unset from the testcase. 1827 */ 1828 if (display->hotplug.ignore_long_hpd) { 1829 lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n"); 1830 return; 1831 } 1832 1833 if (intel_dp->link.seq_train_failures < MAX_SEQ_TRAIN_FAILURES) 1834 return; 1835 1836 if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state)) 1837 return; 1838 1839 intel_dp->link.retrain_disabled = true; 1840 1841 if (!passed) 1842 lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n"); 1843 else 1844 lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n"); 1845 } 1846 1847 void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, 1848 const struct intel_crtc_state *crtc_state) 1849 { 1850 /* 1851 * VIDEO_DIP_CTL register bit 31 should be set to '0' to not 1852 * disable SDP CRC. This is applicable for Display version 13. 1853 * Default value of bit 31 is '0' hence discarding the write 1854 * TODO: Corrective actions on SDP corruption yet to be defined 1855 */ 1856 if (!intel_dp_is_uhbr(crtc_state)) 1857 return; 1858 1859 /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ 1860 drm_dp_dpcd_writeb(&intel_dp->aux, 1861 DP_SDP_ERROR_DETECTION_CONFIGURATION, 1862 DP_SDP_CRC16_128B132B_EN); 1863 1864 lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n"); 1865 } 1866 1867 static int i915_dp_force_link_rate_show(struct seq_file *m, void *data) 1868 { 1869 struct intel_connector *connector = to_intel_connector(m->private); 1870 struct intel_display *display = to_intel_display(connector); 1871 struct intel_dp *intel_dp = intel_attached_dp(connector); 1872 int current_rate = -1; 1873 int force_rate; 1874 int err; 1875 int i; 1876 1877 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1878 if (err) 1879 return err; 1880 1881 if (intel_dp->link.active) 1882 current_rate = intel_dp->link_rate; 1883 force_rate = intel_dp->link.force_rate; 1884 1885 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1886 1887 seq_printf(m, "%sauto%s", 1888 force_rate == 0 ? "[" : "", 1889 force_rate == 0 ? "]" : ""); 1890 1891 for (i = 0; i < intel_dp->num_source_rates; i++) 1892 seq_printf(m, " %s%d%s%s", 1893 intel_dp->source_rates[i] == force_rate ? "[" : "", 1894 intel_dp->source_rates[i], 1895 intel_dp->source_rates[i] == current_rate ? "*" : "", 1896 intel_dp->source_rates[i] == force_rate ? "]" : ""); 1897 1898 seq_putc(m, '\n'); 1899 1900 return 0; 1901 } 1902 1903 static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len) 1904 { 1905 char *kbuf; 1906 const char *p; 1907 int rate; 1908 int ret = 0; 1909 1910 kbuf = memdup_user_nul(ubuf, len); 1911 if (IS_ERR(kbuf)) 1912 return PTR_ERR(kbuf); 1913 1914 p = strim(kbuf); 1915 1916 if (!strcmp(p, "auto")) { 1917 rate = 0; 1918 } else { 1919 ret = kstrtoint(p, 0, &rate); 1920 if (ret < 0) 1921 goto out_free; 1922 1923 if (intel_dp_rate_index(intel_dp->source_rates, 1924 intel_dp->num_source_rates, 1925 rate) < 0) 1926 ret = -EINVAL; 1927 } 1928 1929 out_free: 1930 kfree(kbuf); 1931 1932 return ret < 0 ? ret : rate; 1933 } 1934 1935 static ssize_t i915_dp_force_link_rate_write(struct file *file, 1936 const char __user *ubuf, 1937 size_t len, loff_t *offp) 1938 { 1939 struct seq_file *m = file->private_data; 1940 struct intel_connector *connector = to_intel_connector(m->private); 1941 struct intel_display *display = to_intel_display(connector); 1942 struct intel_dp *intel_dp = intel_attached_dp(connector); 1943 int rate; 1944 int err; 1945 1946 rate = parse_link_rate(intel_dp, ubuf, len); 1947 if (rate < 0) 1948 return rate; 1949 1950 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1951 if (err) 1952 return err; 1953 1954 intel_dp_reset_link_params(intel_dp); 1955 intel_dp->link.force_rate = rate; 1956 1957 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1958 1959 *offp += len; 1960 1961 return len; 1962 } 1963 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_link_rate); 1964 1965 static int i915_dp_force_lane_count_show(struct seq_file *m, void *data) 1966 { 1967 struct intel_connector *connector = to_intel_connector(m->private); 1968 struct intel_display *display = to_intel_display(connector); 1969 struct intel_dp *intel_dp = intel_attached_dp(connector); 1970 int current_lane_count = -1; 1971 int force_lane_count; 1972 int err; 1973 int i; 1974 1975 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1976 if (err) 1977 return err; 1978 1979 if (intel_dp->link.active) 1980 current_lane_count = intel_dp->lane_count; 1981 force_lane_count = intel_dp->link.force_lane_count; 1982 1983 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1984 1985 seq_printf(m, "%sauto%s", 1986 force_lane_count == 0 ? "[" : "", 1987 force_lane_count == 0 ? "]" : ""); 1988 1989 for (i = 1; i <= 4; i <<= 1) 1990 seq_printf(m, " %s%d%s%s", 1991 i == force_lane_count ? "[" : "", 1992 i, 1993 i == current_lane_count ? "*" : "", 1994 i == force_lane_count ? "]" : ""); 1995 1996 seq_putc(m, '\n'); 1997 1998 return 0; 1999 } 2000 2001 static int parse_lane_count(const char __user *ubuf, size_t len) 2002 { 2003 char *kbuf; 2004 const char *p; 2005 int lane_count; 2006 int ret = 0; 2007 2008 kbuf = memdup_user_nul(ubuf, len); 2009 if (IS_ERR(kbuf)) 2010 return PTR_ERR(kbuf); 2011 2012 p = strim(kbuf); 2013 2014 if (!strcmp(p, "auto")) { 2015 lane_count = 0; 2016 } else { 2017 ret = kstrtoint(p, 0, &lane_count); 2018 if (ret < 0) 2019 goto out_free; 2020 2021 switch (lane_count) { 2022 case 1: 2023 case 2: 2024 case 4: 2025 break; 2026 default: 2027 ret = -EINVAL; 2028 } 2029 } 2030 2031 out_free: 2032 kfree(kbuf); 2033 2034 return ret < 0 ? ret : lane_count; 2035 } 2036 2037 static ssize_t i915_dp_force_lane_count_write(struct file *file, 2038 const char __user *ubuf, 2039 size_t len, loff_t *offp) 2040 { 2041 struct seq_file *m = file->private_data; 2042 struct intel_connector *connector = to_intel_connector(m->private); 2043 struct intel_display *display = to_intel_display(connector); 2044 struct intel_dp *intel_dp = intel_attached_dp(connector); 2045 int lane_count; 2046 int err; 2047 2048 lane_count = parse_lane_count(ubuf, len); 2049 if (lane_count < 0) 2050 return lane_count; 2051 2052 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2053 if (err) 2054 return err; 2055 2056 intel_dp_reset_link_params(intel_dp); 2057 intel_dp->link.force_lane_count = lane_count; 2058 2059 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2060 2061 *offp += len; 2062 2063 return len; 2064 } 2065 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_lane_count); 2066 2067 static int i915_dp_max_link_rate_show(void *data, u64 *val) 2068 { 2069 struct intel_connector *connector = to_intel_connector(data); 2070 struct intel_display *display = to_intel_display(connector); 2071 struct intel_dp *intel_dp = intel_attached_dp(connector); 2072 int err; 2073 2074 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2075 if (err) 2076 return err; 2077 2078 *val = intel_dp->link.max_rate; 2079 2080 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2081 2082 return 0; 2083 } 2084 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_link_rate_fops, i915_dp_max_link_rate_show, NULL, "%llu\n"); 2085 2086 static int i915_dp_max_lane_count_show(void *data, u64 *val) 2087 { 2088 struct intel_connector *connector = to_intel_connector(data); 2089 struct intel_display *display = to_intel_display(connector); 2090 struct intel_dp *intel_dp = intel_attached_dp(connector); 2091 int err; 2092 2093 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2094 if (err) 2095 return err; 2096 2097 *val = intel_dp->link.max_lane_count; 2098 2099 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2100 2101 return 0; 2102 } 2103 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n"); 2104 2105 static int i915_dp_force_link_training_failure_show(void *data, u64 *val) 2106 { 2107 struct intel_connector *connector = to_intel_connector(data); 2108 struct intel_display *display = to_intel_display(connector); 2109 struct intel_dp *intel_dp = intel_attached_dp(connector); 2110 int err; 2111 2112 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2113 if (err) 2114 return err; 2115 2116 *val = intel_dp->link.force_train_failure; 2117 2118 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2119 2120 return 0; 2121 } 2122 2123 static int i915_dp_force_link_training_failure_write(void *data, u64 val) 2124 { 2125 struct intel_connector *connector = to_intel_connector(data); 2126 struct intel_display *display = to_intel_display(connector); 2127 struct intel_dp *intel_dp = intel_attached_dp(connector); 2128 int err; 2129 2130 if (val > 2) 2131 return -EINVAL; 2132 2133 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2134 if (err) 2135 return err; 2136 2137 intel_dp->link.force_train_failure = val; 2138 2139 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2140 2141 return 0; 2142 } 2143 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, 2144 i915_dp_force_link_training_failure_show, 2145 i915_dp_force_link_training_failure_write, "%llu\n"); 2146 2147 static int i915_dp_force_link_retrain_show(void *data, u64 *val) 2148 { 2149 struct intel_connector *connector = to_intel_connector(data); 2150 struct intel_display *display = to_intel_display(connector); 2151 struct intel_dp *intel_dp = intel_attached_dp(connector); 2152 int err; 2153 2154 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2155 if (err) 2156 return err; 2157 2158 *val = intel_dp->link.force_retrain; 2159 2160 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2161 2162 return 0; 2163 } 2164 2165 static int i915_dp_force_link_retrain_write(void *data, u64 val) 2166 { 2167 struct intel_connector *connector = to_intel_connector(data); 2168 struct intel_display *display = to_intel_display(connector); 2169 struct intel_dp *intel_dp = intel_attached_dp(connector); 2170 int err; 2171 2172 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2173 if (err) 2174 return err; 2175 2176 intel_dp->link.force_retrain = val; 2177 2178 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2179 2180 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); 2181 2182 return 0; 2183 } 2184 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, 2185 i915_dp_force_link_retrain_show, 2186 i915_dp_force_link_retrain_write, "%llu\n"); 2187 2188 static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data) 2189 { 2190 struct intel_connector *connector = to_intel_connector(m->private); 2191 struct intel_display *display = to_intel_display(connector); 2192 struct intel_dp *intel_dp = intel_attached_dp(connector); 2193 int err; 2194 2195 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2196 if (err) 2197 return err; 2198 2199 seq_printf(m, "%s\n", str_yes_no(intel_dp->link.retrain_disabled)); 2200 2201 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2202 2203 return 0; 2204 } 2205 DEFINE_SHOW_ATTRIBUTE(i915_dp_link_retrain_disabled); 2206 2207 void intel_dp_link_training_debugfs_add(struct intel_connector *connector) 2208 { 2209 struct dentry *root = connector->base.debugfs_entry; 2210 2211 if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort && 2212 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 2213 return; 2214 2215 debugfs_create_file("i915_dp_force_link_rate", 0644, root, 2216 connector, &i915_dp_force_link_rate_fops); 2217 2218 debugfs_create_file("i915_dp_force_lane_count", 0644, root, 2219 connector, &i915_dp_force_lane_count_fops); 2220 2221 debugfs_create_file("i915_dp_max_link_rate", 0444, root, 2222 connector, &i915_dp_max_link_rate_fops); 2223 2224 debugfs_create_file("i915_dp_max_lane_count", 0444, root, 2225 connector, &i915_dp_max_lane_count_fops); 2226 2227 debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, 2228 connector, &i915_dp_force_link_training_failure_fops); 2229 2230 debugfs_create_file("i915_dp_force_link_retrain", 0644, root, 2231 connector, &i915_dp_force_link_retrain_fops); 2232 2233 debugfs_create_file("i915_dp_link_retrain_disabled", 0444, root, 2234 connector, &i915_dp_link_retrain_disabled_fops); 2235 } 2236