1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "i915_drv.h" 25 #include "intel_display_types.h" 26 #include "intel_dp.h" 27 #include "intel_dp_link_training.h" 28 29 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) 30 { 31 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); 32 } 33 34 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 35 { 36 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 37 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 38 } 39 40 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 41 enum drm_dp_phy dp_phy) 42 { 43 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 44 } 45 46 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 47 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 48 enum drm_dp_phy dp_phy) 49 { 50 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 51 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 52 53 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { 54 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 55 "[ENCODER:%d:%s][%s] failed to read the PHY caps\n", 56 encoder->base.base.id, encoder->base.name, 57 drm_dp_phy_name(dp_phy)); 58 return; 59 } 60 61 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 62 "[ENCODER:%d:%s][%s] PHY capabilities: %*ph\n", 63 encoder->base.base.id, encoder->base.name, 64 drm_dp_phy_name(dp_phy), 65 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 66 phy_caps); 67 } 68 69 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, 70 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 71 { 72 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 73 int ret; 74 75 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, 76 intel_dp->lttpr_common_caps); 77 if (ret < 0) 78 goto reset_caps; 79 80 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 81 "[ENCODER:%d:%s] LTTPR common capabilities: %*ph\n", 82 encoder->base.base.id, encoder->base.name, 83 (int)sizeof(intel_dp->lttpr_common_caps), 84 intel_dp->lttpr_common_caps); 85 86 /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ 87 if (intel_dp->lttpr_common_caps[0] < 0x14) 88 goto reset_caps; 89 90 return true; 91 92 reset_caps: 93 intel_dp_reset_lttpr_common_caps(intel_dp); 94 return false; 95 } 96 97 static bool 98 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 99 { 100 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 101 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 102 103 return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1; 104 } 105 106 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 107 { 108 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 109 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 110 int lttpr_count; 111 int i; 112 113 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) 114 return 0; 115 116 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 117 /* 118 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are 119 * detected as this breaks link training at least on the Dell WD19TB 120 * dock. 121 */ 122 if (lttpr_count == 0) 123 return 0; 124 125 /* 126 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of 127 * non-transparent mode and the disable->enable non-transparent mode 128 * sequence. 129 */ 130 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 131 132 /* 133 * In case of unsupported number of LTTPRs or failing to switch to 134 * non-transparent mode fall-back to transparent link training mode, 135 * still taking into account any LTTPR common lane- rate/count limits. 136 */ 137 if (lttpr_count < 0) 138 return 0; 139 140 if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { 141 drm_dbg_kms(&i915->drm, 142 "[ENCODER:%d:%s] Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n", 143 encoder->base.base.id, encoder->base.name); 144 145 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 146 intel_dp_reset_lttpr_count(intel_dp); 147 148 return 0; 149 } 150 151 for (i = 0; i < lttpr_count; i++) 152 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); 153 154 return lttpr_count; 155 } 156 157 /** 158 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode 159 * @intel_dp: Intel DP struct 160 * 161 * Read the LTTPR common and DPRX capabilities and switch to non-transparent 162 * link training mode if any is detected and read the PHY capabilities for all 163 * detected LTTPRs. In case of an LTTPR detection error or if the number of 164 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 165 * transparent mode link training mode. 166 * 167 * Returns: 168 * >0 if LTTPRs were detected and the non-transparent LT mode was set. The 169 * DPRX capabilities are read out. 170 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 171 * detection failure and the transparent LT mode was set. The DPRX 172 * capabilities are read out. 173 * <0 Reading out the DPRX capabilities failed. 174 */ 175 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) 176 { 177 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 178 int lttpr_count = 0; 179 180 /* 181 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 182 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 183 */ 184 if (!intel_dp_is_edp(intel_dp) && 185 (DISPLAY_VER(i915) >= 10 && !IS_GEMINILAKE(i915))) { 186 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 187 188 if (drm_dp_dpcd_probe(&intel_dp->aux, DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV)) 189 return -EIO; 190 191 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) 192 return -EIO; 193 194 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); 195 } 196 197 /* 198 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read 199 * it here. 200 */ 201 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { 202 intel_dp_reset_lttpr_common_caps(intel_dp); 203 return -EIO; 204 } 205 206 return lttpr_count; 207 } 208 209 static u8 dp_voltage_max(u8 preemph) 210 { 211 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 212 case DP_TRAIN_PRE_EMPH_LEVEL_0: 213 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 214 case DP_TRAIN_PRE_EMPH_LEVEL_1: 215 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 216 case DP_TRAIN_PRE_EMPH_LEVEL_2: 217 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 218 case DP_TRAIN_PRE_EMPH_LEVEL_3: 219 default: 220 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 221 } 222 } 223 224 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 225 enum drm_dp_phy dp_phy) 226 { 227 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 228 229 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 230 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 231 else 232 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 233 } 234 235 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 236 enum drm_dp_phy dp_phy) 237 { 238 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 239 240 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 241 return DP_TRAIN_PRE_EMPH_LEVEL_3; 242 else 243 return DP_TRAIN_PRE_EMPH_LEVEL_2; 244 } 245 246 static bool 247 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 248 enum drm_dp_phy dp_phy) 249 { 250 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 251 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 252 253 drm_WARN_ON_ONCE(&i915->drm, lttpr_count <= 0 && dp_phy != DP_PHY_DPRX); 254 255 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 256 } 257 258 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 259 const struct intel_crtc_state *crtc_state, 260 enum drm_dp_phy dp_phy) 261 { 262 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 263 u8 voltage_max; 264 265 /* 266 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 267 * the DPRX_PHY we train. 268 */ 269 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 270 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 271 else 272 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 273 274 drm_WARN_ON_ONCE(&i915->drm, 275 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 276 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 277 278 return voltage_max; 279 } 280 281 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 282 enum drm_dp_phy dp_phy) 283 { 284 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 285 u8 preemph_max; 286 287 /* 288 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 289 * the DPRX_PHY we train. 290 */ 291 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 292 preemph_max = intel_dp->preemph_max(intel_dp); 293 else 294 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 295 296 drm_WARN_ON_ONCE(&i915->drm, 297 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 298 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 299 300 return preemph_max; 301 } 302 303 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, 304 enum drm_dp_phy dp_phy) 305 { 306 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 307 308 return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) || 309 DISPLAY_VER(i915) >= 11; 310 } 311 312 /* 128b/132b */ 313 static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp, 314 const struct intel_crtc_state *crtc_state, 315 enum drm_dp_phy dp_phy, 316 const u8 link_status[DP_LINK_STATUS_SIZE], 317 int lane) 318 { 319 u8 tx_ffe = 0; 320 321 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 322 lane = min(lane, crtc_state->lane_count - 1); 323 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); 324 } else { 325 for (lane = 0; lane < crtc_state->lane_count; lane++) 326 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); 327 } 328 329 return tx_ffe; 330 } 331 332 /* 8b/10b */ 333 static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp, 334 const struct intel_crtc_state *crtc_state, 335 enum drm_dp_phy dp_phy, 336 const u8 link_status[DP_LINK_STATUS_SIZE], 337 int lane) 338 { 339 u8 v = 0; 340 u8 p = 0; 341 u8 voltage_max; 342 u8 preemph_max; 343 344 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 345 lane = min(lane, crtc_state->lane_count - 1); 346 347 v = drm_dp_get_adjust_request_voltage(link_status, lane); 348 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 349 } else { 350 for (lane = 0; lane < crtc_state->lane_count; lane++) { 351 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 352 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 353 } 354 } 355 356 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 357 if (p >= preemph_max) 358 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 359 360 v = min(v, dp_voltage_max(p)); 361 362 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 363 if (v >= voltage_max) 364 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 365 366 return v | p; 367 } 368 369 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, 370 const struct intel_crtc_state *crtc_state, 371 enum drm_dp_phy dp_phy, 372 const u8 link_status[DP_LINK_STATUS_SIZE], 373 int lane) 374 { 375 if (intel_dp_is_uhbr(crtc_state)) 376 return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state, 377 dp_phy, link_status, lane); 378 else 379 return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state, 380 dp_phy, link_status, lane); 381 } 382 383 #define TRAIN_REQ_FMT "%d/%d/%d/%d" 384 #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \ 385 (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT) 386 #define TRAIN_REQ_VSWING_ARGS(link_status) \ 387 _TRAIN_REQ_VSWING_ARGS(link_status, 0), \ 388 _TRAIN_REQ_VSWING_ARGS(link_status, 1), \ 389 _TRAIN_REQ_VSWING_ARGS(link_status, 2), \ 390 _TRAIN_REQ_VSWING_ARGS(link_status, 3) 391 #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \ 392 (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT) 393 #define TRAIN_REQ_PREEMPH_ARGS(link_status) \ 394 _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \ 395 _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \ 396 _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \ 397 _TRAIN_REQ_PREEMPH_ARGS(link_status, 3) 398 #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \ 399 drm_dp_get_adjust_tx_ffe_preset((link_status), (lane)) 400 #define TRAIN_REQ_TX_FFE_ARGS(link_status) \ 401 _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \ 402 _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \ 403 _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \ 404 _TRAIN_REQ_TX_FFE_ARGS(link_status, 3) 405 406 void 407 intel_dp_get_adjust_train(struct intel_dp *intel_dp, 408 const struct intel_crtc_state *crtc_state, 409 enum drm_dp_phy dp_phy, 410 const u8 link_status[DP_LINK_STATUS_SIZE]) 411 { 412 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 413 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 414 int lane; 415 416 if (intel_dp_is_uhbr(crtc_state)) { 417 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 128b/132b, lanes: %d, " 418 "TX FFE request: " TRAIN_REQ_FMT "\n", 419 encoder->base.base.id, encoder->base.name, 420 drm_dp_phy_name(dp_phy), 421 crtc_state->lane_count, 422 TRAIN_REQ_TX_FFE_ARGS(link_status)); 423 } else { 424 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 8b/10b, lanes: %d, " 425 "vswing request: " TRAIN_REQ_FMT ", " 426 "pre-emphasis request: " TRAIN_REQ_FMT "\n", 427 encoder->base.base.id, encoder->base.name, 428 drm_dp_phy_name(dp_phy), 429 crtc_state->lane_count, 430 TRAIN_REQ_VSWING_ARGS(link_status), 431 TRAIN_REQ_PREEMPH_ARGS(link_status)); 432 } 433 434 for (lane = 0; lane < 4; lane++) 435 intel_dp->train_set[lane] = 436 intel_dp_get_lane_adjust_train(intel_dp, crtc_state, 437 dp_phy, link_status, lane); 438 } 439 440 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 441 enum drm_dp_phy dp_phy) 442 { 443 return dp_phy == DP_PHY_DPRX ? 444 DP_TRAINING_PATTERN_SET : 445 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 446 } 447 448 static bool 449 intel_dp_set_link_train(struct intel_dp *intel_dp, 450 const struct intel_crtc_state *crtc_state, 451 enum drm_dp_phy dp_phy, 452 u8 dp_train_pat) 453 { 454 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 455 u8 buf[sizeof(intel_dp->train_set) + 1]; 456 int len; 457 458 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 459 dp_phy, dp_train_pat); 460 461 buf[0] = dp_train_pat; 462 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 463 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 464 len = crtc_state->lane_count + 1; 465 466 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 467 } 468 469 static char dp_training_pattern_name(u8 train_pat) 470 { 471 switch (train_pat) { 472 case DP_TRAINING_PATTERN_1: 473 case DP_TRAINING_PATTERN_2: 474 case DP_TRAINING_PATTERN_3: 475 return '0' + train_pat; 476 case DP_TRAINING_PATTERN_4: 477 return '4'; 478 default: 479 MISSING_CASE(train_pat); 480 return '?'; 481 } 482 } 483 484 void 485 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 486 const struct intel_crtc_state *crtc_state, 487 enum drm_dp_phy dp_phy, 488 u8 dp_train_pat) 489 { 490 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 491 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 492 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat); 493 494 if (train_pat != DP_TRAINING_PATTERN_DISABLE) 495 drm_dbg_kms(&i915->drm, 496 "[ENCODER:%d:%s][%s] Using DP training pattern TPS%c\n", 497 encoder->base.base.id, encoder->base.name, 498 drm_dp_phy_name(dp_phy), 499 dp_training_pattern_name(train_pat)); 500 501 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); 502 } 503 504 #define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" 505 #define _TRAIN_SET_VSWING_ARGS(train_set) \ 506 ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ 507 (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" 508 #define TRAIN_SET_VSWING_ARGS(train_set) \ 509 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ 510 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ 511 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ 512 _TRAIN_SET_VSWING_ARGS((train_set)[3]) 513 #define _TRAIN_SET_PREEMPH_ARGS(train_set) \ 514 ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ 515 (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" 516 #define TRAIN_SET_PREEMPH_ARGS(train_set) \ 517 _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ 518 _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ 519 _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ 520 _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) 521 #define _TRAIN_SET_TX_FFE_ARGS(train_set) \ 522 ((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), "" 523 #define TRAIN_SET_TX_FFE_ARGS(train_set) \ 524 _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \ 525 _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \ 526 _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \ 527 _TRAIN_SET_TX_FFE_ARGS((train_set)[3]) 528 529 void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 530 const struct intel_crtc_state *crtc_state, 531 enum drm_dp_phy dp_phy) 532 { 533 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 534 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 535 536 if (intel_dp_is_uhbr(crtc_state)) { 537 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 128b/132b, lanes: %d, " 538 "TX FFE presets: " TRAIN_SET_FMT "\n", 539 encoder->base.base.id, encoder->base.name, 540 drm_dp_phy_name(dp_phy), 541 crtc_state->lane_count, 542 TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set)); 543 } else { 544 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 8b/10b, lanes: %d, " 545 "vswing levels: " TRAIN_SET_FMT ", " 546 "pre-emphasis levels: " TRAIN_SET_FMT "\n", 547 encoder->base.base.id, encoder->base.name, 548 drm_dp_phy_name(dp_phy), 549 crtc_state->lane_count, 550 TRAIN_SET_VSWING_ARGS(intel_dp->train_set), 551 TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set)); 552 } 553 554 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 555 encoder->set_signal_levels(encoder, crtc_state); 556 } 557 558 static bool 559 intel_dp_reset_link_train(struct intel_dp *intel_dp, 560 const struct intel_crtc_state *crtc_state, 561 enum drm_dp_phy dp_phy, 562 u8 dp_train_pat) 563 { 564 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 565 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 566 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 567 } 568 569 static bool 570 intel_dp_update_link_train(struct intel_dp *intel_dp, 571 const struct intel_crtc_state *crtc_state, 572 enum drm_dp_phy dp_phy) 573 { 574 int reg = dp_phy == DP_PHY_DPRX ? 575 DP_TRAINING_LANE0_SET : 576 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 577 int ret; 578 579 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 580 581 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 582 intel_dp->train_set, crtc_state->lane_count); 583 584 return ret == crtc_state->lane_count; 585 } 586 587 /* 128b/132b */ 588 static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane) 589 { 590 return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) == 591 DP_TX_FFE_PRESET_VALUE_MASK; 592 } 593 594 /* 595 * 8b/10b 596 * 597 * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to 598 * have self contradicting tests around this area. 599 * 600 * In lieu of better ideas let's just stop when we've reached the max supported 601 * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on 602 * whether vswing level 3 is supported or not. 603 */ 604 static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane) 605 { 606 u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 607 DP_TRAIN_VOLTAGE_SWING_SHIFT; 608 u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 609 DP_TRAIN_PRE_EMPHASIS_SHIFT; 610 611 if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0) 612 return false; 613 614 if (v + p != 3) 615 return false; 616 617 return true; 618 } 619 620 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 621 const struct intel_crtc_state *crtc_state) 622 { 623 int lane; 624 625 for (lane = 0; lane < crtc_state->lane_count; lane++) { 626 u8 train_set_lane = intel_dp->train_set[lane]; 627 628 if (intel_dp_is_uhbr(crtc_state)) { 629 if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane)) 630 return false; 631 } else { 632 if (!intel_dp_lane_max_vswing_reached(train_set_lane)) 633 return false; 634 } 635 } 636 637 return true; 638 } 639 640 /* 641 * Prepare link training by configuring the link parameters. On DDI platforms 642 * also enable the port here. 643 */ 644 static bool 645 intel_dp_prepare_link_train(struct intel_dp *intel_dp, 646 const struct intel_crtc_state *crtc_state) 647 { 648 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 649 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 650 u8 link_config[2]; 651 u8 link_bw, rate_select; 652 653 if (intel_dp->prepare_link_retrain) 654 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 655 656 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 657 &link_bw, &rate_select); 658 659 /* 660 * WaEdpLinkRateDataReload 661 * 662 * Parade PS8461E MUX (used on varius TGL+ laptops) needs 663 * to snoop the link rates reported by the sink when we 664 * use LINK_RATE_SET in order to operate in jitter cleaning 665 * mode (as opposed to redriver mode). Unfortunately it 666 * loses track of the snooped link rates when powered down, 667 * so we need to make it re-snoop often. Without this high 668 * link rates are not stable. 669 */ 670 if (!link_bw) { 671 struct intel_connector *connector = intel_dp->attached_connector; 672 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 673 674 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Reloading eDP link rates\n", 675 connector->base.base.id, connector->base.name); 676 677 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 678 sink_rates, sizeof(sink_rates)); 679 } 680 681 if (link_bw) 682 drm_dbg_kms(&i915->drm, 683 "[ENCODER:%d:%s] Using LINK_BW_SET value %02x\n", 684 encoder->base.base.id, encoder->base.name, link_bw); 685 else 686 drm_dbg_kms(&i915->drm, 687 "[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n", 688 encoder->base.base.id, encoder->base.name, rate_select); 689 690 /* Write the link configuration data */ 691 link_config[0] = link_bw; 692 link_config[1] = crtc_state->lane_count; 693 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 694 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 695 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 696 697 /* eDP 1.4 rate select method. */ 698 if (!link_bw) 699 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, 700 &rate_select, 1); 701 702 link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 703 link_config[1] = intel_dp_is_uhbr(crtc_state) ? 704 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; 705 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 706 707 return true; 708 } 709 710 static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state, 711 const u8 old_link_status[DP_LINK_STATUS_SIZE], 712 const u8 new_link_status[DP_LINK_STATUS_SIZE]) 713 { 714 int lane; 715 716 for (lane = 0; lane < crtc_state->lane_count; lane++) { 717 u8 old, new; 718 719 if (intel_dp_is_uhbr(crtc_state)) { 720 old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane); 721 new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane); 722 } else { 723 old = drm_dp_get_adjust_request_voltage(old_link_status, lane) | 724 drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane); 725 new = drm_dp_get_adjust_request_voltage(new_link_status, lane) | 726 drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane); 727 } 728 729 if (old != new) 730 return true; 731 } 732 733 return false; 734 } 735 736 void 737 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy, 738 const u8 link_status[DP_LINK_STATUS_SIZE]) 739 { 740 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 741 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 742 743 drm_dbg_kms(&i915->drm, 744 "[ENCODER:%d:%s][%s] ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n", 745 encoder->base.base.id, encoder->base.name, 746 drm_dp_phy_name(dp_phy), 747 link_status[0], link_status[1], link_status[2], 748 link_status[3], link_status[4], link_status[5]); 749 } 750 751 /* 752 * Perform the link training clock recovery phase on the given DP PHY using 753 * training pattern 1. 754 */ 755 static bool 756 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 757 const struct intel_crtc_state *crtc_state, 758 enum drm_dp_phy dp_phy) 759 { 760 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 761 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 762 u8 old_link_status[DP_LINK_STATUS_SIZE] = {}; 763 int voltage_tries, cr_tries, max_cr_tries; 764 u8 link_status[DP_LINK_STATUS_SIZE]; 765 bool max_vswing_reached = false; 766 int delay_us; 767 768 delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux, 769 intel_dp->dpcd, dp_phy, 770 intel_dp_is_uhbr(crtc_state)); 771 772 /* clock recovery */ 773 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 774 DP_TRAINING_PATTERN_1 | 775 DP_LINK_SCRAMBLING_DISABLE)) { 776 drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to enable link training\n", 777 encoder->base.base.id, encoder->base.name, 778 drm_dp_phy_name(dp_phy)); 779 return false; 780 } 781 782 /* 783 * The DP 1.4 spec defines the max clock recovery retries value 784 * as 10 but for pre-DP 1.4 devices we set a very tolerant 785 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 786 * x 5 identical voltage retries). Since the previous specs didn't 787 * define a limit and created the possibility of an infinite loop 788 * we want to prevent any sync from triggering that corner case. 789 */ 790 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 791 max_cr_tries = 10; 792 else 793 max_cr_tries = 80; 794 795 voltage_tries = 1; 796 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 797 usleep_range(delay_us, 2 * delay_us); 798 799 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 800 link_status) < 0) { 801 drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to get link status\n", 802 encoder->base.base.id, encoder->base.name, 803 drm_dp_phy_name(dp_phy)); 804 return false; 805 } 806 807 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 808 drm_dbg_kms(&i915->drm, 809 "[ENCODER:%d:%s][%s] Clock recovery OK\n", 810 encoder->base.base.id, encoder->base.name, 811 drm_dp_phy_name(dp_phy)); 812 return true; 813 } 814 815 if (voltage_tries == 5) { 816 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 817 drm_dbg_kms(&i915->drm, 818 "[ENCODER:%d:%s][%s] Same voltage tried 5 times\n", 819 encoder->base.base.id, encoder->base.name, 820 drm_dp_phy_name(dp_phy)); 821 return false; 822 } 823 824 if (max_vswing_reached) { 825 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 826 drm_dbg_kms(&i915->drm, 827 "[ENCODER:%d:%s][%s] Max Voltage Swing reached\n", 828 encoder->base.base.id, encoder->base.name, 829 drm_dp_phy_name(dp_phy)); 830 return false; 831 } 832 833 /* Update training set as requested by target */ 834 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 835 link_status); 836 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 837 drm_err(&i915->drm, 838 "[ENCODER:%d:%s][%s] Failed to update link training\n", 839 encoder->base.base.id, encoder->base.name, 840 drm_dp_phy_name(dp_phy)); 841 return false; 842 } 843 844 if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status)) 845 ++voltage_tries; 846 else 847 voltage_tries = 1; 848 849 memcpy(old_link_status, link_status, sizeof(link_status)); 850 851 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 852 max_vswing_reached = true; 853 } 854 855 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 856 drm_err(&i915->drm, 857 "[ENCODER:%d:%s][%s] Failed clock recovery %d times, giving up!\n", 858 encoder->base.base.id, encoder->base.name, 859 drm_dp_phy_name(dp_phy), max_cr_tries); 860 861 return false; 862 } 863 864 /* 865 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 866 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or 867 * 1.2 devices that support it, TPS2 otherwise. 868 */ 869 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 870 const struct intel_crtc_state *crtc_state, 871 enum drm_dp_phy dp_phy) 872 { 873 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 874 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 875 876 /* UHBR+ use separate 128b/132b TPS2 */ 877 if (intel_dp_is_uhbr(crtc_state)) 878 return DP_TRAINING_PATTERN_2; 879 880 /* 881 * TPS4 support is mandatory for all downstream devices that 882 * support HBR3. There are no known eDP panels that support 883 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification. 884 * LTTPRs must support TPS4. 885 */ 886 source_tps4 = intel_dp_source_supports_tps4(i915); 887 sink_tps4 = dp_phy != DP_PHY_DPRX || 888 drm_dp_tps4_supported(intel_dp->dpcd); 889 if (source_tps4 && sink_tps4) { 890 return DP_TRAINING_PATTERN_4; 891 } else if (crtc_state->port_clock == 810000) { 892 if (!source_tps4) 893 drm_dbg_kms(&i915->drm, 894 "8.1 Gbps link rate without source TPS4 support\n"); 895 if (!sink_tps4) 896 drm_dbg_kms(&i915->drm, 897 "8.1 Gbps link rate without sink TPS4 support\n"); 898 } 899 900 /* 901 * TPS3 support is mandatory for downstream devices that 902 * support HBR2. However, not all sinks follow the spec. 903 */ 904 source_tps3 = intel_dp_source_supports_tps3(i915); 905 sink_tps3 = dp_phy != DP_PHY_DPRX || 906 drm_dp_tps3_supported(intel_dp->dpcd); 907 if (source_tps3 && sink_tps3) { 908 return DP_TRAINING_PATTERN_3; 909 } else if (crtc_state->port_clock >= 540000) { 910 if (!source_tps3) 911 drm_dbg_kms(&i915->drm, 912 ">=5.4/6.48 Gbps link rate without source TPS3 support\n"); 913 if (!sink_tps3) 914 drm_dbg_kms(&i915->drm, 915 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 916 } 917 918 return DP_TRAINING_PATTERN_2; 919 } 920 921 /* 922 * Perform the link training channel equalization phase on the given DP PHY 923 * using one of training pattern 2, 3 or 4 depending on the source and 924 * sink capabilities. 925 */ 926 static bool 927 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 928 const struct intel_crtc_state *crtc_state, 929 enum drm_dp_phy dp_phy) 930 { 931 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 932 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 933 int tries; 934 u32 training_pattern; 935 u8 link_status[DP_LINK_STATUS_SIZE]; 936 bool channel_eq = false; 937 int delay_us; 938 939 delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux, 940 intel_dp->dpcd, dp_phy, 941 intel_dp_is_uhbr(crtc_state)); 942 943 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 944 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 945 if (training_pattern != DP_TRAINING_PATTERN_4) 946 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 947 948 /* channel equalization */ 949 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 950 training_pattern)) { 951 drm_err(&i915->drm, 952 "[ENCODER:%d:%s][%s] Failed to start channel equalization\n", 953 encoder->base.base.id, encoder->base.name, 954 drm_dp_phy_name(dp_phy)); 955 return false; 956 } 957 958 for (tries = 0; tries < 5; tries++) { 959 usleep_range(delay_us, 2 * delay_us); 960 961 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 962 link_status) < 0) { 963 drm_err(&i915->drm, 964 "[ENCODER:%d:%s][%s] Failed to get link status\n", 965 encoder->base.base.id, encoder->base.name, 966 drm_dp_phy_name(dp_phy)); 967 break; 968 } 969 970 /* Make sure clock is still ok */ 971 if (!drm_dp_clock_recovery_ok(link_status, 972 crtc_state->lane_count)) { 973 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 974 drm_dbg_kms(&i915->drm, 975 "[ENCODER:%d:%s][%s] Clock recovery check failed, cannot " 976 "continue channel equalization\n", 977 encoder->base.base.id, encoder->base.name, 978 drm_dp_phy_name(dp_phy)); 979 break; 980 } 981 982 if (drm_dp_channel_eq_ok(link_status, 983 crtc_state->lane_count)) { 984 channel_eq = true; 985 drm_dbg_kms(&i915->drm, 986 "[ENCODER:%d:%s][%s] Channel EQ done. DP Training successful\n", 987 encoder->base.base.id, encoder->base.name, 988 drm_dp_phy_name(dp_phy)); 989 break; 990 } 991 992 /* Update training set as requested by target */ 993 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 994 link_status); 995 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 996 drm_err(&i915->drm, 997 "[ENCODER:%d:%s][%s] Failed to update link training\n", 998 encoder->base.base.id, encoder->base.name, 999 drm_dp_phy_name(dp_phy)); 1000 break; 1001 } 1002 } 1003 1004 /* Try 5 times, else fail and try at lower BW */ 1005 if (tries == 5) { 1006 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1007 drm_dbg_kms(&i915->drm, 1008 "[ENCODER:%d:%s][%s] Channel equalization failed 5 times\n", 1009 encoder->base.base.id, encoder->base.name, 1010 drm_dp_phy_name(dp_phy)); 1011 } 1012 1013 return channel_eq; 1014 } 1015 1016 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 1017 enum drm_dp_phy dp_phy) 1018 { 1019 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 1020 u8 val = DP_TRAINING_PATTERN_DISABLE; 1021 1022 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 1023 } 1024 1025 static int 1026 intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp, 1027 const struct intel_crtc_state *crtc_state) 1028 { 1029 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1030 u8 sink_status; 1031 int ret; 1032 1033 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status); 1034 if (ret != 1) { 1035 drm_dbg_kms(&i915->drm, "Failed to read sink status\n"); 1036 return ret < 0 ? ret : -EIO; 1037 } 1038 1039 return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0; 1040 } 1041 1042 /** 1043 * intel_dp_stop_link_train - stop link training 1044 * @intel_dp: DP struct 1045 * @crtc_state: state for CRTC attached to the encoder 1046 * 1047 * Stop the link training of the @intel_dp port, disabling the training 1048 * pattern in the sink's DPCD, and disabling the test pattern symbol 1049 * generation on the port. 1050 * 1051 * What symbols are output on the port after this point is 1052 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 1053 * with the pipe being disabled, on older platforms it's HW specific if/how an 1054 * idle pattern is generated, as the pipe is already enabled here for those. 1055 * 1056 * This function must be called after intel_dp_start_link_train(). 1057 */ 1058 void intel_dp_stop_link_train(struct intel_dp *intel_dp, 1059 const struct intel_crtc_state *crtc_state) 1060 { 1061 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1062 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1063 1064 intel_dp->link_trained = true; 1065 1066 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 1067 intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX, 1068 DP_TRAINING_PATTERN_DISABLE); 1069 1070 if (intel_dp_is_uhbr(crtc_state) && 1071 wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1072 drm_dbg_kms(&i915->drm, 1073 "[ENCODER:%d:%s] 128b/132b intra-hop not clearing\n", 1074 encoder->base.base.id, encoder->base.name); 1075 } 1076 } 1077 1078 static bool 1079 intel_dp_link_train_phy(struct intel_dp *intel_dp, 1080 const struct intel_crtc_state *crtc_state, 1081 enum drm_dp_phy dp_phy) 1082 { 1083 struct intel_connector *connector = intel_dp->attached_connector; 1084 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1085 bool ret = false; 1086 1087 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 1088 goto out; 1089 1090 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 1091 goto out; 1092 1093 ret = true; 1094 1095 out: 1096 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 1097 "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] Link Training %s at link rate = %d, lane count = %d\n", 1098 connector->base.base.id, connector->base.name, 1099 encoder->base.base.id, encoder->base.name, 1100 drm_dp_phy_name(dp_phy), 1101 ret ? "passed" : "failed", 1102 crtc_state->port_clock, crtc_state->lane_count); 1103 1104 return ret; 1105 } 1106 1107 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, 1108 const struct intel_crtc_state *crtc_state) 1109 { 1110 struct intel_connector *intel_connector = intel_dp->attached_connector; 1111 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1112 1113 if (intel_dp->hobl_active) { 1114 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 1115 "[ENCODER:%d:%s] Link Training failed with HOBL active, " 1116 "not enabling it from now on", 1117 encoder->base.base.id, encoder->base.name); 1118 intel_dp->hobl_failed = true; 1119 } else if (intel_dp_get_link_train_fallback_values(intel_dp, 1120 crtc_state->port_clock, 1121 crtc_state->lane_count)) { 1122 return; 1123 } 1124 1125 /* Schedule a Hotplug Uevent to userspace to start modeset */ 1126 schedule_work(&intel_connector->modeset_retry_work); 1127 } 1128 1129 /* Perform the link training on all LTTPRs and the DPRX on a link. */ 1130 static bool 1131 intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 1132 const struct intel_crtc_state *crtc_state, 1133 int lttpr_count) 1134 { 1135 bool ret = true; 1136 int i; 1137 1138 for (i = lttpr_count - 1; i >= 0; i--) { 1139 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 1140 1141 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 1142 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 1143 1144 if (!ret) 1145 break; 1146 } 1147 1148 if (ret) 1149 ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 1150 1151 if (intel_dp->set_idle_link_train) 1152 intel_dp->set_idle_link_train(intel_dp, crtc_state); 1153 1154 return ret; 1155 } 1156 1157 /* 1158 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1) 1159 */ 1160 static bool 1161 intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, 1162 const struct intel_crtc_state *crtc_state) 1163 { 1164 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1165 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1166 u8 link_status[DP_LINK_STATUS_SIZE]; 1167 int delay_us; 1168 int try, max_tries = 20; 1169 unsigned long deadline; 1170 bool timeout = false; 1171 1172 /* 1173 * Reset signal levels. Start transmitting 128b/132b TPS1. 1174 * 1175 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1 1176 * in DP_TRAINING_PATTERN_SET. 1177 */ 1178 if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1179 DP_TRAINING_PATTERN_1)) { 1180 drm_err(&i915->drm, 1181 "[ENCODER:%d:%s] Failed to start 128b/132b TPS1\n", 1182 encoder->base.base.id, encoder->base.name); 1183 return false; 1184 } 1185 1186 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1187 1188 /* Read the initial TX FFE settings. */ 1189 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1190 drm_err(&i915->drm, 1191 "[ENCODER:%d:%s] Failed to read TX FFE presets\n", 1192 encoder->base.base.id, encoder->base.name); 1193 return false; 1194 } 1195 1196 /* Update signal levels and training set as requested. */ 1197 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1198 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1199 drm_err(&i915->drm, 1200 "[ENCODER:%d:%s] Failed to set initial TX FFE settings\n", 1201 encoder->base.base.id, encoder->base.name); 1202 return false; 1203 } 1204 1205 /* Start transmitting 128b/132b TPS2. */ 1206 if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1207 DP_TRAINING_PATTERN_2)) { 1208 drm_err(&i915->drm, 1209 "[ENCODER:%d:%s] Failed to start 128b/132b TPS2\n", 1210 encoder->base.base.id, encoder->base.name); 1211 return false; 1212 } 1213 1214 /* Time budget for the LANEx_EQ_DONE Sequence */ 1215 deadline = jiffies + msecs_to_jiffies_timeout(400); 1216 1217 for (try = 0; try < max_tries; try++) { 1218 usleep_range(delay_us, 2 * delay_us); 1219 1220 /* 1221 * The delay may get updated. The transmitter shall read the 1222 * delay before link status during link training. 1223 */ 1224 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1225 1226 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1227 drm_err(&i915->drm, 1228 "[ENCODER:%d:%s] Failed to read link status\n", 1229 encoder->base.base.id, encoder->base.name); 1230 return false; 1231 } 1232 1233 if (drm_dp_128b132b_link_training_failed(link_status)) { 1234 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1235 drm_err(&i915->drm, 1236 "[ENCODER:%d:%s] Downstream link training failure\n", 1237 encoder->base.base.id, encoder->base.name); 1238 return false; 1239 } 1240 1241 if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) { 1242 drm_dbg_kms(&i915->drm, 1243 "[ENCODER:%d:%s] Lane channel eq done\n", 1244 encoder->base.base.id, encoder->base.name); 1245 break; 1246 } 1247 1248 if (timeout) { 1249 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1250 drm_err(&i915->drm, 1251 "[ENCODER:%d:%s] Lane channel eq timeout\n", 1252 encoder->base.base.id, encoder->base.name); 1253 return false; 1254 } 1255 1256 if (time_after(jiffies, deadline)) 1257 timeout = true; /* try one last time after deadline */ 1258 1259 /* Update signal levels and training set as requested. */ 1260 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1261 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1262 drm_err(&i915->drm, 1263 "[ENCODER:%d:%s] Failed to update TX FFE settings\n", 1264 encoder->base.base.id, encoder->base.name); 1265 return false; 1266 } 1267 } 1268 1269 if (try == max_tries) { 1270 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1271 drm_err(&i915->drm, 1272 "[ENCODER:%d:%s] Max loop count reached\n", 1273 encoder->base.base.id, encoder->base.name); 1274 return false; 1275 } 1276 1277 for (;;) { 1278 if (time_after(jiffies, deadline)) 1279 timeout = true; /* try one last time after deadline */ 1280 1281 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1282 drm_err(&i915->drm, 1283 "[ENCODER:%d:%s] Failed to read link status\n", 1284 encoder->base.base.id, encoder->base.name); 1285 return false; 1286 } 1287 1288 if (drm_dp_128b132b_link_training_failed(link_status)) { 1289 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1290 drm_err(&i915->drm, 1291 "[ENCODER:%d:%s] Downstream link training failure\n", 1292 encoder->base.base.id, encoder->base.name); 1293 return false; 1294 } 1295 1296 if (drm_dp_128b132b_eq_interlane_align_done(link_status)) { 1297 drm_dbg_kms(&i915->drm, 1298 "[ENCODER:%d:%s] Interlane align done\n", 1299 encoder->base.base.id, encoder->base.name); 1300 break; 1301 } 1302 1303 if (timeout) { 1304 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1305 drm_err(&i915->drm, 1306 "[ENCODER:%d:%s] Interlane align timeout\n", 1307 encoder->base.base.id, encoder->base.name); 1308 return false; 1309 } 1310 1311 usleep_range(2000, 3000); 1312 } 1313 1314 return true; 1315 } 1316 1317 /* 1318 * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2) 1319 */ 1320 static bool 1321 intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp, 1322 const struct intel_crtc_state *crtc_state, 1323 int lttpr_count) 1324 { 1325 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1326 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1327 u8 link_status[DP_LINK_STATUS_SIZE]; 1328 unsigned long deadline; 1329 1330 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 1331 DP_TRAINING_PATTERN_2_CDS) != 1) { 1332 drm_err(&i915->drm, 1333 "[ENCODER:%d:%s] Failed to start 128b/132b TPS2 CDS\n", 1334 encoder->base.base.id, encoder->base.name); 1335 return false; 1336 } 1337 1338 /* Time budget for the LANEx_CDS_DONE Sequence */ 1339 deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20); 1340 1341 for (;;) { 1342 bool timeout = false; 1343 1344 if (time_after(jiffies, deadline)) 1345 timeout = true; /* try one last time after deadline */ 1346 1347 usleep_range(2000, 3000); 1348 1349 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1350 drm_err(&i915->drm, 1351 "[ENCODER:%d:%s] Failed to read link status\n", 1352 encoder->base.base.id, encoder->base.name); 1353 return false; 1354 } 1355 1356 if (drm_dp_128b132b_eq_interlane_align_done(link_status) && 1357 drm_dp_128b132b_cds_interlane_align_done(link_status) && 1358 drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) { 1359 drm_dbg_kms(&i915->drm, 1360 "[ENCODER:%d:%s] CDS interlane align done\n", 1361 encoder->base.base.id, encoder->base.name); 1362 break; 1363 } 1364 1365 if (drm_dp_128b132b_link_training_failed(link_status)) { 1366 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1367 drm_err(&i915->drm, 1368 "[ENCODER:%d:%s] Downstream link training failure\n", 1369 encoder->base.base.id, encoder->base.name); 1370 return false; 1371 } 1372 1373 if (timeout) { 1374 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1375 drm_err(&i915->drm, 1376 "[ENCODER:%d:%s] CDS timeout\n", 1377 encoder->base.base.id, encoder->base.name); 1378 return false; 1379 } 1380 } 1381 1382 /* FIXME: Should DP_TRAINING_PATTERN_DISABLE be written first? */ 1383 if (intel_dp->set_idle_link_train) 1384 intel_dp->set_idle_link_train(intel_dp, crtc_state); 1385 1386 return true; 1387 } 1388 1389 /* 1390 * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.) 1391 */ 1392 static bool 1393 intel_dp_128b132b_link_train(struct intel_dp *intel_dp, 1394 const struct intel_crtc_state *crtc_state, 1395 int lttpr_count) 1396 { 1397 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1398 struct intel_connector *connector = intel_dp->attached_connector; 1399 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1400 bool passed = false; 1401 1402 if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1403 drm_err(&i915->drm, 1404 "[ENCODER:%d:%s] 128b/132b intra-hop not clear\n", 1405 encoder->base.base.id, encoder->base.name); 1406 return false; 1407 } 1408 1409 if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) && 1410 intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count)) 1411 passed = true; 1412 1413 drm_dbg_kms(&i915->drm, 1414 "[CONNECTOR:%d:%s][ENCODER:%d:%s] 128b/132b Link Training %s at link rate = %d, lane count = %d\n", 1415 connector->base.base.id, connector->base.name, 1416 encoder->base.base.id, encoder->base.name, 1417 passed ? "passed" : "failed", 1418 crtc_state->port_clock, crtc_state->lane_count); 1419 1420 return passed; 1421 } 1422 1423 /** 1424 * intel_dp_start_link_train - start link training 1425 * @intel_dp: DP struct 1426 * @crtc_state: state for CRTC attached to the encoder 1427 * 1428 * Start the link training of the @intel_dp port, scheduling a fallback 1429 * retraining with reduced link rate/lane parameters if the link training 1430 * fails. 1431 * After calling this function intel_dp_stop_link_train() must be called. 1432 */ 1433 void intel_dp_start_link_train(struct intel_dp *intel_dp, 1434 const struct intel_crtc_state *crtc_state) 1435 { 1436 bool passed; 1437 /* 1438 * TODO: Reiniting LTTPRs here won't be needed once proper connector 1439 * HW state readout is added. 1440 */ 1441 int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); 1442 1443 if (lttpr_count < 0) 1444 /* Still continue with enabling the port and link training. */ 1445 lttpr_count = 0; 1446 1447 intel_dp_prepare_link_train(intel_dp, crtc_state); 1448 1449 if (intel_dp_is_uhbr(crtc_state)) 1450 passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count); 1451 else 1452 passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); 1453 1454 if (!passed) 1455 intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); 1456 } 1457