1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "intel_display_types.h" 25 #include "intel_dp.h" 26 #include "intel_dp_link_training.h" 27 28 static void 29 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE]) 30 { 31 32 DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x", 33 link_status[0], link_status[1], link_status[2], 34 link_status[3], link_status[4], link_status[5]); 35 } 36 37 static u8 dp_voltage_max(u8 preemph) 38 { 39 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 40 case DP_TRAIN_PRE_EMPH_LEVEL_0: 41 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 42 case DP_TRAIN_PRE_EMPH_LEVEL_1: 43 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 44 case DP_TRAIN_PRE_EMPH_LEVEL_2: 45 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 46 case DP_TRAIN_PRE_EMPH_LEVEL_3: 47 default: 48 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 49 } 50 } 51 52 void intel_dp_get_adjust_train(struct intel_dp *intel_dp, 53 const u8 link_status[DP_LINK_STATUS_SIZE]) 54 { 55 u8 v = 0; 56 u8 p = 0; 57 int lane; 58 u8 voltage_max; 59 u8 preemph_max; 60 61 for (lane = 0; lane < intel_dp->lane_count; lane++) { 62 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 63 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 64 } 65 66 preemph_max = intel_dp->preemph_max(intel_dp); 67 if (p >= preemph_max) 68 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 69 70 v = min(v, dp_voltage_max(p)); 71 72 voltage_max = intel_dp->voltage_max(intel_dp); 73 if (v >= voltage_max) 74 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 75 76 for (lane = 0; lane < 4; lane++) 77 intel_dp->train_set[lane] = v | p; 78 } 79 80 static bool 81 intel_dp_set_link_train(struct intel_dp *intel_dp, 82 u8 dp_train_pat) 83 { 84 u8 buf[sizeof(intel_dp->train_set) + 1]; 85 int ret, len; 86 87 intel_dp_program_link_training_pattern(intel_dp, dp_train_pat); 88 89 buf[0] = dp_train_pat; 90 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 91 DP_TRAINING_PATTERN_DISABLE) { 92 /* don't write DP_TRAINING_LANEx_SET on disable */ 93 len = 1; 94 } else { 95 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 96 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 97 len = intel_dp->lane_count + 1; 98 } 99 100 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 101 buf, len); 102 103 return ret == len; 104 } 105 106 static bool 107 intel_dp_reset_link_train(struct intel_dp *intel_dp, 108 u8 dp_train_pat) 109 { 110 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 111 intel_dp_set_signal_levels(intel_dp); 112 return intel_dp_set_link_train(intel_dp, dp_train_pat); 113 } 114 115 static bool 116 intel_dp_update_link_train(struct intel_dp *intel_dp) 117 { 118 int ret; 119 120 intel_dp_set_signal_levels(intel_dp); 121 122 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 123 intel_dp->train_set, intel_dp->lane_count); 124 125 return ret == intel_dp->lane_count; 126 } 127 128 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp) 129 { 130 int lane; 131 132 for (lane = 0; lane < intel_dp->lane_count; lane++) 133 if ((intel_dp->train_set[lane] & 134 DP_TRAIN_MAX_SWING_REACHED) == 0) 135 return false; 136 137 return true; 138 } 139 140 /* Enable corresponding port and start training pattern 1 */ 141 static bool 142 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) 143 { 144 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 145 u8 voltage; 146 int voltage_tries, cr_tries, max_cr_tries; 147 bool max_vswing_reached = false; 148 u8 link_config[2]; 149 u8 link_bw, rate_select; 150 151 if (intel_dp->prepare_link_retrain) 152 intel_dp->prepare_link_retrain(intel_dp); 153 154 intel_dp_compute_rate(intel_dp, intel_dp->link_rate, 155 &link_bw, &rate_select); 156 157 if (link_bw) 158 drm_dbg_kms(&i915->drm, 159 "Using LINK_BW_SET value %02x\n", link_bw); 160 else 161 drm_dbg_kms(&i915->drm, 162 "Using LINK_RATE_SET value %02x\n", rate_select); 163 164 /* Write the link configuration data */ 165 link_config[0] = link_bw; 166 link_config[1] = intel_dp->lane_count; 167 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 168 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 169 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 170 171 /* eDP 1.4 rate select method. */ 172 if (!link_bw) 173 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, 174 &rate_select, 1); 175 176 link_config[0] = 0; 177 link_config[1] = DP_SET_ANSI_8B10B; 178 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 179 180 intel_dp->DP |= DP_PORT_EN; 181 182 /* clock recovery */ 183 if (!intel_dp_reset_link_train(intel_dp, 184 DP_TRAINING_PATTERN_1 | 185 DP_LINK_SCRAMBLING_DISABLE)) { 186 drm_err(&i915->drm, "failed to enable link training\n"); 187 return false; 188 } 189 190 /* 191 * The DP 1.4 spec defines the max clock recovery retries value 192 * as 10 but for pre-DP 1.4 devices we set a very tolerant 193 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 194 * x 5 identical voltage retries). Since the previous specs didn't 195 * define a limit and created the possibility of an infinite loop 196 * we want to prevent any sync from triggering that corner case. 197 */ 198 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 199 max_cr_tries = 10; 200 else 201 max_cr_tries = 80; 202 203 voltage_tries = 1; 204 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 205 u8 link_status[DP_LINK_STATUS_SIZE]; 206 207 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 208 209 if (!intel_dp_get_link_status(intel_dp, link_status)) { 210 drm_err(&i915->drm, "failed to get link status\n"); 211 return false; 212 } 213 214 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 215 drm_dbg_kms(&i915->drm, "clock recovery OK\n"); 216 return true; 217 } 218 219 if (voltage_tries == 5) { 220 drm_dbg_kms(&i915->drm, 221 "Same voltage tried 5 times\n"); 222 return false; 223 } 224 225 if (max_vswing_reached) { 226 drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); 227 return false; 228 } 229 230 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 231 232 /* Update training set as requested by target */ 233 intel_dp_get_adjust_train(intel_dp, link_status); 234 if (!intel_dp_update_link_train(intel_dp)) { 235 drm_err(&i915->drm, 236 "failed to update link training\n"); 237 return false; 238 } 239 240 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == 241 voltage) 242 ++voltage_tries; 243 else 244 voltage_tries = 1; 245 246 if (intel_dp_link_max_vswing_reached(intel_dp)) 247 max_vswing_reached = true; 248 249 } 250 drm_err(&i915->drm, 251 "Failed clock recovery %d times, giving up!\n", max_cr_tries); 252 return false; 253 } 254 255 /* 256 * Pick training pattern for channel equalization. Training pattern 4 for HBR3 257 * or for 1.4 devices that support it, training Pattern 3 for HBR2 258 * or 1.2 devices that support it, Training Pattern 2 otherwise. 259 */ 260 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) 261 { 262 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 263 264 /* 265 * Intel platforms that support HBR3 also support TPS4. It is mandatory 266 * for all downstream devices that support HBR3. There are no known eDP 267 * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 268 * specification. 269 */ 270 source_tps4 = intel_dp_source_supports_hbr3(intel_dp); 271 sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd); 272 if (source_tps4 && sink_tps4) { 273 return DP_TRAINING_PATTERN_4; 274 } else if (intel_dp->link_rate == 810000) { 275 if (!source_tps4) 276 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 277 "8.1 Gbps link rate without source HBR3/TPS4 support\n"); 278 if (!sink_tps4) 279 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 280 "8.1 Gbps link rate without sink TPS4 support\n"); 281 } 282 /* 283 * Intel platforms that support HBR2 also support TPS3. TPS3 support is 284 * also mandatory for downstream devices that support HBR2. However, not 285 * all sinks follow the spec. 286 */ 287 source_tps3 = intel_dp_source_supports_hbr2(intel_dp); 288 sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd); 289 if (source_tps3 && sink_tps3) { 290 return DP_TRAINING_PATTERN_3; 291 } else if (intel_dp->link_rate >= 540000) { 292 if (!source_tps3) 293 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 294 ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); 295 if (!sink_tps3) 296 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 297 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 298 } 299 300 return DP_TRAINING_PATTERN_2; 301 } 302 303 static bool 304 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) 305 { 306 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 307 int tries; 308 u32 training_pattern; 309 u8 link_status[DP_LINK_STATUS_SIZE]; 310 bool channel_eq = false; 311 312 training_pattern = intel_dp_training_pattern(intel_dp); 313 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 314 if (training_pattern != DP_TRAINING_PATTERN_4) 315 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 316 317 /* channel equalization */ 318 if (!intel_dp_set_link_train(intel_dp, 319 training_pattern)) { 320 drm_err(&i915->drm, "failed to start channel equalization\n"); 321 return false; 322 } 323 324 for (tries = 0; tries < 5; tries++) { 325 326 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 327 if (!intel_dp_get_link_status(intel_dp, link_status)) { 328 drm_err(&i915->drm, 329 "failed to get link status\n"); 330 break; 331 } 332 333 /* Make sure clock is still ok */ 334 if (!drm_dp_clock_recovery_ok(link_status, 335 intel_dp->lane_count)) { 336 intel_dp_dump_link_status(link_status); 337 drm_dbg_kms(&i915->drm, 338 "Clock recovery check failed, cannot " 339 "continue channel equalization\n"); 340 break; 341 } 342 343 if (drm_dp_channel_eq_ok(link_status, 344 intel_dp->lane_count)) { 345 channel_eq = true; 346 drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training " 347 "successful\n"); 348 break; 349 } 350 351 /* Update training set as requested by target */ 352 intel_dp_get_adjust_train(intel_dp, link_status); 353 if (!intel_dp_update_link_train(intel_dp)) { 354 drm_err(&i915->drm, 355 "failed to update link training\n"); 356 break; 357 } 358 } 359 360 /* Try 5 times, else fail and try at lower BW */ 361 if (tries == 5) { 362 intel_dp_dump_link_status(link_status); 363 drm_dbg_kms(&i915->drm, 364 "Channel equalization failed 5 times\n"); 365 } 366 367 intel_dp_set_idle_link_train(intel_dp); 368 369 return channel_eq; 370 371 } 372 373 void intel_dp_stop_link_train(struct intel_dp *intel_dp) 374 { 375 intel_dp->link_trained = true; 376 377 intel_dp_set_link_train(intel_dp, 378 DP_TRAINING_PATTERN_DISABLE); 379 } 380 381 void 382 intel_dp_start_link_train(struct intel_dp *intel_dp) 383 { 384 struct intel_connector *intel_connector = intel_dp->attached_connector; 385 386 if (!intel_dp_link_training_clock_recovery(intel_dp)) 387 goto failure_handling; 388 if (!intel_dp_link_training_channel_equalization(intel_dp)) 389 goto failure_handling; 390 391 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 392 "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d", 393 intel_connector->base.base.id, 394 intel_connector->base.name, 395 intel_dp->link_rate, intel_dp->lane_count); 396 return; 397 398 failure_handling: 399 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 400 "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", 401 intel_connector->base.base.id, 402 intel_connector->base.name, 403 intel_dp->link_rate, intel_dp->lane_count); 404 if (!intel_dp_get_link_train_fallback_values(intel_dp, 405 intel_dp->link_rate, 406 intel_dp->lane_count)) 407 /* Schedule a Hotplug Uevent to userspace to start modeset */ 408 schedule_work(&intel_connector->modeset_retry_work); 409 return; 410 } 411