1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 26 #include <drm/display/drm_dp_helper.h> 27 #include <drm/drm_print.h> 28 29 #include "i915_utils.h" 30 #include "intel_display_core.h" 31 #include "intel_display_types.h" 32 #include "intel_dp.h" 33 #include "intel_dp_link_training.h" 34 #include "intel_encoder.h" 35 #include "intel_hotplug.h" 36 #include "intel_panel.h" 37 38 #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " 39 #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \ 40 (_intel_dp)->attached_connector->base.name, \ 41 dp_to_dig_port(_intel_dp)->base.base.base.id, \ 42 dp_to_dig_port(_intel_dp)->base.base.name, \ 43 drm_dp_phy_name(_dp_phy) 44 45 #define lt_dbg(_intel_dp, _dp_phy, _format, ...) \ 46 drm_dbg_kms(to_intel_display(_intel_dp)->drm, \ 47 LT_MSG_PREFIX _format, \ 48 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__) 49 50 #define lt_err(_intel_dp, _dp_phy, _format, ...) do { \ 51 if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \ 52 drm_err(to_intel_display(_intel_dp)->drm, \ 53 LT_MSG_PREFIX _format, \ 54 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \ 55 else \ 56 lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \ 57 } while (0) 58 59 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) 60 { 61 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); 62 } 63 64 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 65 { 66 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 67 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 68 } 69 70 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 71 enum drm_dp_phy dp_phy) 72 { 73 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 74 } 75 76 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 77 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 78 enum drm_dp_phy dp_phy) 79 { 80 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 81 82 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { 83 lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n"); 84 return; 85 } 86 87 lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n", 88 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 89 phy_caps); 90 } 91 92 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, 93 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 94 { 95 int ret; 96 97 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, 98 intel_dp->lttpr_common_caps); 99 if (ret < 0) 100 goto reset_caps; 101 102 lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n", 103 (int)sizeof(intel_dp->lttpr_common_caps), 104 intel_dp->lttpr_common_caps); 105 106 /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ 107 if (intel_dp->lttpr_common_caps[0] < 0x14) 108 goto reset_caps; 109 110 return true; 111 112 reset_caps: 113 intel_dp_reset_lttpr_common_caps(intel_dp); 114 return false; 115 } 116 117 static bool 118 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 119 { 120 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 121 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 122 123 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 124 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val; 125 126 return true; 127 } 128 129 bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp) 130 { 131 return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 132 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] == 133 DP_PHY_REPEATER_MODE_TRANSPARENT; 134 } 135 136 /* 137 * Read the LTTPR common capabilities and switch the LTTPR PHYs to 138 * non-transparent mode if this is supported. Preserve the 139 * transparent/non-transparent mode on an active link. 140 * 141 * Return the number of detected LTTPRs in non-transparent mode or 0 if the 142 * LTTPRs are in transparent mode or the detection failed. 143 */ 144 static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 145 { 146 int lttpr_count; 147 int ret; 148 149 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) 150 return 0; 151 152 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 153 /* 154 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are 155 * detected as this breaks link training at least on the Dell WD19TB 156 * dock. 157 */ 158 if (lttpr_count == 0) 159 return 0; 160 161 /* 162 * Don't change the mode on an active link, to prevent a loss of link 163 * synchronization. See DP Standard v2.0 3.6.7. about the LTTPR 164 * resetting its internal state when the mode is changed from 165 * non-transparent to transparent. 166 */ 167 if (intel_dp->link_trained) { 168 if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp)) 169 goto out_reset_lttpr_count; 170 171 return lttpr_count; 172 } 173 174 ret = drm_dp_lttpr_init(&intel_dp->aux, lttpr_count); 175 if (ret) { 176 lt_dbg(intel_dp, DP_PHY_DPRX, 177 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); 178 179 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 180 181 goto out_reset_lttpr_count; 182 } 183 184 intel_dp_set_lttpr_transparent_mode(intel_dp, false); 185 186 return lttpr_count; 187 188 out_reset_lttpr_count: 189 intel_dp_reset_lttpr_count(intel_dp); 190 191 return 0; 192 } 193 194 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 195 { 196 int lttpr_count; 197 int i; 198 199 lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd); 200 201 for (i = 0; i < lttpr_count; i++) { 202 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); 203 drm_dp_dump_lttpr_desc(&intel_dp->aux, DP_PHY_LTTPR(i)); 204 } 205 206 return lttpr_count; 207 } 208 209 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) 210 { 211 struct intel_display *display = to_intel_display(intel_dp); 212 213 if (intel_dp_is_edp(intel_dp)) 214 return 0; 215 216 /* 217 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 218 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 219 */ 220 if (DISPLAY_VER(display) >= 10 && !display->platform.geminilake) 221 if (drm_dp_dpcd_probe(&intel_dp->aux, 222 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV)) 223 return -EIO; 224 225 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) 226 return -EIO; 227 228 return 0; 229 } 230 231 /** 232 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode 233 * @intel_dp: Intel DP struct 234 * 235 * Read the LTTPR common and DPRX capabilities and switch to non-transparent 236 * link training mode if any is detected and read the PHY capabilities for all 237 * detected LTTPRs. In case of an LTTPR detection error or if the number of 238 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 239 * transparent mode link training mode. 240 * 241 * Returns: 242 * >0 if LTTPRs were detected and the non-transparent LT mode was set. The 243 * DPRX capabilities are read out. 244 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 245 * detection failure and the transparent LT mode was set. The DPRX 246 * capabilities are read out. 247 * <0 Reading out the DPRX capabilities failed. 248 */ 249 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) 250 { 251 struct intel_display *display = to_intel_display(intel_dp); 252 int lttpr_count = 0; 253 254 /* 255 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 256 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 257 */ 258 if (!intel_dp_is_edp(intel_dp) && 259 (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)) { 260 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 261 int err = intel_dp_read_dprx_caps(intel_dp, dpcd); 262 263 if (err != 0) 264 return err; 265 266 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); 267 } 268 269 /* 270 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read 271 * it here. 272 */ 273 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { 274 intel_dp_reset_lttpr_common_caps(intel_dp); 275 return -EIO; 276 } 277 278 return lttpr_count; 279 } 280 281 static u8 dp_voltage_max(u8 preemph) 282 { 283 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 284 case DP_TRAIN_PRE_EMPH_LEVEL_0: 285 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 286 case DP_TRAIN_PRE_EMPH_LEVEL_1: 287 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 288 case DP_TRAIN_PRE_EMPH_LEVEL_2: 289 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 290 case DP_TRAIN_PRE_EMPH_LEVEL_3: 291 default: 292 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 293 } 294 } 295 296 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 297 enum drm_dp_phy dp_phy) 298 { 299 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 300 301 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 302 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 303 else 304 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 305 } 306 307 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 308 enum drm_dp_phy dp_phy) 309 { 310 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 311 312 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 313 return DP_TRAIN_PRE_EMPH_LEVEL_3; 314 else 315 return DP_TRAIN_PRE_EMPH_LEVEL_2; 316 } 317 318 static bool 319 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 320 enum drm_dp_phy dp_phy) 321 { 322 struct intel_display *display = to_intel_display(intel_dp); 323 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 324 325 drm_WARN_ON_ONCE(display->drm, 326 lttpr_count <= 0 && dp_phy != DP_PHY_DPRX); 327 328 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 329 } 330 331 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 332 const struct intel_crtc_state *crtc_state, 333 enum drm_dp_phy dp_phy) 334 { 335 struct intel_display *display = to_intel_display(intel_dp); 336 u8 voltage_max; 337 338 /* 339 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 340 * the DPRX_PHY we train. 341 */ 342 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 343 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 344 else 345 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 346 347 drm_WARN_ON_ONCE(display->drm, 348 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 349 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 350 351 return voltage_max; 352 } 353 354 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 355 enum drm_dp_phy dp_phy) 356 { 357 struct intel_display *display = to_intel_display(intel_dp); 358 u8 preemph_max; 359 360 /* 361 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 362 * the DPRX_PHY we train. 363 */ 364 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 365 preemph_max = intel_dp->preemph_max(intel_dp); 366 else 367 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 368 369 drm_WARN_ON_ONCE(display->drm, 370 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 371 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 372 373 return preemph_max; 374 } 375 376 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, 377 enum drm_dp_phy dp_phy) 378 { 379 struct intel_display *display = to_intel_display(intel_dp); 380 381 return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) || 382 DISPLAY_VER(display) >= 10 || display->platform.broxton; 383 } 384 385 /* 128b/132b */ 386 static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp, 387 const struct intel_crtc_state *crtc_state, 388 enum drm_dp_phy dp_phy, 389 const u8 link_status[DP_LINK_STATUS_SIZE], 390 int lane) 391 { 392 u8 tx_ffe = 0; 393 394 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 395 lane = min(lane, crtc_state->lane_count - 1); 396 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); 397 } else { 398 for (lane = 0; lane < crtc_state->lane_count; lane++) 399 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); 400 } 401 402 return tx_ffe; 403 } 404 405 /* 8b/10b */ 406 static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp, 407 const struct intel_crtc_state *crtc_state, 408 enum drm_dp_phy dp_phy, 409 const u8 link_status[DP_LINK_STATUS_SIZE], 410 int lane) 411 { 412 u8 v = 0; 413 u8 p = 0; 414 u8 voltage_max; 415 u8 preemph_max; 416 417 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 418 lane = min(lane, crtc_state->lane_count - 1); 419 420 v = drm_dp_get_adjust_request_voltage(link_status, lane); 421 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 422 } else { 423 for (lane = 0; lane < crtc_state->lane_count; lane++) { 424 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 425 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 426 } 427 } 428 429 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 430 if (p >= preemph_max) 431 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 432 433 v = min(v, dp_voltage_max(p)); 434 435 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 436 if (v >= voltage_max) 437 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 438 439 return v | p; 440 } 441 442 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, 443 const struct intel_crtc_state *crtc_state, 444 enum drm_dp_phy dp_phy, 445 const u8 link_status[DP_LINK_STATUS_SIZE], 446 int lane) 447 { 448 if (intel_dp_is_uhbr(crtc_state)) 449 return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state, 450 dp_phy, link_status, lane); 451 else 452 return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state, 453 dp_phy, link_status, lane); 454 } 455 456 #define TRAIN_REQ_FMT "%d/%d/%d/%d" 457 #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \ 458 (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT) 459 #define TRAIN_REQ_VSWING_ARGS(link_status) \ 460 _TRAIN_REQ_VSWING_ARGS(link_status, 0), \ 461 _TRAIN_REQ_VSWING_ARGS(link_status, 1), \ 462 _TRAIN_REQ_VSWING_ARGS(link_status, 2), \ 463 _TRAIN_REQ_VSWING_ARGS(link_status, 3) 464 #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \ 465 (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT) 466 #define TRAIN_REQ_PREEMPH_ARGS(link_status) \ 467 _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \ 468 _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \ 469 _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \ 470 _TRAIN_REQ_PREEMPH_ARGS(link_status, 3) 471 #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \ 472 drm_dp_get_adjust_tx_ffe_preset((link_status), (lane)) 473 #define TRAIN_REQ_TX_FFE_ARGS(link_status) \ 474 _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \ 475 _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \ 476 _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \ 477 _TRAIN_REQ_TX_FFE_ARGS(link_status, 3) 478 479 void 480 intel_dp_get_adjust_train(struct intel_dp *intel_dp, 481 const struct intel_crtc_state *crtc_state, 482 enum drm_dp_phy dp_phy, 483 const u8 link_status[DP_LINK_STATUS_SIZE]) 484 { 485 int lane; 486 487 if (intel_dp_is_uhbr(crtc_state)) { 488 lt_dbg(intel_dp, dp_phy, 489 "128b/132b, lanes: %d, " 490 "TX FFE request: " TRAIN_REQ_FMT "\n", 491 crtc_state->lane_count, 492 TRAIN_REQ_TX_FFE_ARGS(link_status)); 493 } else { 494 lt_dbg(intel_dp, dp_phy, 495 "8b/10b, lanes: %d, " 496 "vswing request: " TRAIN_REQ_FMT ", " 497 "pre-emphasis request: " TRAIN_REQ_FMT "\n", 498 crtc_state->lane_count, 499 TRAIN_REQ_VSWING_ARGS(link_status), 500 TRAIN_REQ_PREEMPH_ARGS(link_status)); 501 } 502 503 for (lane = 0; lane < 4; lane++) 504 intel_dp->train_set[lane] = 505 intel_dp_get_lane_adjust_train(intel_dp, crtc_state, 506 dp_phy, link_status, lane); 507 } 508 509 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 510 enum drm_dp_phy dp_phy) 511 { 512 return dp_phy == DP_PHY_DPRX ? 513 DP_TRAINING_PATTERN_SET : 514 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 515 } 516 517 static bool 518 intel_dp_set_link_train(struct intel_dp *intel_dp, 519 const struct intel_crtc_state *crtc_state, 520 enum drm_dp_phy dp_phy, 521 u8 dp_train_pat) 522 { 523 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 524 u8 buf[sizeof(intel_dp->train_set) + 1]; 525 int len; 526 527 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 528 dp_phy, dp_train_pat); 529 530 buf[0] = dp_train_pat; 531 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 532 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 533 len = crtc_state->lane_count + 1; 534 535 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 536 } 537 538 static char dp_training_pattern_name(u8 train_pat) 539 { 540 switch (train_pat) { 541 case DP_TRAINING_PATTERN_1: 542 case DP_TRAINING_PATTERN_2: 543 case DP_TRAINING_PATTERN_3: 544 return '0' + train_pat; 545 case DP_TRAINING_PATTERN_4: 546 return '4'; 547 default: 548 MISSING_CASE(train_pat); 549 return '?'; 550 } 551 } 552 553 void 554 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 555 const struct intel_crtc_state *crtc_state, 556 enum drm_dp_phy dp_phy, 557 u8 dp_train_pat) 558 { 559 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat); 560 561 if (train_pat != DP_TRAINING_PATTERN_DISABLE) 562 lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n", 563 dp_training_pattern_name(train_pat)); 564 565 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); 566 } 567 568 #define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" 569 #define _TRAIN_SET_VSWING_ARGS(train_set) \ 570 ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ 571 (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" 572 #define TRAIN_SET_VSWING_ARGS(train_set) \ 573 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ 574 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ 575 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ 576 _TRAIN_SET_VSWING_ARGS((train_set)[3]) 577 #define _TRAIN_SET_PREEMPH_ARGS(train_set) \ 578 ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ 579 (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" 580 #define TRAIN_SET_PREEMPH_ARGS(train_set) \ 581 _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ 582 _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ 583 _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ 584 _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) 585 #define _TRAIN_SET_TX_FFE_ARGS(train_set) \ 586 ((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), "" 587 #define TRAIN_SET_TX_FFE_ARGS(train_set) \ 588 _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \ 589 _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \ 590 _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \ 591 _TRAIN_SET_TX_FFE_ARGS((train_set)[3]) 592 593 void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 594 const struct intel_crtc_state *crtc_state, 595 enum drm_dp_phy dp_phy) 596 { 597 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 598 599 if (intel_dp_is_uhbr(crtc_state)) { 600 lt_dbg(intel_dp, dp_phy, 601 "128b/132b, lanes: %d, " 602 "TX FFE presets: " TRAIN_SET_FMT "\n", 603 crtc_state->lane_count, 604 TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set)); 605 } else { 606 lt_dbg(intel_dp, dp_phy, 607 "8b/10b, lanes: %d, " 608 "vswing levels: " TRAIN_SET_FMT ", " 609 "pre-emphasis levels: " TRAIN_SET_FMT "\n", 610 crtc_state->lane_count, 611 TRAIN_SET_VSWING_ARGS(intel_dp->train_set), 612 TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set)); 613 } 614 615 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 616 encoder->set_signal_levels(encoder, crtc_state); 617 } 618 619 static bool 620 intel_dp_reset_link_train(struct intel_dp *intel_dp, 621 const struct intel_crtc_state *crtc_state, 622 enum drm_dp_phy dp_phy, 623 u8 dp_train_pat) 624 { 625 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 626 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 627 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 628 } 629 630 static bool 631 intel_dp_update_link_train(struct intel_dp *intel_dp, 632 const struct intel_crtc_state *crtc_state, 633 enum drm_dp_phy dp_phy) 634 { 635 int reg = dp_phy == DP_PHY_DPRX ? 636 DP_TRAINING_LANE0_SET : 637 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 638 int ret; 639 640 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 641 642 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 643 intel_dp->train_set, crtc_state->lane_count); 644 645 return ret == crtc_state->lane_count; 646 } 647 648 /* 128b/132b */ 649 static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane) 650 { 651 return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) == 652 DP_TX_FFE_PRESET_VALUE_MASK; 653 } 654 655 /* 656 * 8b/10b 657 * 658 * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to 659 * have self contradicting tests around this area. 660 * 661 * In lieu of better ideas let's just stop when we've reached the max supported 662 * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on 663 * whether vswing level 3 is supported or not. 664 */ 665 static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane) 666 { 667 u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 668 DP_TRAIN_VOLTAGE_SWING_SHIFT; 669 u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 670 DP_TRAIN_PRE_EMPHASIS_SHIFT; 671 672 if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0) 673 return false; 674 675 if (v + p != 3) 676 return false; 677 678 return true; 679 } 680 681 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 682 const struct intel_crtc_state *crtc_state) 683 { 684 int lane; 685 686 for (lane = 0; lane < crtc_state->lane_count; lane++) { 687 u8 train_set_lane = intel_dp->train_set[lane]; 688 689 if (intel_dp_is_uhbr(crtc_state)) { 690 if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane)) 691 return false; 692 } else { 693 if (!intel_dp_lane_max_vswing_reached(train_set_lane)) 694 return false; 695 } 696 } 697 698 return true; 699 } 700 701 void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr) 702 { 703 u8 link_config[2]; 704 705 link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 706 link_config[1] = drm_dp_is_uhbr_rate(link_rate) ? 707 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; 708 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 709 } 710 711 static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, 712 const struct intel_crtc_state *crtc_state) 713 { 714 intel_dp_link_training_set_mode(intel_dp, 715 crtc_state->port_clock, crtc_state->vrr.flipline); 716 } 717 718 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, 719 int link_bw, int rate_select, int lane_count, 720 bool enhanced_framing) 721 { 722 if (enhanced_framing) 723 lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 724 725 if (link_bw) { 726 /* DP and eDP v1.3 and earlier link bw set method. */ 727 u8 link_config[] = { link_bw, lane_count }; 728 729 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 730 ARRAY_SIZE(link_config)); 731 } else { 732 /* 733 * eDP v1.4 and later link rate set method. 734 * 735 * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if 736 * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET. 737 * 738 * eDP v1.5 sinks allow choosing either, and the last choice 739 * shall be active. 740 */ 741 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count); 742 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select); 743 } 744 } 745 746 static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp, 747 const struct intel_crtc_state *crtc_state, 748 u8 link_bw, u8 rate_select) 749 { 750 intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count, 751 crtc_state->enhanced_framing); 752 } 753 754 /* 755 * Prepare link training by configuring the link parameters. On DDI platforms 756 * also enable the port here. 757 */ 758 static bool 759 intel_dp_prepare_link_train(struct intel_dp *intel_dp, 760 const struct intel_crtc_state *crtc_state) 761 { 762 u8 link_bw, rate_select; 763 764 if (intel_dp->prepare_link_retrain) 765 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 766 767 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 768 &link_bw, &rate_select); 769 770 /* 771 * WaEdpLinkRateDataReload 772 * 773 * Parade PS8461E MUX (used on various TGL+ laptops) needs 774 * to snoop the link rates reported by the sink when we 775 * use LINK_RATE_SET in order to operate in jitter cleaning 776 * mode (as opposed to redriver mode). Unfortunately it 777 * loses track of the snooped link rates when powered down, 778 * so we need to make it re-snoop often. Without this high 779 * link rates are not stable. 780 */ 781 if (!link_bw) { 782 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 783 784 lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n"); 785 786 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 787 sink_rates, sizeof(sink_rates)); 788 } 789 790 if (link_bw) 791 lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n", 792 link_bw); 793 else 794 lt_dbg(intel_dp, DP_PHY_DPRX, 795 "Using LINK_RATE_SET value %02x\n", 796 rate_select); 797 /* 798 * Spec DP2.1 Section 3.5.2.16 799 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate 800 */ 801 intel_dp_update_downspread_ctrl(intel_dp, crtc_state); 802 intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw, 803 rate_select); 804 805 return true; 806 } 807 808 static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state, 809 const u8 old_link_status[DP_LINK_STATUS_SIZE], 810 const u8 new_link_status[DP_LINK_STATUS_SIZE]) 811 { 812 int lane; 813 814 for (lane = 0; lane < crtc_state->lane_count; lane++) { 815 u8 old, new; 816 817 if (intel_dp_is_uhbr(crtc_state)) { 818 old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane); 819 new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane); 820 } else { 821 old = drm_dp_get_adjust_request_voltage(old_link_status, lane) | 822 drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane); 823 new = drm_dp_get_adjust_request_voltage(new_link_status, lane) | 824 drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane); 825 } 826 827 if (old != new) 828 return true; 829 } 830 831 return false; 832 } 833 834 void 835 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy, 836 const u8 link_status[DP_LINK_STATUS_SIZE]) 837 { 838 lt_dbg(intel_dp, dp_phy, 839 "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n", 840 link_status[0], link_status[1], link_status[2], 841 link_status[3], link_status[4], link_status[5]); 842 } 843 844 /* 845 * Perform the link training clock recovery phase on the given DP PHY using 846 * training pattern 1. 847 */ 848 static bool 849 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 850 const struct intel_crtc_state *crtc_state, 851 enum drm_dp_phy dp_phy) 852 { 853 u8 old_link_status[DP_LINK_STATUS_SIZE] = {}; 854 int voltage_tries, cr_tries, max_cr_tries; 855 u8 link_status[DP_LINK_STATUS_SIZE]; 856 bool max_vswing_reached = false; 857 int delay_us; 858 859 delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux, 860 intel_dp->dpcd, dp_phy, 861 intel_dp_is_uhbr(crtc_state)); 862 863 /* clock recovery */ 864 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 865 DP_TRAINING_PATTERN_1 | 866 DP_LINK_SCRAMBLING_DISABLE)) { 867 lt_err(intel_dp, dp_phy, "Failed to enable link training\n"); 868 return false; 869 } 870 871 /* 872 * The DP 1.4 spec defines the max clock recovery retries value 873 * as 10 but for pre-DP 1.4 devices we set a very tolerant 874 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 875 * x 5 identical voltage retries). Since the previous specs didn't 876 * define a limit and created the possibility of an infinite loop 877 * we want to prevent any sync from triggering that corner case. 878 */ 879 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 880 max_cr_tries = 10; 881 else 882 max_cr_tries = 80; 883 884 voltage_tries = 1; 885 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 886 fsleep(delay_us); 887 888 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 889 link_status) < 0) { 890 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 891 return false; 892 } 893 894 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 895 lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n"); 896 return true; 897 } 898 899 if (voltage_tries == 5) { 900 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 901 lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n"); 902 return false; 903 } 904 905 if (max_vswing_reached) { 906 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 907 lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n"); 908 return false; 909 } 910 911 /* Update training set as requested by target */ 912 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 913 link_status); 914 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 915 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 916 return false; 917 } 918 919 if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status)) 920 ++voltage_tries; 921 else 922 voltage_tries = 1; 923 924 memcpy(old_link_status, link_status, sizeof(link_status)); 925 926 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 927 max_vswing_reached = true; 928 } 929 930 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 931 lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n", 932 max_cr_tries); 933 934 return false; 935 } 936 937 /* 938 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 939 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or 940 * 1.2 devices that support it, TPS2 otherwise. 941 */ 942 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 943 const struct intel_crtc_state *crtc_state, 944 enum drm_dp_phy dp_phy) 945 { 946 struct intel_display *display = to_intel_display(intel_dp); 947 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 948 949 /* UHBR+ use separate 128b/132b TPS2 */ 950 if (intel_dp_is_uhbr(crtc_state)) 951 return DP_TRAINING_PATTERN_2; 952 953 /* 954 * TPS4 support is mandatory for all downstream devices that 955 * support HBR3. There are no known eDP panels that support 956 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification. 957 * LTTPRs must support TPS4. 958 */ 959 source_tps4 = intel_dp_source_supports_tps4(display); 960 sink_tps4 = dp_phy != DP_PHY_DPRX || 961 drm_dp_tps4_supported(intel_dp->dpcd); 962 if (source_tps4 && sink_tps4) { 963 return DP_TRAINING_PATTERN_4; 964 } else if (crtc_state->port_clock == 810000) { 965 if (!source_tps4) 966 lt_dbg(intel_dp, dp_phy, 967 "8.1 Gbps link rate without source TPS4 support\n"); 968 if (!sink_tps4) 969 lt_dbg(intel_dp, dp_phy, 970 "8.1 Gbps link rate without sink TPS4 support\n"); 971 } 972 973 /* 974 * TPS3 support is mandatory for downstream devices that 975 * support HBR2. However, not all sinks follow the spec. 976 */ 977 source_tps3 = intel_dp_source_supports_tps3(display); 978 sink_tps3 = dp_phy != DP_PHY_DPRX || 979 drm_dp_tps3_supported(intel_dp->dpcd); 980 if (source_tps3 && sink_tps3) { 981 return DP_TRAINING_PATTERN_3; 982 } else if (crtc_state->port_clock >= 540000) { 983 if (!source_tps3) 984 lt_dbg(intel_dp, dp_phy, 985 ">=5.4/6.48 Gbps link rate without source TPS3 support\n"); 986 if (!sink_tps3) 987 lt_dbg(intel_dp, dp_phy, 988 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 989 } 990 991 return DP_TRAINING_PATTERN_2; 992 } 993 994 /* 995 * Perform the link training channel equalization phase on the given DP PHY 996 * using one of training pattern 2, 3 or 4 depending on the source and 997 * sink capabilities. 998 */ 999 static bool 1000 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 1001 const struct intel_crtc_state *crtc_state, 1002 enum drm_dp_phy dp_phy) 1003 { 1004 int tries; 1005 u32 training_pattern; 1006 u8 link_status[DP_LINK_STATUS_SIZE]; 1007 bool channel_eq = false; 1008 int delay_us; 1009 1010 delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux, 1011 intel_dp->dpcd, dp_phy, 1012 intel_dp_is_uhbr(crtc_state)); 1013 1014 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 1015 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 1016 if (training_pattern != DP_TRAINING_PATTERN_4) 1017 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 1018 1019 /* channel equalization */ 1020 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 1021 training_pattern)) { 1022 lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n"); 1023 return false; 1024 } 1025 1026 for (tries = 0; tries < 5; tries++) { 1027 fsleep(delay_us); 1028 1029 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 1030 link_status) < 0) { 1031 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 1032 break; 1033 } 1034 1035 /* Make sure clock is still ok */ 1036 if (!drm_dp_clock_recovery_ok(link_status, 1037 crtc_state->lane_count)) { 1038 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1039 lt_dbg(intel_dp, dp_phy, 1040 "Clock recovery check failed, cannot continue channel equalization\n"); 1041 break; 1042 } 1043 1044 if (drm_dp_channel_eq_ok(link_status, 1045 crtc_state->lane_count)) { 1046 channel_eq = true; 1047 lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n"); 1048 break; 1049 } 1050 1051 /* Update training set as requested by target */ 1052 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 1053 link_status); 1054 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 1055 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 1056 break; 1057 } 1058 } 1059 1060 /* Try 5 times, else fail and try at lower BW */ 1061 if (tries == 5) { 1062 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1063 lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n"); 1064 } 1065 1066 return channel_eq; 1067 } 1068 1069 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 1070 enum drm_dp_phy dp_phy) 1071 { 1072 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 1073 u8 val = DP_TRAINING_PATTERN_DISABLE; 1074 1075 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 1076 } 1077 1078 static int 1079 intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp, 1080 const struct intel_crtc_state *crtc_state) 1081 { 1082 u8 sink_status; 1083 int ret; 1084 1085 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status); 1086 if (ret != 1) { 1087 lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n"); 1088 return ret < 0 ? ret : -EIO; 1089 } 1090 1091 return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0; 1092 } 1093 1094 /** 1095 * intel_dp_stop_link_train - stop link training 1096 * @intel_dp: DP struct 1097 * @crtc_state: state for CRTC attached to the encoder 1098 * 1099 * Stop the link training of the @intel_dp port, disabling the training 1100 * pattern in the sink's DPCD, and disabling the test pattern symbol 1101 * generation on the port. 1102 * 1103 * What symbols are output on the port after this point is 1104 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 1105 * with the pipe being disabled, on older platforms it's HW specific if/how an 1106 * idle pattern is generated, as the pipe is already enabled here for those. 1107 * 1108 * This function must be called after intel_dp_start_link_train(). 1109 */ 1110 void intel_dp_stop_link_train(struct intel_dp *intel_dp, 1111 const struct intel_crtc_state *crtc_state) 1112 { 1113 intel_dp->link_trained = true; 1114 1115 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 1116 intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX, 1117 DP_TRAINING_PATTERN_DISABLE); 1118 1119 if (intel_dp_is_uhbr(crtc_state) && 1120 wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1121 lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n"); 1122 } 1123 } 1124 1125 static bool 1126 intel_dp_link_train_phy(struct intel_dp *intel_dp, 1127 const struct intel_crtc_state *crtc_state, 1128 enum drm_dp_phy dp_phy) 1129 { 1130 bool ret = false; 1131 1132 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 1133 goto out; 1134 1135 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 1136 goto out; 1137 1138 ret = true; 1139 1140 out: 1141 lt_dbg(intel_dp, dp_phy, 1142 "Link Training %s at link rate = %d, lane count = %d\n", 1143 ret ? "passed" : "failed", 1144 crtc_state->port_clock, crtc_state->lane_count); 1145 1146 return ret; 1147 } 1148 1149 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, 1150 int link_rate, 1151 u8 lane_count) 1152 { 1153 /* FIXME figure out what we actually want here */ 1154 const struct drm_display_mode *fixed_mode = 1155 intel_panel_preferred_fixed_mode(intel_dp->attached_connector); 1156 int mode_rate, max_rate; 1157 1158 mode_rate = intel_dp_link_required(fixed_mode->clock, 18); 1159 max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); 1160 if (mode_rate > max_rate) 1161 return false; 1162 1163 return true; 1164 } 1165 1166 static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp, 1167 const struct intel_crtc_state *crtc_state, 1168 int *new_link_rate, int *new_lane_count) 1169 { 1170 int link_rate; 1171 int lane_count; 1172 int i; 1173 1174 i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 1175 for (i--; i >= 0; i--) { 1176 intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count); 1177 1178 if ((intel_dp->link.force_rate && 1179 intel_dp->link.force_rate != link_rate) || 1180 (intel_dp->link.force_lane_count && 1181 intel_dp->link.force_lane_count != lane_count)) 1182 continue; 1183 1184 break; 1185 } 1186 1187 if (i < 0) 1188 return false; 1189 1190 *new_link_rate = link_rate; 1191 *new_lane_count = lane_count; 1192 1193 return true; 1194 } 1195 1196 static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) 1197 { 1198 int rate_index; 1199 int new_rate; 1200 1201 if (intel_dp->link.force_rate) 1202 return -1; 1203 1204 rate_index = intel_dp_rate_index(intel_dp->common_rates, 1205 intel_dp->num_common_rates, 1206 current_rate); 1207 1208 if (rate_index <= 0) 1209 return -1; 1210 1211 new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); 1212 1213 /* TODO: Make switching from UHBR to non-UHBR rates work. */ 1214 if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate)) 1215 return -1; 1216 1217 return new_rate; 1218 } 1219 1220 static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) 1221 { 1222 if (intel_dp->link.force_lane_count) 1223 return -1; 1224 1225 if (current_lane_count == 1) 1226 return -1; 1227 1228 return current_lane_count >> 1; 1229 } 1230 1231 static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp, 1232 const struct intel_crtc_state *crtc_state, 1233 int *new_link_rate, int *new_lane_count) 1234 { 1235 int link_rate; 1236 int lane_count; 1237 1238 lane_count = crtc_state->lane_count; 1239 link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); 1240 if (link_rate < 0) { 1241 lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); 1242 link_rate = intel_dp_max_common_rate(intel_dp); 1243 } 1244 1245 if (lane_count < 0) 1246 return false; 1247 1248 *new_link_rate = link_rate; 1249 *new_lane_count = lane_count; 1250 1251 return true; 1252 } 1253 1254 static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, 1255 int *new_link_rate, int *new_lane_count) 1256 { 1257 /* TODO: Use the same fallback logic on SST as on MST. */ 1258 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 1259 return reduce_link_params_in_bw_order(intel_dp, crtc_state, 1260 new_link_rate, new_lane_count); 1261 else 1262 return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state, 1263 new_link_rate, new_lane_count); 1264 } 1265 1266 static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 1267 const struct intel_crtc_state *crtc_state) 1268 { 1269 int new_link_rate; 1270 int new_lane_count; 1271 1272 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { 1273 lt_dbg(intel_dp, DP_PHY_DPRX, 1274 "Retrying Link training for eDP with max parameters\n"); 1275 intel_dp->use_max_params = true; 1276 return 0; 1277 } 1278 1279 if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count)) 1280 return -1; 1281 1282 if (intel_dp_is_edp(intel_dp) && 1283 !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { 1284 lt_dbg(intel_dp, DP_PHY_DPRX, 1285 "Retrying Link training for eDP with same parameters\n"); 1286 return 0; 1287 } 1288 1289 lt_dbg(intel_dp, DP_PHY_DPRX, 1290 "Reducing link parameters from %dx%d to %dx%d\n", 1291 crtc_state->lane_count, crtc_state->port_clock, 1292 new_lane_count, new_link_rate); 1293 1294 intel_dp->link.max_rate = new_link_rate; 1295 intel_dp->link.max_lane_count = new_lane_count; 1296 1297 return 0; 1298 } 1299 1300 static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, 1301 struct intel_dp *intel_dp, 1302 const struct intel_crtc_state *crtc_state) 1303 { 1304 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1305 1306 if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { 1307 lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); 1308 return true; 1309 } 1310 1311 if (intel_dp->hobl_active) { 1312 lt_dbg(intel_dp, DP_PHY_DPRX, 1313 "Link Training failed with HOBL active, not enabling it from now on\n"); 1314 intel_dp->hobl_failed = true; 1315 } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { 1316 return false; 1317 } 1318 1319 /* Schedule a Hotplug Uevent to userspace to start modeset */ 1320 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 1321 1322 return true; 1323 } 1324 1325 /* Perform the link training on all LTTPRs and the DPRX on a link. */ 1326 static bool 1327 intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 1328 const struct intel_crtc_state *crtc_state, 1329 int lttpr_count) 1330 { 1331 bool ret = true; 1332 int i; 1333 1334 for (i = lttpr_count - 1; i >= 0; i--) { 1335 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 1336 1337 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 1338 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 1339 1340 if (!ret) 1341 break; 1342 } 1343 1344 if (ret) 1345 ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 1346 1347 if (intel_dp->set_idle_link_train) 1348 intel_dp->set_idle_link_train(intel_dp, crtc_state); 1349 1350 return ret; 1351 } 1352 1353 /* 1354 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1) 1355 */ 1356 static bool 1357 intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, 1358 const struct intel_crtc_state *crtc_state) 1359 { 1360 u8 link_status[DP_LINK_STATUS_SIZE]; 1361 int delay_us; 1362 int try, max_tries = 20; 1363 unsigned long deadline; 1364 bool timeout = false; 1365 1366 /* 1367 * Reset signal levels. Start transmitting 128b/132b TPS1. 1368 * 1369 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1 1370 * in DP_TRAINING_PATTERN_SET. 1371 */ 1372 if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1373 DP_TRAINING_PATTERN_1)) { 1374 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n"); 1375 return false; 1376 } 1377 1378 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1379 1380 /* Read the initial TX FFE settings. */ 1381 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1382 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n"); 1383 return false; 1384 } 1385 1386 /* Update signal levels and training set as requested. */ 1387 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1388 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1389 lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n"); 1390 return false; 1391 } 1392 1393 /* Start transmitting 128b/132b TPS2. */ 1394 if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1395 DP_TRAINING_PATTERN_2)) { 1396 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n"); 1397 return false; 1398 } 1399 1400 /* Time budget for the LANEx_EQ_DONE Sequence */ 1401 deadline = jiffies + msecs_to_jiffies_timeout(450); 1402 1403 for (try = 0; try < max_tries; try++) { 1404 fsleep(delay_us); 1405 1406 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1407 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1408 return false; 1409 } 1410 1411 if (drm_dp_128b132b_link_training_failed(link_status)) { 1412 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1413 lt_err(intel_dp, DP_PHY_DPRX, 1414 "Downstream link training failure\n"); 1415 return false; 1416 } 1417 1418 if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) { 1419 lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n"); 1420 break; 1421 } 1422 1423 if (timeout) { 1424 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1425 lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n"); 1426 return false; 1427 } 1428 1429 if (time_after(jiffies, deadline)) 1430 timeout = true; /* try one last time after deadline */ 1431 1432 /* 1433 * During LT, Tx shall read AUX_RD_INTERVAL just before writing the new FFE 1434 * presets. 1435 */ 1436 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1437 1438 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1439 1440 /* Update signal levels and training set as requested. */ 1441 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1442 lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n"); 1443 return false; 1444 } 1445 } 1446 1447 if (try == max_tries) { 1448 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1449 lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n"); 1450 return false; 1451 } 1452 1453 for (;;) { 1454 if (time_after(jiffies, deadline)) 1455 timeout = true; /* try one last time after deadline */ 1456 1457 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1458 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1459 return false; 1460 } 1461 1462 if (drm_dp_128b132b_link_training_failed(link_status)) { 1463 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1464 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1465 return false; 1466 } 1467 1468 if (drm_dp_128b132b_eq_interlane_align_done(link_status)) { 1469 lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n"); 1470 break; 1471 } 1472 1473 if (timeout) { 1474 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1475 lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n"); 1476 return false; 1477 } 1478 1479 usleep_range(2000, 3000); 1480 } 1481 1482 return true; 1483 } 1484 1485 /* 1486 * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2) 1487 */ 1488 static bool 1489 intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp, 1490 const struct intel_crtc_state *crtc_state, 1491 int lttpr_count) 1492 { 1493 u8 link_status[DP_LINK_STATUS_SIZE]; 1494 unsigned long deadline; 1495 1496 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 1497 DP_TRAINING_PATTERN_2_CDS) != 1) { 1498 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n"); 1499 return false; 1500 } 1501 1502 /* Time budget for the LANEx_CDS_DONE Sequence */ 1503 deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20); 1504 1505 for (;;) { 1506 bool timeout = false; 1507 1508 if (time_after(jiffies, deadline)) 1509 timeout = true; /* try one last time after deadline */ 1510 1511 usleep_range(2000, 3000); 1512 1513 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1514 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1515 return false; 1516 } 1517 1518 if (drm_dp_128b132b_eq_interlane_align_done(link_status) && 1519 drm_dp_128b132b_cds_interlane_align_done(link_status) && 1520 drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) { 1521 lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n"); 1522 break; 1523 } 1524 1525 if (drm_dp_128b132b_link_training_failed(link_status)) { 1526 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1527 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1528 return false; 1529 } 1530 1531 if (timeout) { 1532 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1533 lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n"); 1534 return false; 1535 } 1536 } 1537 1538 return true; 1539 } 1540 1541 /* 1542 * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.) 1543 */ 1544 static bool 1545 intel_dp_128b132b_link_train(struct intel_dp *intel_dp, 1546 const struct intel_crtc_state *crtc_state, 1547 int lttpr_count) 1548 { 1549 bool passed = false; 1550 1551 if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1552 lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n"); 1553 goto out; 1554 } 1555 1556 if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) && 1557 intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count)) 1558 passed = true; 1559 1560 lt_dbg(intel_dp, DP_PHY_DPRX, 1561 "128b/132b Link Training %s at link rate = %d, lane count = %d\n", 1562 passed ? "passed" : "failed", 1563 crtc_state->port_clock, crtc_state->lane_count); 1564 1565 out: 1566 /* 1567 * Ensure that the training pattern does get set to TPS2 even in case 1568 * of a failure, as is the case at the end of a passing link training 1569 * and what is expected by the transcoder. Leaving TPS1 set (and 1570 * disabling the link train mode in DP_TP_CTL later from TPS1 directly) 1571 * would result in a stuck transcoder HW state and flip-done timeouts 1572 * later in the modeset sequence. 1573 */ 1574 if (!passed) 1575 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 1576 DP_PHY_DPRX, DP_TRAINING_PATTERN_2); 1577 1578 return passed; 1579 } 1580 1581 /** 1582 * intel_dp_start_link_train - start link training 1583 * @state: Atomic state 1584 * @intel_dp: DP struct 1585 * @crtc_state: state for CRTC attached to the encoder 1586 * 1587 * Start the link training of the @intel_dp port, scheduling a fallback 1588 * retraining with reduced link rate/lane parameters if the link training 1589 * fails. 1590 * After calling this function intel_dp_stop_link_train() must be called. 1591 */ 1592 void intel_dp_start_link_train(struct intel_atomic_state *state, 1593 struct intel_dp *intel_dp, 1594 const struct intel_crtc_state *crtc_state) 1595 { 1596 struct intel_display *display = to_intel_display(state); 1597 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1598 struct intel_encoder *encoder = &dig_port->base; 1599 bool passed; 1600 /* 1601 * Reinit the LTTPRs here to ensure that they are switched to 1602 * non-transparent mode. During an earlier LTTPR detection this 1603 * could've been prevented by an active link. 1604 */ 1605 int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); 1606 1607 if (lttpr_count < 0) 1608 /* Still continue with enabling the port and link training. */ 1609 lttpr_count = 0; 1610 1611 intel_dp_prepare_link_train(intel_dp, crtc_state); 1612 1613 if (intel_dp_is_uhbr(crtc_state)) 1614 passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count); 1615 else 1616 passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); 1617 1618 if (intel_dp->link.force_train_failure) { 1619 intel_dp->link.force_train_failure--; 1620 lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n"); 1621 } else if (passed) { 1622 intel_dp->link.seq_train_failures = 0; 1623 intel_encoder_link_check_queue_work(encoder, 2000); 1624 return; 1625 } 1626 1627 intel_dp->link.seq_train_failures++; 1628 1629 /* 1630 * Ignore the link failure in CI 1631 * 1632 * In fixed environments like CI, sometimes unexpected long HPDs are 1633 * generated by the displays. If ignore_long_hpd flag is set, such long 1634 * HPDs are ignored. And probably as a consequence of these ignored 1635 * long HPDs, subsequent link trainings are failed resulting into CI 1636 * execution failures. 1637 * 1638 * For test cases which rely on the link training or processing of HPDs 1639 * ignore_long_hpd flag can unset from the testcase. 1640 */ 1641 if (display->hotplug.ignore_long_hpd) { 1642 lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n"); 1643 return; 1644 } 1645 1646 if (intel_dp->link.seq_train_failures < 2) { 1647 intel_encoder_link_check_queue_work(encoder, 0); 1648 return; 1649 } 1650 1651 if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state)) 1652 return; 1653 1654 intel_dp->link.retrain_disabled = true; 1655 1656 if (!passed) 1657 lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n"); 1658 else 1659 lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n"); 1660 } 1661 1662 void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, 1663 const struct intel_crtc_state *crtc_state) 1664 { 1665 /* 1666 * VIDEO_DIP_CTL register bit 31 should be set to '0' to not 1667 * disable SDP CRC. This is applicable for Display version 13. 1668 * Default value of bit 31 is '0' hence discarding the write 1669 * TODO: Corrective actions on SDP corruption yet to be defined 1670 */ 1671 if (!intel_dp_is_uhbr(crtc_state)) 1672 return; 1673 1674 /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ 1675 drm_dp_dpcd_writeb(&intel_dp->aux, 1676 DP_SDP_ERROR_DETECTION_CONFIGURATION, 1677 DP_SDP_CRC16_128B132B_EN); 1678 1679 lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n"); 1680 } 1681 1682 static int i915_dp_force_link_rate_show(struct seq_file *m, void *data) 1683 { 1684 struct intel_connector *connector = to_intel_connector(m->private); 1685 struct intel_display *display = to_intel_display(connector); 1686 struct intel_dp *intel_dp = intel_attached_dp(connector); 1687 int current_rate = -1; 1688 int force_rate; 1689 int err; 1690 int i; 1691 1692 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1693 if (err) 1694 return err; 1695 1696 if (intel_dp->link_trained) 1697 current_rate = intel_dp->link_rate; 1698 force_rate = intel_dp->link.force_rate; 1699 1700 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1701 1702 seq_printf(m, "%sauto%s", 1703 force_rate == 0 ? "[" : "", 1704 force_rate == 0 ? "]" : ""); 1705 1706 for (i = 0; i < intel_dp->num_source_rates; i++) 1707 seq_printf(m, " %s%d%s%s", 1708 intel_dp->source_rates[i] == force_rate ? "[" : "", 1709 intel_dp->source_rates[i], 1710 intel_dp->source_rates[i] == current_rate ? "*" : "", 1711 intel_dp->source_rates[i] == force_rate ? "]" : ""); 1712 1713 seq_putc(m, '\n'); 1714 1715 return 0; 1716 } 1717 1718 static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len) 1719 { 1720 char *kbuf; 1721 const char *p; 1722 int rate; 1723 int ret = 0; 1724 1725 kbuf = memdup_user_nul(ubuf, len); 1726 if (IS_ERR(kbuf)) 1727 return PTR_ERR(kbuf); 1728 1729 p = strim(kbuf); 1730 1731 if (!strcmp(p, "auto")) { 1732 rate = 0; 1733 } else { 1734 ret = kstrtoint(p, 0, &rate); 1735 if (ret < 0) 1736 goto out_free; 1737 1738 if (intel_dp_rate_index(intel_dp->source_rates, 1739 intel_dp->num_source_rates, 1740 rate) < 0) 1741 ret = -EINVAL; 1742 } 1743 1744 out_free: 1745 kfree(kbuf); 1746 1747 return ret < 0 ? ret : rate; 1748 } 1749 1750 static ssize_t i915_dp_force_link_rate_write(struct file *file, 1751 const char __user *ubuf, 1752 size_t len, loff_t *offp) 1753 { 1754 struct seq_file *m = file->private_data; 1755 struct intel_connector *connector = to_intel_connector(m->private); 1756 struct intel_display *display = to_intel_display(connector); 1757 struct intel_dp *intel_dp = intel_attached_dp(connector); 1758 int rate; 1759 int err; 1760 1761 rate = parse_link_rate(intel_dp, ubuf, len); 1762 if (rate < 0) 1763 return rate; 1764 1765 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1766 if (err) 1767 return err; 1768 1769 intel_dp_reset_link_params(intel_dp); 1770 intel_dp->link.force_rate = rate; 1771 1772 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1773 1774 *offp += len; 1775 1776 return len; 1777 } 1778 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_link_rate); 1779 1780 static int i915_dp_force_lane_count_show(struct seq_file *m, void *data) 1781 { 1782 struct intel_connector *connector = to_intel_connector(m->private); 1783 struct intel_display *display = to_intel_display(connector); 1784 struct intel_dp *intel_dp = intel_attached_dp(connector); 1785 int current_lane_count = -1; 1786 int force_lane_count; 1787 int err; 1788 int i; 1789 1790 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1791 if (err) 1792 return err; 1793 1794 if (intel_dp->link_trained) 1795 current_lane_count = intel_dp->lane_count; 1796 force_lane_count = intel_dp->link.force_lane_count; 1797 1798 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1799 1800 seq_printf(m, "%sauto%s", 1801 force_lane_count == 0 ? "[" : "", 1802 force_lane_count == 0 ? "]" : ""); 1803 1804 for (i = 1; i <= 4; i <<= 1) 1805 seq_printf(m, " %s%d%s%s", 1806 i == force_lane_count ? "[" : "", 1807 i, 1808 i == current_lane_count ? "*" : "", 1809 i == force_lane_count ? "]" : ""); 1810 1811 seq_putc(m, '\n'); 1812 1813 return 0; 1814 } 1815 1816 static int parse_lane_count(const char __user *ubuf, size_t len) 1817 { 1818 char *kbuf; 1819 const char *p; 1820 int lane_count; 1821 int ret = 0; 1822 1823 kbuf = memdup_user_nul(ubuf, len); 1824 if (IS_ERR(kbuf)) 1825 return PTR_ERR(kbuf); 1826 1827 p = strim(kbuf); 1828 1829 if (!strcmp(p, "auto")) { 1830 lane_count = 0; 1831 } else { 1832 ret = kstrtoint(p, 0, &lane_count); 1833 if (ret < 0) 1834 goto out_free; 1835 1836 switch (lane_count) { 1837 case 1: 1838 case 2: 1839 case 4: 1840 break; 1841 default: 1842 ret = -EINVAL; 1843 } 1844 } 1845 1846 out_free: 1847 kfree(kbuf); 1848 1849 return ret < 0 ? ret : lane_count; 1850 } 1851 1852 static ssize_t i915_dp_force_lane_count_write(struct file *file, 1853 const char __user *ubuf, 1854 size_t len, loff_t *offp) 1855 { 1856 struct seq_file *m = file->private_data; 1857 struct intel_connector *connector = to_intel_connector(m->private); 1858 struct intel_display *display = to_intel_display(connector); 1859 struct intel_dp *intel_dp = intel_attached_dp(connector); 1860 int lane_count; 1861 int err; 1862 1863 lane_count = parse_lane_count(ubuf, len); 1864 if (lane_count < 0) 1865 return lane_count; 1866 1867 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1868 if (err) 1869 return err; 1870 1871 intel_dp_reset_link_params(intel_dp); 1872 intel_dp->link.force_lane_count = lane_count; 1873 1874 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1875 1876 *offp += len; 1877 1878 return len; 1879 } 1880 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_lane_count); 1881 1882 static int i915_dp_max_link_rate_show(void *data, u64 *val) 1883 { 1884 struct intel_connector *connector = to_intel_connector(data); 1885 struct intel_display *display = to_intel_display(connector); 1886 struct intel_dp *intel_dp = intel_attached_dp(connector); 1887 int err; 1888 1889 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1890 if (err) 1891 return err; 1892 1893 *val = intel_dp->link.max_rate; 1894 1895 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1896 1897 return 0; 1898 } 1899 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_link_rate_fops, i915_dp_max_link_rate_show, NULL, "%llu\n"); 1900 1901 static int i915_dp_max_lane_count_show(void *data, u64 *val) 1902 { 1903 struct intel_connector *connector = to_intel_connector(data); 1904 struct intel_display *display = to_intel_display(connector); 1905 struct intel_dp *intel_dp = intel_attached_dp(connector); 1906 int err; 1907 1908 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1909 if (err) 1910 return err; 1911 1912 *val = intel_dp->link.max_lane_count; 1913 1914 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1915 1916 return 0; 1917 } 1918 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n"); 1919 1920 static int i915_dp_force_link_training_failure_show(void *data, u64 *val) 1921 { 1922 struct intel_connector *connector = to_intel_connector(data); 1923 struct intel_display *display = to_intel_display(connector); 1924 struct intel_dp *intel_dp = intel_attached_dp(connector); 1925 int err; 1926 1927 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1928 if (err) 1929 return err; 1930 1931 *val = intel_dp->link.force_train_failure; 1932 1933 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1934 1935 return 0; 1936 } 1937 1938 static int i915_dp_force_link_training_failure_write(void *data, u64 val) 1939 { 1940 struct intel_connector *connector = to_intel_connector(data); 1941 struct intel_display *display = to_intel_display(connector); 1942 struct intel_dp *intel_dp = intel_attached_dp(connector); 1943 int err; 1944 1945 if (val > 2) 1946 return -EINVAL; 1947 1948 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1949 if (err) 1950 return err; 1951 1952 intel_dp->link.force_train_failure = val; 1953 1954 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1955 1956 return 0; 1957 } 1958 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, 1959 i915_dp_force_link_training_failure_show, 1960 i915_dp_force_link_training_failure_write, "%llu\n"); 1961 1962 static int i915_dp_force_link_retrain_show(void *data, u64 *val) 1963 { 1964 struct intel_connector *connector = to_intel_connector(data); 1965 struct intel_display *display = to_intel_display(connector); 1966 struct intel_dp *intel_dp = intel_attached_dp(connector); 1967 int err; 1968 1969 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1970 if (err) 1971 return err; 1972 1973 *val = intel_dp->link.force_retrain; 1974 1975 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1976 1977 return 0; 1978 } 1979 1980 static int i915_dp_force_link_retrain_write(void *data, u64 val) 1981 { 1982 struct intel_connector *connector = to_intel_connector(data); 1983 struct intel_display *display = to_intel_display(connector); 1984 struct intel_dp *intel_dp = intel_attached_dp(connector); 1985 int err; 1986 1987 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1988 if (err) 1989 return err; 1990 1991 intel_dp->link.force_retrain = val; 1992 1993 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1994 1995 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); 1996 1997 return 0; 1998 } 1999 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, 2000 i915_dp_force_link_retrain_show, 2001 i915_dp_force_link_retrain_write, "%llu\n"); 2002 2003 static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data) 2004 { 2005 struct intel_connector *connector = to_intel_connector(m->private); 2006 struct intel_display *display = to_intel_display(connector); 2007 struct intel_dp *intel_dp = intel_attached_dp(connector); 2008 int err; 2009 2010 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2011 if (err) 2012 return err; 2013 2014 seq_printf(m, "%s\n", str_yes_no(intel_dp->link.retrain_disabled)); 2015 2016 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2017 2018 return 0; 2019 } 2020 DEFINE_SHOW_ATTRIBUTE(i915_dp_link_retrain_disabled); 2021 2022 void intel_dp_link_training_debugfs_add(struct intel_connector *connector) 2023 { 2024 struct dentry *root = connector->base.debugfs_entry; 2025 2026 if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort && 2027 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 2028 return; 2029 2030 debugfs_create_file("i915_dp_force_link_rate", 0644, root, 2031 connector, &i915_dp_force_link_rate_fops); 2032 2033 debugfs_create_file("i915_dp_force_lane_count", 0644, root, 2034 connector, &i915_dp_force_lane_count_fops); 2035 2036 debugfs_create_file("i915_dp_max_link_rate", 0444, root, 2037 connector, &i915_dp_max_link_rate_fops); 2038 2039 debugfs_create_file("i915_dp_max_lane_count", 0444, root, 2040 connector, &i915_dp_max_lane_count_fops); 2041 2042 debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, 2043 connector, &i915_dp_force_link_training_failure_fops); 2044 2045 debugfs_create_file("i915_dp_force_link_retrain", 0644, root, 2046 connector, &i915_dp_force_link_retrain_fops); 2047 2048 debugfs_create_file("i915_dp_link_retrain_disabled", 0444, root, 2049 connector, &i915_dp_link_retrain_disabled_fops); 2050 } 2051