1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "i915_drv.h" 25 #include "intel_display_types.h" 26 #include "intel_dp.h" 27 #include "intel_dp_link_training.h" 28 #include "intel_encoder.h" 29 #include "intel_hotplug.h" 30 #include "intel_panel.h" 31 32 #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " 33 #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \ 34 (_intel_dp)->attached_connector->base.name, \ 35 dp_to_dig_port(_intel_dp)->base.base.base.id, \ 36 dp_to_dig_port(_intel_dp)->base.base.name, \ 37 drm_dp_phy_name(_dp_phy) 38 39 #define lt_dbg(_intel_dp, _dp_phy, _format, ...) \ 40 drm_dbg_kms(&dp_to_i915(_intel_dp)->drm, \ 41 LT_MSG_PREFIX _format, \ 42 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__) 43 44 #define lt_err(_intel_dp, _dp_phy, _format, ...) do { \ 45 if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \ 46 drm_err(&dp_to_i915(_intel_dp)->drm, \ 47 LT_MSG_PREFIX _format, \ 48 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \ 49 else \ 50 lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \ 51 } while (0) 52 53 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) 54 { 55 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); 56 } 57 58 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 59 { 60 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 61 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 62 } 63 64 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 65 enum drm_dp_phy dp_phy) 66 { 67 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 68 } 69 70 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 71 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 72 enum drm_dp_phy dp_phy) 73 { 74 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 75 76 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { 77 lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n"); 78 return; 79 } 80 81 lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n", 82 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 83 phy_caps); 84 } 85 86 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, 87 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 88 { 89 int ret; 90 91 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, 92 intel_dp->lttpr_common_caps); 93 if (ret < 0) 94 goto reset_caps; 95 96 lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n", 97 (int)sizeof(intel_dp->lttpr_common_caps), 98 intel_dp->lttpr_common_caps); 99 100 /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ 101 if (intel_dp->lttpr_common_caps[0] < 0x14) 102 goto reset_caps; 103 104 return true; 105 106 reset_caps: 107 intel_dp_reset_lttpr_common_caps(intel_dp); 108 return false; 109 } 110 111 static bool 112 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 113 { 114 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 115 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 116 117 return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1; 118 } 119 120 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 121 { 122 int lttpr_count; 123 int i; 124 125 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) 126 return 0; 127 128 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 129 /* 130 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are 131 * detected as this breaks link training at least on the Dell WD19TB 132 * dock. 133 */ 134 if (lttpr_count == 0) 135 return 0; 136 137 /* 138 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of 139 * non-transparent mode and the disable->enable non-transparent mode 140 * sequence. 141 */ 142 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 143 144 /* 145 * In case of unsupported number of LTTPRs or failing to switch to 146 * non-transparent mode fall-back to transparent link training mode, 147 * still taking into account any LTTPR common lane- rate/count limits. 148 */ 149 if (lttpr_count < 0) 150 return 0; 151 152 if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { 153 lt_dbg(intel_dp, DP_PHY_DPRX, 154 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); 155 156 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 157 intel_dp_reset_lttpr_count(intel_dp); 158 159 return 0; 160 } 161 162 for (i = 0; i < lttpr_count; i++) 163 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); 164 165 return lttpr_count; 166 } 167 168 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) 169 { 170 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 171 172 if (intel_dp_is_edp(intel_dp)) 173 return 0; 174 175 /* 176 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 177 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 178 */ 179 if (DISPLAY_VER(i915) >= 10 && !IS_GEMINILAKE(i915)) 180 if (drm_dp_dpcd_probe(&intel_dp->aux, 181 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV)) 182 return -EIO; 183 184 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) 185 return -EIO; 186 187 return 0; 188 } 189 190 /** 191 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode 192 * @intel_dp: Intel DP struct 193 * 194 * Read the LTTPR common and DPRX capabilities and switch to non-transparent 195 * link training mode if any is detected and read the PHY capabilities for all 196 * detected LTTPRs. In case of an LTTPR detection error or if the number of 197 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 198 * transparent mode link training mode. 199 * 200 * Returns: 201 * >0 if LTTPRs were detected and the non-transparent LT mode was set. The 202 * DPRX capabilities are read out. 203 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 204 * detection failure and the transparent LT mode was set. The DPRX 205 * capabilities are read out. 206 * <0 Reading out the DPRX capabilities failed. 207 */ 208 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) 209 { 210 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 211 int lttpr_count = 0; 212 213 /* 214 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 215 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 216 */ 217 if (!intel_dp_is_edp(intel_dp) && 218 (DISPLAY_VER(i915) >= 10 && !IS_GEMINILAKE(i915))) { 219 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 220 int err = intel_dp_read_dprx_caps(intel_dp, dpcd); 221 222 if (err != 0) 223 return err; 224 225 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); 226 } 227 228 /* 229 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read 230 * it here. 231 */ 232 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { 233 intel_dp_reset_lttpr_common_caps(intel_dp); 234 return -EIO; 235 } 236 237 return lttpr_count; 238 } 239 240 static u8 dp_voltage_max(u8 preemph) 241 { 242 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 243 case DP_TRAIN_PRE_EMPH_LEVEL_0: 244 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 245 case DP_TRAIN_PRE_EMPH_LEVEL_1: 246 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 247 case DP_TRAIN_PRE_EMPH_LEVEL_2: 248 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 249 case DP_TRAIN_PRE_EMPH_LEVEL_3: 250 default: 251 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 252 } 253 } 254 255 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 256 enum drm_dp_phy dp_phy) 257 { 258 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 259 260 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 261 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 262 else 263 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 264 } 265 266 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 267 enum drm_dp_phy dp_phy) 268 { 269 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 270 271 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 272 return DP_TRAIN_PRE_EMPH_LEVEL_3; 273 else 274 return DP_TRAIN_PRE_EMPH_LEVEL_2; 275 } 276 277 static bool 278 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 279 enum drm_dp_phy dp_phy) 280 { 281 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 282 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 283 284 drm_WARN_ON_ONCE(&i915->drm, lttpr_count <= 0 && dp_phy != DP_PHY_DPRX); 285 286 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 287 } 288 289 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 290 const struct intel_crtc_state *crtc_state, 291 enum drm_dp_phy dp_phy) 292 { 293 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 294 u8 voltage_max; 295 296 /* 297 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 298 * the DPRX_PHY we train. 299 */ 300 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 301 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 302 else 303 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 304 305 drm_WARN_ON_ONCE(&i915->drm, 306 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 307 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 308 309 return voltage_max; 310 } 311 312 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 313 enum drm_dp_phy dp_phy) 314 { 315 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 316 u8 preemph_max; 317 318 /* 319 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 320 * the DPRX_PHY we train. 321 */ 322 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 323 preemph_max = intel_dp->preemph_max(intel_dp); 324 else 325 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 326 327 drm_WARN_ON_ONCE(&i915->drm, 328 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 329 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 330 331 return preemph_max; 332 } 333 334 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, 335 enum drm_dp_phy dp_phy) 336 { 337 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 338 339 return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) || 340 DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915); 341 } 342 343 /* 128b/132b */ 344 static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp, 345 const struct intel_crtc_state *crtc_state, 346 enum drm_dp_phy dp_phy, 347 const u8 link_status[DP_LINK_STATUS_SIZE], 348 int lane) 349 { 350 u8 tx_ffe = 0; 351 352 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 353 lane = min(lane, crtc_state->lane_count - 1); 354 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); 355 } else { 356 for (lane = 0; lane < crtc_state->lane_count; lane++) 357 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); 358 } 359 360 return tx_ffe; 361 } 362 363 /* 8b/10b */ 364 static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp, 365 const struct intel_crtc_state *crtc_state, 366 enum drm_dp_phy dp_phy, 367 const u8 link_status[DP_LINK_STATUS_SIZE], 368 int lane) 369 { 370 u8 v = 0; 371 u8 p = 0; 372 u8 voltage_max; 373 u8 preemph_max; 374 375 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 376 lane = min(lane, crtc_state->lane_count - 1); 377 378 v = drm_dp_get_adjust_request_voltage(link_status, lane); 379 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 380 } else { 381 for (lane = 0; lane < crtc_state->lane_count; lane++) { 382 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 383 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 384 } 385 } 386 387 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 388 if (p >= preemph_max) 389 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 390 391 v = min(v, dp_voltage_max(p)); 392 393 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 394 if (v >= voltage_max) 395 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 396 397 return v | p; 398 } 399 400 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, 401 const struct intel_crtc_state *crtc_state, 402 enum drm_dp_phy dp_phy, 403 const u8 link_status[DP_LINK_STATUS_SIZE], 404 int lane) 405 { 406 if (intel_dp_is_uhbr(crtc_state)) 407 return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state, 408 dp_phy, link_status, lane); 409 else 410 return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state, 411 dp_phy, link_status, lane); 412 } 413 414 #define TRAIN_REQ_FMT "%d/%d/%d/%d" 415 #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \ 416 (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT) 417 #define TRAIN_REQ_VSWING_ARGS(link_status) \ 418 _TRAIN_REQ_VSWING_ARGS(link_status, 0), \ 419 _TRAIN_REQ_VSWING_ARGS(link_status, 1), \ 420 _TRAIN_REQ_VSWING_ARGS(link_status, 2), \ 421 _TRAIN_REQ_VSWING_ARGS(link_status, 3) 422 #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \ 423 (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT) 424 #define TRAIN_REQ_PREEMPH_ARGS(link_status) \ 425 _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \ 426 _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \ 427 _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \ 428 _TRAIN_REQ_PREEMPH_ARGS(link_status, 3) 429 #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \ 430 drm_dp_get_adjust_tx_ffe_preset((link_status), (lane)) 431 #define TRAIN_REQ_TX_FFE_ARGS(link_status) \ 432 _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \ 433 _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \ 434 _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \ 435 _TRAIN_REQ_TX_FFE_ARGS(link_status, 3) 436 437 void 438 intel_dp_get_adjust_train(struct intel_dp *intel_dp, 439 const struct intel_crtc_state *crtc_state, 440 enum drm_dp_phy dp_phy, 441 const u8 link_status[DP_LINK_STATUS_SIZE]) 442 { 443 int lane; 444 445 if (intel_dp_is_uhbr(crtc_state)) { 446 lt_dbg(intel_dp, dp_phy, 447 "128b/132b, lanes: %d, " 448 "TX FFE request: " TRAIN_REQ_FMT "\n", 449 crtc_state->lane_count, 450 TRAIN_REQ_TX_FFE_ARGS(link_status)); 451 } else { 452 lt_dbg(intel_dp, dp_phy, 453 "8b/10b, lanes: %d, " 454 "vswing request: " TRAIN_REQ_FMT ", " 455 "pre-emphasis request: " TRAIN_REQ_FMT "\n", 456 crtc_state->lane_count, 457 TRAIN_REQ_VSWING_ARGS(link_status), 458 TRAIN_REQ_PREEMPH_ARGS(link_status)); 459 } 460 461 for (lane = 0; lane < 4; lane++) 462 intel_dp->train_set[lane] = 463 intel_dp_get_lane_adjust_train(intel_dp, crtc_state, 464 dp_phy, link_status, lane); 465 } 466 467 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 468 enum drm_dp_phy dp_phy) 469 { 470 return dp_phy == DP_PHY_DPRX ? 471 DP_TRAINING_PATTERN_SET : 472 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 473 } 474 475 static bool 476 intel_dp_set_link_train(struct intel_dp *intel_dp, 477 const struct intel_crtc_state *crtc_state, 478 enum drm_dp_phy dp_phy, 479 u8 dp_train_pat) 480 { 481 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 482 u8 buf[sizeof(intel_dp->train_set) + 1]; 483 int len; 484 485 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 486 dp_phy, dp_train_pat); 487 488 buf[0] = dp_train_pat; 489 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 490 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 491 len = crtc_state->lane_count + 1; 492 493 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 494 } 495 496 static char dp_training_pattern_name(u8 train_pat) 497 { 498 switch (train_pat) { 499 case DP_TRAINING_PATTERN_1: 500 case DP_TRAINING_PATTERN_2: 501 case DP_TRAINING_PATTERN_3: 502 return '0' + train_pat; 503 case DP_TRAINING_PATTERN_4: 504 return '4'; 505 default: 506 MISSING_CASE(train_pat); 507 return '?'; 508 } 509 } 510 511 void 512 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 513 const struct intel_crtc_state *crtc_state, 514 enum drm_dp_phy dp_phy, 515 u8 dp_train_pat) 516 { 517 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat); 518 519 if (train_pat != DP_TRAINING_PATTERN_DISABLE) 520 lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n", 521 dp_training_pattern_name(train_pat)); 522 523 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); 524 } 525 526 #define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" 527 #define _TRAIN_SET_VSWING_ARGS(train_set) \ 528 ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ 529 (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" 530 #define TRAIN_SET_VSWING_ARGS(train_set) \ 531 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ 532 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ 533 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ 534 _TRAIN_SET_VSWING_ARGS((train_set)[3]) 535 #define _TRAIN_SET_PREEMPH_ARGS(train_set) \ 536 ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ 537 (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" 538 #define TRAIN_SET_PREEMPH_ARGS(train_set) \ 539 _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ 540 _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ 541 _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ 542 _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) 543 #define _TRAIN_SET_TX_FFE_ARGS(train_set) \ 544 ((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), "" 545 #define TRAIN_SET_TX_FFE_ARGS(train_set) \ 546 _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \ 547 _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \ 548 _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \ 549 _TRAIN_SET_TX_FFE_ARGS((train_set)[3]) 550 551 void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 552 const struct intel_crtc_state *crtc_state, 553 enum drm_dp_phy dp_phy) 554 { 555 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 556 557 if (intel_dp_is_uhbr(crtc_state)) { 558 lt_dbg(intel_dp, dp_phy, 559 "128b/132b, lanes: %d, " 560 "TX FFE presets: " TRAIN_SET_FMT "\n", 561 crtc_state->lane_count, 562 TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set)); 563 } else { 564 lt_dbg(intel_dp, dp_phy, 565 "8b/10b, lanes: %d, " 566 "vswing levels: " TRAIN_SET_FMT ", " 567 "pre-emphasis levels: " TRAIN_SET_FMT "\n", 568 crtc_state->lane_count, 569 TRAIN_SET_VSWING_ARGS(intel_dp->train_set), 570 TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set)); 571 } 572 573 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 574 encoder->set_signal_levels(encoder, crtc_state); 575 } 576 577 static bool 578 intel_dp_reset_link_train(struct intel_dp *intel_dp, 579 const struct intel_crtc_state *crtc_state, 580 enum drm_dp_phy dp_phy, 581 u8 dp_train_pat) 582 { 583 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 584 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 585 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 586 } 587 588 static bool 589 intel_dp_update_link_train(struct intel_dp *intel_dp, 590 const struct intel_crtc_state *crtc_state, 591 enum drm_dp_phy dp_phy) 592 { 593 int reg = dp_phy == DP_PHY_DPRX ? 594 DP_TRAINING_LANE0_SET : 595 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 596 int ret; 597 598 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 599 600 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 601 intel_dp->train_set, crtc_state->lane_count); 602 603 return ret == crtc_state->lane_count; 604 } 605 606 /* 128b/132b */ 607 static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane) 608 { 609 return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) == 610 DP_TX_FFE_PRESET_VALUE_MASK; 611 } 612 613 /* 614 * 8b/10b 615 * 616 * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to 617 * have self contradicting tests around this area. 618 * 619 * In lieu of better ideas let's just stop when we've reached the max supported 620 * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on 621 * whether vswing level 3 is supported or not. 622 */ 623 static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane) 624 { 625 u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 626 DP_TRAIN_VOLTAGE_SWING_SHIFT; 627 u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 628 DP_TRAIN_PRE_EMPHASIS_SHIFT; 629 630 if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0) 631 return false; 632 633 if (v + p != 3) 634 return false; 635 636 return true; 637 } 638 639 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 640 const struct intel_crtc_state *crtc_state) 641 { 642 int lane; 643 644 for (lane = 0; lane < crtc_state->lane_count; lane++) { 645 u8 train_set_lane = intel_dp->train_set[lane]; 646 647 if (intel_dp_is_uhbr(crtc_state)) { 648 if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane)) 649 return false; 650 } else { 651 if (!intel_dp_lane_max_vswing_reached(train_set_lane)) 652 return false; 653 } 654 } 655 656 return true; 657 } 658 659 static void 660 intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, 661 const struct intel_crtc_state *crtc_state) 662 { 663 u8 link_config[2]; 664 665 link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 666 link_config[1] = intel_dp_is_uhbr(crtc_state) ? 667 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; 668 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 669 } 670 671 static void 672 intel_dp_update_link_bw_set(struct intel_dp *intel_dp, 673 const struct intel_crtc_state *crtc_state, 674 u8 link_bw, u8 rate_select) 675 { 676 u8 lane_count = crtc_state->lane_count; 677 678 if (crtc_state->enhanced_framing) 679 lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 680 681 if (link_bw) { 682 /* DP and eDP v1.3 and earlier link bw set method. */ 683 u8 link_config[] = { link_bw, lane_count }; 684 685 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 686 ARRAY_SIZE(link_config)); 687 } else { 688 /* 689 * eDP v1.4 and later link rate set method. 690 * 691 * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if 692 * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET. 693 * 694 * eDP v1.5 sinks allow choosing either, and the last choice 695 * shall be active. 696 */ 697 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count); 698 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select); 699 } 700 } 701 702 /* 703 * Prepare link training by configuring the link parameters. On DDI platforms 704 * also enable the port here. 705 */ 706 static bool 707 intel_dp_prepare_link_train(struct intel_dp *intel_dp, 708 const struct intel_crtc_state *crtc_state) 709 { 710 u8 link_bw, rate_select; 711 712 if (intel_dp->prepare_link_retrain) 713 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 714 715 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 716 &link_bw, &rate_select); 717 718 /* 719 * WaEdpLinkRateDataReload 720 * 721 * Parade PS8461E MUX (used on varius TGL+ laptops) needs 722 * to snoop the link rates reported by the sink when we 723 * use LINK_RATE_SET in order to operate in jitter cleaning 724 * mode (as opposed to redriver mode). Unfortunately it 725 * loses track of the snooped link rates when powered down, 726 * so we need to make it re-snoop often. Without this high 727 * link rates are not stable. 728 */ 729 if (!link_bw) { 730 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 731 732 lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n"); 733 734 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 735 sink_rates, sizeof(sink_rates)); 736 } 737 738 if (link_bw) 739 lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n", 740 link_bw); 741 else 742 lt_dbg(intel_dp, DP_PHY_DPRX, 743 "Using LINK_RATE_SET value %02x\n", 744 rate_select); 745 /* 746 * Spec DP2.1 Section 3.5.2.16 747 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate 748 */ 749 intel_dp_update_downspread_ctrl(intel_dp, crtc_state); 750 intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw, 751 rate_select); 752 753 return true; 754 } 755 756 static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state, 757 const u8 old_link_status[DP_LINK_STATUS_SIZE], 758 const u8 new_link_status[DP_LINK_STATUS_SIZE]) 759 { 760 int lane; 761 762 for (lane = 0; lane < crtc_state->lane_count; lane++) { 763 u8 old, new; 764 765 if (intel_dp_is_uhbr(crtc_state)) { 766 old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane); 767 new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane); 768 } else { 769 old = drm_dp_get_adjust_request_voltage(old_link_status, lane) | 770 drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane); 771 new = drm_dp_get_adjust_request_voltage(new_link_status, lane) | 772 drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane); 773 } 774 775 if (old != new) 776 return true; 777 } 778 779 return false; 780 } 781 782 void 783 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy, 784 const u8 link_status[DP_LINK_STATUS_SIZE]) 785 { 786 lt_dbg(intel_dp, dp_phy, 787 "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n", 788 link_status[0], link_status[1], link_status[2], 789 link_status[3], link_status[4], link_status[5]); 790 } 791 792 /* 793 * Perform the link training clock recovery phase on the given DP PHY using 794 * training pattern 1. 795 */ 796 static bool 797 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 798 const struct intel_crtc_state *crtc_state, 799 enum drm_dp_phy dp_phy) 800 { 801 u8 old_link_status[DP_LINK_STATUS_SIZE] = {}; 802 int voltage_tries, cr_tries, max_cr_tries; 803 u8 link_status[DP_LINK_STATUS_SIZE]; 804 bool max_vswing_reached = false; 805 int delay_us; 806 807 delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux, 808 intel_dp->dpcd, dp_phy, 809 intel_dp_is_uhbr(crtc_state)); 810 811 /* clock recovery */ 812 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 813 DP_TRAINING_PATTERN_1 | 814 DP_LINK_SCRAMBLING_DISABLE)) { 815 lt_err(intel_dp, dp_phy, "Failed to enable link training\n"); 816 return false; 817 } 818 819 /* 820 * The DP 1.4 spec defines the max clock recovery retries value 821 * as 10 but for pre-DP 1.4 devices we set a very tolerant 822 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 823 * x 5 identical voltage retries). Since the previous specs didn't 824 * define a limit and created the possibility of an infinite loop 825 * we want to prevent any sync from triggering that corner case. 826 */ 827 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 828 max_cr_tries = 10; 829 else 830 max_cr_tries = 80; 831 832 voltage_tries = 1; 833 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 834 usleep_range(delay_us, 2 * delay_us); 835 836 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 837 link_status) < 0) { 838 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 839 return false; 840 } 841 842 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 843 lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n"); 844 return true; 845 } 846 847 if (voltage_tries == 5) { 848 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 849 lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n"); 850 return false; 851 } 852 853 if (max_vswing_reached) { 854 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 855 lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n"); 856 return false; 857 } 858 859 /* Update training set as requested by target */ 860 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 861 link_status); 862 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 863 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 864 return false; 865 } 866 867 if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status)) 868 ++voltage_tries; 869 else 870 voltage_tries = 1; 871 872 memcpy(old_link_status, link_status, sizeof(link_status)); 873 874 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 875 max_vswing_reached = true; 876 } 877 878 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 879 lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n", 880 max_cr_tries); 881 882 return false; 883 } 884 885 /* 886 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 887 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or 888 * 1.2 devices that support it, TPS2 otherwise. 889 */ 890 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 891 const struct intel_crtc_state *crtc_state, 892 enum drm_dp_phy dp_phy) 893 { 894 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 895 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 896 897 /* UHBR+ use separate 128b/132b TPS2 */ 898 if (intel_dp_is_uhbr(crtc_state)) 899 return DP_TRAINING_PATTERN_2; 900 901 /* 902 * TPS4 support is mandatory for all downstream devices that 903 * support HBR3. There are no known eDP panels that support 904 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification. 905 * LTTPRs must support TPS4. 906 */ 907 source_tps4 = intel_dp_source_supports_tps4(i915); 908 sink_tps4 = dp_phy != DP_PHY_DPRX || 909 drm_dp_tps4_supported(intel_dp->dpcd); 910 if (source_tps4 && sink_tps4) { 911 return DP_TRAINING_PATTERN_4; 912 } else if (crtc_state->port_clock == 810000) { 913 if (!source_tps4) 914 lt_dbg(intel_dp, dp_phy, 915 "8.1 Gbps link rate without source TPS4 support\n"); 916 if (!sink_tps4) 917 lt_dbg(intel_dp, dp_phy, 918 "8.1 Gbps link rate without sink TPS4 support\n"); 919 } 920 921 /* 922 * TPS3 support is mandatory for downstream devices that 923 * support HBR2. However, not all sinks follow the spec. 924 */ 925 source_tps3 = intel_dp_source_supports_tps3(i915); 926 sink_tps3 = dp_phy != DP_PHY_DPRX || 927 drm_dp_tps3_supported(intel_dp->dpcd); 928 if (source_tps3 && sink_tps3) { 929 return DP_TRAINING_PATTERN_3; 930 } else if (crtc_state->port_clock >= 540000) { 931 if (!source_tps3) 932 lt_dbg(intel_dp, dp_phy, 933 ">=5.4/6.48 Gbps link rate without source TPS3 support\n"); 934 if (!sink_tps3) 935 lt_dbg(intel_dp, dp_phy, 936 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 937 } 938 939 return DP_TRAINING_PATTERN_2; 940 } 941 942 /* 943 * Perform the link training channel equalization phase on the given DP PHY 944 * using one of training pattern 2, 3 or 4 depending on the source and 945 * sink capabilities. 946 */ 947 static bool 948 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 949 const struct intel_crtc_state *crtc_state, 950 enum drm_dp_phy dp_phy) 951 { 952 int tries; 953 u32 training_pattern; 954 u8 link_status[DP_LINK_STATUS_SIZE]; 955 bool channel_eq = false; 956 int delay_us; 957 958 delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux, 959 intel_dp->dpcd, dp_phy, 960 intel_dp_is_uhbr(crtc_state)); 961 962 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 963 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 964 if (training_pattern != DP_TRAINING_PATTERN_4) 965 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 966 967 /* channel equalization */ 968 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 969 training_pattern)) { 970 lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n"); 971 return false; 972 } 973 974 for (tries = 0; tries < 5; tries++) { 975 usleep_range(delay_us, 2 * delay_us); 976 977 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 978 link_status) < 0) { 979 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 980 break; 981 } 982 983 /* Make sure clock is still ok */ 984 if (!drm_dp_clock_recovery_ok(link_status, 985 crtc_state->lane_count)) { 986 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 987 lt_dbg(intel_dp, dp_phy, 988 "Clock recovery check failed, cannot continue channel equalization\n"); 989 break; 990 } 991 992 if (drm_dp_channel_eq_ok(link_status, 993 crtc_state->lane_count)) { 994 channel_eq = true; 995 lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n"); 996 break; 997 } 998 999 /* Update training set as requested by target */ 1000 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 1001 link_status); 1002 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 1003 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 1004 break; 1005 } 1006 } 1007 1008 /* Try 5 times, else fail and try at lower BW */ 1009 if (tries == 5) { 1010 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1011 lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n"); 1012 } 1013 1014 return channel_eq; 1015 } 1016 1017 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 1018 enum drm_dp_phy dp_phy) 1019 { 1020 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 1021 u8 val = DP_TRAINING_PATTERN_DISABLE; 1022 1023 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 1024 } 1025 1026 static int 1027 intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp, 1028 const struct intel_crtc_state *crtc_state) 1029 { 1030 u8 sink_status; 1031 int ret; 1032 1033 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status); 1034 if (ret != 1) { 1035 lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n"); 1036 return ret < 0 ? ret : -EIO; 1037 } 1038 1039 return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0; 1040 } 1041 1042 /** 1043 * intel_dp_stop_link_train - stop link training 1044 * @intel_dp: DP struct 1045 * @crtc_state: state for CRTC attached to the encoder 1046 * 1047 * Stop the link training of the @intel_dp port, disabling the training 1048 * pattern in the sink's DPCD, and disabling the test pattern symbol 1049 * generation on the port. 1050 * 1051 * What symbols are output on the port after this point is 1052 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 1053 * with the pipe being disabled, on older platforms it's HW specific if/how an 1054 * idle pattern is generated, as the pipe is already enabled here for those. 1055 * 1056 * This function must be called after intel_dp_start_link_train(). 1057 */ 1058 void intel_dp_stop_link_train(struct intel_dp *intel_dp, 1059 const struct intel_crtc_state *crtc_state) 1060 { 1061 intel_dp->link_trained = true; 1062 1063 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 1064 intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX, 1065 DP_TRAINING_PATTERN_DISABLE); 1066 1067 if (intel_dp_is_uhbr(crtc_state) && 1068 wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1069 lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n"); 1070 } 1071 } 1072 1073 static bool 1074 intel_dp_link_train_phy(struct intel_dp *intel_dp, 1075 const struct intel_crtc_state *crtc_state, 1076 enum drm_dp_phy dp_phy) 1077 { 1078 bool ret = false; 1079 1080 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 1081 goto out; 1082 1083 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 1084 goto out; 1085 1086 ret = true; 1087 1088 out: 1089 lt_dbg(intel_dp, dp_phy, 1090 "Link Training %s at link rate = %d, lane count = %d\n", 1091 ret ? "passed" : "failed", 1092 crtc_state->port_clock, crtc_state->lane_count); 1093 1094 return ret; 1095 } 1096 1097 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, 1098 int link_rate, 1099 u8 lane_count) 1100 { 1101 /* FIXME figure out what we actually want here */ 1102 const struct drm_display_mode *fixed_mode = 1103 intel_panel_preferred_fixed_mode(intel_dp->attached_connector); 1104 int mode_rate, max_rate; 1105 1106 mode_rate = intel_dp_link_required(fixed_mode->clock, 18); 1107 max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); 1108 if (mode_rate > max_rate) 1109 return false; 1110 1111 return true; 1112 } 1113 1114 static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) 1115 { 1116 int rate_index; 1117 int new_rate; 1118 1119 if (intel_dp->link.force_rate) 1120 return -1; 1121 1122 rate_index = intel_dp_rate_index(intel_dp->common_rates, 1123 intel_dp->num_common_rates, 1124 current_rate); 1125 1126 if (rate_index <= 0) 1127 return -1; 1128 1129 new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); 1130 1131 /* TODO: Make switching from UHBR to non-UHBR rates work. */ 1132 if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate)) 1133 return -1; 1134 1135 return new_rate; 1136 } 1137 1138 static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) 1139 { 1140 if (intel_dp->link.force_lane_count) 1141 return -1; 1142 1143 if (current_lane_count == 1) 1144 return -1; 1145 1146 return current_lane_count >> 1; 1147 } 1148 1149 static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 1150 const struct intel_crtc_state *crtc_state) 1151 { 1152 int new_link_rate; 1153 int new_lane_count; 1154 1155 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { 1156 lt_dbg(intel_dp, DP_PHY_DPRX, 1157 "Retrying Link training for eDP with max parameters\n"); 1158 intel_dp->use_max_params = true; 1159 return 0; 1160 } 1161 1162 new_lane_count = crtc_state->lane_count; 1163 new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); 1164 if (new_link_rate < 0) { 1165 new_lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); 1166 new_link_rate = intel_dp_max_common_rate(intel_dp); 1167 } 1168 1169 if (new_lane_count < 0) 1170 return -1; 1171 1172 if (intel_dp_is_edp(intel_dp) && 1173 !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { 1174 lt_dbg(intel_dp, DP_PHY_DPRX, 1175 "Retrying Link training for eDP with same parameters\n"); 1176 return 0; 1177 } 1178 1179 lt_dbg(intel_dp, DP_PHY_DPRX, 1180 "Reducing link parameters from %dx%d to %dx%d\n", 1181 crtc_state->lane_count, crtc_state->port_clock, 1182 new_lane_count, new_link_rate); 1183 1184 intel_dp->link.max_rate = new_link_rate; 1185 intel_dp->link.max_lane_count = new_lane_count; 1186 1187 return 0; 1188 } 1189 1190 /* NOTE: @state is only valid for MST links and can be %NULL for SST. */ 1191 static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, 1192 struct intel_dp *intel_dp, 1193 const struct intel_crtc_state *crtc_state) 1194 { 1195 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1196 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1197 1198 if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { 1199 lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); 1200 return true; 1201 } 1202 1203 if (intel_dp->hobl_active) { 1204 lt_dbg(intel_dp, DP_PHY_DPRX, 1205 "Link Training failed with HOBL active, not enabling it from now on\n"); 1206 intel_dp->hobl_failed = true; 1207 } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { 1208 return false; 1209 } 1210 1211 if (drm_WARN_ON(&i915->drm, 1212 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 1213 !state)) 1214 return false; 1215 1216 /* Schedule a Hotplug Uevent to userspace to start modeset */ 1217 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 1218 1219 return true; 1220 } 1221 1222 /* Perform the link training on all LTTPRs and the DPRX on a link. */ 1223 static bool 1224 intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 1225 const struct intel_crtc_state *crtc_state, 1226 int lttpr_count) 1227 { 1228 bool ret = true; 1229 int i; 1230 1231 for (i = lttpr_count - 1; i >= 0; i--) { 1232 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 1233 1234 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 1235 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 1236 1237 if (!ret) 1238 break; 1239 } 1240 1241 if (ret) 1242 ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 1243 1244 if (intel_dp->set_idle_link_train) 1245 intel_dp->set_idle_link_train(intel_dp, crtc_state); 1246 1247 return ret; 1248 } 1249 1250 /* 1251 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1) 1252 */ 1253 static bool 1254 intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, 1255 const struct intel_crtc_state *crtc_state) 1256 { 1257 u8 link_status[DP_LINK_STATUS_SIZE]; 1258 int delay_us; 1259 int try, max_tries = 20; 1260 unsigned long deadline; 1261 bool timeout = false; 1262 1263 /* 1264 * Reset signal levels. Start transmitting 128b/132b TPS1. 1265 * 1266 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1 1267 * in DP_TRAINING_PATTERN_SET. 1268 */ 1269 if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1270 DP_TRAINING_PATTERN_1)) { 1271 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n"); 1272 return false; 1273 } 1274 1275 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1276 1277 /* Read the initial TX FFE settings. */ 1278 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1279 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n"); 1280 return false; 1281 } 1282 1283 /* Update signal levels and training set as requested. */ 1284 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1285 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1286 lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n"); 1287 return false; 1288 } 1289 1290 /* Start transmitting 128b/132b TPS2. */ 1291 if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1292 DP_TRAINING_PATTERN_2)) { 1293 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n"); 1294 return false; 1295 } 1296 1297 /* Time budget for the LANEx_EQ_DONE Sequence */ 1298 deadline = jiffies + msecs_to_jiffies_timeout(400); 1299 1300 for (try = 0; try < max_tries; try++) { 1301 usleep_range(delay_us, 2 * delay_us); 1302 1303 /* 1304 * The delay may get updated. The transmitter shall read the 1305 * delay before link status during link training. 1306 */ 1307 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1308 1309 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1310 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1311 return false; 1312 } 1313 1314 if (drm_dp_128b132b_link_training_failed(link_status)) { 1315 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1316 lt_err(intel_dp, DP_PHY_DPRX, 1317 "Downstream link training failure\n"); 1318 return false; 1319 } 1320 1321 if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) { 1322 lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n"); 1323 break; 1324 } 1325 1326 if (timeout) { 1327 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1328 lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n"); 1329 return false; 1330 } 1331 1332 if (time_after(jiffies, deadline)) 1333 timeout = true; /* try one last time after deadline */ 1334 1335 /* Update signal levels and training set as requested. */ 1336 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1337 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1338 lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n"); 1339 return false; 1340 } 1341 } 1342 1343 if (try == max_tries) { 1344 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1345 lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n"); 1346 return false; 1347 } 1348 1349 for (;;) { 1350 if (time_after(jiffies, deadline)) 1351 timeout = true; /* try one last time after deadline */ 1352 1353 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1354 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1355 return false; 1356 } 1357 1358 if (drm_dp_128b132b_link_training_failed(link_status)) { 1359 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1360 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1361 return false; 1362 } 1363 1364 if (drm_dp_128b132b_eq_interlane_align_done(link_status)) { 1365 lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n"); 1366 break; 1367 } 1368 1369 if (timeout) { 1370 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1371 lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n"); 1372 return false; 1373 } 1374 1375 usleep_range(2000, 3000); 1376 } 1377 1378 return true; 1379 } 1380 1381 /* 1382 * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2) 1383 */ 1384 static bool 1385 intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp, 1386 const struct intel_crtc_state *crtc_state, 1387 int lttpr_count) 1388 { 1389 u8 link_status[DP_LINK_STATUS_SIZE]; 1390 unsigned long deadline; 1391 1392 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 1393 DP_TRAINING_PATTERN_2_CDS) != 1) { 1394 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n"); 1395 return false; 1396 } 1397 1398 /* Time budget for the LANEx_CDS_DONE Sequence */ 1399 deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20); 1400 1401 for (;;) { 1402 bool timeout = false; 1403 1404 if (time_after(jiffies, deadline)) 1405 timeout = true; /* try one last time after deadline */ 1406 1407 usleep_range(2000, 3000); 1408 1409 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1410 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1411 return false; 1412 } 1413 1414 if (drm_dp_128b132b_eq_interlane_align_done(link_status) && 1415 drm_dp_128b132b_cds_interlane_align_done(link_status) && 1416 drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) { 1417 lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n"); 1418 break; 1419 } 1420 1421 if (drm_dp_128b132b_link_training_failed(link_status)) { 1422 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1423 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1424 return false; 1425 } 1426 1427 if (timeout) { 1428 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1429 lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n"); 1430 return false; 1431 } 1432 } 1433 1434 return true; 1435 } 1436 1437 /* 1438 * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.) 1439 */ 1440 static bool 1441 intel_dp_128b132b_link_train(struct intel_dp *intel_dp, 1442 const struct intel_crtc_state *crtc_state, 1443 int lttpr_count) 1444 { 1445 bool passed = false; 1446 1447 if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1448 lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n"); 1449 return false; 1450 } 1451 1452 if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) && 1453 intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count)) 1454 passed = true; 1455 1456 lt_dbg(intel_dp, DP_PHY_DPRX, 1457 "128b/132b Link Training %s at link rate = %d, lane count = %d\n", 1458 passed ? "passed" : "failed", 1459 crtc_state->port_clock, crtc_state->lane_count); 1460 1461 return passed; 1462 } 1463 1464 /** 1465 * intel_dp_start_link_train - start link training 1466 * @state: Atomic state 1467 * @intel_dp: DP struct 1468 * @crtc_state: state for CRTC attached to the encoder 1469 * 1470 * Start the link training of the @intel_dp port, scheduling a fallback 1471 * retraining with reduced link rate/lane parameters if the link training 1472 * fails. 1473 * After calling this function intel_dp_stop_link_train() must be called. 1474 * 1475 * NOTE: @state is only valid for MST links and can be %NULL for SST. 1476 */ 1477 void intel_dp_start_link_train(struct intel_atomic_state *state, 1478 struct intel_dp *intel_dp, 1479 const struct intel_crtc_state *crtc_state) 1480 { 1481 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1482 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1483 struct intel_encoder *encoder = &dig_port->base; 1484 bool passed; 1485 1486 /* 1487 * TODO: Reiniting LTTPRs here won't be needed once proper connector 1488 * HW state readout is added. 1489 */ 1490 int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); 1491 1492 if (drm_WARN_ON(&i915->drm, 1493 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 1494 !state)) 1495 return; 1496 1497 if (lttpr_count < 0) 1498 /* Still continue with enabling the port and link training. */ 1499 lttpr_count = 0; 1500 1501 intel_dp_prepare_link_train(intel_dp, crtc_state); 1502 1503 if (intel_dp_is_uhbr(crtc_state)) 1504 passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count); 1505 else 1506 passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); 1507 1508 if (intel_dp->link.force_train_failure) { 1509 intel_dp->link.force_train_failure--; 1510 lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n"); 1511 } else if (passed) { 1512 intel_dp->link.seq_train_failures = 0; 1513 intel_encoder_link_check_queue_work(encoder, 2000); 1514 return; 1515 } 1516 1517 intel_dp->link.seq_train_failures++; 1518 1519 /* 1520 * Ignore the link failure in CI 1521 * 1522 * In fixed enviroments like CI, sometimes unexpected long HPDs are 1523 * generated by the displays. If ignore_long_hpd flag is set, such long 1524 * HPDs are ignored. And probably as a consequence of these ignored 1525 * long HPDs, subsequent link trainings are failed resulting into CI 1526 * execution failures. 1527 * 1528 * For test cases which rely on the link training or processing of HPDs 1529 * ignore_long_hpd flag can unset from the testcase. 1530 */ 1531 if (i915->display.hotplug.ignore_long_hpd) { 1532 lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n"); 1533 return; 1534 } 1535 1536 if (intel_dp->link.seq_train_failures < 2) { 1537 intel_encoder_link_check_queue_work(encoder, 0); 1538 return; 1539 } 1540 1541 if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state)) 1542 return; 1543 1544 intel_dp->link.retrain_disabled = true; 1545 1546 if (!passed) 1547 lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n"); 1548 else 1549 lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n"); 1550 } 1551 1552 void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, 1553 const struct intel_crtc_state *crtc_state) 1554 { 1555 /* 1556 * VIDEO_DIP_CTL register bit 31 should be set to '0' to not 1557 * disable SDP CRC. This is applicable for Display version 13. 1558 * Default value of bit 31 is '0' hence discarding the write 1559 * TODO: Corrective actions on SDP corruption yet to be defined 1560 */ 1561 if (!intel_dp_is_uhbr(crtc_state)) 1562 return; 1563 1564 /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ 1565 drm_dp_dpcd_writeb(&intel_dp->aux, 1566 DP_SDP_ERROR_DETECTION_CONFIGURATION, 1567 DP_SDP_CRC16_128B132B_EN); 1568 1569 lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n"); 1570 } 1571 1572 static struct intel_dp *intel_connector_to_intel_dp(struct intel_connector *connector) 1573 { 1574 if (connector->mst_port) 1575 return connector->mst_port; 1576 else 1577 return enc_to_intel_dp(intel_attached_encoder(connector)); 1578 } 1579 1580 static int i915_dp_force_link_rate_show(struct seq_file *m, void *data) 1581 { 1582 struct intel_connector *connector = to_intel_connector(m->private); 1583 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1584 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1585 int current_rate = -1; 1586 int force_rate; 1587 int err; 1588 int i; 1589 1590 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1591 if (err) 1592 return err; 1593 1594 if (intel_dp->link_trained) 1595 current_rate = intel_dp->link_rate; 1596 force_rate = intel_dp->link.force_rate; 1597 1598 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1599 1600 seq_printf(m, "%sauto%s", 1601 force_rate == 0 ? "[" : "", 1602 force_rate == 0 ? "]" : ""); 1603 1604 for (i = 0; i < intel_dp->num_source_rates; i++) 1605 seq_printf(m, " %s%d%s%s", 1606 intel_dp->source_rates[i] == force_rate ? "[" : "", 1607 intel_dp->source_rates[i], 1608 intel_dp->source_rates[i] == current_rate ? "*" : "", 1609 intel_dp->source_rates[i] == force_rate ? "]" : ""); 1610 1611 seq_putc(m, '\n'); 1612 1613 return 0; 1614 } 1615 1616 static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len) 1617 { 1618 char *kbuf; 1619 const char *p; 1620 int rate; 1621 int ret = 0; 1622 1623 kbuf = memdup_user_nul(ubuf, len); 1624 if (IS_ERR(kbuf)) 1625 return PTR_ERR(kbuf); 1626 1627 p = strim(kbuf); 1628 1629 if (!strcmp(p, "auto")) { 1630 rate = 0; 1631 } else { 1632 ret = kstrtoint(p, 0, &rate); 1633 if (ret < 0) 1634 goto out_free; 1635 1636 if (intel_dp_rate_index(intel_dp->source_rates, 1637 intel_dp->num_source_rates, 1638 rate) < 0) 1639 ret = -EINVAL; 1640 } 1641 1642 out_free: 1643 kfree(kbuf); 1644 1645 return ret < 0 ? ret : rate; 1646 } 1647 1648 static ssize_t i915_dp_force_link_rate_write(struct file *file, 1649 const char __user *ubuf, 1650 size_t len, loff_t *offp) 1651 { 1652 struct seq_file *m = file->private_data; 1653 struct intel_connector *connector = to_intel_connector(m->private); 1654 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1655 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1656 int rate; 1657 int err; 1658 1659 rate = parse_link_rate(intel_dp, ubuf, len); 1660 if (rate < 0) 1661 return rate; 1662 1663 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1664 if (err) 1665 return err; 1666 1667 intel_dp_reset_link_params(intel_dp); 1668 intel_dp->link.force_rate = rate; 1669 1670 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1671 1672 *offp += len; 1673 1674 return len; 1675 } 1676 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_link_rate); 1677 1678 static int i915_dp_force_lane_count_show(struct seq_file *m, void *data) 1679 { 1680 struct intel_connector *connector = to_intel_connector(m->private); 1681 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1682 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1683 int current_lane_count = -1; 1684 int force_lane_count; 1685 int err; 1686 int i; 1687 1688 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1689 if (err) 1690 return err; 1691 1692 if (intel_dp->link_trained) 1693 current_lane_count = intel_dp->lane_count; 1694 force_lane_count = intel_dp->link.force_lane_count; 1695 1696 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1697 1698 seq_printf(m, "%sauto%s", 1699 force_lane_count == 0 ? "[" : "", 1700 force_lane_count == 0 ? "]" : ""); 1701 1702 for (i = 1; i <= 4; i <<= 1) 1703 seq_printf(m, " %s%d%s%s", 1704 i == force_lane_count ? "[" : "", 1705 i, 1706 i == current_lane_count ? "*" : "", 1707 i == force_lane_count ? "]" : ""); 1708 1709 seq_putc(m, '\n'); 1710 1711 return 0; 1712 } 1713 1714 static int parse_lane_count(const char __user *ubuf, size_t len) 1715 { 1716 char *kbuf; 1717 const char *p; 1718 int lane_count; 1719 int ret = 0; 1720 1721 kbuf = memdup_user_nul(ubuf, len); 1722 if (IS_ERR(kbuf)) 1723 return PTR_ERR(kbuf); 1724 1725 p = strim(kbuf); 1726 1727 if (!strcmp(p, "auto")) { 1728 lane_count = 0; 1729 } else { 1730 ret = kstrtoint(p, 0, &lane_count); 1731 if (ret < 0) 1732 goto out_free; 1733 1734 switch (lane_count) { 1735 case 1: 1736 case 2: 1737 case 4: 1738 break; 1739 default: 1740 ret = -EINVAL; 1741 } 1742 } 1743 1744 out_free: 1745 kfree(kbuf); 1746 1747 return ret < 0 ? ret : lane_count; 1748 } 1749 1750 static ssize_t i915_dp_force_lane_count_write(struct file *file, 1751 const char __user *ubuf, 1752 size_t len, loff_t *offp) 1753 { 1754 struct seq_file *m = file->private_data; 1755 struct intel_connector *connector = to_intel_connector(m->private); 1756 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1757 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1758 int lane_count; 1759 int err; 1760 1761 lane_count = parse_lane_count(ubuf, len); 1762 if (lane_count < 0) 1763 return lane_count; 1764 1765 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1766 if (err) 1767 return err; 1768 1769 intel_dp_reset_link_params(intel_dp); 1770 intel_dp->link.force_lane_count = lane_count; 1771 1772 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1773 1774 *offp += len; 1775 1776 return len; 1777 } 1778 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_lane_count); 1779 1780 static int i915_dp_max_link_rate_show(void *data, u64 *val) 1781 { 1782 struct intel_connector *connector = to_intel_connector(data); 1783 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1784 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1785 int err; 1786 1787 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1788 if (err) 1789 return err; 1790 1791 *val = intel_dp->link.max_rate; 1792 1793 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1794 1795 return 0; 1796 } 1797 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_link_rate_fops, i915_dp_max_link_rate_show, NULL, "%llu\n"); 1798 1799 static int i915_dp_max_lane_count_show(void *data, u64 *val) 1800 { 1801 struct intel_connector *connector = to_intel_connector(data); 1802 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1803 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1804 int err; 1805 1806 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1807 if (err) 1808 return err; 1809 1810 *val = intel_dp->link.max_lane_count; 1811 1812 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1813 1814 return 0; 1815 } 1816 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n"); 1817 1818 static int i915_dp_force_link_training_failure_show(void *data, u64 *val) 1819 { 1820 struct intel_connector *connector = to_intel_connector(data); 1821 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1822 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1823 int err; 1824 1825 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1826 if (err) 1827 return err; 1828 1829 *val = intel_dp->link.force_train_failure; 1830 1831 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1832 1833 return 0; 1834 } 1835 1836 static int i915_dp_force_link_training_failure_write(void *data, u64 val) 1837 { 1838 struct intel_connector *connector = to_intel_connector(data); 1839 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1840 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1841 int err; 1842 1843 if (val > 2) 1844 return -EINVAL; 1845 1846 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1847 if (err) 1848 return err; 1849 1850 intel_dp->link.force_train_failure = val; 1851 1852 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1853 1854 return 0; 1855 } 1856 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, 1857 i915_dp_force_link_training_failure_show, 1858 i915_dp_force_link_training_failure_write, "%llu\n"); 1859 1860 static int i915_dp_force_link_retrain_show(void *data, u64 *val) 1861 { 1862 struct intel_connector *connector = to_intel_connector(data); 1863 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1864 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1865 int err; 1866 1867 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1868 if (err) 1869 return err; 1870 1871 *val = intel_dp->link.force_retrain; 1872 1873 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1874 1875 return 0; 1876 } 1877 1878 static int i915_dp_force_link_retrain_write(void *data, u64 val) 1879 { 1880 struct intel_connector *connector = to_intel_connector(data); 1881 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1882 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1883 int err; 1884 1885 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1886 if (err) 1887 return err; 1888 1889 intel_dp->link.force_retrain = val; 1890 1891 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1892 1893 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); 1894 1895 return 0; 1896 } 1897 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, 1898 i915_dp_force_link_retrain_show, 1899 i915_dp_force_link_retrain_write, "%llu\n"); 1900 1901 static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data) 1902 { 1903 struct intel_connector *connector = to_intel_connector(m->private); 1904 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1905 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1906 int err; 1907 1908 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1909 if (err) 1910 return err; 1911 1912 seq_printf(m, "%s\n", str_yes_no(intel_dp->link.retrain_disabled)); 1913 1914 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1915 1916 return 0; 1917 } 1918 DEFINE_SHOW_ATTRIBUTE(i915_dp_link_retrain_disabled); 1919 1920 void intel_dp_link_training_debugfs_add(struct intel_connector *connector) 1921 { 1922 struct dentry *root = connector->base.debugfs_entry; 1923 1924 if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort && 1925 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 1926 return; 1927 1928 debugfs_create_file("i915_dp_force_link_rate", 0644, root, 1929 connector, &i915_dp_force_link_rate_fops); 1930 1931 debugfs_create_file("i915_dp_force_lane_count", 0644, root, 1932 connector, &i915_dp_force_lane_count_fops); 1933 1934 debugfs_create_file("i915_dp_max_link_rate", 0444, root, 1935 connector, &i915_dp_max_link_rate_fops); 1936 1937 debugfs_create_file("i915_dp_max_lane_count", 0444, root, 1938 connector, &i915_dp_max_lane_count_fops); 1939 1940 debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, 1941 connector, &i915_dp_force_link_training_failure_fops); 1942 1943 debugfs_create_file("i915_dp_force_link_retrain", 0644, root, 1944 connector, &i915_dp_force_link_retrain_fops); 1945 1946 debugfs_create_file("i915_dp_link_retrain_disabled", 0444, root, 1947 connector, &i915_dp_link_retrain_disabled_fops); 1948 } 1949