1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <drm/display/drm_dp_helper.h> 25 26 #include "i915_drv.h" 27 #include "intel_display_types.h" 28 #include "intel_dp.h" 29 #include "intel_dp_link_training.h" 30 #include "intel_encoder.h" 31 #include "intel_hotplug.h" 32 #include "intel_panel.h" 33 34 #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " 35 #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \ 36 (_intel_dp)->attached_connector->base.name, \ 37 dp_to_dig_port(_intel_dp)->base.base.base.id, \ 38 dp_to_dig_port(_intel_dp)->base.base.name, \ 39 drm_dp_phy_name(_dp_phy) 40 41 #define lt_dbg(_intel_dp, _dp_phy, _format, ...) \ 42 drm_dbg_kms(&dp_to_i915(_intel_dp)->drm, \ 43 LT_MSG_PREFIX _format, \ 44 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__) 45 46 #define lt_err(_intel_dp, _dp_phy, _format, ...) do { \ 47 if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \ 48 drm_err(&dp_to_i915(_intel_dp)->drm, \ 49 LT_MSG_PREFIX _format, \ 50 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \ 51 else \ 52 lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \ 53 } while (0) 54 55 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) 56 { 57 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); 58 } 59 60 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 61 { 62 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 63 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 64 } 65 66 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 67 enum drm_dp_phy dp_phy) 68 { 69 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 70 } 71 72 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 73 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 74 enum drm_dp_phy dp_phy) 75 { 76 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 77 78 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { 79 lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n"); 80 return; 81 } 82 83 lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n", 84 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 85 phy_caps); 86 } 87 88 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, 89 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 90 { 91 int ret; 92 93 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, 94 intel_dp->lttpr_common_caps); 95 if (ret < 0) 96 goto reset_caps; 97 98 lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n", 99 (int)sizeof(intel_dp->lttpr_common_caps), 100 intel_dp->lttpr_common_caps); 101 102 /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ 103 if (intel_dp->lttpr_common_caps[0] < 0x14) 104 goto reset_caps; 105 106 return true; 107 108 reset_caps: 109 intel_dp_reset_lttpr_common_caps(intel_dp); 110 return false; 111 } 112 113 static bool 114 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 115 { 116 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 117 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 118 119 if (drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) != 1) 120 return false; 121 122 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 123 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val; 124 125 return true; 126 } 127 128 static bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp) 129 { 130 return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 131 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] == 132 DP_PHY_REPEATER_MODE_TRANSPARENT; 133 } 134 135 /* 136 * Read the LTTPR common capabilities and switch the LTTPR PHYs to 137 * non-transparent mode if this is supported. Preserve the 138 * transparent/non-transparent mode on an active link. 139 * 140 * Return the number of detected LTTPRs in non-transparent mode or 0 if the 141 * LTTPRs are in transparent mode or the detection failed. 142 */ 143 static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 144 { 145 int lttpr_count; 146 147 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) 148 return 0; 149 150 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 151 /* 152 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are 153 * detected as this breaks link training at least on the Dell WD19TB 154 * dock. 155 */ 156 if (lttpr_count == 0) 157 return 0; 158 159 /* 160 * Don't change the mode on an active link, to prevent a loss of link 161 * synchronization. See DP Standard v2.0 3.6.7. about the LTTPR 162 * resetting its internal state when the mode is changed from 163 * non-transparent to transparent. 164 */ 165 if (intel_dp->link_trained) { 166 if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp)) 167 goto out_reset_lttpr_count; 168 169 return lttpr_count; 170 } 171 172 /* 173 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of 174 * non-transparent mode and the disable->enable non-transparent mode 175 * sequence. 176 */ 177 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 178 179 /* 180 * In case of unsupported number of LTTPRs or failing to switch to 181 * non-transparent mode fall-back to transparent link training mode, 182 * still taking into account any LTTPR common lane- rate/count limits. 183 */ 184 if (lttpr_count < 0) 185 goto out_reset_lttpr_count; 186 187 if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { 188 lt_dbg(intel_dp, DP_PHY_DPRX, 189 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); 190 191 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 192 193 goto out_reset_lttpr_count; 194 } 195 196 return lttpr_count; 197 198 out_reset_lttpr_count: 199 intel_dp_reset_lttpr_count(intel_dp); 200 201 return 0; 202 } 203 204 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 205 { 206 int lttpr_count; 207 int i; 208 209 lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd); 210 211 for (i = 0; i < lttpr_count; i++) 212 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); 213 214 return lttpr_count; 215 } 216 217 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) 218 { 219 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 220 221 if (intel_dp_is_edp(intel_dp)) 222 return 0; 223 224 /* 225 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 226 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 227 */ 228 if (DISPLAY_VER(i915) >= 10 && !IS_GEMINILAKE(i915)) 229 if (drm_dp_dpcd_probe(&intel_dp->aux, 230 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV)) 231 return -EIO; 232 233 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) 234 return -EIO; 235 236 return 0; 237 } 238 239 /** 240 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode 241 * @intel_dp: Intel DP struct 242 * 243 * Read the LTTPR common and DPRX capabilities and switch to non-transparent 244 * link training mode if any is detected and read the PHY capabilities for all 245 * detected LTTPRs. In case of an LTTPR detection error or if the number of 246 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 247 * transparent mode link training mode. 248 * 249 * Returns: 250 * >0 if LTTPRs were detected and the non-transparent LT mode was set. The 251 * DPRX capabilities are read out. 252 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 253 * detection failure and the transparent LT mode was set. The DPRX 254 * capabilities are read out. 255 * <0 Reading out the DPRX capabilities failed. 256 */ 257 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) 258 { 259 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 260 int lttpr_count = 0; 261 262 /* 263 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 264 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 265 */ 266 if (!intel_dp_is_edp(intel_dp) && 267 (DISPLAY_VER(i915) >= 10 && !IS_GEMINILAKE(i915))) { 268 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 269 int err = intel_dp_read_dprx_caps(intel_dp, dpcd); 270 271 if (err != 0) 272 return err; 273 274 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); 275 } 276 277 /* 278 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read 279 * it here. 280 */ 281 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { 282 intel_dp_reset_lttpr_common_caps(intel_dp); 283 return -EIO; 284 } 285 286 return lttpr_count; 287 } 288 289 static u8 dp_voltage_max(u8 preemph) 290 { 291 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 292 case DP_TRAIN_PRE_EMPH_LEVEL_0: 293 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 294 case DP_TRAIN_PRE_EMPH_LEVEL_1: 295 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 296 case DP_TRAIN_PRE_EMPH_LEVEL_2: 297 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 298 case DP_TRAIN_PRE_EMPH_LEVEL_3: 299 default: 300 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 301 } 302 } 303 304 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 305 enum drm_dp_phy dp_phy) 306 { 307 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 308 309 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 310 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 311 else 312 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 313 } 314 315 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 316 enum drm_dp_phy dp_phy) 317 { 318 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 319 320 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 321 return DP_TRAIN_PRE_EMPH_LEVEL_3; 322 else 323 return DP_TRAIN_PRE_EMPH_LEVEL_2; 324 } 325 326 static bool 327 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 328 enum drm_dp_phy dp_phy) 329 { 330 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 331 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 332 333 drm_WARN_ON_ONCE(&i915->drm, lttpr_count <= 0 && dp_phy != DP_PHY_DPRX); 334 335 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 336 } 337 338 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 339 const struct intel_crtc_state *crtc_state, 340 enum drm_dp_phy dp_phy) 341 { 342 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 343 u8 voltage_max; 344 345 /* 346 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 347 * the DPRX_PHY we train. 348 */ 349 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 350 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 351 else 352 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 353 354 drm_WARN_ON_ONCE(&i915->drm, 355 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 356 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 357 358 return voltage_max; 359 } 360 361 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 362 enum drm_dp_phy dp_phy) 363 { 364 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 365 u8 preemph_max; 366 367 /* 368 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 369 * the DPRX_PHY we train. 370 */ 371 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 372 preemph_max = intel_dp->preemph_max(intel_dp); 373 else 374 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 375 376 drm_WARN_ON_ONCE(&i915->drm, 377 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 378 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 379 380 return preemph_max; 381 } 382 383 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, 384 enum drm_dp_phy dp_phy) 385 { 386 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 387 388 return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) || 389 DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915); 390 } 391 392 /* 128b/132b */ 393 static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp, 394 const struct intel_crtc_state *crtc_state, 395 enum drm_dp_phy dp_phy, 396 const u8 link_status[DP_LINK_STATUS_SIZE], 397 int lane) 398 { 399 u8 tx_ffe = 0; 400 401 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 402 lane = min(lane, crtc_state->lane_count - 1); 403 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); 404 } else { 405 for (lane = 0; lane < crtc_state->lane_count; lane++) 406 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); 407 } 408 409 return tx_ffe; 410 } 411 412 /* 8b/10b */ 413 static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp, 414 const struct intel_crtc_state *crtc_state, 415 enum drm_dp_phy dp_phy, 416 const u8 link_status[DP_LINK_STATUS_SIZE], 417 int lane) 418 { 419 u8 v = 0; 420 u8 p = 0; 421 u8 voltage_max; 422 u8 preemph_max; 423 424 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 425 lane = min(lane, crtc_state->lane_count - 1); 426 427 v = drm_dp_get_adjust_request_voltage(link_status, lane); 428 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 429 } else { 430 for (lane = 0; lane < crtc_state->lane_count; lane++) { 431 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 432 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 433 } 434 } 435 436 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 437 if (p >= preemph_max) 438 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 439 440 v = min(v, dp_voltage_max(p)); 441 442 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 443 if (v >= voltage_max) 444 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 445 446 return v | p; 447 } 448 449 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, 450 const struct intel_crtc_state *crtc_state, 451 enum drm_dp_phy dp_phy, 452 const u8 link_status[DP_LINK_STATUS_SIZE], 453 int lane) 454 { 455 if (intel_dp_is_uhbr(crtc_state)) 456 return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state, 457 dp_phy, link_status, lane); 458 else 459 return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state, 460 dp_phy, link_status, lane); 461 } 462 463 #define TRAIN_REQ_FMT "%d/%d/%d/%d" 464 #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \ 465 (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT) 466 #define TRAIN_REQ_VSWING_ARGS(link_status) \ 467 _TRAIN_REQ_VSWING_ARGS(link_status, 0), \ 468 _TRAIN_REQ_VSWING_ARGS(link_status, 1), \ 469 _TRAIN_REQ_VSWING_ARGS(link_status, 2), \ 470 _TRAIN_REQ_VSWING_ARGS(link_status, 3) 471 #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \ 472 (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT) 473 #define TRAIN_REQ_PREEMPH_ARGS(link_status) \ 474 _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \ 475 _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \ 476 _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \ 477 _TRAIN_REQ_PREEMPH_ARGS(link_status, 3) 478 #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \ 479 drm_dp_get_adjust_tx_ffe_preset((link_status), (lane)) 480 #define TRAIN_REQ_TX_FFE_ARGS(link_status) \ 481 _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \ 482 _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \ 483 _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \ 484 _TRAIN_REQ_TX_FFE_ARGS(link_status, 3) 485 486 void 487 intel_dp_get_adjust_train(struct intel_dp *intel_dp, 488 const struct intel_crtc_state *crtc_state, 489 enum drm_dp_phy dp_phy, 490 const u8 link_status[DP_LINK_STATUS_SIZE]) 491 { 492 int lane; 493 494 if (intel_dp_is_uhbr(crtc_state)) { 495 lt_dbg(intel_dp, dp_phy, 496 "128b/132b, lanes: %d, " 497 "TX FFE request: " TRAIN_REQ_FMT "\n", 498 crtc_state->lane_count, 499 TRAIN_REQ_TX_FFE_ARGS(link_status)); 500 } else { 501 lt_dbg(intel_dp, dp_phy, 502 "8b/10b, lanes: %d, " 503 "vswing request: " TRAIN_REQ_FMT ", " 504 "pre-emphasis request: " TRAIN_REQ_FMT "\n", 505 crtc_state->lane_count, 506 TRAIN_REQ_VSWING_ARGS(link_status), 507 TRAIN_REQ_PREEMPH_ARGS(link_status)); 508 } 509 510 for (lane = 0; lane < 4; lane++) 511 intel_dp->train_set[lane] = 512 intel_dp_get_lane_adjust_train(intel_dp, crtc_state, 513 dp_phy, link_status, lane); 514 } 515 516 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 517 enum drm_dp_phy dp_phy) 518 { 519 return dp_phy == DP_PHY_DPRX ? 520 DP_TRAINING_PATTERN_SET : 521 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 522 } 523 524 static bool 525 intel_dp_set_link_train(struct intel_dp *intel_dp, 526 const struct intel_crtc_state *crtc_state, 527 enum drm_dp_phy dp_phy, 528 u8 dp_train_pat) 529 { 530 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 531 u8 buf[sizeof(intel_dp->train_set) + 1]; 532 int len; 533 534 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 535 dp_phy, dp_train_pat); 536 537 buf[0] = dp_train_pat; 538 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 539 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 540 len = crtc_state->lane_count + 1; 541 542 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 543 } 544 545 static char dp_training_pattern_name(u8 train_pat) 546 { 547 switch (train_pat) { 548 case DP_TRAINING_PATTERN_1: 549 case DP_TRAINING_PATTERN_2: 550 case DP_TRAINING_PATTERN_3: 551 return '0' + train_pat; 552 case DP_TRAINING_PATTERN_4: 553 return '4'; 554 default: 555 MISSING_CASE(train_pat); 556 return '?'; 557 } 558 } 559 560 void 561 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 562 const struct intel_crtc_state *crtc_state, 563 enum drm_dp_phy dp_phy, 564 u8 dp_train_pat) 565 { 566 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat); 567 568 if (train_pat != DP_TRAINING_PATTERN_DISABLE) 569 lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n", 570 dp_training_pattern_name(train_pat)); 571 572 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); 573 } 574 575 #define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" 576 #define _TRAIN_SET_VSWING_ARGS(train_set) \ 577 ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ 578 (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" 579 #define TRAIN_SET_VSWING_ARGS(train_set) \ 580 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ 581 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ 582 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ 583 _TRAIN_SET_VSWING_ARGS((train_set)[3]) 584 #define _TRAIN_SET_PREEMPH_ARGS(train_set) \ 585 ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ 586 (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" 587 #define TRAIN_SET_PREEMPH_ARGS(train_set) \ 588 _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ 589 _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ 590 _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ 591 _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) 592 #define _TRAIN_SET_TX_FFE_ARGS(train_set) \ 593 ((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), "" 594 #define TRAIN_SET_TX_FFE_ARGS(train_set) \ 595 _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \ 596 _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \ 597 _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \ 598 _TRAIN_SET_TX_FFE_ARGS((train_set)[3]) 599 600 void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 601 const struct intel_crtc_state *crtc_state, 602 enum drm_dp_phy dp_phy) 603 { 604 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 605 606 if (intel_dp_is_uhbr(crtc_state)) { 607 lt_dbg(intel_dp, dp_phy, 608 "128b/132b, lanes: %d, " 609 "TX FFE presets: " TRAIN_SET_FMT "\n", 610 crtc_state->lane_count, 611 TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set)); 612 } else { 613 lt_dbg(intel_dp, dp_phy, 614 "8b/10b, lanes: %d, " 615 "vswing levels: " TRAIN_SET_FMT ", " 616 "pre-emphasis levels: " TRAIN_SET_FMT "\n", 617 crtc_state->lane_count, 618 TRAIN_SET_VSWING_ARGS(intel_dp->train_set), 619 TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set)); 620 } 621 622 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 623 encoder->set_signal_levels(encoder, crtc_state); 624 } 625 626 static bool 627 intel_dp_reset_link_train(struct intel_dp *intel_dp, 628 const struct intel_crtc_state *crtc_state, 629 enum drm_dp_phy dp_phy, 630 u8 dp_train_pat) 631 { 632 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 633 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 634 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 635 } 636 637 static bool 638 intel_dp_update_link_train(struct intel_dp *intel_dp, 639 const struct intel_crtc_state *crtc_state, 640 enum drm_dp_phy dp_phy) 641 { 642 int reg = dp_phy == DP_PHY_DPRX ? 643 DP_TRAINING_LANE0_SET : 644 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 645 int ret; 646 647 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 648 649 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 650 intel_dp->train_set, crtc_state->lane_count); 651 652 return ret == crtc_state->lane_count; 653 } 654 655 /* 128b/132b */ 656 static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane) 657 { 658 return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) == 659 DP_TX_FFE_PRESET_VALUE_MASK; 660 } 661 662 /* 663 * 8b/10b 664 * 665 * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to 666 * have self contradicting tests around this area. 667 * 668 * In lieu of better ideas let's just stop when we've reached the max supported 669 * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on 670 * whether vswing level 3 is supported or not. 671 */ 672 static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane) 673 { 674 u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 675 DP_TRAIN_VOLTAGE_SWING_SHIFT; 676 u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 677 DP_TRAIN_PRE_EMPHASIS_SHIFT; 678 679 if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0) 680 return false; 681 682 if (v + p != 3) 683 return false; 684 685 return true; 686 } 687 688 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 689 const struct intel_crtc_state *crtc_state) 690 { 691 int lane; 692 693 for (lane = 0; lane < crtc_state->lane_count; lane++) { 694 u8 train_set_lane = intel_dp->train_set[lane]; 695 696 if (intel_dp_is_uhbr(crtc_state)) { 697 if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane)) 698 return false; 699 } else { 700 if (!intel_dp_lane_max_vswing_reached(train_set_lane)) 701 return false; 702 } 703 } 704 705 return true; 706 } 707 708 void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr) 709 { 710 u8 link_config[2]; 711 712 link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 713 link_config[1] = drm_dp_is_uhbr_rate(link_rate) ? 714 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; 715 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 716 } 717 718 static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, 719 const struct intel_crtc_state *crtc_state) 720 { 721 intel_dp_link_training_set_mode(intel_dp, 722 crtc_state->port_clock, crtc_state->vrr.flipline); 723 } 724 725 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, 726 int link_bw, int rate_select, int lane_count, 727 bool enhanced_framing) 728 { 729 if (enhanced_framing) 730 lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 731 732 if (link_bw) { 733 /* DP and eDP v1.3 and earlier link bw set method. */ 734 u8 link_config[] = { link_bw, lane_count }; 735 736 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 737 ARRAY_SIZE(link_config)); 738 } else { 739 /* 740 * eDP v1.4 and later link rate set method. 741 * 742 * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if 743 * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET. 744 * 745 * eDP v1.5 sinks allow choosing either, and the last choice 746 * shall be active. 747 */ 748 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count); 749 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select); 750 } 751 } 752 753 static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp, 754 const struct intel_crtc_state *crtc_state, 755 u8 link_bw, u8 rate_select) 756 { 757 intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count, 758 crtc_state->enhanced_framing); 759 } 760 761 /* 762 * Prepare link training by configuring the link parameters. On DDI platforms 763 * also enable the port here. 764 */ 765 static bool 766 intel_dp_prepare_link_train(struct intel_dp *intel_dp, 767 const struct intel_crtc_state *crtc_state) 768 { 769 u8 link_bw, rate_select; 770 771 if (intel_dp->prepare_link_retrain) 772 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 773 774 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 775 &link_bw, &rate_select); 776 777 /* 778 * WaEdpLinkRateDataReload 779 * 780 * Parade PS8461E MUX (used on varius TGL+ laptops) needs 781 * to snoop the link rates reported by the sink when we 782 * use LINK_RATE_SET in order to operate in jitter cleaning 783 * mode (as opposed to redriver mode). Unfortunately it 784 * loses track of the snooped link rates when powered down, 785 * so we need to make it re-snoop often. Without this high 786 * link rates are not stable. 787 */ 788 if (!link_bw) { 789 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 790 791 lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n"); 792 793 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 794 sink_rates, sizeof(sink_rates)); 795 } 796 797 if (link_bw) 798 lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n", 799 link_bw); 800 else 801 lt_dbg(intel_dp, DP_PHY_DPRX, 802 "Using LINK_RATE_SET value %02x\n", 803 rate_select); 804 /* 805 * Spec DP2.1 Section 3.5.2.16 806 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate 807 */ 808 intel_dp_update_downspread_ctrl(intel_dp, crtc_state); 809 intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw, 810 rate_select); 811 812 return true; 813 } 814 815 static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state, 816 const u8 old_link_status[DP_LINK_STATUS_SIZE], 817 const u8 new_link_status[DP_LINK_STATUS_SIZE]) 818 { 819 int lane; 820 821 for (lane = 0; lane < crtc_state->lane_count; lane++) { 822 u8 old, new; 823 824 if (intel_dp_is_uhbr(crtc_state)) { 825 old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane); 826 new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane); 827 } else { 828 old = drm_dp_get_adjust_request_voltage(old_link_status, lane) | 829 drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane); 830 new = drm_dp_get_adjust_request_voltage(new_link_status, lane) | 831 drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane); 832 } 833 834 if (old != new) 835 return true; 836 } 837 838 return false; 839 } 840 841 void 842 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy, 843 const u8 link_status[DP_LINK_STATUS_SIZE]) 844 { 845 lt_dbg(intel_dp, dp_phy, 846 "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n", 847 link_status[0], link_status[1], link_status[2], 848 link_status[3], link_status[4], link_status[5]); 849 } 850 851 /* 852 * Perform the link training clock recovery phase on the given DP PHY using 853 * training pattern 1. 854 */ 855 static bool 856 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 857 const struct intel_crtc_state *crtc_state, 858 enum drm_dp_phy dp_phy) 859 { 860 u8 old_link_status[DP_LINK_STATUS_SIZE] = {}; 861 int voltage_tries, cr_tries, max_cr_tries; 862 u8 link_status[DP_LINK_STATUS_SIZE]; 863 bool max_vswing_reached = false; 864 int delay_us; 865 866 delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux, 867 intel_dp->dpcd, dp_phy, 868 intel_dp_is_uhbr(crtc_state)); 869 870 /* clock recovery */ 871 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 872 DP_TRAINING_PATTERN_1 | 873 DP_LINK_SCRAMBLING_DISABLE)) { 874 lt_err(intel_dp, dp_phy, "Failed to enable link training\n"); 875 return false; 876 } 877 878 /* 879 * The DP 1.4 spec defines the max clock recovery retries value 880 * as 10 but for pre-DP 1.4 devices we set a very tolerant 881 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 882 * x 5 identical voltage retries). Since the previous specs didn't 883 * define a limit and created the possibility of an infinite loop 884 * we want to prevent any sync from triggering that corner case. 885 */ 886 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 887 max_cr_tries = 10; 888 else 889 max_cr_tries = 80; 890 891 voltage_tries = 1; 892 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 893 usleep_range(delay_us, 2 * delay_us); 894 895 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 896 link_status) < 0) { 897 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 898 return false; 899 } 900 901 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 902 lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n"); 903 return true; 904 } 905 906 if (voltage_tries == 5) { 907 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 908 lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n"); 909 return false; 910 } 911 912 if (max_vswing_reached) { 913 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 914 lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n"); 915 return false; 916 } 917 918 /* Update training set as requested by target */ 919 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 920 link_status); 921 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 922 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 923 return false; 924 } 925 926 if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status)) 927 ++voltage_tries; 928 else 929 voltage_tries = 1; 930 931 memcpy(old_link_status, link_status, sizeof(link_status)); 932 933 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 934 max_vswing_reached = true; 935 } 936 937 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 938 lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n", 939 max_cr_tries); 940 941 return false; 942 } 943 944 /* 945 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 946 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or 947 * 1.2 devices that support it, TPS2 otherwise. 948 */ 949 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 950 const struct intel_crtc_state *crtc_state, 951 enum drm_dp_phy dp_phy) 952 { 953 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 954 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 955 956 /* UHBR+ use separate 128b/132b TPS2 */ 957 if (intel_dp_is_uhbr(crtc_state)) 958 return DP_TRAINING_PATTERN_2; 959 960 /* 961 * TPS4 support is mandatory for all downstream devices that 962 * support HBR3. There are no known eDP panels that support 963 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification. 964 * LTTPRs must support TPS4. 965 */ 966 source_tps4 = intel_dp_source_supports_tps4(i915); 967 sink_tps4 = dp_phy != DP_PHY_DPRX || 968 drm_dp_tps4_supported(intel_dp->dpcd); 969 if (source_tps4 && sink_tps4) { 970 return DP_TRAINING_PATTERN_4; 971 } else if (crtc_state->port_clock == 810000) { 972 if (!source_tps4) 973 lt_dbg(intel_dp, dp_phy, 974 "8.1 Gbps link rate without source TPS4 support\n"); 975 if (!sink_tps4) 976 lt_dbg(intel_dp, dp_phy, 977 "8.1 Gbps link rate without sink TPS4 support\n"); 978 } 979 980 /* 981 * TPS3 support is mandatory for downstream devices that 982 * support HBR2. However, not all sinks follow the spec. 983 */ 984 source_tps3 = intel_dp_source_supports_tps3(i915); 985 sink_tps3 = dp_phy != DP_PHY_DPRX || 986 drm_dp_tps3_supported(intel_dp->dpcd); 987 if (source_tps3 && sink_tps3) { 988 return DP_TRAINING_PATTERN_3; 989 } else if (crtc_state->port_clock >= 540000) { 990 if (!source_tps3) 991 lt_dbg(intel_dp, dp_phy, 992 ">=5.4/6.48 Gbps link rate without source TPS3 support\n"); 993 if (!sink_tps3) 994 lt_dbg(intel_dp, dp_phy, 995 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 996 } 997 998 return DP_TRAINING_PATTERN_2; 999 } 1000 1001 /* 1002 * Perform the link training channel equalization phase on the given DP PHY 1003 * using one of training pattern 2, 3 or 4 depending on the source and 1004 * sink capabilities. 1005 */ 1006 static bool 1007 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 1008 const struct intel_crtc_state *crtc_state, 1009 enum drm_dp_phy dp_phy) 1010 { 1011 int tries; 1012 u32 training_pattern; 1013 u8 link_status[DP_LINK_STATUS_SIZE]; 1014 bool channel_eq = false; 1015 int delay_us; 1016 1017 delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux, 1018 intel_dp->dpcd, dp_phy, 1019 intel_dp_is_uhbr(crtc_state)); 1020 1021 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 1022 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 1023 if (training_pattern != DP_TRAINING_PATTERN_4) 1024 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 1025 1026 /* channel equalization */ 1027 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 1028 training_pattern)) { 1029 lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n"); 1030 return false; 1031 } 1032 1033 for (tries = 0; tries < 5; tries++) { 1034 usleep_range(delay_us, 2 * delay_us); 1035 1036 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 1037 link_status) < 0) { 1038 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 1039 break; 1040 } 1041 1042 /* Make sure clock is still ok */ 1043 if (!drm_dp_clock_recovery_ok(link_status, 1044 crtc_state->lane_count)) { 1045 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1046 lt_dbg(intel_dp, dp_phy, 1047 "Clock recovery check failed, cannot continue channel equalization\n"); 1048 break; 1049 } 1050 1051 if (drm_dp_channel_eq_ok(link_status, 1052 crtc_state->lane_count)) { 1053 channel_eq = true; 1054 lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n"); 1055 break; 1056 } 1057 1058 /* Update training set as requested by target */ 1059 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 1060 link_status); 1061 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 1062 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 1063 break; 1064 } 1065 } 1066 1067 /* Try 5 times, else fail and try at lower BW */ 1068 if (tries == 5) { 1069 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1070 lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n"); 1071 } 1072 1073 return channel_eq; 1074 } 1075 1076 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 1077 enum drm_dp_phy dp_phy) 1078 { 1079 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 1080 u8 val = DP_TRAINING_PATTERN_DISABLE; 1081 1082 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 1083 } 1084 1085 static int 1086 intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp, 1087 const struct intel_crtc_state *crtc_state) 1088 { 1089 u8 sink_status; 1090 int ret; 1091 1092 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status); 1093 if (ret != 1) { 1094 lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n"); 1095 return ret < 0 ? ret : -EIO; 1096 } 1097 1098 return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0; 1099 } 1100 1101 /** 1102 * intel_dp_stop_link_train - stop link training 1103 * @intel_dp: DP struct 1104 * @crtc_state: state for CRTC attached to the encoder 1105 * 1106 * Stop the link training of the @intel_dp port, disabling the training 1107 * pattern in the sink's DPCD, and disabling the test pattern symbol 1108 * generation on the port. 1109 * 1110 * What symbols are output on the port after this point is 1111 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 1112 * with the pipe being disabled, on older platforms it's HW specific if/how an 1113 * idle pattern is generated, as the pipe is already enabled here for those. 1114 * 1115 * This function must be called after intel_dp_start_link_train(). 1116 */ 1117 void intel_dp_stop_link_train(struct intel_dp *intel_dp, 1118 const struct intel_crtc_state *crtc_state) 1119 { 1120 intel_dp->link_trained = true; 1121 1122 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 1123 intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX, 1124 DP_TRAINING_PATTERN_DISABLE); 1125 1126 if (intel_dp_is_uhbr(crtc_state) && 1127 wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1128 lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n"); 1129 } 1130 } 1131 1132 static bool 1133 intel_dp_link_train_phy(struct intel_dp *intel_dp, 1134 const struct intel_crtc_state *crtc_state, 1135 enum drm_dp_phy dp_phy) 1136 { 1137 bool ret = false; 1138 1139 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 1140 goto out; 1141 1142 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 1143 goto out; 1144 1145 ret = true; 1146 1147 out: 1148 lt_dbg(intel_dp, dp_phy, 1149 "Link Training %s at link rate = %d, lane count = %d\n", 1150 ret ? "passed" : "failed", 1151 crtc_state->port_clock, crtc_state->lane_count); 1152 1153 return ret; 1154 } 1155 1156 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, 1157 int link_rate, 1158 u8 lane_count) 1159 { 1160 /* FIXME figure out what we actually want here */ 1161 const struct drm_display_mode *fixed_mode = 1162 intel_panel_preferred_fixed_mode(intel_dp->attached_connector); 1163 int mode_rate, max_rate; 1164 1165 mode_rate = intel_dp_link_required(fixed_mode->clock, 18); 1166 max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); 1167 if (mode_rate > max_rate) 1168 return false; 1169 1170 return true; 1171 } 1172 1173 static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp, 1174 const struct intel_crtc_state *crtc_state, 1175 int *new_link_rate, int *new_lane_count) 1176 { 1177 int link_rate; 1178 int lane_count; 1179 int i; 1180 1181 i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 1182 for (i--; i >= 0; i--) { 1183 intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count); 1184 1185 if ((intel_dp->link.force_rate && 1186 intel_dp->link.force_rate != link_rate) || 1187 (intel_dp->link.force_lane_count && 1188 intel_dp->link.force_lane_count != lane_count)) 1189 continue; 1190 1191 break; 1192 } 1193 1194 if (i < 0) 1195 return false; 1196 1197 *new_link_rate = link_rate; 1198 *new_lane_count = lane_count; 1199 1200 return true; 1201 } 1202 1203 static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) 1204 { 1205 int rate_index; 1206 int new_rate; 1207 1208 if (intel_dp->link.force_rate) 1209 return -1; 1210 1211 rate_index = intel_dp_rate_index(intel_dp->common_rates, 1212 intel_dp->num_common_rates, 1213 current_rate); 1214 1215 if (rate_index <= 0) 1216 return -1; 1217 1218 new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); 1219 1220 /* TODO: Make switching from UHBR to non-UHBR rates work. */ 1221 if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate)) 1222 return -1; 1223 1224 return new_rate; 1225 } 1226 1227 static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) 1228 { 1229 if (intel_dp->link.force_lane_count) 1230 return -1; 1231 1232 if (current_lane_count == 1) 1233 return -1; 1234 1235 return current_lane_count >> 1; 1236 } 1237 1238 static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp, 1239 const struct intel_crtc_state *crtc_state, 1240 int *new_link_rate, int *new_lane_count) 1241 { 1242 int link_rate; 1243 int lane_count; 1244 1245 lane_count = crtc_state->lane_count; 1246 link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); 1247 if (link_rate < 0) { 1248 lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); 1249 link_rate = intel_dp_max_common_rate(intel_dp); 1250 } 1251 1252 if (lane_count < 0) 1253 return false; 1254 1255 *new_link_rate = link_rate; 1256 *new_lane_count = lane_count; 1257 1258 return true; 1259 } 1260 1261 static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, 1262 int *new_link_rate, int *new_lane_count) 1263 { 1264 /* TODO: Use the same fallback logic on SST as on MST. */ 1265 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 1266 return reduce_link_params_in_bw_order(intel_dp, crtc_state, 1267 new_link_rate, new_lane_count); 1268 else 1269 return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state, 1270 new_link_rate, new_lane_count); 1271 } 1272 1273 static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 1274 const struct intel_crtc_state *crtc_state) 1275 { 1276 int new_link_rate; 1277 int new_lane_count; 1278 1279 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { 1280 lt_dbg(intel_dp, DP_PHY_DPRX, 1281 "Retrying Link training for eDP with max parameters\n"); 1282 intel_dp->use_max_params = true; 1283 return 0; 1284 } 1285 1286 if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count)) 1287 return -1; 1288 1289 if (intel_dp_is_edp(intel_dp) && 1290 !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { 1291 lt_dbg(intel_dp, DP_PHY_DPRX, 1292 "Retrying Link training for eDP with same parameters\n"); 1293 return 0; 1294 } 1295 1296 lt_dbg(intel_dp, DP_PHY_DPRX, 1297 "Reducing link parameters from %dx%d to %dx%d\n", 1298 crtc_state->lane_count, crtc_state->port_clock, 1299 new_lane_count, new_link_rate); 1300 1301 intel_dp->link.max_rate = new_link_rate; 1302 intel_dp->link.max_lane_count = new_lane_count; 1303 1304 return 0; 1305 } 1306 1307 static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, 1308 struct intel_dp *intel_dp, 1309 const struct intel_crtc_state *crtc_state) 1310 { 1311 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1312 1313 if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { 1314 lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); 1315 return true; 1316 } 1317 1318 if (intel_dp->hobl_active) { 1319 lt_dbg(intel_dp, DP_PHY_DPRX, 1320 "Link Training failed with HOBL active, not enabling it from now on\n"); 1321 intel_dp->hobl_failed = true; 1322 } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { 1323 return false; 1324 } 1325 1326 /* Schedule a Hotplug Uevent to userspace to start modeset */ 1327 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 1328 1329 return true; 1330 } 1331 1332 /* Perform the link training on all LTTPRs and the DPRX on a link. */ 1333 static bool 1334 intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 1335 const struct intel_crtc_state *crtc_state, 1336 int lttpr_count) 1337 { 1338 bool ret = true; 1339 int i; 1340 1341 for (i = lttpr_count - 1; i >= 0; i--) { 1342 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 1343 1344 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 1345 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 1346 1347 if (!ret) 1348 break; 1349 } 1350 1351 if (ret) 1352 ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 1353 1354 if (intel_dp->set_idle_link_train) 1355 intel_dp->set_idle_link_train(intel_dp, crtc_state); 1356 1357 return ret; 1358 } 1359 1360 /* 1361 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1) 1362 */ 1363 static bool 1364 intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, 1365 const struct intel_crtc_state *crtc_state) 1366 { 1367 u8 link_status[DP_LINK_STATUS_SIZE]; 1368 int delay_us; 1369 int try, max_tries = 20; 1370 unsigned long deadline; 1371 bool timeout = false; 1372 1373 /* 1374 * Reset signal levels. Start transmitting 128b/132b TPS1. 1375 * 1376 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1 1377 * in DP_TRAINING_PATTERN_SET. 1378 */ 1379 if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1380 DP_TRAINING_PATTERN_1)) { 1381 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n"); 1382 return false; 1383 } 1384 1385 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1386 1387 /* Read the initial TX FFE settings. */ 1388 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1389 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n"); 1390 return false; 1391 } 1392 1393 /* Update signal levels and training set as requested. */ 1394 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1395 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1396 lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n"); 1397 return false; 1398 } 1399 1400 /* Start transmitting 128b/132b TPS2. */ 1401 if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1402 DP_TRAINING_PATTERN_2)) { 1403 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n"); 1404 return false; 1405 } 1406 1407 /* Time budget for the LANEx_EQ_DONE Sequence */ 1408 deadline = jiffies + msecs_to_jiffies_timeout(400); 1409 1410 for (try = 0; try < max_tries; try++) { 1411 usleep_range(delay_us, 2 * delay_us); 1412 1413 /* 1414 * The delay may get updated. The transmitter shall read the 1415 * delay before link status during link training. 1416 */ 1417 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1418 1419 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1420 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1421 return false; 1422 } 1423 1424 if (drm_dp_128b132b_link_training_failed(link_status)) { 1425 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1426 lt_err(intel_dp, DP_PHY_DPRX, 1427 "Downstream link training failure\n"); 1428 return false; 1429 } 1430 1431 if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) { 1432 lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n"); 1433 break; 1434 } 1435 1436 if (timeout) { 1437 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1438 lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n"); 1439 return false; 1440 } 1441 1442 if (time_after(jiffies, deadline)) 1443 timeout = true; /* try one last time after deadline */ 1444 1445 /* Update signal levels and training set as requested. */ 1446 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1447 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1448 lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n"); 1449 return false; 1450 } 1451 } 1452 1453 if (try == max_tries) { 1454 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1455 lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n"); 1456 return false; 1457 } 1458 1459 for (;;) { 1460 if (time_after(jiffies, deadline)) 1461 timeout = true; /* try one last time after deadline */ 1462 1463 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1464 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1465 return false; 1466 } 1467 1468 if (drm_dp_128b132b_link_training_failed(link_status)) { 1469 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1470 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1471 return false; 1472 } 1473 1474 if (drm_dp_128b132b_eq_interlane_align_done(link_status)) { 1475 lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n"); 1476 break; 1477 } 1478 1479 if (timeout) { 1480 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1481 lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n"); 1482 return false; 1483 } 1484 1485 usleep_range(2000, 3000); 1486 } 1487 1488 return true; 1489 } 1490 1491 /* 1492 * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2) 1493 */ 1494 static bool 1495 intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp, 1496 const struct intel_crtc_state *crtc_state, 1497 int lttpr_count) 1498 { 1499 u8 link_status[DP_LINK_STATUS_SIZE]; 1500 unsigned long deadline; 1501 1502 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 1503 DP_TRAINING_PATTERN_2_CDS) != 1) { 1504 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n"); 1505 return false; 1506 } 1507 1508 /* Time budget for the LANEx_CDS_DONE Sequence */ 1509 deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20); 1510 1511 for (;;) { 1512 bool timeout = false; 1513 1514 if (time_after(jiffies, deadline)) 1515 timeout = true; /* try one last time after deadline */ 1516 1517 usleep_range(2000, 3000); 1518 1519 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1520 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1521 return false; 1522 } 1523 1524 if (drm_dp_128b132b_eq_interlane_align_done(link_status) && 1525 drm_dp_128b132b_cds_interlane_align_done(link_status) && 1526 drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) { 1527 lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n"); 1528 break; 1529 } 1530 1531 if (drm_dp_128b132b_link_training_failed(link_status)) { 1532 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1533 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1534 return false; 1535 } 1536 1537 if (timeout) { 1538 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1539 lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n"); 1540 return false; 1541 } 1542 } 1543 1544 return true; 1545 } 1546 1547 /* 1548 * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.) 1549 */ 1550 static bool 1551 intel_dp_128b132b_link_train(struct intel_dp *intel_dp, 1552 const struct intel_crtc_state *crtc_state, 1553 int lttpr_count) 1554 { 1555 bool passed = false; 1556 1557 if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1558 lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n"); 1559 return false; 1560 } 1561 1562 if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) && 1563 intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count)) 1564 passed = true; 1565 1566 lt_dbg(intel_dp, DP_PHY_DPRX, 1567 "128b/132b Link Training %s at link rate = %d, lane count = %d\n", 1568 passed ? "passed" : "failed", 1569 crtc_state->port_clock, crtc_state->lane_count); 1570 1571 return passed; 1572 } 1573 1574 /** 1575 * intel_dp_start_link_train - start link training 1576 * @state: Atomic state 1577 * @intel_dp: DP struct 1578 * @crtc_state: state for CRTC attached to the encoder 1579 * 1580 * Start the link training of the @intel_dp port, scheduling a fallback 1581 * retraining with reduced link rate/lane parameters if the link training 1582 * fails. 1583 * After calling this function intel_dp_stop_link_train() must be called. 1584 */ 1585 void intel_dp_start_link_train(struct intel_atomic_state *state, 1586 struct intel_dp *intel_dp, 1587 const struct intel_crtc_state *crtc_state) 1588 { 1589 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1590 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1591 struct intel_encoder *encoder = &dig_port->base; 1592 bool passed; 1593 /* 1594 * Reinit the LTTPRs here to ensure that they are switched to 1595 * non-transparent mode. During an earlier LTTPR detection this 1596 * could've been prevented by an active link. 1597 */ 1598 int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); 1599 1600 if (lttpr_count < 0) 1601 /* Still continue with enabling the port and link training. */ 1602 lttpr_count = 0; 1603 1604 intel_dp_prepare_link_train(intel_dp, crtc_state); 1605 1606 if (intel_dp_is_uhbr(crtc_state)) 1607 passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count); 1608 else 1609 passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); 1610 1611 if (intel_dp->link.force_train_failure) { 1612 intel_dp->link.force_train_failure--; 1613 lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n"); 1614 } else if (passed) { 1615 intel_dp->link.seq_train_failures = 0; 1616 intel_encoder_link_check_queue_work(encoder, 2000); 1617 return; 1618 } 1619 1620 intel_dp->link.seq_train_failures++; 1621 1622 /* 1623 * Ignore the link failure in CI 1624 * 1625 * In fixed enviroments like CI, sometimes unexpected long HPDs are 1626 * generated by the displays. If ignore_long_hpd flag is set, such long 1627 * HPDs are ignored. And probably as a consequence of these ignored 1628 * long HPDs, subsequent link trainings are failed resulting into CI 1629 * execution failures. 1630 * 1631 * For test cases which rely on the link training or processing of HPDs 1632 * ignore_long_hpd flag can unset from the testcase. 1633 */ 1634 if (i915->display.hotplug.ignore_long_hpd) { 1635 lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n"); 1636 return; 1637 } 1638 1639 if (intel_dp->link.seq_train_failures < 2) { 1640 intel_encoder_link_check_queue_work(encoder, 0); 1641 return; 1642 } 1643 1644 if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state)) 1645 return; 1646 1647 intel_dp->link.retrain_disabled = true; 1648 1649 if (!passed) 1650 lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n"); 1651 else 1652 lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n"); 1653 } 1654 1655 void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, 1656 const struct intel_crtc_state *crtc_state) 1657 { 1658 /* 1659 * VIDEO_DIP_CTL register bit 31 should be set to '0' to not 1660 * disable SDP CRC. This is applicable for Display version 13. 1661 * Default value of bit 31 is '0' hence discarding the write 1662 * TODO: Corrective actions on SDP corruption yet to be defined 1663 */ 1664 if (!intel_dp_is_uhbr(crtc_state)) 1665 return; 1666 1667 /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ 1668 drm_dp_dpcd_writeb(&intel_dp->aux, 1669 DP_SDP_ERROR_DETECTION_CONFIGURATION, 1670 DP_SDP_CRC16_128B132B_EN); 1671 1672 lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n"); 1673 } 1674 1675 static struct intel_dp *intel_connector_to_intel_dp(struct intel_connector *connector) 1676 { 1677 if (connector->mst_port) 1678 return connector->mst_port; 1679 else 1680 return enc_to_intel_dp(intel_attached_encoder(connector)); 1681 } 1682 1683 static int i915_dp_force_link_rate_show(struct seq_file *m, void *data) 1684 { 1685 struct intel_connector *connector = to_intel_connector(m->private); 1686 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1687 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1688 int current_rate = -1; 1689 int force_rate; 1690 int err; 1691 int i; 1692 1693 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1694 if (err) 1695 return err; 1696 1697 if (intel_dp->link_trained) 1698 current_rate = intel_dp->link_rate; 1699 force_rate = intel_dp->link.force_rate; 1700 1701 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1702 1703 seq_printf(m, "%sauto%s", 1704 force_rate == 0 ? "[" : "", 1705 force_rate == 0 ? "]" : ""); 1706 1707 for (i = 0; i < intel_dp->num_source_rates; i++) 1708 seq_printf(m, " %s%d%s%s", 1709 intel_dp->source_rates[i] == force_rate ? "[" : "", 1710 intel_dp->source_rates[i], 1711 intel_dp->source_rates[i] == current_rate ? "*" : "", 1712 intel_dp->source_rates[i] == force_rate ? "]" : ""); 1713 1714 seq_putc(m, '\n'); 1715 1716 return 0; 1717 } 1718 1719 static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len) 1720 { 1721 char *kbuf; 1722 const char *p; 1723 int rate; 1724 int ret = 0; 1725 1726 kbuf = memdup_user_nul(ubuf, len); 1727 if (IS_ERR(kbuf)) 1728 return PTR_ERR(kbuf); 1729 1730 p = strim(kbuf); 1731 1732 if (!strcmp(p, "auto")) { 1733 rate = 0; 1734 } else { 1735 ret = kstrtoint(p, 0, &rate); 1736 if (ret < 0) 1737 goto out_free; 1738 1739 if (intel_dp_rate_index(intel_dp->source_rates, 1740 intel_dp->num_source_rates, 1741 rate) < 0) 1742 ret = -EINVAL; 1743 } 1744 1745 out_free: 1746 kfree(kbuf); 1747 1748 return ret < 0 ? ret : rate; 1749 } 1750 1751 static ssize_t i915_dp_force_link_rate_write(struct file *file, 1752 const char __user *ubuf, 1753 size_t len, loff_t *offp) 1754 { 1755 struct seq_file *m = file->private_data; 1756 struct intel_connector *connector = to_intel_connector(m->private); 1757 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1758 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1759 int rate; 1760 int err; 1761 1762 rate = parse_link_rate(intel_dp, ubuf, len); 1763 if (rate < 0) 1764 return rate; 1765 1766 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1767 if (err) 1768 return err; 1769 1770 intel_dp_reset_link_params(intel_dp); 1771 intel_dp->link.force_rate = rate; 1772 1773 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1774 1775 *offp += len; 1776 1777 return len; 1778 } 1779 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_link_rate); 1780 1781 static int i915_dp_force_lane_count_show(struct seq_file *m, void *data) 1782 { 1783 struct intel_connector *connector = to_intel_connector(m->private); 1784 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1785 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1786 int current_lane_count = -1; 1787 int force_lane_count; 1788 int err; 1789 int i; 1790 1791 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1792 if (err) 1793 return err; 1794 1795 if (intel_dp->link_trained) 1796 current_lane_count = intel_dp->lane_count; 1797 force_lane_count = intel_dp->link.force_lane_count; 1798 1799 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1800 1801 seq_printf(m, "%sauto%s", 1802 force_lane_count == 0 ? "[" : "", 1803 force_lane_count == 0 ? "]" : ""); 1804 1805 for (i = 1; i <= 4; i <<= 1) 1806 seq_printf(m, " %s%d%s%s", 1807 i == force_lane_count ? "[" : "", 1808 i, 1809 i == current_lane_count ? "*" : "", 1810 i == force_lane_count ? "]" : ""); 1811 1812 seq_putc(m, '\n'); 1813 1814 return 0; 1815 } 1816 1817 static int parse_lane_count(const char __user *ubuf, size_t len) 1818 { 1819 char *kbuf; 1820 const char *p; 1821 int lane_count; 1822 int ret = 0; 1823 1824 kbuf = memdup_user_nul(ubuf, len); 1825 if (IS_ERR(kbuf)) 1826 return PTR_ERR(kbuf); 1827 1828 p = strim(kbuf); 1829 1830 if (!strcmp(p, "auto")) { 1831 lane_count = 0; 1832 } else { 1833 ret = kstrtoint(p, 0, &lane_count); 1834 if (ret < 0) 1835 goto out_free; 1836 1837 switch (lane_count) { 1838 case 1: 1839 case 2: 1840 case 4: 1841 break; 1842 default: 1843 ret = -EINVAL; 1844 } 1845 } 1846 1847 out_free: 1848 kfree(kbuf); 1849 1850 return ret < 0 ? ret : lane_count; 1851 } 1852 1853 static ssize_t i915_dp_force_lane_count_write(struct file *file, 1854 const char __user *ubuf, 1855 size_t len, loff_t *offp) 1856 { 1857 struct seq_file *m = file->private_data; 1858 struct intel_connector *connector = to_intel_connector(m->private); 1859 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1860 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1861 int lane_count; 1862 int err; 1863 1864 lane_count = parse_lane_count(ubuf, len); 1865 if (lane_count < 0) 1866 return lane_count; 1867 1868 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1869 if (err) 1870 return err; 1871 1872 intel_dp_reset_link_params(intel_dp); 1873 intel_dp->link.force_lane_count = lane_count; 1874 1875 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1876 1877 *offp += len; 1878 1879 return len; 1880 } 1881 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_lane_count); 1882 1883 static int i915_dp_max_link_rate_show(void *data, u64 *val) 1884 { 1885 struct intel_connector *connector = to_intel_connector(data); 1886 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1887 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1888 int err; 1889 1890 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1891 if (err) 1892 return err; 1893 1894 *val = intel_dp->link.max_rate; 1895 1896 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1897 1898 return 0; 1899 } 1900 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_link_rate_fops, i915_dp_max_link_rate_show, NULL, "%llu\n"); 1901 1902 static int i915_dp_max_lane_count_show(void *data, u64 *val) 1903 { 1904 struct intel_connector *connector = to_intel_connector(data); 1905 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1906 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1907 int err; 1908 1909 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1910 if (err) 1911 return err; 1912 1913 *val = intel_dp->link.max_lane_count; 1914 1915 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1916 1917 return 0; 1918 } 1919 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n"); 1920 1921 static int i915_dp_force_link_training_failure_show(void *data, u64 *val) 1922 { 1923 struct intel_connector *connector = to_intel_connector(data); 1924 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1925 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1926 int err; 1927 1928 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1929 if (err) 1930 return err; 1931 1932 *val = intel_dp->link.force_train_failure; 1933 1934 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1935 1936 return 0; 1937 } 1938 1939 static int i915_dp_force_link_training_failure_write(void *data, u64 val) 1940 { 1941 struct intel_connector *connector = to_intel_connector(data); 1942 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1943 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1944 int err; 1945 1946 if (val > 2) 1947 return -EINVAL; 1948 1949 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1950 if (err) 1951 return err; 1952 1953 intel_dp->link.force_train_failure = val; 1954 1955 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1956 1957 return 0; 1958 } 1959 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, 1960 i915_dp_force_link_training_failure_show, 1961 i915_dp_force_link_training_failure_write, "%llu\n"); 1962 1963 static int i915_dp_force_link_retrain_show(void *data, u64 *val) 1964 { 1965 struct intel_connector *connector = to_intel_connector(data); 1966 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1967 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1968 int err; 1969 1970 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1971 if (err) 1972 return err; 1973 1974 *val = intel_dp->link.force_retrain; 1975 1976 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1977 1978 return 0; 1979 } 1980 1981 static int i915_dp_force_link_retrain_write(void *data, u64 val) 1982 { 1983 struct intel_connector *connector = to_intel_connector(data); 1984 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1985 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 1986 int err; 1987 1988 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 1989 if (err) 1990 return err; 1991 1992 intel_dp->link.force_retrain = val; 1993 1994 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 1995 1996 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); 1997 1998 return 0; 1999 } 2000 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, 2001 i915_dp_force_link_retrain_show, 2002 i915_dp_force_link_retrain_write, "%llu\n"); 2003 2004 static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data) 2005 { 2006 struct intel_connector *connector = to_intel_connector(m->private); 2007 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2008 struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); 2009 int err; 2010 2011 err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); 2012 if (err) 2013 return err; 2014 2015 seq_printf(m, "%s\n", str_yes_no(intel_dp->link.retrain_disabled)); 2016 2017 drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); 2018 2019 return 0; 2020 } 2021 DEFINE_SHOW_ATTRIBUTE(i915_dp_link_retrain_disabled); 2022 2023 void intel_dp_link_training_debugfs_add(struct intel_connector *connector) 2024 { 2025 struct dentry *root = connector->base.debugfs_entry; 2026 2027 if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort && 2028 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 2029 return; 2030 2031 debugfs_create_file("i915_dp_force_link_rate", 0644, root, 2032 connector, &i915_dp_force_link_rate_fops); 2033 2034 debugfs_create_file("i915_dp_force_lane_count", 0644, root, 2035 connector, &i915_dp_force_lane_count_fops); 2036 2037 debugfs_create_file("i915_dp_max_link_rate", 0444, root, 2038 connector, &i915_dp_max_link_rate_fops); 2039 2040 debugfs_create_file("i915_dp_max_lane_count", 0444, root, 2041 connector, &i915_dp_max_lane_count_fops); 2042 2043 debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, 2044 connector, &i915_dp_force_link_training_failure_fops); 2045 2046 debugfs_create_file("i915_dp_force_link_retrain", 0644, root, 2047 connector, &i915_dp_force_link_retrain_fops); 2048 2049 debugfs_create_file("i915_dp_link_retrain_disabled", 0444, root, 2050 connector, &i915_dp_link_retrain_disabled_fops); 2051 } 2052