1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 26 #include <drm/display/drm_dp_helper.h> 27 28 #include "i915_utils.h" 29 #include "intel_display_core.h" 30 #include "intel_display_types.h" 31 #include "intel_dp.h" 32 #include "intel_dp_link_training.h" 33 #include "intel_encoder.h" 34 #include "intel_hotplug.h" 35 #include "intel_panel.h" 36 37 #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " 38 #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \ 39 (_intel_dp)->attached_connector->base.name, \ 40 dp_to_dig_port(_intel_dp)->base.base.base.id, \ 41 dp_to_dig_port(_intel_dp)->base.base.name, \ 42 drm_dp_phy_name(_dp_phy) 43 44 #define lt_dbg(_intel_dp, _dp_phy, _format, ...) \ 45 drm_dbg_kms(to_intel_display(_intel_dp)->drm, \ 46 LT_MSG_PREFIX _format, \ 47 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__) 48 49 #define lt_err(_intel_dp, _dp_phy, _format, ...) do { \ 50 if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \ 51 drm_err(to_intel_display(_intel_dp)->drm, \ 52 LT_MSG_PREFIX _format, \ 53 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \ 54 else \ 55 lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \ 56 } while (0) 57 58 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) 59 { 60 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); 61 } 62 63 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 64 { 65 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 66 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 67 } 68 69 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 70 enum drm_dp_phy dp_phy) 71 { 72 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 73 } 74 75 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 76 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 77 enum drm_dp_phy dp_phy) 78 { 79 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 80 81 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { 82 lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n"); 83 return; 84 } 85 86 lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n", 87 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 88 phy_caps); 89 } 90 91 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, 92 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 93 { 94 int ret; 95 96 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, 97 intel_dp->lttpr_common_caps); 98 if (ret < 0) 99 goto reset_caps; 100 101 lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n", 102 (int)sizeof(intel_dp->lttpr_common_caps), 103 intel_dp->lttpr_common_caps); 104 105 /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ 106 if (intel_dp->lttpr_common_caps[0] < 0x14) 107 goto reset_caps; 108 109 return true; 110 111 reset_caps: 112 intel_dp_reset_lttpr_common_caps(intel_dp); 113 return false; 114 } 115 116 static bool 117 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 118 { 119 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 120 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 121 122 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 123 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val; 124 125 return true; 126 } 127 128 bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp) 129 { 130 return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 131 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] == 132 DP_PHY_REPEATER_MODE_TRANSPARENT; 133 } 134 135 /* 136 * Read the LTTPR common capabilities and switch the LTTPR PHYs to 137 * non-transparent mode if this is supported. Preserve the 138 * transparent/non-transparent mode on an active link. 139 * 140 * Return the number of detected LTTPRs in non-transparent mode or 0 if the 141 * LTTPRs are in transparent mode or the detection failed. 142 */ 143 static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 144 { 145 int lttpr_count; 146 int ret; 147 148 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) 149 return 0; 150 151 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 152 /* 153 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are 154 * detected as this breaks link training at least on the Dell WD19TB 155 * dock. 156 */ 157 if (lttpr_count == 0) 158 return 0; 159 160 /* 161 * Don't change the mode on an active link, to prevent a loss of link 162 * synchronization. See DP Standard v2.0 3.6.7. about the LTTPR 163 * resetting its internal state when the mode is changed from 164 * non-transparent to transparent. 165 */ 166 if (intel_dp->link_trained) { 167 if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp)) 168 goto out_reset_lttpr_count; 169 170 return lttpr_count; 171 } 172 173 ret = drm_dp_lttpr_init(&intel_dp->aux, lttpr_count); 174 if (ret) { 175 lt_dbg(intel_dp, DP_PHY_DPRX, 176 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); 177 178 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 179 180 goto out_reset_lttpr_count; 181 } 182 183 intel_dp_set_lttpr_transparent_mode(intel_dp, false); 184 185 return lttpr_count; 186 187 out_reset_lttpr_count: 188 intel_dp_reset_lttpr_count(intel_dp); 189 190 return 0; 191 } 192 193 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 194 { 195 int lttpr_count; 196 int i; 197 198 lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd); 199 200 for (i = 0; i < lttpr_count; i++) { 201 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); 202 drm_dp_dump_lttpr_desc(&intel_dp->aux, DP_PHY_LTTPR(i)); 203 } 204 205 return lttpr_count; 206 } 207 208 int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) 209 { 210 struct intel_display *display = to_intel_display(intel_dp); 211 212 if (intel_dp_is_edp(intel_dp)) 213 return 0; 214 215 /* 216 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 217 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 218 */ 219 if (DISPLAY_VER(display) >= 10 && !display->platform.geminilake) 220 if (drm_dp_dpcd_probe(&intel_dp->aux, 221 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV)) 222 return -EIO; 223 224 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) 225 return -EIO; 226 227 return 0; 228 } 229 230 /** 231 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode 232 * @intel_dp: Intel DP struct 233 * 234 * Read the LTTPR common and DPRX capabilities and switch to non-transparent 235 * link training mode if any is detected and read the PHY capabilities for all 236 * detected LTTPRs. In case of an LTTPR detection error or if the number of 237 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 238 * transparent mode link training mode. 239 * 240 * Returns: 241 * >0 if LTTPRs were detected and the non-transparent LT mode was set. The 242 * DPRX capabilities are read out. 243 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 244 * detection failure and the transparent LT mode was set. The DPRX 245 * capabilities are read out. 246 * <0 Reading out the DPRX capabilities failed. 247 */ 248 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) 249 { 250 struct intel_display *display = to_intel_display(intel_dp); 251 int lttpr_count = 0; 252 253 /* 254 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 255 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 256 */ 257 if (!intel_dp_is_edp(intel_dp) && 258 (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)) { 259 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 260 int err = intel_dp_read_dprx_caps(intel_dp, dpcd); 261 262 if (err != 0) 263 return err; 264 265 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); 266 } 267 268 /* 269 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read 270 * it here. 271 */ 272 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { 273 intel_dp_reset_lttpr_common_caps(intel_dp); 274 return -EIO; 275 } 276 277 return lttpr_count; 278 } 279 280 static u8 dp_voltage_max(u8 preemph) 281 { 282 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 283 case DP_TRAIN_PRE_EMPH_LEVEL_0: 284 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 285 case DP_TRAIN_PRE_EMPH_LEVEL_1: 286 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 287 case DP_TRAIN_PRE_EMPH_LEVEL_2: 288 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 289 case DP_TRAIN_PRE_EMPH_LEVEL_3: 290 default: 291 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 292 } 293 } 294 295 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 296 enum drm_dp_phy dp_phy) 297 { 298 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 299 300 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 301 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 302 else 303 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 304 } 305 306 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 307 enum drm_dp_phy dp_phy) 308 { 309 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 310 311 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 312 return DP_TRAIN_PRE_EMPH_LEVEL_3; 313 else 314 return DP_TRAIN_PRE_EMPH_LEVEL_2; 315 } 316 317 static bool 318 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 319 enum drm_dp_phy dp_phy) 320 { 321 struct intel_display *display = to_intel_display(intel_dp); 322 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 323 324 drm_WARN_ON_ONCE(display->drm, 325 lttpr_count <= 0 && dp_phy != DP_PHY_DPRX); 326 327 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 328 } 329 330 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 331 const struct intel_crtc_state *crtc_state, 332 enum drm_dp_phy dp_phy) 333 { 334 struct intel_display *display = to_intel_display(intel_dp); 335 u8 voltage_max; 336 337 /* 338 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 339 * the DPRX_PHY we train. 340 */ 341 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 342 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 343 else 344 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 345 346 drm_WARN_ON_ONCE(display->drm, 347 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 348 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 349 350 return voltage_max; 351 } 352 353 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 354 enum drm_dp_phy dp_phy) 355 { 356 struct intel_display *display = to_intel_display(intel_dp); 357 u8 preemph_max; 358 359 /* 360 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 361 * the DPRX_PHY we train. 362 */ 363 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 364 preemph_max = intel_dp->preemph_max(intel_dp); 365 else 366 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 367 368 drm_WARN_ON_ONCE(display->drm, 369 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 370 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 371 372 return preemph_max; 373 } 374 375 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, 376 enum drm_dp_phy dp_phy) 377 { 378 struct intel_display *display = to_intel_display(intel_dp); 379 380 return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) || 381 DISPLAY_VER(display) >= 10 || display->platform.broxton; 382 } 383 384 /* 128b/132b */ 385 static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp, 386 const struct intel_crtc_state *crtc_state, 387 enum drm_dp_phy dp_phy, 388 const u8 link_status[DP_LINK_STATUS_SIZE], 389 int lane) 390 { 391 u8 tx_ffe = 0; 392 393 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 394 lane = min(lane, crtc_state->lane_count - 1); 395 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); 396 } else { 397 for (lane = 0; lane < crtc_state->lane_count; lane++) 398 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); 399 } 400 401 return tx_ffe; 402 } 403 404 /* 8b/10b */ 405 static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp, 406 const struct intel_crtc_state *crtc_state, 407 enum drm_dp_phy dp_phy, 408 const u8 link_status[DP_LINK_STATUS_SIZE], 409 int lane) 410 { 411 u8 v = 0; 412 u8 p = 0; 413 u8 voltage_max; 414 u8 preemph_max; 415 416 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 417 lane = min(lane, crtc_state->lane_count - 1); 418 419 v = drm_dp_get_adjust_request_voltage(link_status, lane); 420 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 421 } else { 422 for (lane = 0; lane < crtc_state->lane_count; lane++) { 423 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 424 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 425 } 426 } 427 428 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 429 if (p >= preemph_max) 430 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 431 432 v = min(v, dp_voltage_max(p)); 433 434 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 435 if (v >= voltage_max) 436 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 437 438 return v | p; 439 } 440 441 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, 442 const struct intel_crtc_state *crtc_state, 443 enum drm_dp_phy dp_phy, 444 const u8 link_status[DP_LINK_STATUS_SIZE], 445 int lane) 446 { 447 if (intel_dp_is_uhbr(crtc_state)) 448 return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state, 449 dp_phy, link_status, lane); 450 else 451 return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state, 452 dp_phy, link_status, lane); 453 } 454 455 #define TRAIN_REQ_FMT "%d/%d/%d/%d" 456 #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \ 457 (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT) 458 #define TRAIN_REQ_VSWING_ARGS(link_status) \ 459 _TRAIN_REQ_VSWING_ARGS(link_status, 0), \ 460 _TRAIN_REQ_VSWING_ARGS(link_status, 1), \ 461 _TRAIN_REQ_VSWING_ARGS(link_status, 2), \ 462 _TRAIN_REQ_VSWING_ARGS(link_status, 3) 463 #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \ 464 (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT) 465 #define TRAIN_REQ_PREEMPH_ARGS(link_status) \ 466 _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \ 467 _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \ 468 _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \ 469 _TRAIN_REQ_PREEMPH_ARGS(link_status, 3) 470 #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \ 471 drm_dp_get_adjust_tx_ffe_preset((link_status), (lane)) 472 #define TRAIN_REQ_TX_FFE_ARGS(link_status) \ 473 _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \ 474 _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \ 475 _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \ 476 _TRAIN_REQ_TX_FFE_ARGS(link_status, 3) 477 478 void 479 intel_dp_get_adjust_train(struct intel_dp *intel_dp, 480 const struct intel_crtc_state *crtc_state, 481 enum drm_dp_phy dp_phy, 482 const u8 link_status[DP_LINK_STATUS_SIZE]) 483 { 484 int lane; 485 486 if (intel_dp_is_uhbr(crtc_state)) { 487 lt_dbg(intel_dp, dp_phy, 488 "128b/132b, lanes: %d, " 489 "TX FFE request: " TRAIN_REQ_FMT "\n", 490 crtc_state->lane_count, 491 TRAIN_REQ_TX_FFE_ARGS(link_status)); 492 } else { 493 lt_dbg(intel_dp, dp_phy, 494 "8b/10b, lanes: %d, " 495 "vswing request: " TRAIN_REQ_FMT ", " 496 "pre-emphasis request: " TRAIN_REQ_FMT "\n", 497 crtc_state->lane_count, 498 TRAIN_REQ_VSWING_ARGS(link_status), 499 TRAIN_REQ_PREEMPH_ARGS(link_status)); 500 } 501 502 for (lane = 0; lane < 4; lane++) 503 intel_dp->train_set[lane] = 504 intel_dp_get_lane_adjust_train(intel_dp, crtc_state, 505 dp_phy, link_status, lane); 506 } 507 508 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 509 enum drm_dp_phy dp_phy) 510 { 511 return dp_phy == DP_PHY_DPRX ? 512 DP_TRAINING_PATTERN_SET : 513 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 514 } 515 516 static bool 517 intel_dp_set_link_train(struct intel_dp *intel_dp, 518 const struct intel_crtc_state *crtc_state, 519 enum drm_dp_phy dp_phy, 520 u8 dp_train_pat) 521 { 522 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 523 u8 buf[sizeof(intel_dp->train_set) + 1]; 524 int len; 525 526 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 527 dp_phy, dp_train_pat); 528 529 buf[0] = dp_train_pat; 530 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 531 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 532 len = crtc_state->lane_count + 1; 533 534 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 535 } 536 537 static char dp_training_pattern_name(u8 train_pat) 538 { 539 switch (train_pat) { 540 case DP_TRAINING_PATTERN_1: 541 case DP_TRAINING_PATTERN_2: 542 case DP_TRAINING_PATTERN_3: 543 return '0' + train_pat; 544 case DP_TRAINING_PATTERN_4: 545 return '4'; 546 default: 547 MISSING_CASE(train_pat); 548 return '?'; 549 } 550 } 551 552 void 553 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 554 const struct intel_crtc_state *crtc_state, 555 enum drm_dp_phy dp_phy, 556 u8 dp_train_pat) 557 { 558 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat); 559 560 if (train_pat != DP_TRAINING_PATTERN_DISABLE) 561 lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n", 562 dp_training_pattern_name(train_pat)); 563 564 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); 565 } 566 567 #define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" 568 #define _TRAIN_SET_VSWING_ARGS(train_set) \ 569 ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ 570 (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" 571 #define TRAIN_SET_VSWING_ARGS(train_set) \ 572 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ 573 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ 574 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ 575 _TRAIN_SET_VSWING_ARGS((train_set)[3]) 576 #define _TRAIN_SET_PREEMPH_ARGS(train_set) \ 577 ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ 578 (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" 579 #define TRAIN_SET_PREEMPH_ARGS(train_set) \ 580 _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ 581 _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ 582 _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ 583 _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) 584 #define _TRAIN_SET_TX_FFE_ARGS(train_set) \ 585 ((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), "" 586 #define TRAIN_SET_TX_FFE_ARGS(train_set) \ 587 _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \ 588 _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \ 589 _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \ 590 _TRAIN_SET_TX_FFE_ARGS((train_set)[3]) 591 592 void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 593 const struct intel_crtc_state *crtc_state, 594 enum drm_dp_phy dp_phy) 595 { 596 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 597 598 if (intel_dp_is_uhbr(crtc_state)) { 599 lt_dbg(intel_dp, dp_phy, 600 "128b/132b, lanes: %d, " 601 "TX FFE presets: " TRAIN_SET_FMT "\n", 602 crtc_state->lane_count, 603 TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set)); 604 } else { 605 lt_dbg(intel_dp, dp_phy, 606 "8b/10b, lanes: %d, " 607 "vswing levels: " TRAIN_SET_FMT ", " 608 "pre-emphasis levels: " TRAIN_SET_FMT "\n", 609 crtc_state->lane_count, 610 TRAIN_SET_VSWING_ARGS(intel_dp->train_set), 611 TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set)); 612 } 613 614 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 615 encoder->set_signal_levels(encoder, crtc_state); 616 } 617 618 static bool 619 intel_dp_reset_link_train(struct intel_dp *intel_dp, 620 const struct intel_crtc_state *crtc_state, 621 enum drm_dp_phy dp_phy, 622 u8 dp_train_pat) 623 { 624 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 625 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 626 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 627 } 628 629 static bool 630 intel_dp_update_link_train(struct intel_dp *intel_dp, 631 const struct intel_crtc_state *crtc_state, 632 enum drm_dp_phy dp_phy) 633 { 634 int reg = dp_phy == DP_PHY_DPRX ? 635 DP_TRAINING_LANE0_SET : 636 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 637 int ret; 638 639 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 640 641 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 642 intel_dp->train_set, crtc_state->lane_count); 643 644 return ret == crtc_state->lane_count; 645 } 646 647 /* 128b/132b */ 648 static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane) 649 { 650 return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) == 651 DP_TX_FFE_PRESET_VALUE_MASK; 652 } 653 654 /* 655 * 8b/10b 656 * 657 * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to 658 * have self contradicting tests around this area. 659 * 660 * In lieu of better ideas let's just stop when we've reached the max supported 661 * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on 662 * whether vswing level 3 is supported or not. 663 */ 664 static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane) 665 { 666 u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 667 DP_TRAIN_VOLTAGE_SWING_SHIFT; 668 u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 669 DP_TRAIN_PRE_EMPHASIS_SHIFT; 670 671 if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0) 672 return false; 673 674 if (v + p != 3) 675 return false; 676 677 return true; 678 } 679 680 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 681 const struct intel_crtc_state *crtc_state) 682 { 683 int lane; 684 685 for (lane = 0; lane < crtc_state->lane_count; lane++) { 686 u8 train_set_lane = intel_dp->train_set[lane]; 687 688 if (intel_dp_is_uhbr(crtc_state)) { 689 if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane)) 690 return false; 691 } else { 692 if (!intel_dp_lane_max_vswing_reached(train_set_lane)) 693 return false; 694 } 695 } 696 697 return true; 698 } 699 700 void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr) 701 { 702 u8 link_config[2]; 703 704 link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 705 link_config[1] = drm_dp_is_uhbr_rate(link_rate) ? 706 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; 707 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 708 } 709 710 static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, 711 const struct intel_crtc_state *crtc_state) 712 { 713 intel_dp_link_training_set_mode(intel_dp, 714 crtc_state->port_clock, crtc_state->vrr.flipline); 715 } 716 717 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, 718 int link_bw, int rate_select, int lane_count, 719 bool enhanced_framing) 720 { 721 if (enhanced_framing) 722 lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 723 724 if (link_bw) { 725 /* DP and eDP v1.3 and earlier link bw set method. */ 726 u8 link_config[] = { link_bw, lane_count }; 727 728 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 729 ARRAY_SIZE(link_config)); 730 } else { 731 /* 732 * eDP v1.4 and later link rate set method. 733 * 734 * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if 735 * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET. 736 * 737 * eDP v1.5 sinks allow choosing either, and the last choice 738 * shall be active. 739 */ 740 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count); 741 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select); 742 } 743 } 744 745 static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp, 746 const struct intel_crtc_state *crtc_state, 747 u8 link_bw, u8 rate_select) 748 { 749 intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count, 750 crtc_state->enhanced_framing); 751 } 752 753 /* 754 * Prepare link training by configuring the link parameters. On DDI platforms 755 * also enable the port here. 756 */ 757 static bool 758 intel_dp_prepare_link_train(struct intel_dp *intel_dp, 759 const struct intel_crtc_state *crtc_state) 760 { 761 u8 link_bw, rate_select; 762 763 if (intel_dp->prepare_link_retrain) 764 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 765 766 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 767 &link_bw, &rate_select); 768 769 /* 770 * WaEdpLinkRateDataReload 771 * 772 * Parade PS8461E MUX (used on varius TGL+ laptops) needs 773 * to snoop the link rates reported by the sink when we 774 * use LINK_RATE_SET in order to operate in jitter cleaning 775 * mode (as opposed to redriver mode). Unfortunately it 776 * loses track of the snooped link rates when powered down, 777 * so we need to make it re-snoop often. Without this high 778 * link rates are not stable. 779 */ 780 if (!link_bw) { 781 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 782 783 lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n"); 784 785 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 786 sink_rates, sizeof(sink_rates)); 787 } 788 789 if (link_bw) 790 lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n", 791 link_bw); 792 else 793 lt_dbg(intel_dp, DP_PHY_DPRX, 794 "Using LINK_RATE_SET value %02x\n", 795 rate_select); 796 /* 797 * Spec DP2.1 Section 3.5.2.16 798 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate 799 */ 800 intel_dp_update_downspread_ctrl(intel_dp, crtc_state); 801 intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw, 802 rate_select); 803 804 return true; 805 } 806 807 static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state, 808 const u8 old_link_status[DP_LINK_STATUS_SIZE], 809 const u8 new_link_status[DP_LINK_STATUS_SIZE]) 810 { 811 int lane; 812 813 for (lane = 0; lane < crtc_state->lane_count; lane++) { 814 u8 old, new; 815 816 if (intel_dp_is_uhbr(crtc_state)) { 817 old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane); 818 new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane); 819 } else { 820 old = drm_dp_get_adjust_request_voltage(old_link_status, lane) | 821 drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane); 822 new = drm_dp_get_adjust_request_voltage(new_link_status, lane) | 823 drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane); 824 } 825 826 if (old != new) 827 return true; 828 } 829 830 return false; 831 } 832 833 void 834 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy, 835 const u8 link_status[DP_LINK_STATUS_SIZE]) 836 { 837 lt_dbg(intel_dp, dp_phy, 838 "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n", 839 link_status[0], link_status[1], link_status[2], 840 link_status[3], link_status[4], link_status[5]); 841 } 842 843 /* 844 * Perform the link training clock recovery phase on the given DP PHY using 845 * training pattern 1. 846 */ 847 static bool 848 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 849 const struct intel_crtc_state *crtc_state, 850 enum drm_dp_phy dp_phy) 851 { 852 u8 old_link_status[DP_LINK_STATUS_SIZE] = {}; 853 int voltage_tries, cr_tries, max_cr_tries; 854 u8 link_status[DP_LINK_STATUS_SIZE]; 855 bool max_vswing_reached = false; 856 int delay_us; 857 858 delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux, 859 intel_dp->dpcd, dp_phy, 860 intel_dp_is_uhbr(crtc_state)); 861 862 /* clock recovery */ 863 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 864 DP_TRAINING_PATTERN_1 | 865 DP_LINK_SCRAMBLING_DISABLE)) { 866 lt_err(intel_dp, dp_phy, "Failed to enable link training\n"); 867 return false; 868 } 869 870 /* 871 * The DP 1.4 spec defines the max clock recovery retries value 872 * as 10 but for pre-DP 1.4 devices we set a very tolerant 873 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 874 * x 5 identical voltage retries). Since the previous specs didn't 875 * define a limit and created the possibility of an infinite loop 876 * we want to prevent any sync from triggering that corner case. 877 */ 878 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 879 max_cr_tries = 10; 880 else 881 max_cr_tries = 80; 882 883 voltage_tries = 1; 884 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 885 fsleep(delay_us); 886 887 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 888 link_status) < 0) { 889 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 890 return false; 891 } 892 893 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 894 lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n"); 895 return true; 896 } 897 898 if (voltage_tries == 5) { 899 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 900 lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n"); 901 return false; 902 } 903 904 if (max_vswing_reached) { 905 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 906 lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n"); 907 return false; 908 } 909 910 /* Update training set as requested by target */ 911 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 912 link_status); 913 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 914 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 915 return false; 916 } 917 918 if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status)) 919 ++voltage_tries; 920 else 921 voltage_tries = 1; 922 923 memcpy(old_link_status, link_status, sizeof(link_status)); 924 925 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 926 max_vswing_reached = true; 927 } 928 929 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 930 lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n", 931 max_cr_tries); 932 933 return false; 934 } 935 936 /* 937 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 938 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or 939 * 1.2 devices that support it, TPS2 otherwise. 940 */ 941 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 942 const struct intel_crtc_state *crtc_state, 943 enum drm_dp_phy dp_phy) 944 { 945 struct intel_display *display = to_intel_display(intel_dp); 946 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 947 948 /* UHBR+ use separate 128b/132b TPS2 */ 949 if (intel_dp_is_uhbr(crtc_state)) 950 return DP_TRAINING_PATTERN_2; 951 952 /* 953 * TPS4 support is mandatory for all downstream devices that 954 * support HBR3. There are no known eDP panels that support 955 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification. 956 * LTTPRs must support TPS4. 957 */ 958 source_tps4 = intel_dp_source_supports_tps4(display); 959 sink_tps4 = dp_phy != DP_PHY_DPRX || 960 drm_dp_tps4_supported(intel_dp->dpcd); 961 if (source_tps4 && sink_tps4) { 962 return DP_TRAINING_PATTERN_4; 963 } else if (crtc_state->port_clock == 810000) { 964 if (!source_tps4) 965 lt_dbg(intel_dp, dp_phy, 966 "8.1 Gbps link rate without source TPS4 support\n"); 967 if (!sink_tps4) 968 lt_dbg(intel_dp, dp_phy, 969 "8.1 Gbps link rate without sink TPS4 support\n"); 970 } 971 972 /* 973 * TPS3 support is mandatory for downstream devices that 974 * support HBR2. However, not all sinks follow the spec. 975 */ 976 source_tps3 = intel_dp_source_supports_tps3(display); 977 sink_tps3 = dp_phy != DP_PHY_DPRX || 978 drm_dp_tps3_supported(intel_dp->dpcd); 979 if (source_tps3 && sink_tps3) { 980 return DP_TRAINING_PATTERN_3; 981 } else if (crtc_state->port_clock >= 540000) { 982 if (!source_tps3) 983 lt_dbg(intel_dp, dp_phy, 984 ">=5.4/6.48 Gbps link rate without source TPS3 support\n"); 985 if (!sink_tps3) 986 lt_dbg(intel_dp, dp_phy, 987 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 988 } 989 990 return DP_TRAINING_PATTERN_2; 991 } 992 993 /* 994 * Perform the link training channel equalization phase on the given DP PHY 995 * using one of training pattern 2, 3 or 4 depending on the source and 996 * sink capabilities. 997 */ 998 static bool 999 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 1000 const struct intel_crtc_state *crtc_state, 1001 enum drm_dp_phy dp_phy) 1002 { 1003 int tries; 1004 u32 training_pattern; 1005 u8 link_status[DP_LINK_STATUS_SIZE]; 1006 bool channel_eq = false; 1007 int delay_us; 1008 1009 delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux, 1010 intel_dp->dpcd, dp_phy, 1011 intel_dp_is_uhbr(crtc_state)); 1012 1013 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 1014 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 1015 if (training_pattern != DP_TRAINING_PATTERN_4) 1016 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 1017 1018 /* channel equalization */ 1019 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 1020 training_pattern)) { 1021 lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n"); 1022 return false; 1023 } 1024 1025 for (tries = 0; tries < 5; tries++) { 1026 fsleep(delay_us); 1027 1028 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 1029 link_status) < 0) { 1030 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 1031 break; 1032 } 1033 1034 /* Make sure clock is still ok */ 1035 if (!drm_dp_clock_recovery_ok(link_status, 1036 crtc_state->lane_count)) { 1037 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1038 lt_dbg(intel_dp, dp_phy, 1039 "Clock recovery check failed, cannot continue channel equalization\n"); 1040 break; 1041 } 1042 1043 if (drm_dp_channel_eq_ok(link_status, 1044 crtc_state->lane_count)) { 1045 channel_eq = true; 1046 lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n"); 1047 break; 1048 } 1049 1050 /* Update training set as requested by target */ 1051 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 1052 link_status); 1053 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 1054 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 1055 break; 1056 } 1057 } 1058 1059 /* Try 5 times, else fail and try at lower BW */ 1060 if (tries == 5) { 1061 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1062 lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n"); 1063 } 1064 1065 return channel_eq; 1066 } 1067 1068 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 1069 enum drm_dp_phy dp_phy) 1070 { 1071 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 1072 u8 val = DP_TRAINING_PATTERN_DISABLE; 1073 1074 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 1075 } 1076 1077 static int 1078 intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp, 1079 const struct intel_crtc_state *crtc_state) 1080 { 1081 u8 sink_status; 1082 int ret; 1083 1084 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status); 1085 if (ret != 1) { 1086 lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n"); 1087 return ret < 0 ? ret : -EIO; 1088 } 1089 1090 return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0; 1091 } 1092 1093 /** 1094 * intel_dp_stop_link_train - stop link training 1095 * @intel_dp: DP struct 1096 * @crtc_state: state for CRTC attached to the encoder 1097 * 1098 * Stop the link training of the @intel_dp port, disabling the training 1099 * pattern in the sink's DPCD, and disabling the test pattern symbol 1100 * generation on the port. 1101 * 1102 * What symbols are output on the port after this point is 1103 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 1104 * with the pipe being disabled, on older platforms it's HW specific if/how an 1105 * idle pattern is generated, as the pipe is already enabled here for those. 1106 * 1107 * This function must be called after intel_dp_start_link_train(). 1108 */ 1109 void intel_dp_stop_link_train(struct intel_dp *intel_dp, 1110 const struct intel_crtc_state *crtc_state) 1111 { 1112 intel_dp->link_trained = true; 1113 1114 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 1115 intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX, 1116 DP_TRAINING_PATTERN_DISABLE); 1117 1118 if (intel_dp_is_uhbr(crtc_state) && 1119 wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1120 lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n"); 1121 } 1122 } 1123 1124 static bool 1125 intel_dp_link_train_phy(struct intel_dp *intel_dp, 1126 const struct intel_crtc_state *crtc_state, 1127 enum drm_dp_phy dp_phy) 1128 { 1129 bool ret = false; 1130 1131 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 1132 goto out; 1133 1134 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 1135 goto out; 1136 1137 ret = true; 1138 1139 out: 1140 lt_dbg(intel_dp, dp_phy, 1141 "Link Training %s at link rate = %d, lane count = %d\n", 1142 ret ? "passed" : "failed", 1143 crtc_state->port_clock, crtc_state->lane_count); 1144 1145 return ret; 1146 } 1147 1148 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, 1149 int link_rate, 1150 u8 lane_count) 1151 { 1152 /* FIXME figure out what we actually want here */ 1153 const struct drm_display_mode *fixed_mode = 1154 intel_panel_preferred_fixed_mode(intel_dp->attached_connector); 1155 int mode_rate, max_rate; 1156 1157 mode_rate = intel_dp_link_required(fixed_mode->clock, 18); 1158 max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); 1159 if (mode_rate > max_rate) 1160 return false; 1161 1162 return true; 1163 } 1164 1165 static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp, 1166 const struct intel_crtc_state *crtc_state, 1167 int *new_link_rate, int *new_lane_count) 1168 { 1169 int link_rate; 1170 int lane_count; 1171 int i; 1172 1173 i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 1174 for (i--; i >= 0; i--) { 1175 intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count); 1176 1177 if ((intel_dp->link.force_rate && 1178 intel_dp->link.force_rate != link_rate) || 1179 (intel_dp->link.force_lane_count && 1180 intel_dp->link.force_lane_count != lane_count)) 1181 continue; 1182 1183 break; 1184 } 1185 1186 if (i < 0) 1187 return false; 1188 1189 *new_link_rate = link_rate; 1190 *new_lane_count = lane_count; 1191 1192 return true; 1193 } 1194 1195 static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) 1196 { 1197 int rate_index; 1198 int new_rate; 1199 1200 if (intel_dp->link.force_rate) 1201 return -1; 1202 1203 rate_index = intel_dp_rate_index(intel_dp->common_rates, 1204 intel_dp->num_common_rates, 1205 current_rate); 1206 1207 if (rate_index <= 0) 1208 return -1; 1209 1210 new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); 1211 1212 /* TODO: Make switching from UHBR to non-UHBR rates work. */ 1213 if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate)) 1214 return -1; 1215 1216 return new_rate; 1217 } 1218 1219 static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) 1220 { 1221 if (intel_dp->link.force_lane_count) 1222 return -1; 1223 1224 if (current_lane_count == 1) 1225 return -1; 1226 1227 return current_lane_count >> 1; 1228 } 1229 1230 static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp, 1231 const struct intel_crtc_state *crtc_state, 1232 int *new_link_rate, int *new_lane_count) 1233 { 1234 int link_rate; 1235 int lane_count; 1236 1237 lane_count = crtc_state->lane_count; 1238 link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); 1239 if (link_rate < 0) { 1240 lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); 1241 link_rate = intel_dp_max_common_rate(intel_dp); 1242 } 1243 1244 if (lane_count < 0) 1245 return false; 1246 1247 *new_link_rate = link_rate; 1248 *new_lane_count = lane_count; 1249 1250 return true; 1251 } 1252 1253 static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, 1254 int *new_link_rate, int *new_lane_count) 1255 { 1256 /* TODO: Use the same fallback logic on SST as on MST. */ 1257 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 1258 return reduce_link_params_in_bw_order(intel_dp, crtc_state, 1259 new_link_rate, new_lane_count); 1260 else 1261 return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state, 1262 new_link_rate, new_lane_count); 1263 } 1264 1265 static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 1266 const struct intel_crtc_state *crtc_state) 1267 { 1268 int new_link_rate; 1269 int new_lane_count; 1270 1271 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { 1272 lt_dbg(intel_dp, DP_PHY_DPRX, 1273 "Retrying Link training for eDP with max parameters\n"); 1274 intel_dp->use_max_params = true; 1275 return 0; 1276 } 1277 1278 if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count)) 1279 return -1; 1280 1281 if (intel_dp_is_edp(intel_dp) && 1282 !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { 1283 lt_dbg(intel_dp, DP_PHY_DPRX, 1284 "Retrying Link training for eDP with same parameters\n"); 1285 return 0; 1286 } 1287 1288 lt_dbg(intel_dp, DP_PHY_DPRX, 1289 "Reducing link parameters from %dx%d to %dx%d\n", 1290 crtc_state->lane_count, crtc_state->port_clock, 1291 new_lane_count, new_link_rate); 1292 1293 intel_dp->link.max_rate = new_link_rate; 1294 intel_dp->link.max_lane_count = new_lane_count; 1295 1296 return 0; 1297 } 1298 1299 static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, 1300 struct intel_dp *intel_dp, 1301 const struct intel_crtc_state *crtc_state) 1302 { 1303 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1304 1305 if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { 1306 lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); 1307 return true; 1308 } 1309 1310 if (intel_dp->hobl_active) { 1311 lt_dbg(intel_dp, DP_PHY_DPRX, 1312 "Link Training failed with HOBL active, not enabling it from now on\n"); 1313 intel_dp->hobl_failed = true; 1314 } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { 1315 return false; 1316 } 1317 1318 /* Schedule a Hotplug Uevent to userspace to start modeset */ 1319 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 1320 1321 return true; 1322 } 1323 1324 /* Perform the link training on all LTTPRs and the DPRX on a link. */ 1325 static bool 1326 intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 1327 const struct intel_crtc_state *crtc_state, 1328 int lttpr_count) 1329 { 1330 bool ret = true; 1331 int i; 1332 1333 for (i = lttpr_count - 1; i >= 0; i--) { 1334 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 1335 1336 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 1337 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 1338 1339 if (!ret) 1340 break; 1341 } 1342 1343 if (ret) 1344 ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 1345 1346 if (intel_dp->set_idle_link_train) 1347 intel_dp->set_idle_link_train(intel_dp, crtc_state); 1348 1349 return ret; 1350 } 1351 1352 /* 1353 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1) 1354 */ 1355 static bool 1356 intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, 1357 const struct intel_crtc_state *crtc_state) 1358 { 1359 u8 link_status[DP_LINK_STATUS_SIZE]; 1360 int delay_us; 1361 int try, max_tries = 20; 1362 unsigned long deadline; 1363 bool timeout = false; 1364 1365 /* 1366 * Reset signal levels. Start transmitting 128b/132b TPS1. 1367 * 1368 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1 1369 * in DP_TRAINING_PATTERN_SET. 1370 */ 1371 if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1372 DP_TRAINING_PATTERN_1)) { 1373 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n"); 1374 return false; 1375 } 1376 1377 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1378 1379 /* Read the initial TX FFE settings. */ 1380 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1381 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n"); 1382 return false; 1383 } 1384 1385 /* Update signal levels and training set as requested. */ 1386 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1387 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1388 lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n"); 1389 return false; 1390 } 1391 1392 /* Start transmitting 128b/132b TPS2. */ 1393 if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1394 DP_TRAINING_PATTERN_2)) { 1395 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n"); 1396 return false; 1397 } 1398 1399 /* Time budget for the LANEx_EQ_DONE Sequence */ 1400 deadline = jiffies + msecs_to_jiffies_timeout(450); 1401 1402 for (try = 0; try < max_tries; try++) { 1403 fsleep(delay_us); 1404 1405 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1406 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1407 return false; 1408 } 1409 1410 if (drm_dp_128b132b_link_training_failed(link_status)) { 1411 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1412 lt_err(intel_dp, DP_PHY_DPRX, 1413 "Downstream link training failure\n"); 1414 return false; 1415 } 1416 1417 if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) { 1418 lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n"); 1419 break; 1420 } 1421 1422 if (timeout) { 1423 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1424 lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n"); 1425 return false; 1426 } 1427 1428 if (time_after(jiffies, deadline)) 1429 timeout = true; /* try one last time after deadline */ 1430 1431 /* 1432 * During LT, Tx shall read AUX_RD_INTERVAL just before writing the new FFE 1433 * presets. 1434 */ 1435 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1436 1437 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1438 1439 /* Update signal levels and training set as requested. */ 1440 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1441 lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n"); 1442 return false; 1443 } 1444 } 1445 1446 if (try == max_tries) { 1447 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1448 lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n"); 1449 return false; 1450 } 1451 1452 for (;;) { 1453 if (time_after(jiffies, deadline)) 1454 timeout = true; /* try one last time after deadline */ 1455 1456 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1457 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1458 return false; 1459 } 1460 1461 if (drm_dp_128b132b_link_training_failed(link_status)) { 1462 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1463 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1464 return false; 1465 } 1466 1467 if (drm_dp_128b132b_eq_interlane_align_done(link_status)) { 1468 lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n"); 1469 break; 1470 } 1471 1472 if (timeout) { 1473 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1474 lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n"); 1475 return false; 1476 } 1477 1478 usleep_range(2000, 3000); 1479 } 1480 1481 return true; 1482 } 1483 1484 /* 1485 * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2) 1486 */ 1487 static bool 1488 intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp, 1489 const struct intel_crtc_state *crtc_state, 1490 int lttpr_count) 1491 { 1492 u8 link_status[DP_LINK_STATUS_SIZE]; 1493 unsigned long deadline; 1494 1495 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 1496 DP_TRAINING_PATTERN_2_CDS) != 1) { 1497 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n"); 1498 return false; 1499 } 1500 1501 /* Time budget for the LANEx_CDS_DONE Sequence */ 1502 deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20); 1503 1504 for (;;) { 1505 bool timeout = false; 1506 1507 if (time_after(jiffies, deadline)) 1508 timeout = true; /* try one last time after deadline */ 1509 1510 usleep_range(2000, 3000); 1511 1512 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1513 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1514 return false; 1515 } 1516 1517 if (drm_dp_128b132b_eq_interlane_align_done(link_status) && 1518 drm_dp_128b132b_cds_interlane_align_done(link_status) && 1519 drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) { 1520 lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n"); 1521 break; 1522 } 1523 1524 if (drm_dp_128b132b_link_training_failed(link_status)) { 1525 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1526 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1527 return false; 1528 } 1529 1530 if (timeout) { 1531 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1532 lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n"); 1533 return false; 1534 } 1535 } 1536 1537 return true; 1538 } 1539 1540 /* 1541 * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.) 1542 */ 1543 static bool 1544 intel_dp_128b132b_link_train(struct intel_dp *intel_dp, 1545 const struct intel_crtc_state *crtc_state, 1546 int lttpr_count) 1547 { 1548 bool passed = false; 1549 1550 if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1551 lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n"); 1552 goto out; 1553 } 1554 1555 if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) && 1556 intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count)) 1557 passed = true; 1558 1559 lt_dbg(intel_dp, DP_PHY_DPRX, 1560 "128b/132b Link Training %s at link rate = %d, lane count = %d\n", 1561 passed ? "passed" : "failed", 1562 crtc_state->port_clock, crtc_state->lane_count); 1563 1564 out: 1565 /* 1566 * Ensure that the training pattern does get set to TPS2 even in case 1567 * of a failure, as is the case at the end of a passing link training 1568 * and what is expected by the transcoder. Leaving TPS1 set (and 1569 * disabling the link train mode in DP_TP_CTL later from TPS1 directly) 1570 * would result in a stuck transcoder HW state and flip-done timeouts 1571 * later in the modeset sequence. 1572 */ 1573 if (!passed) 1574 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 1575 DP_PHY_DPRX, DP_TRAINING_PATTERN_2); 1576 1577 return passed; 1578 } 1579 1580 /** 1581 * intel_dp_start_link_train - start link training 1582 * @state: Atomic state 1583 * @intel_dp: DP struct 1584 * @crtc_state: state for CRTC attached to the encoder 1585 * 1586 * Start the link training of the @intel_dp port, scheduling a fallback 1587 * retraining with reduced link rate/lane parameters if the link training 1588 * fails. 1589 * After calling this function intel_dp_stop_link_train() must be called. 1590 */ 1591 void intel_dp_start_link_train(struct intel_atomic_state *state, 1592 struct intel_dp *intel_dp, 1593 const struct intel_crtc_state *crtc_state) 1594 { 1595 struct intel_display *display = to_intel_display(state); 1596 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1597 struct intel_encoder *encoder = &dig_port->base; 1598 bool passed; 1599 /* 1600 * Reinit the LTTPRs here to ensure that they are switched to 1601 * non-transparent mode. During an earlier LTTPR detection this 1602 * could've been prevented by an active link. 1603 */ 1604 int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); 1605 1606 if (lttpr_count < 0) 1607 /* Still continue with enabling the port and link training. */ 1608 lttpr_count = 0; 1609 1610 intel_dp_prepare_link_train(intel_dp, crtc_state); 1611 1612 if (intel_dp_is_uhbr(crtc_state)) 1613 passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count); 1614 else 1615 passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); 1616 1617 if (intel_dp->link.force_train_failure) { 1618 intel_dp->link.force_train_failure--; 1619 lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n"); 1620 } else if (passed) { 1621 intel_dp->link.seq_train_failures = 0; 1622 intel_encoder_link_check_queue_work(encoder, 2000); 1623 return; 1624 } 1625 1626 intel_dp->link.seq_train_failures++; 1627 1628 /* 1629 * Ignore the link failure in CI 1630 * 1631 * In fixed enviroments like CI, sometimes unexpected long HPDs are 1632 * generated by the displays. If ignore_long_hpd flag is set, such long 1633 * HPDs are ignored. And probably as a consequence of these ignored 1634 * long HPDs, subsequent link trainings are failed resulting into CI 1635 * execution failures. 1636 * 1637 * For test cases which rely on the link training or processing of HPDs 1638 * ignore_long_hpd flag can unset from the testcase. 1639 */ 1640 if (display->hotplug.ignore_long_hpd) { 1641 lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n"); 1642 return; 1643 } 1644 1645 if (intel_dp->link.seq_train_failures < 2) { 1646 intel_encoder_link_check_queue_work(encoder, 0); 1647 return; 1648 } 1649 1650 if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state)) 1651 return; 1652 1653 intel_dp->link.retrain_disabled = true; 1654 1655 if (!passed) 1656 lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n"); 1657 else 1658 lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n"); 1659 } 1660 1661 void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, 1662 const struct intel_crtc_state *crtc_state) 1663 { 1664 /* 1665 * VIDEO_DIP_CTL register bit 31 should be set to '0' to not 1666 * disable SDP CRC. This is applicable for Display version 13. 1667 * Default value of bit 31 is '0' hence discarding the write 1668 * TODO: Corrective actions on SDP corruption yet to be defined 1669 */ 1670 if (!intel_dp_is_uhbr(crtc_state)) 1671 return; 1672 1673 /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ 1674 drm_dp_dpcd_writeb(&intel_dp->aux, 1675 DP_SDP_ERROR_DETECTION_CONFIGURATION, 1676 DP_SDP_CRC16_128B132B_EN); 1677 1678 lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n"); 1679 } 1680 1681 static int i915_dp_force_link_rate_show(struct seq_file *m, void *data) 1682 { 1683 struct intel_connector *connector = to_intel_connector(m->private); 1684 struct intel_display *display = to_intel_display(connector); 1685 struct intel_dp *intel_dp = intel_attached_dp(connector); 1686 int current_rate = -1; 1687 int force_rate; 1688 int err; 1689 int i; 1690 1691 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1692 if (err) 1693 return err; 1694 1695 if (intel_dp->link_trained) 1696 current_rate = intel_dp->link_rate; 1697 force_rate = intel_dp->link.force_rate; 1698 1699 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1700 1701 seq_printf(m, "%sauto%s", 1702 force_rate == 0 ? "[" : "", 1703 force_rate == 0 ? "]" : ""); 1704 1705 for (i = 0; i < intel_dp->num_source_rates; i++) 1706 seq_printf(m, " %s%d%s%s", 1707 intel_dp->source_rates[i] == force_rate ? "[" : "", 1708 intel_dp->source_rates[i], 1709 intel_dp->source_rates[i] == current_rate ? "*" : "", 1710 intel_dp->source_rates[i] == force_rate ? "]" : ""); 1711 1712 seq_putc(m, '\n'); 1713 1714 return 0; 1715 } 1716 1717 static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len) 1718 { 1719 char *kbuf; 1720 const char *p; 1721 int rate; 1722 int ret = 0; 1723 1724 kbuf = memdup_user_nul(ubuf, len); 1725 if (IS_ERR(kbuf)) 1726 return PTR_ERR(kbuf); 1727 1728 p = strim(kbuf); 1729 1730 if (!strcmp(p, "auto")) { 1731 rate = 0; 1732 } else { 1733 ret = kstrtoint(p, 0, &rate); 1734 if (ret < 0) 1735 goto out_free; 1736 1737 if (intel_dp_rate_index(intel_dp->source_rates, 1738 intel_dp->num_source_rates, 1739 rate) < 0) 1740 ret = -EINVAL; 1741 } 1742 1743 out_free: 1744 kfree(kbuf); 1745 1746 return ret < 0 ? ret : rate; 1747 } 1748 1749 static ssize_t i915_dp_force_link_rate_write(struct file *file, 1750 const char __user *ubuf, 1751 size_t len, loff_t *offp) 1752 { 1753 struct seq_file *m = file->private_data; 1754 struct intel_connector *connector = to_intel_connector(m->private); 1755 struct intel_display *display = to_intel_display(connector); 1756 struct intel_dp *intel_dp = intel_attached_dp(connector); 1757 int rate; 1758 int err; 1759 1760 rate = parse_link_rate(intel_dp, ubuf, len); 1761 if (rate < 0) 1762 return rate; 1763 1764 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1765 if (err) 1766 return err; 1767 1768 intel_dp_reset_link_params(intel_dp); 1769 intel_dp->link.force_rate = rate; 1770 1771 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1772 1773 *offp += len; 1774 1775 return len; 1776 } 1777 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_link_rate); 1778 1779 static int i915_dp_force_lane_count_show(struct seq_file *m, void *data) 1780 { 1781 struct intel_connector *connector = to_intel_connector(m->private); 1782 struct intel_display *display = to_intel_display(connector); 1783 struct intel_dp *intel_dp = intel_attached_dp(connector); 1784 int current_lane_count = -1; 1785 int force_lane_count; 1786 int err; 1787 int i; 1788 1789 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1790 if (err) 1791 return err; 1792 1793 if (intel_dp->link_trained) 1794 current_lane_count = intel_dp->lane_count; 1795 force_lane_count = intel_dp->link.force_lane_count; 1796 1797 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1798 1799 seq_printf(m, "%sauto%s", 1800 force_lane_count == 0 ? "[" : "", 1801 force_lane_count == 0 ? "]" : ""); 1802 1803 for (i = 1; i <= 4; i <<= 1) 1804 seq_printf(m, " %s%d%s%s", 1805 i == force_lane_count ? "[" : "", 1806 i, 1807 i == current_lane_count ? "*" : "", 1808 i == force_lane_count ? "]" : ""); 1809 1810 seq_putc(m, '\n'); 1811 1812 return 0; 1813 } 1814 1815 static int parse_lane_count(const char __user *ubuf, size_t len) 1816 { 1817 char *kbuf; 1818 const char *p; 1819 int lane_count; 1820 int ret = 0; 1821 1822 kbuf = memdup_user_nul(ubuf, len); 1823 if (IS_ERR(kbuf)) 1824 return PTR_ERR(kbuf); 1825 1826 p = strim(kbuf); 1827 1828 if (!strcmp(p, "auto")) { 1829 lane_count = 0; 1830 } else { 1831 ret = kstrtoint(p, 0, &lane_count); 1832 if (ret < 0) 1833 goto out_free; 1834 1835 switch (lane_count) { 1836 case 1: 1837 case 2: 1838 case 4: 1839 break; 1840 default: 1841 ret = -EINVAL; 1842 } 1843 } 1844 1845 out_free: 1846 kfree(kbuf); 1847 1848 return ret < 0 ? ret : lane_count; 1849 } 1850 1851 static ssize_t i915_dp_force_lane_count_write(struct file *file, 1852 const char __user *ubuf, 1853 size_t len, loff_t *offp) 1854 { 1855 struct seq_file *m = file->private_data; 1856 struct intel_connector *connector = to_intel_connector(m->private); 1857 struct intel_display *display = to_intel_display(connector); 1858 struct intel_dp *intel_dp = intel_attached_dp(connector); 1859 int lane_count; 1860 int err; 1861 1862 lane_count = parse_lane_count(ubuf, len); 1863 if (lane_count < 0) 1864 return lane_count; 1865 1866 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1867 if (err) 1868 return err; 1869 1870 intel_dp_reset_link_params(intel_dp); 1871 intel_dp->link.force_lane_count = lane_count; 1872 1873 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1874 1875 *offp += len; 1876 1877 return len; 1878 } 1879 DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_lane_count); 1880 1881 static int i915_dp_max_link_rate_show(void *data, u64 *val) 1882 { 1883 struct intel_connector *connector = to_intel_connector(data); 1884 struct intel_display *display = to_intel_display(connector); 1885 struct intel_dp *intel_dp = intel_attached_dp(connector); 1886 int err; 1887 1888 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1889 if (err) 1890 return err; 1891 1892 *val = intel_dp->link.max_rate; 1893 1894 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1895 1896 return 0; 1897 } 1898 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_link_rate_fops, i915_dp_max_link_rate_show, NULL, "%llu\n"); 1899 1900 static int i915_dp_max_lane_count_show(void *data, u64 *val) 1901 { 1902 struct intel_connector *connector = to_intel_connector(data); 1903 struct intel_display *display = to_intel_display(connector); 1904 struct intel_dp *intel_dp = intel_attached_dp(connector); 1905 int err; 1906 1907 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1908 if (err) 1909 return err; 1910 1911 *val = intel_dp->link.max_lane_count; 1912 1913 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1914 1915 return 0; 1916 } 1917 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n"); 1918 1919 static int i915_dp_force_link_training_failure_show(void *data, u64 *val) 1920 { 1921 struct intel_connector *connector = to_intel_connector(data); 1922 struct intel_display *display = to_intel_display(connector); 1923 struct intel_dp *intel_dp = intel_attached_dp(connector); 1924 int err; 1925 1926 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1927 if (err) 1928 return err; 1929 1930 *val = intel_dp->link.force_train_failure; 1931 1932 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1933 1934 return 0; 1935 } 1936 1937 static int i915_dp_force_link_training_failure_write(void *data, u64 val) 1938 { 1939 struct intel_connector *connector = to_intel_connector(data); 1940 struct intel_display *display = to_intel_display(connector); 1941 struct intel_dp *intel_dp = intel_attached_dp(connector); 1942 int err; 1943 1944 if (val > 2) 1945 return -EINVAL; 1946 1947 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1948 if (err) 1949 return err; 1950 1951 intel_dp->link.force_train_failure = val; 1952 1953 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1954 1955 return 0; 1956 } 1957 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, 1958 i915_dp_force_link_training_failure_show, 1959 i915_dp_force_link_training_failure_write, "%llu\n"); 1960 1961 static int i915_dp_force_link_retrain_show(void *data, u64 *val) 1962 { 1963 struct intel_connector *connector = to_intel_connector(data); 1964 struct intel_display *display = to_intel_display(connector); 1965 struct intel_dp *intel_dp = intel_attached_dp(connector); 1966 int err; 1967 1968 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1969 if (err) 1970 return err; 1971 1972 *val = intel_dp->link.force_retrain; 1973 1974 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1975 1976 return 0; 1977 } 1978 1979 static int i915_dp_force_link_retrain_write(void *data, u64 val) 1980 { 1981 struct intel_connector *connector = to_intel_connector(data); 1982 struct intel_display *display = to_intel_display(connector); 1983 struct intel_dp *intel_dp = intel_attached_dp(connector); 1984 int err; 1985 1986 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1987 if (err) 1988 return err; 1989 1990 intel_dp->link.force_retrain = val; 1991 1992 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1993 1994 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); 1995 1996 return 0; 1997 } 1998 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, 1999 i915_dp_force_link_retrain_show, 2000 i915_dp_force_link_retrain_write, "%llu\n"); 2001 2002 static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data) 2003 { 2004 struct intel_connector *connector = to_intel_connector(m->private); 2005 struct intel_display *display = to_intel_display(connector); 2006 struct intel_dp *intel_dp = intel_attached_dp(connector); 2007 int err; 2008 2009 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2010 if (err) 2011 return err; 2012 2013 seq_printf(m, "%s\n", str_yes_no(intel_dp->link.retrain_disabled)); 2014 2015 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2016 2017 return 0; 2018 } 2019 DEFINE_SHOW_ATTRIBUTE(i915_dp_link_retrain_disabled); 2020 2021 void intel_dp_link_training_debugfs_add(struct intel_connector *connector) 2022 { 2023 struct dentry *root = connector->base.debugfs_entry; 2024 2025 if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort && 2026 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 2027 return; 2028 2029 debugfs_create_file("i915_dp_force_link_rate", 0644, root, 2030 connector, &i915_dp_force_link_rate_fops); 2031 2032 debugfs_create_file("i915_dp_force_lane_count", 0644, root, 2033 connector, &i915_dp_force_lane_count_fops); 2034 2035 debugfs_create_file("i915_dp_max_link_rate", 0444, root, 2036 connector, &i915_dp_max_link_rate_fops); 2037 2038 debugfs_create_file("i915_dp_max_lane_count", 0444, root, 2039 connector, &i915_dp_max_lane_count_fops); 2040 2041 debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, 2042 connector, &i915_dp_force_link_training_failure_fops); 2043 2044 debugfs_create_file("i915_dp_force_link_retrain", 0644, root, 2045 connector, &i915_dp_force_link_retrain_fops); 2046 2047 debugfs_create_file("i915_dp_link_retrain_disabled", 0444, root, 2048 connector, &i915_dp_link_retrain_disabled_fops); 2049 } 2050