1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2020 Google, Inc. 4 * 5 * Authors: 6 * Sean Paul <seanpaul@chromium.org> 7 */ 8 9 #include <drm/display/drm_dp_helper.h> 10 #include <drm/display/drm_dp_mst_helper.h> 11 #include <drm/display/drm_hdcp_helper.h> 12 #include <drm/drm_print.h> 13 14 #include "i915_reg.h" 15 #include "intel_ddi.h" 16 #include "intel_de.h" 17 #include "intel_display_types.h" 18 #include "intel_dp.h" 19 #include "intel_dp_hdcp.h" 20 #include "intel_hdcp.h" 21 #include "intel_hdcp_regs.h" 22 #include "intel_hdcp_shim.h" 23 24 static u32 transcoder_to_stream_enc_status(enum transcoder cpu_transcoder) 25 { 26 switch (cpu_transcoder) { 27 case TRANSCODER_A: 28 return HDCP_STATUS_STREAM_A_ENC; 29 case TRANSCODER_B: 30 return HDCP_STATUS_STREAM_B_ENC; 31 case TRANSCODER_C: 32 return HDCP_STATUS_STREAM_C_ENC; 33 case TRANSCODER_D: 34 return HDCP_STATUS_STREAM_D_ENC; 35 default: 36 return 0; 37 } 38 } 39 40 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_connector *connector, 41 int timeout) 42 { 43 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 44 struct intel_dp *dp = &dig_port->dp; 45 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 46 long ret; 47 48 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) 49 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, 50 msecs_to_jiffies(timeout)); 51 52 if (!ret) 53 drm_dbg_kms(connector->base.dev, 54 "Timedout at waiting for CP_IRQ\n"); 55 } 56 57 static 58 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 59 u8 *an) 60 { 61 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 62 u8 aksv[DRM_HDCP_KSV_LEN] = {}; 63 ssize_t dpcd_ret; 64 65 /* Output An first, that's easy */ 66 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN, 67 an, DRM_HDCP_AN_LEN); 68 if (dpcd_ret != DRM_HDCP_AN_LEN) { 69 drm_dbg_kms(&i915->drm, 70 "Failed to write An over DP/AUX (%zd)\n", 71 dpcd_ret); 72 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 73 } 74 75 /* 76 * Since Aksv is Oh-So-Secret, we can't access it in software. So we 77 * send an empty buffer of the correct length through the DP helpers. On 78 * the other side, in the transfer hook, we'll generate a flag based on 79 * the destination address which will tickle the hardware to output the 80 * Aksv on our behalf after the header is sent. 81 */ 82 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV, 83 aksv, DRM_HDCP_KSV_LEN); 84 if (dpcd_ret != DRM_HDCP_KSV_LEN) { 85 drm_dbg_kms(&i915->drm, 86 "Failed to write Aksv over DP/AUX (%zd)\n", 87 dpcd_ret); 88 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 89 } 90 return 0; 91 } 92 93 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port, 94 u8 *bksv) 95 { 96 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 97 ssize_t ret; 98 99 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, 100 DRM_HDCP_KSV_LEN); 101 if (ret != DRM_HDCP_KSV_LEN) { 102 drm_dbg_kms(&i915->drm, 103 "Read Bksv from DP/AUX failed (%zd)\n", ret); 104 return ret >= 0 ? -EIO : ret; 105 } 106 return 0; 107 } 108 109 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port, 110 u8 *bstatus) 111 { 112 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 113 ssize_t ret; 114 115 /* 116 * For some reason the HDMI and DP HDCP specs call this register 117 * definition by different names. In the HDMI spec, it's called BSTATUS, 118 * but in DP it's called BINFO. 119 */ 120 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO, 121 bstatus, DRM_HDCP_BSTATUS_LEN); 122 if (ret != DRM_HDCP_BSTATUS_LEN) { 123 drm_dbg_kms(&i915->drm, 124 "Read bstatus from DP/AUX failed (%zd)\n", ret); 125 return ret >= 0 ? -EIO : ret; 126 } 127 return 0; 128 } 129 130 static 131 int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux, 132 struct drm_i915_private *i915, 133 u8 *bcaps) 134 { 135 ssize_t ret; 136 137 ret = drm_dp_dpcd_read(aux, DP_AUX_HDCP_BCAPS, 138 bcaps, 1); 139 if (ret != 1) { 140 drm_dbg_kms(&i915->drm, 141 "Read bcaps from DP/AUX failed (%zd)\n", ret); 142 return ret >= 0 ? -EIO : ret; 143 } 144 145 return 0; 146 } 147 148 static 149 int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port, 150 bool *repeater_present) 151 { 152 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 153 ssize_t ret; 154 u8 bcaps; 155 156 ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps); 157 if (ret) 158 return ret; 159 160 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; 161 return 0; 162 } 163 164 static 165 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 166 u8 *ri_prime) 167 { 168 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 169 ssize_t ret; 170 171 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, 172 ri_prime, DRM_HDCP_RI_LEN); 173 if (ret != DRM_HDCP_RI_LEN) { 174 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", 175 ret); 176 return ret >= 0 ? -EIO : ret; 177 } 178 return 0; 179 } 180 181 static 182 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 183 bool *ksv_ready) 184 { 185 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 186 ssize_t ret; 187 u8 bstatus; 188 189 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 190 &bstatus, 1); 191 if (ret != 1) { 192 drm_dbg_kms(&i915->drm, 193 "Read bstatus from DP/AUX failed (%zd)\n", ret); 194 return ret >= 0 ? -EIO : ret; 195 } 196 *ksv_ready = bstatus & DP_BSTATUS_READY; 197 return 0; 198 } 199 200 static 201 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 202 int num_downstream, u8 *ksv_fifo) 203 { 204 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 205 ssize_t ret; 206 int i; 207 208 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ 209 for (i = 0; i < num_downstream; i += 3) { 210 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; 211 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 212 DP_AUX_HDCP_KSV_FIFO, 213 ksv_fifo + i * DRM_HDCP_KSV_LEN, 214 len); 215 if (ret != len) { 216 drm_dbg_kms(&i915->drm, 217 "Read ksv[%d] from DP/AUX failed (%zd)\n", 218 i, ret); 219 return ret >= 0 ? -EIO : ret; 220 } 221 } 222 return 0; 223 } 224 225 static 226 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 227 int i, u32 *part) 228 { 229 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 230 ssize_t ret; 231 232 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 233 return -EINVAL; 234 235 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 236 DP_AUX_HDCP_V_PRIME(i), part, 237 DRM_HDCP_V_PRIME_PART_LEN); 238 if (ret != DRM_HDCP_V_PRIME_PART_LEN) { 239 drm_dbg_kms(&i915->drm, 240 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); 241 return ret >= 0 ? -EIO : ret; 242 } 243 return 0; 244 } 245 246 static 247 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 248 enum transcoder cpu_transcoder, 249 bool enable) 250 { 251 /* Not used for single stream DisplayPort setups */ 252 return 0; 253 } 254 255 static 256 bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port, 257 struct intel_connector *connector) 258 { 259 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 260 ssize_t ret; 261 u8 bstatus; 262 263 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 264 &bstatus, 1); 265 if (ret != 1) { 266 drm_dbg_kms(&i915->drm, 267 "Read bstatus from DP/AUX failed (%zd)\n", ret); 268 return false; 269 } 270 271 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); 272 } 273 274 static 275 int intel_dp_hdcp_get_capability(struct intel_digital_port *dig_port, 276 bool *hdcp_capable) 277 { 278 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 279 ssize_t ret; 280 u8 bcaps; 281 282 ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps); 283 if (ret) 284 return ret; 285 286 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; 287 return 0; 288 } 289 290 struct hdcp2_dp_errata_stream_type { 291 u8 msg_id; 292 u8 stream_type; 293 } __packed; 294 295 struct hdcp2_dp_msg_data { 296 u8 msg_id; 297 u32 offset; 298 bool msg_detectable; 299 u32 timeout; 300 u32 timeout2; /* Added for non_paired situation */ 301 /* Timeout to read entire msg */ 302 u32 msg_read_timeout; 303 }; 304 305 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { 306 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0}, 307 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, 308 false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS}, 309 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, 310 false, 0, 0, 0 }, 311 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, 312 false, 0, 0, 0 }, 313 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, 314 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, 315 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS}, 316 { HDCP_2_2_AKE_SEND_PAIRING_INFO, 317 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, 318 HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS }, 319 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 }, 320 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, 321 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 }, 322 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, 323 0, 0, 0 }, 324 { HDCP_2_2_REP_SEND_RECVID_LIST, 325 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, 326 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 }, 327 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, 328 0, 0, 0 }, 329 { HDCP_2_2_REP_STREAM_MANAGE, 330 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, 331 0, 0, 0}, 332 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, 333 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 }, 334 /* local define to shovel this through the write_2_2 interface */ 335 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 336 { HDCP_2_2_ERRATA_DP_STREAM_TYPE, 337 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, 338 0, 0 }, 339 }; 340 341 static int 342 intel_dp_hdcp2_read_rx_status(struct intel_connector *connector, 343 u8 *rx_status) 344 { 345 struct drm_i915_private *i915 = to_i915(connector->base.dev); 346 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 347 struct drm_dp_aux *aux = &dig_port->dp.aux; 348 ssize_t ret; 349 350 ret = drm_dp_dpcd_read(aux, 351 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, 352 HDCP_2_2_DP_RXSTATUS_LEN); 353 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { 354 drm_dbg_kms(&i915->drm, 355 "Read bstatus from DP/AUX failed (%zd)\n", ret); 356 return ret >= 0 ? -EIO : ret; 357 } 358 359 return 0; 360 } 361 362 static 363 int hdcp2_detect_msg_availability(struct intel_connector *connector, 364 u8 msg_id, bool *msg_ready) 365 { 366 u8 rx_status; 367 int ret; 368 369 *msg_ready = false; 370 ret = intel_dp_hdcp2_read_rx_status(connector, &rx_status); 371 if (ret < 0) 372 return ret; 373 374 switch (msg_id) { 375 case HDCP_2_2_AKE_SEND_HPRIME: 376 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) 377 *msg_ready = true; 378 break; 379 case HDCP_2_2_AKE_SEND_PAIRING_INFO: 380 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) 381 *msg_ready = true; 382 break; 383 case HDCP_2_2_REP_SEND_RECVID_LIST: 384 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 385 *msg_ready = true; 386 break; 387 default: 388 drm_err(connector->base.dev, 389 "Unidentified msg_id: %d\n", msg_id); 390 return -EINVAL; 391 } 392 393 return 0; 394 } 395 396 static ssize_t 397 intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector, 398 const struct hdcp2_dp_msg_data *hdcp2_msg_data) 399 { 400 struct drm_i915_private *i915 = to_i915(connector->base.dev); 401 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 402 struct intel_dp *dp = &dig_port->dp; 403 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 404 u8 msg_id = hdcp2_msg_data->msg_id; 405 int ret, timeout; 406 bool msg_ready = false; 407 408 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) 409 timeout = hdcp2_msg_data->timeout2; 410 else 411 timeout = hdcp2_msg_data->timeout; 412 413 /* 414 * There is no way to detect the CERT, LPRIME and STREAM_READY 415 * availability. So Wait for timeout and read the msg. 416 */ 417 if (!hdcp2_msg_data->msg_detectable) { 418 mdelay(timeout); 419 ret = 0; 420 } else { 421 /* 422 * As we want to check the msg availability at timeout, Ignoring 423 * the timeout at wait for CP_IRQ. 424 */ 425 intel_dp_hdcp_wait_for_cp_irq(connector, timeout); 426 ret = hdcp2_detect_msg_availability(connector, msg_id, 427 &msg_ready); 428 if (!msg_ready) 429 ret = -ETIMEDOUT; 430 } 431 432 if (ret) 433 drm_dbg_kms(&i915->drm, 434 "msg_id %d, ret %d, timeout(mSec): %d\n", 435 hdcp2_msg_data->msg_id, ret, timeout); 436 437 return ret; 438 } 439 440 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) 441 { 442 int i; 443 444 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++) 445 if (hdcp2_dp_msg_data[i].msg_id == msg_id) 446 return &hdcp2_dp_msg_data[i]; 447 448 return NULL; 449 } 450 451 static 452 int intel_dp_hdcp2_write_msg(struct intel_connector *connector, 453 void *buf, size_t size) 454 { 455 unsigned int offset; 456 u8 *byte = buf; 457 ssize_t ret, bytes_to_write, len; 458 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 459 struct drm_dp_aux *aux = &dig_port->dp.aux; 460 const struct hdcp2_dp_msg_data *hdcp2_msg_data; 461 462 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); 463 if (!hdcp2_msg_data) 464 return -EINVAL; 465 466 offset = hdcp2_msg_data->offset; 467 468 /* No msg_id in DP HDCP2.2 msgs */ 469 bytes_to_write = size - 1; 470 byte++; 471 472 while (bytes_to_write) { 473 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? 474 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; 475 476 ret = drm_dp_dpcd_write(aux, 477 offset, (void *)byte, len); 478 if (ret < 0) 479 return ret; 480 481 bytes_to_write -= ret; 482 byte += ret; 483 offset += ret; 484 } 485 486 return size; 487 } 488 489 static 490 ssize_t get_receiver_id_list_rx_info(struct intel_connector *connector, 491 u32 *dev_cnt, u8 *byte) 492 { 493 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 494 struct drm_dp_aux *aux = &dig_port->dp.aux; 495 ssize_t ret; 496 u8 *rx_info = byte; 497 498 ret = drm_dp_dpcd_read(aux, 499 DP_HDCP_2_2_REG_RXINFO_OFFSET, 500 (void *)rx_info, HDCP_2_2_RXINFO_LEN); 501 if (ret != HDCP_2_2_RXINFO_LEN) 502 return ret >= 0 ? -EIO : ret; 503 504 *dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 505 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 506 507 if (*dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) 508 *dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; 509 510 return ret; 511 } 512 513 static 514 int intel_dp_hdcp2_read_msg(struct intel_connector *connector, 515 u8 msg_id, void *buf, size_t size) 516 { 517 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 518 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 519 struct drm_dp_aux *aux = &dig_port->dp.aux; 520 struct intel_dp *dp = &dig_port->dp; 521 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 522 unsigned int offset; 523 u8 *byte = buf; 524 ssize_t ret, bytes_to_recv, len; 525 const struct hdcp2_dp_msg_data *hdcp2_msg_data; 526 ktime_t msg_end = ktime_set(0, 0); 527 bool msg_expired; 528 u32 dev_cnt; 529 530 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); 531 if (!hdcp2_msg_data) 532 return -EINVAL; 533 offset = hdcp2_msg_data->offset; 534 535 ret = intel_dp_hdcp2_wait_for_msg(connector, hdcp2_msg_data); 536 if (ret < 0) 537 return ret; 538 539 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count); 540 541 /* DP adaptation msgs has no msg_id */ 542 byte++; 543 544 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { 545 ret = get_receiver_id_list_rx_info(connector, &dev_cnt, byte); 546 if (ret < 0) 547 return ret; 548 549 byte += ret; 550 size = sizeof(struct hdcp2_rep_send_receiverid_list) - 551 HDCP_2_2_RXINFO_LEN - HDCP_2_2_RECEIVER_IDS_MAX_LEN + 552 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); 553 offset += HDCP_2_2_RXINFO_LEN; 554 } 555 556 bytes_to_recv = size - 1; 557 558 while (bytes_to_recv) { 559 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? 560 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; 561 562 /* Entire msg read timeout since initiate of msg read */ 563 if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0) { 564 msg_end = ktime_add_ms(ktime_get_raw(), 565 hdcp2_msg_data->msg_read_timeout); 566 } 567 568 ret = drm_dp_dpcd_read(aux, offset, 569 (void *)byte, len); 570 if (ret < 0) { 571 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", 572 msg_id, ret); 573 return ret; 574 } 575 576 bytes_to_recv -= ret; 577 byte += ret; 578 offset += ret; 579 } 580 581 if (hdcp2_msg_data->msg_read_timeout > 0) { 582 msg_expired = ktime_after(ktime_get_raw(), msg_end); 583 if (msg_expired) { 584 drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n", 585 msg_id, hdcp2_msg_data->msg_read_timeout); 586 return -ETIMEDOUT; 587 } 588 } 589 590 byte = buf; 591 *byte = msg_id; 592 593 return size; 594 } 595 596 static 597 int intel_dp_hdcp2_config_stream_type(struct intel_connector *connector, 598 bool is_repeater, u8 content_type) 599 { 600 int ret; 601 struct hdcp2_dp_errata_stream_type stream_type_msg; 602 603 if (is_repeater) 604 return 0; 605 606 /* 607 * Errata for DP: As Stream type is used for encryption, Receiver 608 * should be communicated with stream type for the decryption of the 609 * content. 610 * Repeater will be communicated with stream type as a part of it's 611 * auth later in time. 612 */ 613 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; 614 stream_type_msg.stream_type = content_type; 615 616 ret = intel_dp_hdcp2_write_msg(connector, &stream_type_msg, 617 sizeof(stream_type_msg)); 618 619 return ret < 0 ? ret : 0; 620 621 } 622 623 static 624 int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port, 625 struct intel_connector *connector) 626 { 627 u8 rx_status; 628 int ret; 629 630 ret = intel_dp_hdcp2_read_rx_status(connector, 631 &rx_status); 632 if (ret) 633 return ret; 634 635 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) 636 ret = HDCP_REAUTH_REQUEST; 637 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) 638 ret = HDCP_LINK_INTEGRITY_FAILURE; 639 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 640 ret = HDCP_TOPOLOGY_CHANGE; 641 642 return ret; 643 } 644 645 static 646 int _intel_dp_hdcp2_get_capability(struct drm_dp_aux *aux, 647 bool *capable) 648 { 649 u8 rx_caps[3]; 650 int ret, i; 651 652 *capable = false; 653 654 /* 655 * Some HDCP monitors act really shady by not giving the correct hdcp 656 * capability on the first rx_caps read and usually take an extra read 657 * to give the capability. We read rx_caps three times before we 658 * declare a monitor not capable of HDCP 2.2. 659 */ 660 for (i = 0; i < 3; i++) { 661 ret = drm_dp_dpcd_read(aux, 662 DP_HDCP_2_2_REG_RX_CAPS_OFFSET, 663 rx_caps, HDCP_2_2_RXCAPS_LEN); 664 if (ret != HDCP_2_2_RXCAPS_LEN) 665 return ret >= 0 ? -EIO : ret; 666 667 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && 668 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) { 669 *capable = true; 670 break; 671 } 672 } 673 674 return 0; 675 } 676 677 static 678 int intel_dp_hdcp2_get_capability(struct intel_connector *connector, 679 bool *capable) 680 { 681 struct intel_digital_port *dig_port; 682 struct drm_dp_aux *aux; 683 684 *capable = false; 685 if (!intel_attached_encoder(connector)) 686 return -EINVAL; 687 688 dig_port = intel_attached_dig_port(connector); 689 aux = &dig_port->dp.aux; 690 691 return _intel_dp_hdcp2_get_capability(aux, capable); 692 } 693 694 static 695 int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector, 696 bool *hdcp_capable, 697 bool *hdcp2_capable) 698 { 699 struct drm_i915_private *i915 = to_i915(connector->base.dev); 700 struct drm_dp_aux *aux; 701 u8 bcaps; 702 int ret; 703 704 *hdcp_capable = false; 705 *hdcp2_capable = false; 706 if (!connector->mst_port) 707 return -EINVAL; 708 709 aux = &connector->port->aux; 710 ret = _intel_dp_hdcp2_get_capability(aux, hdcp2_capable); 711 if (ret) 712 drm_dbg_kms(&i915->drm, 713 "HDCP2 DPCD capability read failed err: %d\n", ret); 714 715 ret = intel_dp_hdcp_read_bcaps(aux, i915, &bcaps); 716 if (ret) 717 return ret; 718 719 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; 720 721 return 0; 722 } 723 724 static const struct intel_hdcp_shim intel_dp_hdcp_shim = { 725 .write_an_aksv = intel_dp_hdcp_write_an_aksv, 726 .read_bksv = intel_dp_hdcp_read_bksv, 727 .read_bstatus = intel_dp_hdcp_read_bstatus, 728 .repeater_present = intel_dp_hdcp_repeater_present, 729 .read_ri_prime = intel_dp_hdcp_read_ri_prime, 730 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 731 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 732 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 733 .toggle_signalling = intel_dp_hdcp_toggle_signalling, 734 .check_link = intel_dp_hdcp_check_link, 735 .hdcp_get_capability = intel_dp_hdcp_get_capability, 736 .write_2_2_msg = intel_dp_hdcp2_write_msg, 737 .read_2_2_msg = intel_dp_hdcp2_read_msg, 738 .config_stream_type = intel_dp_hdcp2_config_stream_type, 739 .check_2_2_link = intel_dp_hdcp2_check_link, 740 .hdcp_2_2_get_capability = intel_dp_hdcp2_get_capability, 741 .protocol = HDCP_PROTOCOL_DP, 742 }; 743 744 static int 745 intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector, 746 bool enable) 747 { 748 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 749 struct drm_i915_private *i915 = to_i915(connector->base.dev); 750 struct intel_hdcp *hdcp = &connector->hdcp; 751 int ret; 752 753 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 754 hdcp->stream_transcoder, enable, 755 TRANS_DDI_HDCP_SELECT); 756 if (ret) 757 drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n", 758 enable ? "Enable" : "Disable", ret); 759 return ret; 760 } 761 762 static int 763 intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector, 764 bool enable) 765 { 766 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 767 struct drm_i915_private *i915 = to_i915(connector->base.dev); 768 struct intel_hdcp *hdcp = &connector->hdcp; 769 enum port port = dig_port->base.port; 770 enum transcoder cpu_transcoder = hdcp->stream_transcoder; 771 u32 stream_enc_status; 772 int ret; 773 774 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 775 if (ret) 776 return ret; 777 778 stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder); 779 if (!stream_enc_status) 780 return -EINVAL; 781 782 /* Wait for encryption confirmation */ 783 if (intel_de_wait(i915, HDCP_STATUS(i915, cpu_transcoder, port), 784 stream_enc_status, enable ? stream_enc_status : 0, 785 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 786 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 787 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 788 return -ETIMEDOUT; 789 } 790 791 return 0; 792 } 793 794 static int 795 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector, 796 bool enable) 797 { 798 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 799 struct drm_i915_private *i915 = to_i915(connector->base.dev); 800 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 801 struct intel_hdcp *hdcp = &connector->hdcp; 802 enum transcoder cpu_transcoder = hdcp->stream_transcoder; 803 enum pipe pipe = (enum pipe)cpu_transcoder; 804 enum port port = dig_port->base.port; 805 int ret; 806 807 drm_WARN_ON(&i915->drm, enable && 808 !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port)) 809 & AUTH_STREAM_TYPE) != data->streams[0].stream_type); 810 811 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 812 if (ret) 813 return ret; 814 815 /* Wait for encryption confirmation */ 816 if (intel_de_wait(i915, HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe), 817 STREAM_ENCRYPTION_STATUS, 818 enable ? STREAM_ENCRYPTION_STATUS : 0, 819 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 820 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 821 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 822 return -ETIMEDOUT; 823 } 824 825 return 0; 826 } 827 828 static 829 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port, 830 struct intel_connector *connector) 831 { 832 struct intel_hdcp *hdcp = &connector->hdcp; 833 int ret; 834 835 /* 836 * We do need to do the Link Check only for the connector involved with 837 * HDCP port authentication and encryption. 838 * We can re-use the hdcp->is_repeater flag to know that the connector 839 * involved with HDCP port authentication and encryption. 840 */ 841 if (hdcp->is_repeater) { 842 ret = intel_dp_hdcp2_check_link(dig_port, connector); 843 if (ret) 844 return ret; 845 } 846 847 return 0; 848 } 849 850 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { 851 .write_an_aksv = intel_dp_hdcp_write_an_aksv, 852 .read_bksv = intel_dp_hdcp_read_bksv, 853 .read_bstatus = intel_dp_hdcp_read_bstatus, 854 .repeater_present = intel_dp_hdcp_repeater_present, 855 .read_ri_prime = intel_dp_hdcp_read_ri_prime, 856 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 857 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 858 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 859 .toggle_signalling = intel_dp_hdcp_toggle_signalling, 860 .stream_encryption = intel_dp_mst_hdcp_stream_encryption, 861 .check_link = intel_dp_hdcp_check_link, 862 .hdcp_get_capability = intel_dp_hdcp_get_capability, 863 .write_2_2_msg = intel_dp_hdcp2_write_msg, 864 .read_2_2_msg = intel_dp_hdcp2_read_msg, 865 .config_stream_type = intel_dp_hdcp2_config_stream_type, 866 .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption, 867 .check_2_2_link = intel_dp_mst_hdcp2_check_link, 868 .hdcp_2_2_get_capability = intel_dp_hdcp2_get_capability, 869 .get_remote_hdcp_capability = intel_dp_hdcp_get_remote_capability, 870 .protocol = HDCP_PROTOCOL_DP, 871 }; 872 873 int intel_dp_hdcp_init(struct intel_digital_port *dig_port, 874 struct intel_connector *intel_connector) 875 { 876 struct drm_device *dev = intel_connector->base.dev; 877 struct drm_i915_private *dev_priv = to_i915(dev); 878 struct intel_encoder *intel_encoder = &dig_port->base; 879 enum port port = intel_encoder->port; 880 struct intel_dp *intel_dp = &dig_port->dp; 881 882 if (!is_hdcp_supported(dev_priv, port)) 883 return 0; 884 885 if (intel_connector->mst_port) 886 return intel_hdcp_init(intel_connector, dig_port, 887 &intel_dp_mst_hdcp_shim); 888 else if (!intel_dp_is_edp(intel_dp)) 889 return intel_hdcp_init(intel_connector, dig_port, 890 &intel_dp_hdcp_shim); 891 892 return 0; 893 } 894