1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2020 Google, Inc. 4 * 5 * Authors: 6 * Sean Paul <seanpaul@chromium.org> 7 */ 8 9 #include <drm/display/drm_dp_helper.h> 10 #include <drm/display/drm_dp_mst_helper.h> 11 #include <drm/display/drm_hdcp_helper.h> 12 #include <drm/drm_print.h> 13 14 #include "i915_reg.h" 15 #include "intel_ddi.h" 16 #include "intel_de.h" 17 #include "intel_display_types.h" 18 #include "intel_dp.h" 19 #include "intel_dp_hdcp.h" 20 #include "intel_hdcp.h" 21 #include "intel_hdcp_regs.h" 22 23 static u32 transcoder_to_stream_enc_status(enum transcoder cpu_transcoder) 24 { 25 switch (cpu_transcoder) { 26 case TRANSCODER_A: 27 return HDCP_STATUS_STREAM_A_ENC; 28 case TRANSCODER_B: 29 return HDCP_STATUS_STREAM_B_ENC; 30 case TRANSCODER_C: 31 return HDCP_STATUS_STREAM_C_ENC; 32 case TRANSCODER_D: 33 return HDCP_STATUS_STREAM_D_ENC; 34 default: 35 return 0; 36 } 37 } 38 39 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_connector *connector, 40 int timeout) 41 { 42 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 43 struct intel_dp *dp = &dig_port->dp; 44 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 45 long ret; 46 47 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) 48 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, 49 msecs_to_jiffies(timeout)); 50 51 if (!ret) 52 drm_dbg_kms(connector->base.dev, 53 "Timedout at waiting for CP_IRQ\n"); 54 } 55 56 static 57 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 58 u8 *an) 59 { 60 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 61 u8 aksv[DRM_HDCP_KSV_LEN] = {}; 62 ssize_t dpcd_ret; 63 64 /* Output An first, that's easy */ 65 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN, 66 an, DRM_HDCP_AN_LEN); 67 if (dpcd_ret != DRM_HDCP_AN_LEN) { 68 drm_dbg_kms(&i915->drm, 69 "Failed to write An over DP/AUX (%zd)\n", 70 dpcd_ret); 71 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 72 } 73 74 /* 75 * Since Aksv is Oh-So-Secret, we can't access it in software. So we 76 * send an empty buffer of the correct length through the DP helpers. On 77 * the other side, in the transfer hook, we'll generate a flag based on 78 * the destination address which will tickle the hardware to output the 79 * Aksv on our behalf after the header is sent. 80 */ 81 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV, 82 aksv, DRM_HDCP_KSV_LEN); 83 if (dpcd_ret != DRM_HDCP_KSV_LEN) { 84 drm_dbg_kms(&i915->drm, 85 "Failed to write Aksv over DP/AUX (%zd)\n", 86 dpcd_ret); 87 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 88 } 89 return 0; 90 } 91 92 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port, 93 u8 *bksv) 94 { 95 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 96 ssize_t ret; 97 98 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, 99 DRM_HDCP_KSV_LEN); 100 if (ret != DRM_HDCP_KSV_LEN) { 101 drm_dbg_kms(&i915->drm, 102 "Read Bksv from DP/AUX failed (%zd)\n", ret); 103 return ret >= 0 ? -EIO : ret; 104 } 105 return 0; 106 } 107 108 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port, 109 u8 *bstatus) 110 { 111 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 112 ssize_t ret; 113 114 /* 115 * For some reason the HDMI and DP HDCP specs call this register 116 * definition by different names. In the HDMI spec, it's called BSTATUS, 117 * but in DP it's called BINFO. 118 */ 119 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO, 120 bstatus, DRM_HDCP_BSTATUS_LEN); 121 if (ret != DRM_HDCP_BSTATUS_LEN) { 122 drm_dbg_kms(&i915->drm, 123 "Read bstatus from DP/AUX failed (%zd)\n", ret); 124 return ret >= 0 ? -EIO : ret; 125 } 126 return 0; 127 } 128 129 static 130 int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux, 131 struct drm_i915_private *i915, 132 u8 *bcaps) 133 { 134 ssize_t ret; 135 136 ret = drm_dp_dpcd_read(aux, DP_AUX_HDCP_BCAPS, 137 bcaps, 1); 138 if (ret != 1) { 139 drm_dbg_kms(&i915->drm, 140 "Read bcaps from DP/AUX failed (%zd)\n", ret); 141 return ret >= 0 ? -EIO : ret; 142 } 143 144 return 0; 145 } 146 147 static 148 int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port, 149 bool *repeater_present) 150 { 151 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 152 ssize_t ret; 153 u8 bcaps; 154 155 ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps); 156 if (ret) 157 return ret; 158 159 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; 160 return 0; 161 } 162 163 static 164 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 165 u8 *ri_prime) 166 { 167 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 168 ssize_t ret; 169 170 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, 171 ri_prime, DRM_HDCP_RI_LEN); 172 if (ret != DRM_HDCP_RI_LEN) { 173 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", 174 ret); 175 return ret >= 0 ? -EIO : ret; 176 } 177 return 0; 178 } 179 180 static 181 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 182 bool *ksv_ready) 183 { 184 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 185 ssize_t ret; 186 u8 bstatus; 187 188 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 189 &bstatus, 1); 190 if (ret != 1) { 191 drm_dbg_kms(&i915->drm, 192 "Read bstatus from DP/AUX failed (%zd)\n", ret); 193 return ret >= 0 ? -EIO : ret; 194 } 195 *ksv_ready = bstatus & DP_BSTATUS_READY; 196 return 0; 197 } 198 199 static 200 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 201 int num_downstream, u8 *ksv_fifo) 202 { 203 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 204 ssize_t ret; 205 int i; 206 207 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ 208 for (i = 0; i < num_downstream; i += 3) { 209 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; 210 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 211 DP_AUX_HDCP_KSV_FIFO, 212 ksv_fifo + i * DRM_HDCP_KSV_LEN, 213 len); 214 if (ret != len) { 215 drm_dbg_kms(&i915->drm, 216 "Read ksv[%d] from DP/AUX failed (%zd)\n", 217 i, ret); 218 return ret >= 0 ? -EIO : ret; 219 } 220 } 221 return 0; 222 } 223 224 static 225 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 226 int i, u32 *part) 227 { 228 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 229 ssize_t ret; 230 231 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 232 return -EINVAL; 233 234 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 235 DP_AUX_HDCP_V_PRIME(i), part, 236 DRM_HDCP_V_PRIME_PART_LEN); 237 if (ret != DRM_HDCP_V_PRIME_PART_LEN) { 238 drm_dbg_kms(&i915->drm, 239 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); 240 return ret >= 0 ? -EIO : ret; 241 } 242 return 0; 243 } 244 245 static 246 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 247 enum transcoder cpu_transcoder, 248 bool enable) 249 { 250 /* Not used for single stream DisplayPort setups */ 251 return 0; 252 } 253 254 static 255 bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port, 256 struct intel_connector *connector) 257 { 258 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 259 ssize_t ret; 260 u8 bstatus; 261 262 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 263 &bstatus, 1); 264 if (ret != 1) { 265 drm_dbg_kms(&i915->drm, 266 "Read bstatus from DP/AUX failed (%zd)\n", ret); 267 return false; 268 } 269 270 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); 271 } 272 273 static 274 int intel_dp_hdcp_get_capability(struct intel_digital_port *dig_port, 275 bool *hdcp_capable) 276 { 277 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 278 ssize_t ret; 279 u8 bcaps; 280 281 ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps); 282 if (ret) 283 return ret; 284 285 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; 286 return 0; 287 } 288 289 struct hdcp2_dp_errata_stream_type { 290 u8 msg_id; 291 u8 stream_type; 292 } __packed; 293 294 struct hdcp2_dp_msg_data { 295 u8 msg_id; 296 u32 offset; 297 bool msg_detectable; 298 u32 timeout; 299 u32 timeout2; /* Added for non_paired situation */ 300 /* Timeout to read entire msg */ 301 u32 msg_read_timeout; 302 }; 303 304 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { 305 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0}, 306 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, 307 false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS}, 308 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, 309 false, 0, 0, 0 }, 310 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, 311 false, 0, 0, 0 }, 312 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, 313 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, 314 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS}, 315 { HDCP_2_2_AKE_SEND_PAIRING_INFO, 316 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, 317 HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS }, 318 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 }, 319 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, 320 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 }, 321 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, 322 0, 0, 0 }, 323 { HDCP_2_2_REP_SEND_RECVID_LIST, 324 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, 325 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 }, 326 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, 327 0, 0, 0 }, 328 { HDCP_2_2_REP_STREAM_MANAGE, 329 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, 330 0, 0, 0}, 331 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, 332 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 }, 333 /* local define to shovel this through the write_2_2 interface */ 334 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 335 { HDCP_2_2_ERRATA_DP_STREAM_TYPE, 336 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, 337 0, 0 }, 338 }; 339 340 static int 341 intel_dp_hdcp2_read_rx_status(struct intel_connector *connector, 342 u8 *rx_status) 343 { 344 struct drm_i915_private *i915 = to_i915(connector->base.dev); 345 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 346 struct drm_dp_aux *aux = &dig_port->dp.aux; 347 ssize_t ret; 348 349 ret = drm_dp_dpcd_read(aux, 350 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, 351 HDCP_2_2_DP_RXSTATUS_LEN); 352 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { 353 drm_dbg_kms(&i915->drm, 354 "Read bstatus from DP/AUX failed (%zd)\n", ret); 355 return ret >= 0 ? -EIO : ret; 356 } 357 358 return 0; 359 } 360 361 static 362 int hdcp2_detect_msg_availability(struct intel_connector *connector, 363 u8 msg_id, bool *msg_ready) 364 { 365 u8 rx_status; 366 int ret; 367 368 *msg_ready = false; 369 ret = intel_dp_hdcp2_read_rx_status(connector, &rx_status); 370 if (ret < 0) 371 return ret; 372 373 switch (msg_id) { 374 case HDCP_2_2_AKE_SEND_HPRIME: 375 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) 376 *msg_ready = true; 377 break; 378 case HDCP_2_2_AKE_SEND_PAIRING_INFO: 379 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) 380 *msg_ready = true; 381 break; 382 case HDCP_2_2_REP_SEND_RECVID_LIST: 383 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 384 *msg_ready = true; 385 break; 386 default: 387 drm_err(connector->base.dev, 388 "Unidentified msg_id: %d\n", msg_id); 389 return -EINVAL; 390 } 391 392 return 0; 393 } 394 395 static ssize_t 396 intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector, 397 const struct hdcp2_dp_msg_data *hdcp2_msg_data) 398 { 399 struct drm_i915_private *i915 = to_i915(connector->base.dev); 400 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 401 struct intel_dp *dp = &dig_port->dp; 402 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 403 u8 msg_id = hdcp2_msg_data->msg_id; 404 int ret, timeout; 405 bool msg_ready = false; 406 407 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) 408 timeout = hdcp2_msg_data->timeout2; 409 else 410 timeout = hdcp2_msg_data->timeout; 411 412 /* 413 * There is no way to detect the CERT, LPRIME and STREAM_READY 414 * availability. So Wait for timeout and read the msg. 415 */ 416 if (!hdcp2_msg_data->msg_detectable) { 417 mdelay(timeout); 418 ret = 0; 419 } else { 420 /* 421 * As we want to check the msg availability at timeout, Ignoring 422 * the timeout at wait for CP_IRQ. 423 */ 424 intel_dp_hdcp_wait_for_cp_irq(connector, timeout); 425 ret = hdcp2_detect_msg_availability(connector, msg_id, 426 &msg_ready); 427 if (!msg_ready) 428 ret = -ETIMEDOUT; 429 } 430 431 if (ret) 432 drm_dbg_kms(&i915->drm, 433 "msg_id %d, ret %d, timeout(mSec): %d\n", 434 hdcp2_msg_data->msg_id, ret, timeout); 435 436 return ret; 437 } 438 439 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) 440 { 441 int i; 442 443 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++) 444 if (hdcp2_dp_msg_data[i].msg_id == msg_id) 445 return &hdcp2_dp_msg_data[i]; 446 447 return NULL; 448 } 449 450 static 451 int intel_dp_hdcp2_write_msg(struct intel_connector *connector, 452 void *buf, size_t size) 453 { 454 unsigned int offset; 455 u8 *byte = buf; 456 ssize_t ret, bytes_to_write, len; 457 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 458 struct drm_dp_aux *aux = &dig_port->dp.aux; 459 const struct hdcp2_dp_msg_data *hdcp2_msg_data; 460 461 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); 462 if (!hdcp2_msg_data) 463 return -EINVAL; 464 465 offset = hdcp2_msg_data->offset; 466 467 /* No msg_id in DP HDCP2.2 msgs */ 468 bytes_to_write = size - 1; 469 byte++; 470 471 while (bytes_to_write) { 472 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? 473 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; 474 475 ret = drm_dp_dpcd_write(aux, 476 offset, (void *)byte, len); 477 if (ret < 0) 478 return ret; 479 480 bytes_to_write -= ret; 481 byte += ret; 482 offset += ret; 483 } 484 485 return size; 486 } 487 488 static 489 ssize_t get_receiver_id_list_rx_info(struct intel_connector *connector, 490 u32 *dev_cnt, u8 *byte) 491 { 492 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 493 struct drm_dp_aux *aux = &dig_port->dp.aux; 494 ssize_t ret; 495 u8 *rx_info = byte; 496 497 ret = drm_dp_dpcd_read(aux, 498 DP_HDCP_2_2_REG_RXINFO_OFFSET, 499 (void *)rx_info, HDCP_2_2_RXINFO_LEN); 500 if (ret != HDCP_2_2_RXINFO_LEN) 501 return ret >= 0 ? -EIO : ret; 502 503 *dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 504 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 505 506 if (*dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) 507 *dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; 508 509 return ret; 510 } 511 512 static 513 int intel_dp_hdcp2_read_msg(struct intel_connector *connector, 514 u8 msg_id, void *buf, size_t size) 515 { 516 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 517 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 518 struct drm_dp_aux *aux = &dig_port->dp.aux; 519 struct intel_dp *dp = &dig_port->dp; 520 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 521 unsigned int offset; 522 u8 *byte = buf; 523 ssize_t ret, bytes_to_recv, len; 524 const struct hdcp2_dp_msg_data *hdcp2_msg_data; 525 ktime_t msg_end = ktime_set(0, 0); 526 bool msg_expired; 527 u32 dev_cnt; 528 529 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); 530 if (!hdcp2_msg_data) 531 return -EINVAL; 532 offset = hdcp2_msg_data->offset; 533 534 ret = intel_dp_hdcp2_wait_for_msg(connector, hdcp2_msg_data); 535 if (ret < 0) 536 return ret; 537 538 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count); 539 540 /* DP adaptation msgs has no msg_id */ 541 byte++; 542 543 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { 544 ret = get_receiver_id_list_rx_info(connector, &dev_cnt, byte); 545 if (ret < 0) 546 return ret; 547 548 byte += ret; 549 size = sizeof(struct hdcp2_rep_send_receiverid_list) - 550 HDCP_2_2_RXINFO_LEN - HDCP_2_2_RECEIVER_IDS_MAX_LEN + 551 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); 552 offset += HDCP_2_2_RXINFO_LEN; 553 } 554 555 bytes_to_recv = size - 1; 556 557 while (bytes_to_recv) { 558 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? 559 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; 560 561 /* Entire msg read timeout since initiate of msg read */ 562 if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0) { 563 msg_end = ktime_add_ms(ktime_get_raw(), 564 hdcp2_msg_data->msg_read_timeout); 565 } 566 567 ret = drm_dp_dpcd_read(aux, offset, 568 (void *)byte, len); 569 if (ret < 0) { 570 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", 571 msg_id, ret); 572 return ret; 573 } 574 575 bytes_to_recv -= ret; 576 byte += ret; 577 offset += ret; 578 } 579 580 if (hdcp2_msg_data->msg_read_timeout > 0) { 581 msg_expired = ktime_after(ktime_get_raw(), msg_end); 582 if (msg_expired) { 583 drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n", 584 msg_id, hdcp2_msg_data->msg_read_timeout); 585 return -ETIMEDOUT; 586 } 587 } 588 589 byte = buf; 590 *byte = msg_id; 591 592 return size; 593 } 594 595 static 596 int intel_dp_hdcp2_config_stream_type(struct intel_connector *connector, 597 bool is_repeater, u8 content_type) 598 { 599 int ret; 600 struct hdcp2_dp_errata_stream_type stream_type_msg; 601 602 if (is_repeater) 603 return 0; 604 605 /* 606 * Errata for DP: As Stream type is used for encryption, Receiver 607 * should be communicated with stream type for the decryption of the 608 * content. 609 * Repeater will be communicated with stream type as a part of it's 610 * auth later in time. 611 */ 612 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; 613 stream_type_msg.stream_type = content_type; 614 615 ret = intel_dp_hdcp2_write_msg(connector, &stream_type_msg, 616 sizeof(stream_type_msg)); 617 618 return ret < 0 ? ret : 0; 619 620 } 621 622 static 623 int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port, 624 struct intel_connector *connector) 625 { 626 u8 rx_status; 627 int ret; 628 629 ret = intel_dp_hdcp2_read_rx_status(connector, 630 &rx_status); 631 if (ret) 632 return ret; 633 634 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) 635 ret = HDCP_REAUTH_REQUEST; 636 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) 637 ret = HDCP_LINK_INTEGRITY_FAILURE; 638 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 639 ret = HDCP_TOPOLOGY_CHANGE; 640 641 return ret; 642 } 643 644 static 645 int _intel_dp_hdcp2_get_capability(struct drm_dp_aux *aux, 646 bool *capable) 647 { 648 u8 rx_caps[3]; 649 int ret, i; 650 651 *capable = false; 652 653 /* 654 * Some HDCP monitors act really shady by not giving the correct hdcp 655 * capability on the first rx_caps read and usually take an extra read 656 * to give the capability. We read rx_caps three times before we 657 * declare a monitor not capable of HDCP 2.2. 658 */ 659 for (i = 0; i < 3; i++) { 660 ret = drm_dp_dpcd_read(aux, 661 DP_HDCP_2_2_REG_RX_CAPS_OFFSET, 662 rx_caps, HDCP_2_2_RXCAPS_LEN); 663 if (ret != HDCP_2_2_RXCAPS_LEN) 664 return ret >= 0 ? -EIO : ret; 665 666 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && 667 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) { 668 *capable = true; 669 break; 670 } 671 } 672 673 return 0; 674 } 675 676 static 677 int intel_dp_hdcp2_get_capability(struct intel_connector *connector, 678 bool *capable) 679 { 680 struct intel_digital_port *dig_port; 681 struct drm_dp_aux *aux; 682 683 *capable = false; 684 if (!intel_attached_encoder(connector)) 685 return -EINVAL; 686 687 dig_port = intel_attached_dig_port(connector); 688 aux = &dig_port->dp.aux; 689 690 return _intel_dp_hdcp2_get_capability(aux, capable); 691 } 692 693 static 694 int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector, 695 bool *hdcp_capable, 696 bool *hdcp2_capable) 697 { 698 struct drm_i915_private *i915 = to_i915(connector->base.dev); 699 struct drm_dp_aux *aux; 700 u8 bcaps; 701 int ret; 702 703 *hdcp_capable = false; 704 *hdcp2_capable = false; 705 if (!connector->mst_port) 706 return -EINVAL; 707 708 aux = &connector->port->aux; 709 ret = _intel_dp_hdcp2_get_capability(aux, hdcp2_capable); 710 if (ret) 711 drm_dbg_kms(&i915->drm, 712 "HDCP2 DPCD capability read failed err: %d\n", ret); 713 714 ret = intel_dp_hdcp_read_bcaps(aux, i915, &bcaps); 715 if (ret) 716 return ret; 717 718 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; 719 720 return 0; 721 } 722 723 static const struct intel_hdcp_shim intel_dp_hdcp_shim = { 724 .write_an_aksv = intel_dp_hdcp_write_an_aksv, 725 .read_bksv = intel_dp_hdcp_read_bksv, 726 .read_bstatus = intel_dp_hdcp_read_bstatus, 727 .repeater_present = intel_dp_hdcp_repeater_present, 728 .read_ri_prime = intel_dp_hdcp_read_ri_prime, 729 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 730 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 731 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 732 .toggle_signalling = intel_dp_hdcp_toggle_signalling, 733 .check_link = intel_dp_hdcp_check_link, 734 .hdcp_get_capability = intel_dp_hdcp_get_capability, 735 .write_2_2_msg = intel_dp_hdcp2_write_msg, 736 .read_2_2_msg = intel_dp_hdcp2_read_msg, 737 .config_stream_type = intel_dp_hdcp2_config_stream_type, 738 .check_2_2_link = intel_dp_hdcp2_check_link, 739 .hdcp_2_2_get_capability = intel_dp_hdcp2_get_capability, 740 .protocol = HDCP_PROTOCOL_DP, 741 }; 742 743 static int 744 intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector, 745 bool enable) 746 { 747 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 748 struct drm_i915_private *i915 = to_i915(connector->base.dev); 749 struct intel_hdcp *hdcp = &connector->hdcp; 750 int ret; 751 752 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 753 hdcp->stream_transcoder, enable, 754 TRANS_DDI_HDCP_SELECT); 755 if (ret) 756 drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n", 757 enable ? "Enable" : "Disable", ret); 758 return ret; 759 } 760 761 static int 762 intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector, 763 bool enable) 764 { 765 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 766 struct drm_i915_private *i915 = to_i915(connector->base.dev); 767 struct intel_hdcp *hdcp = &connector->hdcp; 768 enum port port = dig_port->base.port; 769 enum transcoder cpu_transcoder = hdcp->stream_transcoder; 770 u32 stream_enc_status; 771 int ret; 772 773 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 774 if (ret) 775 return ret; 776 777 stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder); 778 if (!stream_enc_status) 779 return -EINVAL; 780 781 /* Wait for encryption confirmation */ 782 if (intel_de_wait(i915, HDCP_STATUS(i915, cpu_transcoder, port), 783 stream_enc_status, enable ? stream_enc_status : 0, 784 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 785 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 786 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 787 return -ETIMEDOUT; 788 } 789 790 return 0; 791 } 792 793 static int 794 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector, 795 bool enable) 796 { 797 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 798 struct drm_i915_private *i915 = to_i915(connector->base.dev); 799 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 800 struct intel_hdcp *hdcp = &connector->hdcp; 801 enum transcoder cpu_transcoder = hdcp->stream_transcoder; 802 enum pipe pipe = (enum pipe)cpu_transcoder; 803 enum port port = dig_port->base.port; 804 int ret; 805 806 drm_WARN_ON(&i915->drm, enable && 807 !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port)) 808 & AUTH_STREAM_TYPE) != data->streams[0].stream_type); 809 810 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 811 if (ret) 812 return ret; 813 814 /* Wait for encryption confirmation */ 815 if (intel_de_wait(i915, HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe), 816 STREAM_ENCRYPTION_STATUS, 817 enable ? STREAM_ENCRYPTION_STATUS : 0, 818 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 819 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 820 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 821 return -ETIMEDOUT; 822 } 823 824 return 0; 825 } 826 827 static 828 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port, 829 struct intel_connector *connector) 830 { 831 struct intel_hdcp *hdcp = &connector->hdcp; 832 int ret; 833 834 /* 835 * We do need to do the Link Check only for the connector involved with 836 * HDCP port authentication and encryption. 837 * We can re-use the hdcp->is_repeater flag to know that the connector 838 * involved with HDCP port authentication and encryption. 839 */ 840 if (hdcp->is_repeater) { 841 ret = intel_dp_hdcp2_check_link(dig_port, connector); 842 if (ret) 843 return ret; 844 } 845 846 return 0; 847 } 848 849 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { 850 .write_an_aksv = intel_dp_hdcp_write_an_aksv, 851 .read_bksv = intel_dp_hdcp_read_bksv, 852 .read_bstatus = intel_dp_hdcp_read_bstatus, 853 .repeater_present = intel_dp_hdcp_repeater_present, 854 .read_ri_prime = intel_dp_hdcp_read_ri_prime, 855 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 856 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 857 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 858 .toggle_signalling = intel_dp_hdcp_toggle_signalling, 859 .stream_encryption = intel_dp_mst_hdcp_stream_encryption, 860 .check_link = intel_dp_hdcp_check_link, 861 .hdcp_get_capability = intel_dp_hdcp_get_capability, 862 .write_2_2_msg = intel_dp_hdcp2_write_msg, 863 .read_2_2_msg = intel_dp_hdcp2_read_msg, 864 .config_stream_type = intel_dp_hdcp2_config_stream_type, 865 .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption, 866 .check_2_2_link = intel_dp_mst_hdcp2_check_link, 867 .hdcp_2_2_get_capability = intel_dp_hdcp2_get_capability, 868 .get_remote_hdcp_capability = intel_dp_hdcp_get_remote_capability, 869 .protocol = HDCP_PROTOCOL_DP, 870 }; 871 872 int intel_dp_hdcp_init(struct intel_digital_port *dig_port, 873 struct intel_connector *intel_connector) 874 { 875 struct drm_device *dev = intel_connector->base.dev; 876 struct drm_i915_private *dev_priv = to_i915(dev); 877 struct intel_encoder *intel_encoder = &dig_port->base; 878 enum port port = intel_encoder->port; 879 struct intel_dp *intel_dp = &dig_port->dp; 880 881 if (!is_hdcp_supported(dev_priv, port)) 882 return 0; 883 884 if (intel_connector->mst_port) 885 return intel_hdcp_init(intel_connector, dig_port, 886 &intel_dp_mst_hdcp_shim); 887 else if (!intel_dp_is_edp(intel_dp)) 888 return intel_hdcp_init(intel_connector, dig_port, 889 &intel_dp_hdcp_shim); 890 891 return 0; 892 } 893