1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DP_AUX_REGS_H__ 7 #define __INTEL_DP_AUX_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 /* 12 * The aux channel provides a way to talk to the signal sink for DDC etc. Max 13 * packet size supported is 20 bytes in each direction, hence the 5 fixed data 14 * registers 15 */ 16 17 /* 18 * Wrapper macro to convert from aux_ch to the index used in some of the 19 * registers. 20 */ 21 #define __xe2lpd_aux_ch_idx(aux_ch) \ 22 (aux_ch >= AUX_CH_USBC1 ? aux_ch : AUX_CH_USBC4 + 1 + (aux_ch) - AUX_CH_A) 23 24 #define _DPA_AUX_CH_CTL 0x64010 25 #define _DPB_AUX_CH_CTL 0x64110 26 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, \ 27 _DPB_AUX_CH_CTL) 28 #define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \ 29 _PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)) 30 31 #define _PCH_DPB_AUX_CH_CTL 0xe4110 32 #define _PCH_DPC_AUX_CH_CTL 0xe4210 33 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 34 35 #define _XELPDP_USBC1_AUX_CH_CTL 0x16f210 36 #define _XELPDP_USBC2_AUX_CH_CTL 0x16f410 37 #define _XELPDP_DP_AUX_CH_CTL(aux_ch) \ 38 _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \ 39 _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL, \ 40 _XELPDP_USBC1_AUX_CH_CTL, \ 41 _XELPDP_USBC2_AUX_CH_CTL)) 42 #define XELPDP_DP_AUX_CH_CTL(i915__, aux_ch) \ 43 (DISPLAY_VER(i915__) >= 20 ? \ 44 _XELPDP_DP_AUX_CH_CTL(__xe2lpd_aux_ch_idx(aux_ch)) : \ 45 _XELPDP_DP_AUX_CH_CTL(aux_ch)) 46 #define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31) 47 #define DP_AUX_CH_CTL_DONE REG_BIT(30) 48 #define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29) 49 #define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28) 50 #define DP_AUX_CH_CTL_TIME_OUT_MASK REG_GENMASK(27, 26) 51 #define DP_AUX_CH_CTL_TIME_OUT_400us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 0) 52 #define DP_AUX_CH_CTL_TIME_OUT_600us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 1) 53 #define DP_AUX_CH_CTL_TIME_OUT_800us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 2) 54 #define DP_AUX_CH_CTL_TIME_OUT_MAX REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 3) /* Varies per platform */ 55 #define DP_AUX_CH_CTL_RECEIVE_ERROR REG_BIT(25) 56 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK REG_GENMASK(24, 20) 57 #define DP_AUX_CH_CTL_MESSAGE_SIZE(x) REG_FIELD_PREP(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, (x)) 58 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK REG_GENMASK(19, 16) /* pre-skl */ 59 #define DP_AUX_CH_CTL_PRECHARGE_2US(x) REG_FIELD_PREP(DP_AUX_CH_CTL_PRECHARGE_2US_MASK, (x)) 60 #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) /* mtl+ */ 61 #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) /* mtl+ */ 62 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT REG_BIT(15) 63 #define DP_AUX_CH_CTL_MANCHESTER_TEST REG_BIT(14) /* pre-hsw */ 64 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL REG_BIT(14) /* skl+ */ 65 #define DP_AUX_CH_CTL_SYNC_TEST REG_BIT(13) /* pre-hsw */ 66 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL REG_BIT(13) /* skl+ */ 67 #define DP_AUX_CH_CTL_DEGLITCH_TEST REG_BIT(12) /* pre-hsw */ 68 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL REG_BIT(12) /* skl+ */ 69 #define DP_AUX_CH_CTL_PRECHARGE_TEST REG_BIT(11) /* pre-hsw */ 70 #define DP_AUX_CH_CTL_TBT_IO REG_BIT(11) /* icl+ */ 71 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK REG_GENMASK(10, 0) /* pre-skl */ 72 #define DP_AUX_CH_CTL_BIT_CLOCK_2X(x) REG_FIELD_PREP(DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK, (x)) 73 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK REG_GENMASK(9, 5) /* skl+ */ 74 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK, (c) - 1) 75 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */ 76 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1) 77 78 #define _DPA_AUX_CH_DATA1 0x64014 79 #define _DPB_AUX_CH_DATA1 0x64114 80 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \ 81 _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 82 #define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \ 83 _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 84 85 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 86 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 87 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 88 89 #define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214 90 #define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414 91 #define _XELPDP_DP_AUX_CH_DATA(aux_ch, i) \ 92 _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \ 93 _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1, \ 94 _XELPDP_USBC1_AUX_CH_DATA1, \ 95 _XELPDP_USBC2_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 96 #define XELPDP_DP_AUX_CH_DATA(i915__, aux_ch, i) \ 97 (DISPLAY_VER(i915__) >= 20 ? \ 98 _XELPDP_DP_AUX_CH_DATA(__xe2lpd_aux_ch_idx(aux_ch), i) : \ 99 _XELPDP_DP_AUX_CH_DATA(aux_ch, i)) 100 101 /* PICA Power Well Control */ 102 #define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04) 103 #define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31) 104 #define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30) 105 106 #endif /* __INTEL_DP_AUX_REGS_H__ */ 107