1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020-2021 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "i915_trace.h" 9 #include "intel_de.h" 10 #include "intel_display_types.h" 11 #include "intel_dp_aux.h" 12 #include "intel_pps.h" 13 #include "intel_tc.h" 14 15 static u32 intel_dp_aux_pack(const u8 *src, int src_bytes) 16 { 17 int i; 18 u32 v = 0; 19 20 if (src_bytes > 4) 21 src_bytes = 4; 22 for (i = 0; i < src_bytes; i++) 23 v |= ((u32)src[i]) << ((3 - i) * 8); 24 return v; 25 } 26 27 static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes) 28 { 29 int i; 30 31 if (dst_bytes > 4) 32 dst_bytes = 4; 33 for (i = 0; i < dst_bytes; i++) 34 dst[i] = src >> ((3 - i) * 8); 35 } 36 37 static u32 38 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 39 { 40 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 41 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 42 const unsigned int timeout_ms = 10; 43 u32 status; 44 int ret; 45 46 ret = __intel_de_wait_for_register(i915, ch_ctl, 47 DP_AUX_CH_CTL_SEND_BUSY, 0, 48 2, timeout_ms, &status); 49 50 if (ret == -ETIMEDOUT) 51 drm_err(&i915->drm, 52 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 53 intel_dp->aux.name, timeout_ms, status); 54 55 return status; 56 } 57 58 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 59 { 60 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 61 62 if (index) 63 return 0; 64 65 /* 66 * The clock divider is based off the hrawclk, and would like to run at 67 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 68 */ 69 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000); 70 } 71 72 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 73 { 74 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 75 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 76 u32 freq; 77 78 if (index) 79 return 0; 80 81 /* 82 * The clock divider is based off the cdclk or PCH rawclk, and would 83 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 84 * divide by 2000 and use that 85 */ 86 if (dig_port->aux_ch == AUX_CH_A) 87 freq = dev_priv->display.cdclk.hw.cdclk; 88 else 89 freq = RUNTIME_INFO(dev_priv)->rawclk_freq; 90 return DIV_ROUND_CLOSEST(freq, 2000); 91 } 92 93 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 94 { 95 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 96 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 97 98 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { 99 /* Workaround for non-ULT HSW */ 100 switch (index) { 101 case 0: return 63; 102 case 1: return 72; 103 default: return 0; 104 } 105 } 106 107 return ilk_get_aux_clock_divider(intel_dp, index); 108 } 109 110 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 111 { 112 /* 113 * SKL doesn't need us to program the AUX clock divider (Hardware will 114 * derive the clock from CDCLK automatically). We still implement the 115 * get_aux_clock_divider vfunc to plug-in into the existing code. 116 */ 117 return index ? 0 : 1; 118 } 119 120 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 121 int send_bytes, 122 u32 aux_clock_divider) 123 { 124 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 125 struct drm_i915_private *dev_priv = 126 to_i915(dig_port->base.base.dev); 127 u32 timeout; 128 129 /* Max timeout value on G4x-BDW: 1.6ms */ 130 if (IS_BROADWELL(dev_priv)) 131 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 132 else 133 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 134 135 return DP_AUX_CH_CTL_SEND_BUSY | 136 DP_AUX_CH_CTL_DONE | 137 DP_AUX_CH_CTL_INTERRUPT | 138 DP_AUX_CH_CTL_TIME_OUT_ERROR | 139 timeout | 140 DP_AUX_CH_CTL_RECEIVE_ERROR | 141 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 142 (3 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 143 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 144 } 145 146 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 147 int send_bytes, 148 u32 unused) 149 { 150 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 151 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 152 u32 ret; 153 154 /* 155 * Max timeout values: 156 * SKL-GLK: 1.6ms 157 * ICL+: 4ms 158 */ 159 ret = DP_AUX_CH_CTL_SEND_BUSY | 160 DP_AUX_CH_CTL_DONE | 161 DP_AUX_CH_CTL_INTERRUPT | 162 DP_AUX_CH_CTL_TIME_OUT_ERROR | 163 DP_AUX_CH_CTL_TIME_OUT_MAX | 164 DP_AUX_CH_CTL_RECEIVE_ERROR | 165 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 166 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 167 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 168 169 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 170 ret |= DP_AUX_CH_CTL_TBT_IO; 171 172 /* 173 * Power request bit is already set during aux power well enable. 174 * Preserve the bit across aux transactions. 175 */ 176 if (DISPLAY_VER(i915) >= 14) 177 ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; 178 179 return ret; 180 } 181 182 static int 183 intel_dp_aux_xfer(struct intel_dp *intel_dp, 184 const u8 *send, int send_bytes, 185 u8 *recv, int recv_size, 186 u32 aux_send_ctl_flags) 187 { 188 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 189 struct drm_i915_private *i915 = 190 to_i915(dig_port->base.base.dev); 191 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 192 bool is_tc_port = intel_phy_is_tc(i915, phy); 193 i915_reg_t ch_ctl, ch_data[5]; 194 u32 aux_clock_divider; 195 enum intel_display_power_domain aux_domain; 196 intel_wakeref_t aux_wakeref; 197 intel_wakeref_t pps_wakeref; 198 int i, ret, recv_bytes; 199 int try, clock = 0; 200 u32 status; 201 bool vdd; 202 203 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 204 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 205 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 206 207 if (is_tc_port) 208 intel_tc_port_lock(dig_port); 209 210 aux_domain = intel_aux_power_domain(dig_port); 211 212 aux_wakeref = intel_display_power_get(i915, aux_domain); 213 pps_wakeref = intel_pps_lock(intel_dp); 214 215 /* 216 * We will be called with VDD already enabled for dpcd/edid/oui reads. 217 * In such cases we want to leave VDD enabled and it's up to upper layers 218 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 219 * ourselves. 220 */ 221 vdd = intel_pps_vdd_on_unlocked(intel_dp); 222 223 /* 224 * dp aux is extremely sensitive to irq latency, hence request the 225 * lowest possible wakeup latency and so prevent the cpu from going into 226 * deep sleep states. 227 */ 228 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 229 230 intel_pps_check_power_unlocked(intel_dp); 231 232 /* Try to wait for any previous AUX channel activity */ 233 for (try = 0; try < 3; try++) { 234 status = intel_de_read_notrace(i915, ch_ctl); 235 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 236 break; 237 msleep(1); 238 } 239 /* just trace the final value */ 240 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 241 242 if (try == 3) { 243 const u32 status = intel_de_read(i915, ch_ctl); 244 245 if (status != intel_dp->aux_busy_last_status) { 246 drm_WARN(&i915->drm, 1, 247 "%s: not started (status 0x%08x)\n", 248 intel_dp->aux.name, status); 249 intel_dp->aux_busy_last_status = status; 250 } 251 252 ret = -EBUSY; 253 goto out; 254 } 255 256 /* Only 5 data registers! */ 257 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { 258 ret = -E2BIG; 259 goto out; 260 } 261 262 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 263 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 264 send_bytes, 265 aux_clock_divider); 266 267 send_ctl |= aux_send_ctl_flags; 268 269 /* Must try at least 3 times according to DP spec */ 270 for (try = 0; try < 5; try++) { 271 /* Load the send data into the aux channel data registers */ 272 for (i = 0; i < send_bytes; i += 4) 273 intel_de_write(i915, ch_data[i >> 2], 274 intel_dp_aux_pack(send + i, 275 send_bytes - i)); 276 277 /* Send the command and wait for it to complete */ 278 intel_de_write(i915, ch_ctl, send_ctl); 279 280 status = intel_dp_aux_wait_done(intel_dp); 281 282 /* Clear done status and any errors */ 283 intel_de_write(i915, ch_ctl, 284 status | DP_AUX_CH_CTL_DONE | 285 DP_AUX_CH_CTL_TIME_OUT_ERROR | 286 DP_AUX_CH_CTL_RECEIVE_ERROR); 287 288 /* 289 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 290 * 400us delay required for errors and timeouts 291 * Timeout errors from the HW already meet this 292 * requirement so skip to next iteration 293 */ 294 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 295 continue; 296 297 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 298 usleep_range(400, 500); 299 continue; 300 } 301 if (status & DP_AUX_CH_CTL_DONE) 302 goto done; 303 } 304 } 305 306 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 307 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", 308 intel_dp->aux.name, status); 309 ret = -EBUSY; 310 goto out; 311 } 312 313 done: 314 /* 315 * Check for timeout or receive error. Timeouts occur when the sink is 316 * not connected. 317 */ 318 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 319 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", 320 intel_dp->aux.name, status); 321 ret = -EIO; 322 goto out; 323 } 324 325 /* 326 * Timeouts occur when the device isn't connected, so they're "normal" 327 * -- don't fill the kernel log with these 328 */ 329 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 330 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", 331 intel_dp->aux.name, status); 332 ret = -ETIMEDOUT; 333 goto out; 334 } 335 336 /* Unload any bytes sent back from the other side */ 337 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 338 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 339 340 /* 341 * By BSpec: "Message sizes of 0 or >20 are not allowed." 342 * We have no idea of what happened so we return -EBUSY so 343 * drm layer takes care for the necessary retries. 344 */ 345 if (recv_bytes == 0 || recv_bytes > 20) { 346 drm_dbg_kms(&i915->drm, 347 "%s: Forbidden recv_bytes = %d on aux transaction\n", 348 intel_dp->aux.name, recv_bytes); 349 ret = -EBUSY; 350 goto out; 351 } 352 353 if (recv_bytes > recv_size) 354 recv_bytes = recv_size; 355 356 for (i = 0; i < recv_bytes; i += 4) 357 intel_dp_aux_unpack(intel_de_read(i915, ch_data[i >> 2]), 358 recv + i, recv_bytes - i); 359 360 ret = recv_bytes; 361 out: 362 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 363 364 if (vdd) 365 intel_pps_vdd_off_unlocked(intel_dp, false); 366 367 intel_pps_unlock(intel_dp, pps_wakeref); 368 intel_display_power_put_async(i915, aux_domain, aux_wakeref); 369 370 if (is_tc_port) 371 intel_tc_port_unlock(dig_port); 372 373 return ret; 374 } 375 376 #define BARE_ADDRESS_SIZE 3 377 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 378 379 static void 380 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 381 const struct drm_dp_aux_msg *msg) 382 { 383 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 384 txbuf[1] = (msg->address >> 8) & 0xff; 385 txbuf[2] = msg->address & 0xff; 386 txbuf[3] = msg->size - 1; 387 } 388 389 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 390 { 391 /* 392 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 393 * select bit to inform the hardware to send the Aksv after our header 394 * since we can't access that data from software. 395 */ 396 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 397 msg->address == DP_AUX_HDCP_AKSV) 398 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 399 400 return 0; 401 } 402 403 static ssize_t 404 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 405 { 406 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 407 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 408 u8 txbuf[20], rxbuf[20]; 409 size_t txsize, rxsize; 410 u32 flags = intel_dp_aux_xfer_flags(msg); 411 int ret; 412 413 intel_dp_aux_header(txbuf, msg); 414 415 switch (msg->request & ~DP_AUX_I2C_MOT) { 416 case DP_AUX_NATIVE_WRITE: 417 case DP_AUX_I2C_WRITE: 418 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 419 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 420 rxsize = 2; /* 0 or 1 data bytes */ 421 422 if (drm_WARN_ON(&i915->drm, txsize > 20)) 423 return -E2BIG; 424 425 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size); 426 427 if (msg->buffer) 428 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 429 430 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 431 rxbuf, rxsize, flags); 432 if (ret > 0) { 433 msg->reply = rxbuf[0] >> 4; 434 435 if (ret > 1) { 436 /* Number of bytes written in a short write. */ 437 ret = clamp_t(int, rxbuf[1], 0, msg->size); 438 } else { 439 /* Return payload size. */ 440 ret = msg->size; 441 } 442 } 443 break; 444 445 case DP_AUX_NATIVE_READ: 446 case DP_AUX_I2C_READ: 447 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 448 rxsize = msg->size + 1; 449 450 if (drm_WARN_ON(&i915->drm, rxsize > 20)) 451 return -E2BIG; 452 453 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 454 rxbuf, rxsize, flags); 455 if (ret > 0) { 456 msg->reply = rxbuf[0] >> 4; 457 /* 458 * Assume happy day, and copy the data. The caller is 459 * expected to check msg->reply before touching it. 460 * 461 * Return payload size. 462 */ 463 ret--; 464 memcpy(msg->buffer, rxbuf + 1, ret); 465 } 466 break; 467 468 default: 469 ret = -EINVAL; 470 break; 471 } 472 473 return ret; 474 } 475 476 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 477 { 478 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 479 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 480 enum aux_ch aux_ch = dig_port->aux_ch; 481 482 switch (aux_ch) { 483 case AUX_CH_B: 484 case AUX_CH_C: 485 case AUX_CH_D: 486 return DP_AUX_CH_CTL(aux_ch); 487 default: 488 MISSING_CASE(aux_ch); 489 return DP_AUX_CH_CTL(AUX_CH_B); 490 } 491 } 492 493 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 494 { 495 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 496 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 497 enum aux_ch aux_ch = dig_port->aux_ch; 498 499 switch (aux_ch) { 500 case AUX_CH_B: 501 case AUX_CH_C: 502 case AUX_CH_D: 503 return DP_AUX_CH_DATA(aux_ch, index); 504 default: 505 MISSING_CASE(aux_ch); 506 return DP_AUX_CH_DATA(AUX_CH_B, index); 507 } 508 } 509 510 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 511 { 512 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 513 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 514 enum aux_ch aux_ch = dig_port->aux_ch; 515 516 switch (aux_ch) { 517 case AUX_CH_A: 518 return DP_AUX_CH_CTL(aux_ch); 519 case AUX_CH_B: 520 case AUX_CH_C: 521 case AUX_CH_D: 522 return PCH_DP_AUX_CH_CTL(aux_ch); 523 default: 524 MISSING_CASE(aux_ch); 525 return DP_AUX_CH_CTL(AUX_CH_A); 526 } 527 } 528 529 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 530 { 531 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 532 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 533 enum aux_ch aux_ch = dig_port->aux_ch; 534 535 switch (aux_ch) { 536 case AUX_CH_A: 537 return DP_AUX_CH_DATA(aux_ch, index); 538 case AUX_CH_B: 539 case AUX_CH_C: 540 case AUX_CH_D: 541 return PCH_DP_AUX_CH_DATA(aux_ch, index); 542 default: 543 MISSING_CASE(aux_ch); 544 return DP_AUX_CH_DATA(AUX_CH_A, index); 545 } 546 } 547 548 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 549 { 550 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 551 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 552 enum aux_ch aux_ch = dig_port->aux_ch; 553 554 switch (aux_ch) { 555 case AUX_CH_A: 556 case AUX_CH_B: 557 case AUX_CH_C: 558 case AUX_CH_D: 559 case AUX_CH_E: 560 case AUX_CH_F: 561 return DP_AUX_CH_CTL(aux_ch); 562 default: 563 MISSING_CASE(aux_ch); 564 return DP_AUX_CH_CTL(AUX_CH_A); 565 } 566 } 567 568 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 569 { 570 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 571 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 572 enum aux_ch aux_ch = dig_port->aux_ch; 573 574 switch (aux_ch) { 575 case AUX_CH_A: 576 case AUX_CH_B: 577 case AUX_CH_C: 578 case AUX_CH_D: 579 case AUX_CH_E: 580 case AUX_CH_F: 581 return DP_AUX_CH_DATA(aux_ch, index); 582 default: 583 MISSING_CASE(aux_ch); 584 return DP_AUX_CH_DATA(AUX_CH_A, index); 585 } 586 } 587 588 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 589 { 590 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 591 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 592 enum aux_ch aux_ch = dig_port->aux_ch; 593 594 switch (aux_ch) { 595 case AUX_CH_A: 596 case AUX_CH_B: 597 case AUX_CH_C: 598 case AUX_CH_USBC1: 599 case AUX_CH_USBC2: 600 case AUX_CH_USBC3: 601 case AUX_CH_USBC4: 602 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 603 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 604 return DP_AUX_CH_CTL(aux_ch); 605 default: 606 MISSING_CASE(aux_ch); 607 return DP_AUX_CH_CTL(AUX_CH_A); 608 } 609 } 610 611 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 612 { 613 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 614 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 615 enum aux_ch aux_ch = dig_port->aux_ch; 616 617 switch (aux_ch) { 618 case AUX_CH_A: 619 case AUX_CH_B: 620 case AUX_CH_C: 621 case AUX_CH_USBC1: 622 case AUX_CH_USBC2: 623 case AUX_CH_USBC3: 624 case AUX_CH_USBC4: 625 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 626 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 627 return DP_AUX_CH_DATA(aux_ch, index); 628 default: 629 MISSING_CASE(aux_ch); 630 return DP_AUX_CH_DATA(AUX_CH_A, index); 631 } 632 } 633 634 static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) 635 { 636 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 637 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 638 enum aux_ch aux_ch = dig_port->aux_ch; 639 640 switch (aux_ch) { 641 case AUX_CH_A: 642 case AUX_CH_B: 643 case AUX_CH_USBC1: 644 case AUX_CH_USBC2: 645 case AUX_CH_USBC3: 646 case AUX_CH_USBC4: 647 return XELPDP_DP_AUX_CH_CTL(aux_ch); 648 default: 649 MISSING_CASE(aux_ch); 650 return XELPDP_DP_AUX_CH_CTL(AUX_CH_A); 651 } 652 } 653 654 static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) 655 { 656 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 657 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 658 enum aux_ch aux_ch = dig_port->aux_ch; 659 660 switch (aux_ch) { 661 case AUX_CH_A: 662 case AUX_CH_B: 663 case AUX_CH_USBC1: 664 case AUX_CH_USBC2: 665 case AUX_CH_USBC3: 666 case AUX_CH_USBC4: 667 return XELPDP_DP_AUX_CH_DATA(aux_ch, index); 668 default: 669 MISSING_CASE(aux_ch); 670 return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index); 671 } 672 } 673 674 void intel_dp_aux_fini(struct intel_dp *intel_dp) 675 { 676 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 677 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 678 679 kfree(intel_dp->aux.name); 680 } 681 682 void intel_dp_aux_init(struct intel_dp *intel_dp) 683 { 684 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 685 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 686 struct intel_encoder *encoder = &dig_port->base; 687 enum aux_ch aux_ch = dig_port->aux_ch; 688 689 if (DISPLAY_VER(dev_priv) >= 14) { 690 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; 691 intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; 692 } else if (DISPLAY_VER(dev_priv) >= 12) { 693 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 694 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 695 } else if (DISPLAY_VER(dev_priv) >= 9) { 696 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 697 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 698 } else if (HAS_PCH_SPLIT(dev_priv)) { 699 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 700 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 701 } else { 702 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 703 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 704 } 705 706 if (DISPLAY_VER(dev_priv) >= 9) 707 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 708 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 709 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 710 else if (HAS_PCH_SPLIT(dev_priv)) 711 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 712 else 713 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 714 715 if (DISPLAY_VER(dev_priv) >= 9) 716 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 717 else 718 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 719 720 intel_dp->aux.drm_dev = &dev_priv->drm; 721 drm_dp_aux_init(&intel_dp->aux); 722 723 /* Failure to allocate our preferred name is not critical */ 724 if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD) 725 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 726 aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D), 727 encoder->base.name); 728 else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) 729 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s", 730 aux_ch - AUX_CH_USBC1 + '1', 731 encoder->base.name); 732 else 733 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 734 aux_ch_name(aux_ch), 735 encoder->base.name); 736 737 intel_dp->aux.transfer = intel_dp_aux_transfer; 738 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 739 } 740