1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020-2021 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "intel_de.h" 9 #include "intel_display_jiffies.h" 10 #include "intel_display_types.h" 11 #include "intel_display_utils.h" 12 #include "intel_dp.h" 13 #include "intel_dp_aux.h" 14 #include "intel_dp_aux_regs.h" 15 #include "intel_parent.h" 16 #include "intel_pps.h" 17 #include "intel_quirks.h" 18 #include "intel_tc.h" 19 #include "intel_uncore_trace.h" 20 21 #define AUX_CH_NAME_BUFSIZE 6 22 23 static const char *aux_ch_name(struct intel_display *display, 24 char *buf, int size, enum aux_ch aux_ch) 25 { 26 if (DISPLAY_VER(display) >= 13 && aux_ch >= AUX_CH_D_XELPD) 27 snprintf(buf, size, "%c", 'A' + aux_ch - AUX_CH_D_XELPD + AUX_CH_D); 28 else if (DISPLAY_VER(display) >= 12 && aux_ch >= AUX_CH_USBC1) 29 snprintf(buf, size, "USBC%c", '1' + aux_ch - AUX_CH_USBC1); 30 else 31 snprintf(buf, size, "%c", 'A' + aux_ch); 32 33 return buf; 34 } 35 36 u32 intel_dp_aux_pack(const u8 *src, int src_bytes) 37 { 38 int i; 39 u32 v = 0; 40 41 if (src_bytes > 4) 42 src_bytes = 4; 43 for (i = 0; i < src_bytes; i++) 44 v |= ((u32)src[i]) << ((3 - i) * 8); 45 return v; 46 } 47 48 static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes) 49 { 50 int i; 51 52 if (dst_bytes > 4) 53 dst_bytes = 4; 54 for (i = 0; i < dst_bytes; i++) 55 dst[i] = src >> ((3 - i) * 8); 56 } 57 58 static u32 59 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 60 { 61 struct intel_display *display = to_intel_display(intel_dp); 62 intel_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 63 const unsigned int timeout_ms = 10; 64 bool done = true; 65 u32 status; 66 int ret; 67 68 if (intel_parent_irq_enabled(display)) { 69 #define C (((status = intel_de_read_notrace(display, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 70 done = wait_event_timeout(display->gmbus.wait_queue, C, 71 msecs_to_jiffies_timeout(timeout_ms)); 72 73 #undef C 74 } else { 75 ret = intel_de_wait_ms(display, ch_ctl, 76 DP_AUX_CH_CTL_SEND_BUSY, 0, 77 timeout_ms, &status); 78 79 if (ret == -ETIMEDOUT) 80 done = false; 81 } 82 83 if (!done) 84 drm_err(display->drm, 85 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 86 intel_dp->aux.name, timeout_ms, status); 87 88 return status; 89 } 90 91 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 92 { 93 struct intel_display *display = to_intel_display(intel_dp); 94 95 if (index) 96 return 0; 97 98 /* 99 * The clock divider is based off the hrawclk, and would like to run at 100 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 101 */ 102 return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 2000); 103 } 104 105 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 106 { 107 struct intel_display *display = to_intel_display(intel_dp); 108 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 109 u32 freq; 110 111 if (index) 112 return 0; 113 114 /* 115 * The clock divider is based off the cdclk or PCH rawclk, and would 116 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 117 * divide by 2000 and use that 118 */ 119 if (dig_port->aux_ch == AUX_CH_A) 120 freq = display->cdclk.hw.cdclk; 121 else 122 freq = DISPLAY_RUNTIME_INFO(display)->rawclk_freq; 123 return DIV_ROUND_CLOSEST(freq, 2000); 124 } 125 126 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 127 { 128 struct intel_display *display = to_intel_display(intel_dp); 129 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 130 131 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(display)) { 132 /* Workaround for non-ULT HSW */ 133 switch (index) { 134 case 0: return 63; 135 case 1: return 72; 136 default: return 0; 137 } 138 } 139 140 return ilk_get_aux_clock_divider(intel_dp, index); 141 } 142 143 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 144 { 145 /* 146 * SKL doesn't need us to program the AUX clock divider (Hardware will 147 * derive the clock from CDCLK automatically). We still implement the 148 * get_aux_clock_divider vfunc to plug-in into the existing code. 149 */ 150 return index ? 0 : 1; 151 } 152 153 static int intel_dp_aux_sync_len(void) 154 { 155 int precharge = 16; /* 10-16 */ 156 int preamble = 16; 157 158 return precharge + preamble; 159 } 160 161 int intel_dp_aux_fw_sync_len(struct intel_dp *intel_dp) 162 { 163 int precharge = 10; /* 10-16 */ 164 int preamble = 8; 165 166 /* 167 * We faced some glitches on Dell Precision 5490 MTL laptop with panel: 168 * "Manufacturer: AUO, Model: 63898" when using HW default 18. Using 20 169 * is fixing these problems with the panel. It is still within range 170 * mentioned in eDP specification. Increasing Fast Wake sync length is 171 * causing problems with other panels: increase length as a quirk for 172 * this specific laptop. 173 */ 174 if (intel_has_dpcd_quirk(intel_dp, QUIRK_FW_SYNC_LEN)) 175 precharge += 2; 176 177 return precharge + preamble; 178 } 179 180 static int g4x_dp_aux_precharge_len(void) 181 { 182 int precharge_min = 10; 183 int preamble = 16; 184 185 /* HW wants the length of the extra precharge in 2us units */ 186 return (intel_dp_aux_sync_len() - 187 precharge_min - preamble) / 2; 188 } 189 190 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 191 int send_bytes, 192 u32 aux_clock_divider) 193 { 194 struct intel_display *display = to_intel_display(intel_dp); 195 u32 timeout; 196 197 /* Max timeout value on G4x-BDW: 1.6ms */ 198 if (display->platform.broadwell) 199 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 200 else 201 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 202 203 return DP_AUX_CH_CTL_SEND_BUSY | 204 DP_AUX_CH_CTL_DONE | 205 DP_AUX_CH_CTL_INTERRUPT | 206 DP_AUX_CH_CTL_TIME_OUT_ERROR | 207 timeout | 208 DP_AUX_CH_CTL_RECEIVE_ERROR | 209 DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) | 210 DP_AUX_CH_CTL_PRECHARGE_2US(g4x_dp_aux_precharge_len()) | 211 DP_AUX_CH_CTL_BIT_CLOCK_2X(aux_clock_divider); 212 } 213 214 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 215 int send_bytes, 216 u32 unused) 217 { 218 struct intel_display *display = to_intel_display(intel_dp); 219 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 220 u32 ret; 221 222 /* 223 * Max timeout values: 224 * SKL-GLK: 1.6ms 225 * ICL+: 4ms 226 */ 227 ret = DP_AUX_CH_CTL_SEND_BUSY | 228 DP_AUX_CH_CTL_DONE | 229 DP_AUX_CH_CTL_INTERRUPT | 230 DP_AUX_CH_CTL_TIME_OUT_ERROR | 231 DP_AUX_CH_CTL_TIME_OUT_MAX | 232 DP_AUX_CH_CTL_RECEIVE_ERROR | 233 DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) | 234 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len(intel_dp)) | 235 DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len()); 236 237 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 238 ret |= DP_AUX_CH_CTL_TBT_IO; 239 240 /* 241 * Power request bit is already set during aux power well enable. 242 * Preserve the bit across aux transactions. 243 */ 244 if (DISPLAY_VER(display) >= 14) 245 ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; 246 247 return ret; 248 } 249 250 static int 251 intel_dp_aux_xfer(struct intel_dp *intel_dp, 252 const u8 *send, int send_bytes, 253 u8 *recv, int recv_size, 254 u32 aux_send_ctl_flags) 255 { 256 struct intel_display *display = to_intel_display(intel_dp); 257 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 258 struct intel_encoder *encoder = &dig_port->base; 259 intel_reg_t ch_ctl, ch_data[5]; 260 u32 aux_clock_divider; 261 enum intel_display_power_domain aux_domain; 262 struct ref_tracker *aux_wakeref; 263 struct ref_tracker *pps_wakeref = NULL; 264 int i, ret, recv_bytes; 265 int try, clock = 0; 266 u32 status; 267 bool vdd; 268 269 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 270 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 271 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 272 273 intel_digital_port_lock(encoder); 274 /* 275 * Abort transfers on a disconnected port as required by 276 * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX 277 * timeouts that would otherwise happen. 278 */ 279 if (!intel_dp_is_edp(intel_dp) && 280 !intel_digital_port_connected_locked(&dig_port->base)) { 281 ret = -ENXIO; 282 goto out_unlock; 283 } 284 285 aux_domain = intel_aux_power_domain(dig_port); 286 287 aux_wakeref = intel_display_power_get(display, aux_domain); 288 289 /* 290 * The PPS state needs to be locked for: 291 * - eDP on all platforms, since AUX transfers on eDP need VDD power 292 * (either forced or via panel power) which depends on the PPS 293 * state. 294 * - non-eDP on platforms where the PPS is a pipe instance (VLV/CHV), 295 * since changing the PPS state (via a parallel modeset for 296 * instance) may interfere with the AUX transfers on a non-eDP 297 * output as well. 298 */ 299 if (intel_dp_is_edp(intel_dp) || 300 display->platform.valleyview || display->platform.cherryview) 301 pps_wakeref = intel_pps_lock(intel_dp); 302 303 /* 304 * We will be called with VDD already enabled for dpcd/edid/oui reads. 305 * In such cases we want to leave VDD enabled and it's up to upper layers 306 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 307 * ourselves. 308 */ 309 vdd = intel_pps_vdd_on_unlocked(intel_dp); 310 311 /* 312 * dp aux is extremely sensitive to irq latency, hence request the 313 * lowest possible wakeup latency and so prevent the cpu from going into 314 * deep sleep states. 315 */ 316 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 317 318 intel_pps_check_power_unlocked(intel_dp); 319 320 /* 321 * FIXME PSR should be disabled here to prevent 322 * it using the same AUX CH simultaneously 323 */ 324 325 /* Try to wait for any previous AUX channel activity */ 326 for (try = 0; try < 3; try++) { 327 status = intel_de_read_notrace(display, ch_ctl); 328 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 329 break; 330 msleep(1); 331 } 332 /* just trace the final value */ 333 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 334 335 if (try == 3) { 336 const u32 status = intel_de_read(display, ch_ctl); 337 338 if (status != intel_dp->aux_busy_last_status) { 339 drm_WARN(display->drm, 1, 340 "%s: not started (status 0x%08x)\n", 341 intel_dp->aux.name, status); 342 intel_dp->aux_busy_last_status = status; 343 } 344 345 ret = -EBUSY; 346 goto out; 347 } 348 349 /* Only 5 data registers! */ 350 if (drm_WARN_ON(display->drm, send_bytes > 20 || recv_size > 20)) { 351 ret = -E2BIG; 352 goto out; 353 } 354 355 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 356 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 357 send_bytes, 358 aux_clock_divider); 359 360 send_ctl |= aux_send_ctl_flags; 361 362 /* Must try at least 3 times according to DP spec */ 363 for (try = 0; try < 5; try++) { 364 /* Load the send data into the aux channel data registers */ 365 for (i = 0; i < send_bytes; i += 4) 366 intel_de_write(display, ch_data[i >> 2], 367 intel_dp_aux_pack(send + i, 368 send_bytes - i)); 369 370 /* Send the command and wait for it to complete */ 371 intel_de_write(display, ch_ctl, send_ctl); 372 373 status = intel_dp_aux_wait_done(intel_dp); 374 375 /* Clear done status and any errors */ 376 intel_de_write(display, ch_ctl, 377 status | DP_AUX_CH_CTL_DONE | 378 DP_AUX_CH_CTL_TIME_OUT_ERROR | 379 DP_AUX_CH_CTL_RECEIVE_ERROR); 380 381 /* 382 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 383 * 400us delay required for errors and timeouts 384 * Timeout errors from the HW already meet this 385 * requirement so skip to next iteration 386 */ 387 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 388 continue; 389 390 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 391 usleep_range(400, 500); 392 continue; 393 } 394 if (status & DP_AUX_CH_CTL_DONE) 395 goto done; 396 } 397 } 398 399 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 400 drm_err(display->drm, "%s: not done (status 0x%08x)\n", 401 intel_dp->aux.name, status); 402 ret = -EBUSY; 403 goto out; 404 } 405 406 done: 407 /* 408 * Check for timeout or receive error. Timeouts occur when the sink is 409 * not connected. 410 */ 411 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 412 drm_err(display->drm, "%s: receive error (status 0x%08x)\n", 413 intel_dp->aux.name, status); 414 ret = -EIO; 415 goto out; 416 } 417 418 /* 419 * Timeouts occur when the device isn't connected, so they're "normal" 420 * -- don't fill the kernel log with these 421 */ 422 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 423 drm_dbg_kms(display->drm, "%s: timeout (status 0x%08x)\n", 424 intel_dp->aux.name, status); 425 ret = -ETIMEDOUT; 426 goto out; 427 } 428 429 /* Unload any bytes sent back from the other side */ 430 recv_bytes = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, status); 431 432 /* 433 * By BSpec: "Message sizes of 0 or >20 are not allowed." 434 * We have no idea of what happened so we return -EBUSY so 435 * drm layer takes care for the necessary retries. 436 */ 437 if (recv_bytes == 0 || recv_bytes > 20) { 438 drm_dbg_kms(display->drm, 439 "%s: Forbidden recv_bytes = %d on aux transaction\n", 440 intel_dp->aux.name, recv_bytes); 441 ret = -EBUSY; 442 goto out; 443 } 444 445 if (recv_bytes > recv_size) 446 recv_bytes = recv_size; 447 448 for (i = 0; i < recv_bytes; i += 4) 449 intel_dp_aux_unpack(intel_de_read(display, ch_data[i >> 2]), 450 recv + i, recv_bytes - i); 451 452 ret = recv_bytes; 453 out: 454 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 455 456 if (vdd) 457 intel_pps_vdd_off_unlocked(intel_dp, false); 458 459 if (pps_wakeref) 460 intel_pps_unlock(intel_dp, pps_wakeref); 461 462 intel_display_power_put_async(display, aux_domain, aux_wakeref); 463 out_unlock: 464 intel_digital_port_unlock(encoder); 465 466 return ret; 467 } 468 469 #define BARE_ADDRESS_SIZE 3 470 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 471 472 static void 473 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 474 const struct drm_dp_aux_msg *msg) 475 { 476 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 477 txbuf[1] = (msg->address >> 8) & 0xff; 478 txbuf[2] = msg->address & 0xff; 479 txbuf[3] = msg->size - 1; 480 } 481 482 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 483 { 484 /* 485 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 486 * select bit to inform the hardware to send the Aksv after our header 487 * since we can't access that data from software. 488 */ 489 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 490 msg->address == DP_AUX_HDCP_AKSV) 491 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 492 493 return 0; 494 } 495 496 static ssize_t 497 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 498 { 499 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 500 struct intel_display *display = to_intel_display(intel_dp); 501 u8 txbuf[20], rxbuf[20]; 502 size_t txsize, rxsize; 503 u32 flags = intel_dp_aux_xfer_flags(msg); 504 int ret; 505 506 intel_dp_aux_header(txbuf, msg); 507 508 switch (msg->request & ~DP_AUX_I2C_MOT) { 509 case DP_AUX_NATIVE_WRITE: 510 case DP_AUX_I2C_WRITE: 511 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 512 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 513 rxsize = 2; /* 0 or 1 data bytes */ 514 515 if (drm_WARN_ON(display->drm, txsize > 20)) 516 return -E2BIG; 517 518 drm_WARN_ON(display->drm, !msg->buffer != !msg->size); 519 520 if (msg->buffer) 521 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 522 523 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 524 rxbuf, rxsize, flags); 525 if (ret > 0) { 526 msg->reply = rxbuf[0] >> 4; 527 528 if (ret > 1) { 529 /* Number of bytes written in a short write. */ 530 ret = clamp_t(int, rxbuf[1], 0, msg->size); 531 } else { 532 /* Return payload size. */ 533 ret = msg->size; 534 } 535 } 536 break; 537 538 case DP_AUX_NATIVE_READ: 539 case DP_AUX_I2C_READ: 540 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 541 rxsize = msg->size + 1; 542 543 if (drm_WARN_ON(display->drm, rxsize > 20)) 544 return -E2BIG; 545 546 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 547 rxbuf, rxsize, flags); 548 if (ret > 0) { 549 msg->reply = rxbuf[0] >> 4; 550 /* 551 * Assume happy day, and copy the data. The caller is 552 * expected to check msg->reply before touching it. 553 * 554 * Return payload size. 555 */ 556 ret--; 557 memcpy(msg->buffer, rxbuf + 1, ret); 558 } 559 break; 560 561 default: 562 ret = -EINVAL; 563 break; 564 } 565 566 return ret; 567 } 568 569 static intel_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp) 570 { 571 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 572 enum aux_ch aux_ch = dig_port->aux_ch; 573 574 switch (aux_ch) { 575 case AUX_CH_B: 576 case AUX_CH_C: 577 case AUX_CH_D: 578 return VLV_DP_AUX_CH_CTL(aux_ch); 579 default: 580 MISSING_CASE(aux_ch); 581 return VLV_DP_AUX_CH_CTL(AUX_CH_B); 582 } 583 } 584 585 static intel_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index) 586 { 587 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 588 enum aux_ch aux_ch = dig_port->aux_ch; 589 590 switch (aux_ch) { 591 case AUX_CH_B: 592 case AUX_CH_C: 593 case AUX_CH_D: 594 return VLV_DP_AUX_CH_DATA(aux_ch, index); 595 default: 596 MISSING_CASE(aux_ch); 597 return VLV_DP_AUX_CH_DATA(AUX_CH_B, index); 598 } 599 } 600 601 static intel_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 602 { 603 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 604 enum aux_ch aux_ch = dig_port->aux_ch; 605 606 switch (aux_ch) { 607 case AUX_CH_B: 608 case AUX_CH_C: 609 case AUX_CH_D: 610 return DP_AUX_CH_CTL(aux_ch); 611 default: 612 MISSING_CASE(aux_ch); 613 return DP_AUX_CH_CTL(AUX_CH_B); 614 } 615 } 616 617 static intel_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 618 { 619 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 620 enum aux_ch aux_ch = dig_port->aux_ch; 621 622 switch (aux_ch) { 623 case AUX_CH_B: 624 case AUX_CH_C: 625 case AUX_CH_D: 626 return DP_AUX_CH_DATA(aux_ch, index); 627 default: 628 MISSING_CASE(aux_ch); 629 return DP_AUX_CH_DATA(AUX_CH_B, index); 630 } 631 } 632 633 static intel_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 634 { 635 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 636 enum aux_ch aux_ch = dig_port->aux_ch; 637 638 switch (aux_ch) { 639 case AUX_CH_A: 640 return DP_AUX_CH_CTL(aux_ch); 641 case AUX_CH_B: 642 case AUX_CH_C: 643 case AUX_CH_D: 644 return PCH_DP_AUX_CH_CTL(aux_ch); 645 default: 646 MISSING_CASE(aux_ch); 647 return DP_AUX_CH_CTL(AUX_CH_A); 648 } 649 } 650 651 static intel_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 652 { 653 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 654 enum aux_ch aux_ch = dig_port->aux_ch; 655 656 switch (aux_ch) { 657 case AUX_CH_A: 658 return DP_AUX_CH_DATA(aux_ch, index); 659 case AUX_CH_B: 660 case AUX_CH_C: 661 case AUX_CH_D: 662 return PCH_DP_AUX_CH_DATA(aux_ch, index); 663 default: 664 MISSING_CASE(aux_ch); 665 return DP_AUX_CH_DATA(AUX_CH_A, index); 666 } 667 } 668 669 static intel_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 670 { 671 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 672 enum aux_ch aux_ch = dig_port->aux_ch; 673 674 switch (aux_ch) { 675 case AUX_CH_A: 676 case AUX_CH_B: 677 case AUX_CH_C: 678 case AUX_CH_D: 679 case AUX_CH_E: 680 case AUX_CH_F: 681 return DP_AUX_CH_CTL(aux_ch); 682 default: 683 MISSING_CASE(aux_ch); 684 return DP_AUX_CH_CTL(AUX_CH_A); 685 } 686 } 687 688 static intel_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 689 { 690 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 691 enum aux_ch aux_ch = dig_port->aux_ch; 692 693 switch (aux_ch) { 694 case AUX_CH_A: 695 case AUX_CH_B: 696 case AUX_CH_C: 697 case AUX_CH_D: 698 case AUX_CH_E: 699 case AUX_CH_F: 700 return DP_AUX_CH_DATA(aux_ch, index); 701 default: 702 MISSING_CASE(aux_ch); 703 return DP_AUX_CH_DATA(AUX_CH_A, index); 704 } 705 } 706 707 static intel_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 708 { 709 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 710 enum aux_ch aux_ch = dig_port->aux_ch; 711 712 switch (aux_ch) { 713 case AUX_CH_A: 714 case AUX_CH_B: 715 case AUX_CH_C: 716 case AUX_CH_USBC1: 717 case AUX_CH_USBC2: 718 case AUX_CH_USBC3: 719 case AUX_CH_USBC4: 720 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 721 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 722 return DP_AUX_CH_CTL(aux_ch); 723 default: 724 MISSING_CASE(aux_ch); 725 return DP_AUX_CH_CTL(AUX_CH_A); 726 } 727 } 728 729 static intel_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 730 { 731 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 732 enum aux_ch aux_ch = dig_port->aux_ch; 733 734 switch (aux_ch) { 735 case AUX_CH_A: 736 case AUX_CH_B: 737 case AUX_CH_C: 738 case AUX_CH_USBC1: 739 case AUX_CH_USBC2: 740 case AUX_CH_USBC3: 741 case AUX_CH_USBC4: 742 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 743 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 744 return DP_AUX_CH_DATA(aux_ch, index); 745 default: 746 MISSING_CASE(aux_ch); 747 return DP_AUX_CH_DATA(AUX_CH_A, index); 748 } 749 } 750 751 static intel_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) 752 { 753 struct intel_display *display = to_intel_display(intel_dp); 754 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 755 enum aux_ch aux_ch = dig_port->aux_ch; 756 757 switch (aux_ch) { 758 case AUX_CH_A: 759 case AUX_CH_B: 760 case AUX_CH_USBC1: 761 case AUX_CH_USBC2: 762 case AUX_CH_USBC3: 763 case AUX_CH_USBC4: 764 return XELPDP_DP_AUX_CH_CTL(display, aux_ch); 765 default: 766 MISSING_CASE(aux_ch); 767 return XELPDP_DP_AUX_CH_CTL(display, AUX_CH_A); 768 } 769 } 770 771 static intel_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) 772 { 773 struct intel_display *display = to_intel_display(intel_dp); 774 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 775 enum aux_ch aux_ch = dig_port->aux_ch; 776 777 switch (aux_ch) { 778 case AUX_CH_A: 779 case AUX_CH_B: 780 case AUX_CH_USBC1: 781 case AUX_CH_USBC2: 782 case AUX_CH_USBC3: 783 case AUX_CH_USBC4: 784 return XELPDP_DP_AUX_CH_DATA(display, aux_ch, index); 785 default: 786 MISSING_CASE(aux_ch); 787 return XELPDP_DP_AUX_CH_DATA(display, AUX_CH_A, index); 788 } 789 } 790 791 void intel_dp_aux_fini(struct intel_dp *intel_dp) 792 { 793 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 794 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 795 796 kfree(intel_dp->aux.name); 797 } 798 799 void intel_dp_aux_init(struct intel_dp *intel_dp) 800 { 801 struct intel_display *display = to_intel_display(intel_dp); 802 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 803 struct intel_encoder *encoder = &dig_port->base; 804 enum aux_ch aux_ch = dig_port->aux_ch; 805 char buf[AUX_CH_NAME_BUFSIZE]; 806 807 if (DISPLAY_VER(display) >= 14) { 808 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; 809 intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; 810 } else if (DISPLAY_VER(display) >= 12) { 811 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 812 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 813 } else if (DISPLAY_VER(display) >= 9) { 814 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 815 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 816 } else if (HAS_PCH_SPLIT(display)) { 817 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 818 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 819 } else if (display->platform.valleyview || display->platform.cherryview) { 820 intel_dp->aux_ch_ctl_reg = vlv_aux_ctl_reg; 821 intel_dp->aux_ch_data_reg = vlv_aux_data_reg; 822 } else { 823 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 824 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 825 } 826 827 if (DISPLAY_VER(display) >= 9) 828 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 829 else if (display->platform.broadwell || display->platform.haswell) 830 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 831 else if (HAS_PCH_SPLIT(display)) 832 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 833 else 834 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 835 836 if (DISPLAY_VER(display) >= 9) 837 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 838 else 839 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 840 841 intel_dp->aux.drm_dev = display->drm; 842 drm_dp_aux_init(&intel_dp->aux); 843 844 /* Failure to allocate our preferred name is not critical */ 845 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %s/%s", 846 aux_ch_name(display, buf, sizeof(buf), aux_ch), 847 encoder->base.name); 848 849 intel_dp->aux.transfer = intel_dp_aux_transfer; 850 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 851 852 intel_dp_dpcd_set_probe(intel_dp, true); 853 } 854 855 static enum aux_ch default_aux_ch(struct intel_encoder *encoder) 856 { 857 struct intel_display *display = to_intel_display(encoder); 858 859 /* SKL has DDI E but no AUX E */ 860 if (DISPLAY_VER(display) == 9 && encoder->port == PORT_E) 861 return AUX_CH_A; 862 863 return (enum aux_ch)encoder->port; 864 } 865 866 static struct intel_encoder * 867 get_encoder_by_aux_ch(struct intel_encoder *encoder, 868 enum aux_ch aux_ch) 869 { 870 struct intel_display *display = to_intel_display(encoder); 871 struct intel_encoder *other; 872 873 for_each_intel_encoder(display->drm, other) { 874 if (other == encoder) 875 continue; 876 877 if (!intel_encoder_is_dig_port(other)) 878 continue; 879 880 if (enc_to_dig_port(other)->aux_ch == aux_ch) 881 return other; 882 } 883 884 return NULL; 885 } 886 887 enum aux_ch intel_dp_aux_ch(struct intel_encoder *encoder) 888 { 889 struct intel_display *display = to_intel_display(encoder); 890 struct intel_encoder *other; 891 const char *source; 892 enum aux_ch aux_ch; 893 char buf[AUX_CH_NAME_BUFSIZE]; 894 895 aux_ch = intel_bios_dp_aux_ch(encoder->devdata); 896 source = "VBT"; 897 898 if (aux_ch == AUX_CH_NONE) { 899 aux_ch = default_aux_ch(encoder); 900 source = "platform default"; 901 } 902 903 if (aux_ch == AUX_CH_NONE) 904 return AUX_CH_NONE; 905 906 /* FIXME validate aux_ch against platform caps */ 907 908 other = get_encoder_by_aux_ch(encoder, aux_ch); 909 if (other) { 910 drm_dbg_kms(display->drm, 911 "[ENCODER:%d:%s] AUX CH %s already claimed by [ENCODER:%d:%s]\n", 912 encoder->base.base.id, encoder->base.name, 913 aux_ch_name(display, buf, sizeof(buf), aux_ch), 914 other->base.base.id, other->base.name); 915 return AUX_CH_NONE; 916 } 917 918 drm_dbg_kms(display->drm, 919 "[ENCODER:%d:%s] Using AUX CH %s (%s)\n", 920 encoder->base.base.id, encoder->base.name, 921 aux_ch_name(display, buf, sizeof(buf), aux_ch), source); 922 923 return aux_ch; 924 } 925 926 void intel_dp_aux_irq_handler(struct intel_display *display) 927 { 928 wake_up_all(&display->gmbus.wait_queue); 929 } 930