1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020-2021 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_de.h" 9 #include "intel_display_types.h" 10 #include "intel_dp.h" 11 #include "intel_dp_aux.h" 12 #include "intel_dp_aux_regs.h" 13 #include "intel_pps.h" 14 #include "intel_quirks.h" 15 #include "intel_tc.h" 16 #include "intel_uncore_trace.h" 17 18 #define AUX_CH_NAME_BUFSIZE 6 19 20 static const char *aux_ch_name(struct intel_display *display, 21 char *buf, int size, enum aux_ch aux_ch) 22 { 23 if (DISPLAY_VER(display) >= 13 && aux_ch >= AUX_CH_D_XELPD) 24 snprintf(buf, size, "%c", 'A' + aux_ch - AUX_CH_D_XELPD + AUX_CH_D); 25 else if (DISPLAY_VER(display) >= 12 && aux_ch >= AUX_CH_USBC1) 26 snprintf(buf, size, "USBC%c", '1' + aux_ch - AUX_CH_USBC1); 27 else 28 snprintf(buf, size, "%c", 'A' + aux_ch); 29 30 return buf; 31 } 32 33 u32 intel_dp_aux_pack(const u8 *src, int src_bytes) 34 { 35 int i; 36 u32 v = 0; 37 38 if (src_bytes > 4) 39 src_bytes = 4; 40 for (i = 0; i < src_bytes; i++) 41 v |= ((u32)src[i]) << ((3 - i) * 8); 42 return v; 43 } 44 45 static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes) 46 { 47 int i; 48 49 if (dst_bytes > 4) 50 dst_bytes = 4; 51 for (i = 0; i < dst_bytes; i++) 52 dst[i] = src >> ((3 - i) * 8); 53 } 54 55 static u32 56 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 57 { 58 struct intel_display *display = to_intel_display(intel_dp); 59 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 60 const unsigned int timeout_ms = 10; 61 u32 status; 62 int ret; 63 64 ret = intel_de_wait_custom(display, ch_ctl, DP_AUX_CH_CTL_SEND_BUSY, 65 0, 66 2, timeout_ms, &status); 67 68 if (ret == -ETIMEDOUT) 69 drm_err(display->drm, 70 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 71 intel_dp->aux.name, timeout_ms, status); 72 73 return status; 74 } 75 76 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 77 { 78 struct intel_display *display = to_intel_display(intel_dp); 79 80 if (index) 81 return 0; 82 83 /* 84 * The clock divider is based off the hrawclk, and would like to run at 85 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 86 */ 87 return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 2000); 88 } 89 90 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 91 { 92 struct intel_display *display = to_intel_display(intel_dp); 93 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 94 u32 freq; 95 96 if (index) 97 return 0; 98 99 /* 100 * The clock divider is based off the cdclk or PCH rawclk, and would 101 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 102 * divide by 2000 and use that 103 */ 104 if (dig_port->aux_ch == AUX_CH_A) 105 freq = display->cdclk.hw.cdclk; 106 else 107 freq = DISPLAY_RUNTIME_INFO(display)->rawclk_freq; 108 return DIV_ROUND_CLOSEST(freq, 2000); 109 } 110 111 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 112 { 113 struct intel_display *display = to_intel_display(intel_dp); 114 struct drm_i915_private *i915 = to_i915(display->drm); 115 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 116 117 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(i915)) { 118 /* Workaround for non-ULT HSW */ 119 switch (index) { 120 case 0: return 63; 121 case 1: return 72; 122 default: return 0; 123 } 124 } 125 126 return ilk_get_aux_clock_divider(intel_dp, index); 127 } 128 129 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 130 { 131 /* 132 * SKL doesn't need us to program the AUX clock divider (Hardware will 133 * derive the clock from CDCLK automatically). We still implement the 134 * get_aux_clock_divider vfunc to plug-in into the existing code. 135 */ 136 return index ? 0 : 1; 137 } 138 139 static int intel_dp_aux_sync_len(void) 140 { 141 int precharge = 16; /* 10-16 */ 142 int preamble = 16; 143 144 return precharge + preamble; 145 } 146 147 int intel_dp_aux_fw_sync_len(struct intel_dp *intel_dp) 148 { 149 int precharge = 10; /* 10-16 */ 150 int preamble = 8; 151 152 /* 153 * We faced some glitches on Dell Precision 5490 MTL laptop with panel: 154 * "Manufacturer: AUO, Model: 63898" when using HW default 18. Using 20 155 * is fixing these problems with the panel. It is still within range 156 * mentioned in eDP specification. Increasing Fast Wake sync length is 157 * causing problems with other panels: increase length as a quirk for 158 * this specific laptop. 159 */ 160 if (intel_has_dpcd_quirk(intel_dp, QUIRK_FW_SYNC_LEN)) 161 precharge += 2; 162 163 return precharge + preamble; 164 } 165 166 static int g4x_dp_aux_precharge_len(void) 167 { 168 int precharge_min = 10; 169 int preamble = 16; 170 171 /* HW wants the length of the extra precharge in 2us units */ 172 return (intel_dp_aux_sync_len() - 173 precharge_min - preamble) / 2; 174 } 175 176 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 177 int send_bytes, 178 u32 aux_clock_divider) 179 { 180 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 181 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 182 u32 timeout; 183 184 /* Max timeout value on G4x-BDW: 1.6ms */ 185 if (IS_BROADWELL(i915)) 186 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 187 else 188 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 189 190 return DP_AUX_CH_CTL_SEND_BUSY | 191 DP_AUX_CH_CTL_DONE | 192 DP_AUX_CH_CTL_INTERRUPT | 193 DP_AUX_CH_CTL_TIME_OUT_ERROR | 194 timeout | 195 DP_AUX_CH_CTL_RECEIVE_ERROR | 196 DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) | 197 DP_AUX_CH_CTL_PRECHARGE_2US(g4x_dp_aux_precharge_len()) | 198 DP_AUX_CH_CTL_BIT_CLOCK_2X(aux_clock_divider); 199 } 200 201 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 202 int send_bytes, 203 u32 unused) 204 { 205 struct intel_display *display = to_intel_display(intel_dp); 206 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 207 u32 ret; 208 209 /* 210 * Max timeout values: 211 * SKL-GLK: 1.6ms 212 * ICL+: 4ms 213 */ 214 ret = DP_AUX_CH_CTL_SEND_BUSY | 215 DP_AUX_CH_CTL_DONE | 216 DP_AUX_CH_CTL_INTERRUPT | 217 DP_AUX_CH_CTL_TIME_OUT_ERROR | 218 DP_AUX_CH_CTL_TIME_OUT_MAX | 219 DP_AUX_CH_CTL_RECEIVE_ERROR | 220 DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) | 221 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len(intel_dp)) | 222 DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len()); 223 224 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 225 ret |= DP_AUX_CH_CTL_TBT_IO; 226 227 /* 228 * Power request bit is already set during aux power well enable. 229 * Preserve the bit across aux transactions. 230 */ 231 if (DISPLAY_VER(display) >= 14) 232 ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; 233 234 return ret; 235 } 236 237 static int 238 intel_dp_aux_xfer(struct intel_dp *intel_dp, 239 const u8 *send, int send_bytes, 240 u8 *recv, int recv_size, 241 u32 aux_send_ctl_flags) 242 { 243 struct intel_display *display = to_intel_display(intel_dp); 244 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 245 struct intel_encoder *encoder = &dig_port->base; 246 i915_reg_t ch_ctl, ch_data[5]; 247 u32 aux_clock_divider; 248 enum intel_display_power_domain aux_domain; 249 intel_wakeref_t aux_wakeref; 250 intel_wakeref_t pps_wakeref = NULL; 251 int i, ret, recv_bytes; 252 int try, clock = 0; 253 u32 status; 254 bool vdd; 255 256 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 257 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 258 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 259 260 intel_digital_port_lock(encoder); 261 /* 262 * Abort transfers on a disconnected port as required by 263 * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX 264 * timeouts that would otherwise happen. 265 */ 266 if (!intel_dp_is_edp(intel_dp) && 267 !intel_digital_port_connected_locked(&dig_port->base)) { 268 ret = -ENXIO; 269 goto out_unlock; 270 } 271 272 aux_domain = intel_aux_power_domain(dig_port); 273 274 aux_wakeref = intel_display_power_get(display, aux_domain); 275 276 /* 277 * The PPS state needs to be locked for: 278 * - eDP on all platforms, since AUX transfers on eDP need VDD power 279 * (either forced or via panel power) which depends on the PPS 280 * state. 281 * - non-eDP on platforms where the PPS is a pipe instance (VLV/CHV), 282 * since changing the PPS state (via a parallel modeset for 283 * instance) may interfere with the AUX transfers on a non-eDP 284 * output as well. 285 */ 286 if (intel_dp_is_edp(intel_dp) || 287 display->platform.valleyview || display->platform.cherryview) 288 pps_wakeref = intel_pps_lock(intel_dp); 289 290 /* 291 * We will be called with VDD already enabled for dpcd/edid/oui reads. 292 * In such cases we want to leave VDD enabled and it's up to upper layers 293 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 294 * ourselves. 295 */ 296 vdd = intel_pps_vdd_on_unlocked(intel_dp); 297 298 /* 299 * dp aux is extremely sensitive to irq latency, hence request the 300 * lowest possible wakeup latency and so prevent the cpu from going into 301 * deep sleep states. 302 */ 303 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 304 305 intel_pps_check_power_unlocked(intel_dp); 306 307 /* 308 * FIXME PSR should be disabled here to prevent 309 * it using the same AUX CH simultaneously 310 */ 311 312 /* Try to wait for any previous AUX channel activity */ 313 for (try = 0; try < 3; try++) { 314 status = intel_de_read_notrace(display, ch_ctl); 315 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 316 break; 317 msleep(1); 318 } 319 /* just trace the final value */ 320 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 321 322 if (try == 3) { 323 const u32 status = intel_de_read(display, ch_ctl); 324 325 if (status != intel_dp->aux_busy_last_status) { 326 drm_WARN(display->drm, 1, 327 "%s: not started (status 0x%08x)\n", 328 intel_dp->aux.name, status); 329 intel_dp->aux_busy_last_status = status; 330 } 331 332 ret = -EBUSY; 333 goto out; 334 } 335 336 /* Only 5 data registers! */ 337 if (drm_WARN_ON(display->drm, send_bytes > 20 || recv_size > 20)) { 338 ret = -E2BIG; 339 goto out; 340 } 341 342 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 343 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 344 send_bytes, 345 aux_clock_divider); 346 347 send_ctl |= aux_send_ctl_flags; 348 349 /* Must try at least 3 times according to DP spec */ 350 for (try = 0; try < 5; try++) { 351 /* Load the send data into the aux channel data registers */ 352 for (i = 0; i < send_bytes; i += 4) 353 intel_de_write(display, ch_data[i >> 2], 354 intel_dp_aux_pack(send + i, 355 send_bytes - i)); 356 357 /* Send the command and wait for it to complete */ 358 intel_de_write(display, ch_ctl, send_ctl); 359 360 status = intel_dp_aux_wait_done(intel_dp); 361 362 /* Clear done status and any errors */ 363 intel_de_write(display, ch_ctl, 364 status | DP_AUX_CH_CTL_DONE | 365 DP_AUX_CH_CTL_TIME_OUT_ERROR | 366 DP_AUX_CH_CTL_RECEIVE_ERROR); 367 368 /* 369 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 370 * 400us delay required for errors and timeouts 371 * Timeout errors from the HW already meet this 372 * requirement so skip to next iteration 373 */ 374 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 375 continue; 376 377 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 378 usleep_range(400, 500); 379 continue; 380 } 381 if (status & DP_AUX_CH_CTL_DONE) 382 goto done; 383 } 384 } 385 386 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 387 drm_err(display->drm, "%s: not done (status 0x%08x)\n", 388 intel_dp->aux.name, status); 389 ret = -EBUSY; 390 goto out; 391 } 392 393 done: 394 /* 395 * Check for timeout or receive error. Timeouts occur when the sink is 396 * not connected. 397 */ 398 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 399 drm_err(display->drm, "%s: receive error (status 0x%08x)\n", 400 intel_dp->aux.name, status); 401 ret = -EIO; 402 goto out; 403 } 404 405 /* 406 * Timeouts occur when the device isn't connected, so they're "normal" 407 * -- don't fill the kernel log with these 408 */ 409 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 410 drm_dbg_kms(display->drm, "%s: timeout (status 0x%08x)\n", 411 intel_dp->aux.name, status); 412 ret = -ETIMEDOUT; 413 goto out; 414 } 415 416 /* Unload any bytes sent back from the other side */ 417 recv_bytes = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, status); 418 419 /* 420 * By BSpec: "Message sizes of 0 or >20 are not allowed." 421 * We have no idea of what happened so we return -EBUSY so 422 * drm layer takes care for the necessary retries. 423 */ 424 if (recv_bytes == 0 || recv_bytes > 20) { 425 drm_dbg_kms(display->drm, 426 "%s: Forbidden recv_bytes = %d on aux transaction\n", 427 intel_dp->aux.name, recv_bytes); 428 ret = -EBUSY; 429 goto out; 430 } 431 432 if (recv_bytes > recv_size) 433 recv_bytes = recv_size; 434 435 for (i = 0; i < recv_bytes; i += 4) 436 intel_dp_aux_unpack(intel_de_read(display, ch_data[i >> 2]), 437 recv + i, recv_bytes - i); 438 439 ret = recv_bytes; 440 out: 441 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 442 443 if (vdd) 444 intel_pps_vdd_off_unlocked(intel_dp, false); 445 446 if (pps_wakeref) 447 intel_pps_unlock(intel_dp, pps_wakeref); 448 449 intel_display_power_put_async(display, aux_domain, aux_wakeref); 450 out_unlock: 451 intel_digital_port_unlock(encoder); 452 453 return ret; 454 } 455 456 #define BARE_ADDRESS_SIZE 3 457 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 458 459 static void 460 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 461 const struct drm_dp_aux_msg *msg) 462 { 463 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 464 txbuf[1] = (msg->address >> 8) & 0xff; 465 txbuf[2] = msg->address & 0xff; 466 txbuf[3] = msg->size - 1; 467 } 468 469 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 470 { 471 /* 472 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 473 * select bit to inform the hardware to send the Aksv after our header 474 * since we can't access that data from software. 475 */ 476 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 477 msg->address == DP_AUX_HDCP_AKSV) 478 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 479 480 return 0; 481 } 482 483 static ssize_t 484 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 485 { 486 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 487 struct intel_display *display = to_intel_display(intel_dp); 488 u8 txbuf[20], rxbuf[20]; 489 size_t txsize, rxsize; 490 u32 flags = intel_dp_aux_xfer_flags(msg); 491 int ret; 492 493 intel_dp_aux_header(txbuf, msg); 494 495 switch (msg->request & ~DP_AUX_I2C_MOT) { 496 case DP_AUX_NATIVE_WRITE: 497 case DP_AUX_I2C_WRITE: 498 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 499 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 500 rxsize = 2; /* 0 or 1 data bytes */ 501 502 if (drm_WARN_ON(display->drm, txsize > 20)) 503 return -E2BIG; 504 505 drm_WARN_ON(display->drm, !msg->buffer != !msg->size); 506 507 if (msg->buffer) 508 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 509 510 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 511 rxbuf, rxsize, flags); 512 if (ret > 0) { 513 msg->reply = rxbuf[0] >> 4; 514 515 if (ret > 1) { 516 /* Number of bytes written in a short write. */ 517 ret = clamp_t(int, rxbuf[1], 0, msg->size); 518 } else { 519 /* Return payload size. */ 520 ret = msg->size; 521 } 522 } 523 break; 524 525 case DP_AUX_NATIVE_READ: 526 case DP_AUX_I2C_READ: 527 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 528 rxsize = msg->size + 1; 529 530 if (drm_WARN_ON(display->drm, rxsize > 20)) 531 return -E2BIG; 532 533 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 534 rxbuf, rxsize, flags); 535 if (ret > 0) { 536 msg->reply = rxbuf[0] >> 4; 537 /* 538 * Assume happy day, and copy the data. The caller is 539 * expected to check msg->reply before touching it. 540 * 541 * Return payload size. 542 */ 543 ret--; 544 memcpy(msg->buffer, rxbuf + 1, ret); 545 } 546 break; 547 548 default: 549 ret = -EINVAL; 550 break; 551 } 552 553 return ret; 554 } 555 556 static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp) 557 { 558 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 559 enum aux_ch aux_ch = dig_port->aux_ch; 560 561 switch (aux_ch) { 562 case AUX_CH_B: 563 case AUX_CH_C: 564 case AUX_CH_D: 565 return VLV_DP_AUX_CH_CTL(aux_ch); 566 default: 567 MISSING_CASE(aux_ch); 568 return VLV_DP_AUX_CH_CTL(AUX_CH_B); 569 } 570 } 571 572 static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index) 573 { 574 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 575 enum aux_ch aux_ch = dig_port->aux_ch; 576 577 switch (aux_ch) { 578 case AUX_CH_B: 579 case AUX_CH_C: 580 case AUX_CH_D: 581 return VLV_DP_AUX_CH_DATA(aux_ch, index); 582 default: 583 MISSING_CASE(aux_ch); 584 return VLV_DP_AUX_CH_DATA(AUX_CH_B, index); 585 } 586 } 587 588 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 589 { 590 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 591 enum aux_ch aux_ch = dig_port->aux_ch; 592 593 switch (aux_ch) { 594 case AUX_CH_B: 595 case AUX_CH_C: 596 case AUX_CH_D: 597 return DP_AUX_CH_CTL(aux_ch); 598 default: 599 MISSING_CASE(aux_ch); 600 return DP_AUX_CH_CTL(AUX_CH_B); 601 } 602 } 603 604 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 605 { 606 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 607 enum aux_ch aux_ch = dig_port->aux_ch; 608 609 switch (aux_ch) { 610 case AUX_CH_B: 611 case AUX_CH_C: 612 case AUX_CH_D: 613 return DP_AUX_CH_DATA(aux_ch, index); 614 default: 615 MISSING_CASE(aux_ch); 616 return DP_AUX_CH_DATA(AUX_CH_B, index); 617 } 618 } 619 620 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 621 { 622 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 623 enum aux_ch aux_ch = dig_port->aux_ch; 624 625 switch (aux_ch) { 626 case AUX_CH_A: 627 return DP_AUX_CH_CTL(aux_ch); 628 case AUX_CH_B: 629 case AUX_CH_C: 630 case AUX_CH_D: 631 return PCH_DP_AUX_CH_CTL(aux_ch); 632 default: 633 MISSING_CASE(aux_ch); 634 return DP_AUX_CH_CTL(AUX_CH_A); 635 } 636 } 637 638 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 639 { 640 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 641 enum aux_ch aux_ch = dig_port->aux_ch; 642 643 switch (aux_ch) { 644 case AUX_CH_A: 645 return DP_AUX_CH_DATA(aux_ch, index); 646 case AUX_CH_B: 647 case AUX_CH_C: 648 case AUX_CH_D: 649 return PCH_DP_AUX_CH_DATA(aux_ch, index); 650 default: 651 MISSING_CASE(aux_ch); 652 return DP_AUX_CH_DATA(AUX_CH_A, index); 653 } 654 } 655 656 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 657 { 658 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 659 enum aux_ch aux_ch = dig_port->aux_ch; 660 661 switch (aux_ch) { 662 case AUX_CH_A: 663 case AUX_CH_B: 664 case AUX_CH_C: 665 case AUX_CH_D: 666 case AUX_CH_E: 667 case AUX_CH_F: 668 return DP_AUX_CH_CTL(aux_ch); 669 default: 670 MISSING_CASE(aux_ch); 671 return DP_AUX_CH_CTL(AUX_CH_A); 672 } 673 } 674 675 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 676 { 677 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 678 enum aux_ch aux_ch = dig_port->aux_ch; 679 680 switch (aux_ch) { 681 case AUX_CH_A: 682 case AUX_CH_B: 683 case AUX_CH_C: 684 case AUX_CH_D: 685 case AUX_CH_E: 686 case AUX_CH_F: 687 return DP_AUX_CH_DATA(aux_ch, index); 688 default: 689 MISSING_CASE(aux_ch); 690 return DP_AUX_CH_DATA(AUX_CH_A, index); 691 } 692 } 693 694 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 695 { 696 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 697 enum aux_ch aux_ch = dig_port->aux_ch; 698 699 switch (aux_ch) { 700 case AUX_CH_A: 701 case AUX_CH_B: 702 case AUX_CH_C: 703 case AUX_CH_USBC1: 704 case AUX_CH_USBC2: 705 case AUX_CH_USBC3: 706 case AUX_CH_USBC4: 707 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 708 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 709 return DP_AUX_CH_CTL(aux_ch); 710 default: 711 MISSING_CASE(aux_ch); 712 return DP_AUX_CH_CTL(AUX_CH_A); 713 } 714 } 715 716 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 717 { 718 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 719 enum aux_ch aux_ch = dig_port->aux_ch; 720 721 switch (aux_ch) { 722 case AUX_CH_A: 723 case AUX_CH_B: 724 case AUX_CH_C: 725 case AUX_CH_USBC1: 726 case AUX_CH_USBC2: 727 case AUX_CH_USBC3: 728 case AUX_CH_USBC4: 729 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 730 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 731 return DP_AUX_CH_DATA(aux_ch, index); 732 default: 733 MISSING_CASE(aux_ch); 734 return DP_AUX_CH_DATA(AUX_CH_A, index); 735 } 736 } 737 738 static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) 739 { 740 struct intel_display *display = to_intel_display(intel_dp); 741 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 742 enum aux_ch aux_ch = dig_port->aux_ch; 743 744 switch (aux_ch) { 745 case AUX_CH_A: 746 case AUX_CH_B: 747 case AUX_CH_USBC1: 748 case AUX_CH_USBC2: 749 case AUX_CH_USBC3: 750 case AUX_CH_USBC4: 751 return XELPDP_DP_AUX_CH_CTL(display, aux_ch); 752 default: 753 MISSING_CASE(aux_ch); 754 return XELPDP_DP_AUX_CH_CTL(display, AUX_CH_A); 755 } 756 } 757 758 static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) 759 { 760 struct intel_display *display = to_intel_display(intel_dp); 761 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 762 enum aux_ch aux_ch = dig_port->aux_ch; 763 764 switch (aux_ch) { 765 case AUX_CH_A: 766 case AUX_CH_B: 767 case AUX_CH_USBC1: 768 case AUX_CH_USBC2: 769 case AUX_CH_USBC3: 770 case AUX_CH_USBC4: 771 return XELPDP_DP_AUX_CH_DATA(display, aux_ch, index); 772 default: 773 MISSING_CASE(aux_ch); 774 return XELPDP_DP_AUX_CH_DATA(display, AUX_CH_A, index); 775 } 776 } 777 778 void intel_dp_aux_fini(struct intel_dp *intel_dp) 779 { 780 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 781 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 782 783 kfree(intel_dp->aux.name); 784 } 785 786 void intel_dp_aux_init(struct intel_dp *intel_dp) 787 { 788 struct intel_display *display = to_intel_display(intel_dp); 789 struct drm_i915_private *i915 = to_i915(display->drm); 790 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 791 struct intel_encoder *encoder = &dig_port->base; 792 enum aux_ch aux_ch = dig_port->aux_ch; 793 char buf[AUX_CH_NAME_BUFSIZE]; 794 795 if (DISPLAY_VER(display) >= 14) { 796 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; 797 intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; 798 } else if (DISPLAY_VER(display) >= 12) { 799 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 800 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 801 } else if (DISPLAY_VER(display) >= 9) { 802 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 803 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 804 } else if (HAS_PCH_SPLIT(i915)) { 805 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 806 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 807 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 808 intel_dp->aux_ch_ctl_reg = vlv_aux_ctl_reg; 809 intel_dp->aux_ch_data_reg = vlv_aux_data_reg; 810 } else { 811 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 812 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 813 } 814 815 if (DISPLAY_VER(display) >= 9) 816 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 817 else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) 818 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 819 else if (HAS_PCH_SPLIT(i915)) 820 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 821 else 822 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 823 824 if (DISPLAY_VER(display) >= 9) 825 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 826 else 827 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 828 829 intel_dp->aux.drm_dev = display->drm; 830 drm_dp_aux_init(&intel_dp->aux); 831 832 /* Failure to allocate our preferred name is not critical */ 833 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %s/%s", 834 aux_ch_name(display, buf, sizeof(buf), aux_ch), 835 encoder->base.name); 836 837 intel_dp->aux.transfer = intel_dp_aux_transfer; 838 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 839 } 840 841 static enum aux_ch default_aux_ch(struct intel_encoder *encoder) 842 { 843 struct intel_display *display = to_intel_display(encoder); 844 845 /* SKL has DDI E but no AUX E */ 846 if (DISPLAY_VER(display) == 9 && encoder->port == PORT_E) 847 return AUX_CH_A; 848 849 return (enum aux_ch)encoder->port; 850 } 851 852 static struct intel_encoder * 853 get_encoder_by_aux_ch(struct intel_encoder *encoder, 854 enum aux_ch aux_ch) 855 { 856 struct intel_display *display = to_intel_display(encoder); 857 struct intel_encoder *other; 858 859 for_each_intel_encoder(display->drm, other) { 860 if (other == encoder) 861 continue; 862 863 if (!intel_encoder_is_dig_port(other)) 864 continue; 865 866 if (enc_to_dig_port(other)->aux_ch == aux_ch) 867 return other; 868 } 869 870 return NULL; 871 } 872 873 enum aux_ch intel_dp_aux_ch(struct intel_encoder *encoder) 874 { 875 struct intel_display *display = to_intel_display(encoder); 876 struct intel_encoder *other; 877 const char *source; 878 enum aux_ch aux_ch; 879 char buf[AUX_CH_NAME_BUFSIZE]; 880 881 aux_ch = intel_bios_dp_aux_ch(encoder->devdata); 882 source = "VBT"; 883 884 if (aux_ch == AUX_CH_NONE) { 885 aux_ch = default_aux_ch(encoder); 886 source = "platform default"; 887 } 888 889 if (aux_ch == AUX_CH_NONE) 890 return AUX_CH_NONE; 891 892 /* FIXME validate aux_ch against platform caps */ 893 894 other = get_encoder_by_aux_ch(encoder, aux_ch); 895 if (other) { 896 drm_dbg_kms(display->drm, 897 "[ENCODER:%d:%s] AUX CH %s already claimed by [ENCODER:%d:%s]\n", 898 encoder->base.base.id, encoder->base.name, 899 aux_ch_name(display, buf, sizeof(buf), aux_ch), 900 other->base.base.id, other->base.name); 901 return AUX_CH_NONE; 902 } 903 904 drm_dbg_kms(display->drm, 905 "[ENCODER:%d:%s] Using AUX CH %s (%s)\n", 906 encoder->base.base.id, encoder->base.name, 907 aux_ch_name(display, buf, sizeof(buf), aux_ch), source); 908 909 return aux_ch; 910 } 911 912 void intel_dp_aux_irq_handler(struct intel_display *display) 913 { 914 wake_up_all(&display->gmbus.wait_queue); 915 } 916