1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020-2021 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "i915_trace.h" 9 #include "intel_bios.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_dp.h" 13 #include "intel_dp_aux.h" 14 #include "intel_dp_aux_regs.h" 15 #include "intel_pps.h" 16 #include "intel_quirks.h" 17 #include "intel_tc.h" 18 19 #define AUX_CH_NAME_BUFSIZE 6 20 21 static const char *aux_ch_name(struct drm_i915_private *i915, 22 char *buf, int size, enum aux_ch aux_ch) 23 { 24 if (DISPLAY_VER(i915) >= 13 && aux_ch >= AUX_CH_D_XELPD) 25 snprintf(buf, size, "%c", 'A' + aux_ch - AUX_CH_D_XELPD + AUX_CH_D); 26 else if (DISPLAY_VER(i915) >= 12 && aux_ch >= AUX_CH_USBC1) 27 snprintf(buf, size, "USBC%c", '1' + aux_ch - AUX_CH_USBC1); 28 else 29 snprintf(buf, size, "%c", 'A' + aux_ch); 30 31 return buf; 32 } 33 34 u32 intel_dp_aux_pack(const u8 *src, int src_bytes) 35 { 36 int i; 37 u32 v = 0; 38 39 if (src_bytes > 4) 40 src_bytes = 4; 41 for (i = 0; i < src_bytes; i++) 42 v |= ((u32)src[i]) << ((3 - i) * 8); 43 return v; 44 } 45 46 static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes) 47 { 48 int i; 49 50 if (dst_bytes > 4) 51 dst_bytes = 4; 52 for (i = 0; i < dst_bytes; i++) 53 dst[i] = src >> ((3 - i) * 8); 54 } 55 56 static u32 57 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 58 { 59 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 60 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 61 const unsigned int timeout_ms = 10; 62 u32 status; 63 int ret; 64 65 ret = intel_de_wait_custom(i915, ch_ctl, DP_AUX_CH_CTL_SEND_BUSY, 0, 66 2, timeout_ms, &status); 67 68 if (ret == -ETIMEDOUT) 69 drm_err(&i915->drm, 70 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 71 intel_dp->aux.name, timeout_ms, status); 72 73 return status; 74 } 75 76 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 77 { 78 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 79 80 if (index) 81 return 0; 82 83 /* 84 * The clock divider is based off the hrawclk, and would like to run at 85 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 86 */ 87 return DIV_ROUND_CLOSEST(RUNTIME_INFO(i915)->rawclk_freq, 2000); 88 } 89 90 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 91 { 92 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 93 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 94 u32 freq; 95 96 if (index) 97 return 0; 98 99 /* 100 * The clock divider is based off the cdclk or PCH rawclk, and would 101 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 102 * divide by 2000 and use that 103 */ 104 if (dig_port->aux_ch == AUX_CH_A) 105 freq = i915->display.cdclk.hw.cdclk; 106 else 107 freq = RUNTIME_INFO(i915)->rawclk_freq; 108 return DIV_ROUND_CLOSEST(freq, 2000); 109 } 110 111 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 112 { 113 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 114 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 115 116 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(i915)) { 117 /* Workaround for non-ULT HSW */ 118 switch (index) { 119 case 0: return 63; 120 case 1: return 72; 121 default: return 0; 122 } 123 } 124 125 return ilk_get_aux_clock_divider(intel_dp, index); 126 } 127 128 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 129 { 130 /* 131 * SKL doesn't need us to program the AUX clock divider (Hardware will 132 * derive the clock from CDCLK automatically). We still implement the 133 * get_aux_clock_divider vfunc to plug-in into the existing code. 134 */ 135 return index ? 0 : 1; 136 } 137 138 static int intel_dp_aux_sync_len(void) 139 { 140 int precharge = 16; /* 10-16 */ 141 int preamble = 16; 142 143 return precharge + preamble; 144 } 145 146 int intel_dp_aux_fw_sync_len(struct intel_dp *intel_dp) 147 { 148 int precharge = 10; /* 10-16 */ 149 int preamble = 8; 150 151 /* 152 * We faced some glitches on Dell Precision 5490 MTL laptop with panel: 153 * "Manufacturer: AUO, Model: 63898" when using HW default 18. Using 20 154 * is fixing these problems with the panel. It is still within range 155 * mentioned in eDP specification. Increasing Fast Wake sync length is 156 * causing problems with other panels: increase length as a quirk for 157 * this specific laptop. 158 */ 159 if (intel_has_dpcd_quirk(intel_dp, QUIRK_FW_SYNC_LEN)) 160 precharge += 2; 161 162 return precharge + preamble; 163 } 164 165 static int g4x_dp_aux_precharge_len(void) 166 { 167 int precharge_min = 10; 168 int preamble = 16; 169 170 /* HW wants the length of the extra precharge in 2us units */ 171 return (intel_dp_aux_sync_len() - 172 precharge_min - preamble) / 2; 173 } 174 175 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 176 int send_bytes, 177 u32 aux_clock_divider) 178 { 179 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 180 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 181 u32 timeout; 182 183 /* Max timeout value on G4x-BDW: 1.6ms */ 184 if (IS_BROADWELL(i915)) 185 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 186 else 187 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 188 189 return DP_AUX_CH_CTL_SEND_BUSY | 190 DP_AUX_CH_CTL_DONE | 191 DP_AUX_CH_CTL_INTERRUPT | 192 DP_AUX_CH_CTL_TIME_OUT_ERROR | 193 timeout | 194 DP_AUX_CH_CTL_RECEIVE_ERROR | 195 DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) | 196 DP_AUX_CH_CTL_PRECHARGE_2US(g4x_dp_aux_precharge_len()) | 197 DP_AUX_CH_CTL_BIT_CLOCK_2X(aux_clock_divider); 198 } 199 200 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 201 int send_bytes, 202 u32 unused) 203 { 204 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 205 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 206 u32 ret; 207 208 /* 209 * Max timeout values: 210 * SKL-GLK: 1.6ms 211 * ICL+: 4ms 212 */ 213 ret = DP_AUX_CH_CTL_SEND_BUSY | 214 DP_AUX_CH_CTL_DONE | 215 DP_AUX_CH_CTL_INTERRUPT | 216 DP_AUX_CH_CTL_TIME_OUT_ERROR | 217 DP_AUX_CH_CTL_TIME_OUT_MAX | 218 DP_AUX_CH_CTL_RECEIVE_ERROR | 219 DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) | 220 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len(intel_dp)) | 221 DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len()); 222 223 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 224 ret |= DP_AUX_CH_CTL_TBT_IO; 225 226 /* 227 * Power request bit is already set during aux power well enable. 228 * Preserve the bit across aux transactions. 229 */ 230 if (DISPLAY_VER(i915) >= 14) 231 ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; 232 233 return ret; 234 } 235 236 static int 237 intel_dp_aux_xfer(struct intel_dp *intel_dp, 238 const u8 *send, int send_bytes, 239 u8 *recv, int recv_size, 240 u32 aux_send_ctl_flags) 241 { 242 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 243 struct intel_encoder *encoder = &dig_port->base; 244 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 245 i915_reg_t ch_ctl, ch_data[5]; 246 u32 aux_clock_divider; 247 enum intel_display_power_domain aux_domain; 248 intel_wakeref_t aux_wakeref; 249 intel_wakeref_t pps_wakeref; 250 int i, ret, recv_bytes; 251 int try, clock = 0; 252 u32 status; 253 bool vdd; 254 255 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 256 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 257 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 258 259 intel_digital_port_lock(encoder); 260 /* 261 * Abort transfers on a disconnected port as required by 262 * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX 263 * timeouts that would otherwise happen. 264 */ 265 if (!intel_dp_is_edp(intel_dp) && 266 !intel_digital_port_connected_locked(&dig_port->base)) { 267 ret = -ENXIO; 268 goto out_unlock; 269 } 270 271 aux_domain = intel_aux_power_domain(dig_port); 272 273 aux_wakeref = intel_display_power_get(i915, aux_domain); 274 pps_wakeref = intel_pps_lock(intel_dp); 275 276 /* 277 * We will be called with VDD already enabled for dpcd/edid/oui reads. 278 * In such cases we want to leave VDD enabled and it's up to upper layers 279 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 280 * ourselves. 281 */ 282 vdd = intel_pps_vdd_on_unlocked(intel_dp); 283 284 /* 285 * dp aux is extremely sensitive to irq latency, hence request the 286 * lowest possible wakeup latency and so prevent the cpu from going into 287 * deep sleep states. 288 */ 289 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 290 291 intel_pps_check_power_unlocked(intel_dp); 292 293 /* 294 * FIXME PSR should be disabled here to prevent 295 * it using the same AUX CH simultaneously 296 */ 297 298 /* Try to wait for any previous AUX channel activity */ 299 for (try = 0; try < 3; try++) { 300 status = intel_de_read_notrace(i915, ch_ctl); 301 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 302 break; 303 msleep(1); 304 } 305 /* just trace the final value */ 306 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 307 308 if (try == 3) { 309 const u32 status = intel_de_read(i915, ch_ctl); 310 311 if (status != intel_dp->aux_busy_last_status) { 312 drm_WARN(&i915->drm, 1, 313 "%s: not started (status 0x%08x)\n", 314 intel_dp->aux.name, status); 315 intel_dp->aux_busy_last_status = status; 316 } 317 318 ret = -EBUSY; 319 goto out; 320 } 321 322 /* Only 5 data registers! */ 323 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { 324 ret = -E2BIG; 325 goto out; 326 } 327 328 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 329 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 330 send_bytes, 331 aux_clock_divider); 332 333 send_ctl |= aux_send_ctl_flags; 334 335 /* Must try at least 3 times according to DP spec */ 336 for (try = 0; try < 5; try++) { 337 /* Load the send data into the aux channel data registers */ 338 for (i = 0; i < send_bytes; i += 4) 339 intel_de_write(i915, ch_data[i >> 2], 340 intel_dp_aux_pack(send + i, 341 send_bytes - i)); 342 343 /* Send the command and wait for it to complete */ 344 intel_de_write(i915, ch_ctl, send_ctl); 345 346 status = intel_dp_aux_wait_done(intel_dp); 347 348 /* Clear done status and any errors */ 349 intel_de_write(i915, ch_ctl, 350 status | DP_AUX_CH_CTL_DONE | 351 DP_AUX_CH_CTL_TIME_OUT_ERROR | 352 DP_AUX_CH_CTL_RECEIVE_ERROR); 353 354 /* 355 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 356 * 400us delay required for errors and timeouts 357 * Timeout errors from the HW already meet this 358 * requirement so skip to next iteration 359 */ 360 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 361 continue; 362 363 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 364 usleep_range(400, 500); 365 continue; 366 } 367 if (status & DP_AUX_CH_CTL_DONE) 368 goto done; 369 } 370 } 371 372 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 373 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", 374 intel_dp->aux.name, status); 375 ret = -EBUSY; 376 goto out; 377 } 378 379 done: 380 /* 381 * Check for timeout or receive error. Timeouts occur when the sink is 382 * not connected. 383 */ 384 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 385 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", 386 intel_dp->aux.name, status); 387 ret = -EIO; 388 goto out; 389 } 390 391 /* 392 * Timeouts occur when the device isn't connected, so they're "normal" 393 * -- don't fill the kernel log with these 394 */ 395 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 396 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", 397 intel_dp->aux.name, status); 398 ret = -ETIMEDOUT; 399 goto out; 400 } 401 402 /* Unload any bytes sent back from the other side */ 403 recv_bytes = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, status); 404 405 /* 406 * By BSpec: "Message sizes of 0 or >20 are not allowed." 407 * We have no idea of what happened so we return -EBUSY so 408 * drm layer takes care for the necessary retries. 409 */ 410 if (recv_bytes == 0 || recv_bytes > 20) { 411 drm_dbg_kms(&i915->drm, 412 "%s: Forbidden recv_bytes = %d on aux transaction\n", 413 intel_dp->aux.name, recv_bytes); 414 ret = -EBUSY; 415 goto out; 416 } 417 418 if (recv_bytes > recv_size) 419 recv_bytes = recv_size; 420 421 for (i = 0; i < recv_bytes; i += 4) 422 intel_dp_aux_unpack(intel_de_read(i915, ch_data[i >> 2]), 423 recv + i, recv_bytes - i); 424 425 ret = recv_bytes; 426 out: 427 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 428 429 if (vdd) 430 intel_pps_vdd_off_unlocked(intel_dp, false); 431 432 intel_pps_unlock(intel_dp, pps_wakeref); 433 intel_display_power_put_async(i915, aux_domain, aux_wakeref); 434 out_unlock: 435 intel_digital_port_unlock(encoder); 436 437 return ret; 438 } 439 440 #define BARE_ADDRESS_SIZE 3 441 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 442 443 static void 444 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 445 const struct drm_dp_aux_msg *msg) 446 { 447 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 448 txbuf[1] = (msg->address >> 8) & 0xff; 449 txbuf[2] = msg->address & 0xff; 450 txbuf[3] = msg->size - 1; 451 } 452 453 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 454 { 455 /* 456 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 457 * select bit to inform the hardware to send the Aksv after our header 458 * since we can't access that data from software. 459 */ 460 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 461 msg->address == DP_AUX_HDCP_AKSV) 462 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 463 464 return 0; 465 } 466 467 static ssize_t 468 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 469 { 470 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 471 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 472 u8 txbuf[20], rxbuf[20]; 473 size_t txsize, rxsize; 474 u32 flags = intel_dp_aux_xfer_flags(msg); 475 int ret; 476 477 intel_dp_aux_header(txbuf, msg); 478 479 switch (msg->request & ~DP_AUX_I2C_MOT) { 480 case DP_AUX_NATIVE_WRITE: 481 case DP_AUX_I2C_WRITE: 482 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 483 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 484 rxsize = 2; /* 0 or 1 data bytes */ 485 486 if (drm_WARN_ON(&i915->drm, txsize > 20)) 487 return -E2BIG; 488 489 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size); 490 491 if (msg->buffer) 492 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 493 494 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 495 rxbuf, rxsize, flags); 496 if (ret > 0) { 497 msg->reply = rxbuf[0] >> 4; 498 499 if (ret > 1) { 500 /* Number of bytes written in a short write. */ 501 ret = clamp_t(int, rxbuf[1], 0, msg->size); 502 } else { 503 /* Return payload size. */ 504 ret = msg->size; 505 } 506 } 507 break; 508 509 case DP_AUX_NATIVE_READ: 510 case DP_AUX_I2C_READ: 511 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 512 rxsize = msg->size + 1; 513 514 if (drm_WARN_ON(&i915->drm, rxsize > 20)) 515 return -E2BIG; 516 517 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 518 rxbuf, rxsize, flags); 519 if (ret > 0) { 520 msg->reply = rxbuf[0] >> 4; 521 /* 522 * Assume happy day, and copy the data. The caller is 523 * expected to check msg->reply before touching it. 524 * 525 * Return payload size. 526 */ 527 ret--; 528 memcpy(msg->buffer, rxbuf + 1, ret); 529 } 530 break; 531 532 default: 533 ret = -EINVAL; 534 break; 535 } 536 537 return ret; 538 } 539 540 static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp) 541 { 542 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 543 enum aux_ch aux_ch = dig_port->aux_ch; 544 545 switch (aux_ch) { 546 case AUX_CH_B: 547 case AUX_CH_C: 548 case AUX_CH_D: 549 return VLV_DP_AUX_CH_CTL(aux_ch); 550 default: 551 MISSING_CASE(aux_ch); 552 return VLV_DP_AUX_CH_CTL(AUX_CH_B); 553 } 554 } 555 556 static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index) 557 { 558 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 559 enum aux_ch aux_ch = dig_port->aux_ch; 560 561 switch (aux_ch) { 562 case AUX_CH_B: 563 case AUX_CH_C: 564 case AUX_CH_D: 565 return VLV_DP_AUX_CH_DATA(aux_ch, index); 566 default: 567 MISSING_CASE(aux_ch); 568 return VLV_DP_AUX_CH_DATA(AUX_CH_B, index); 569 } 570 } 571 572 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 573 { 574 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 575 enum aux_ch aux_ch = dig_port->aux_ch; 576 577 switch (aux_ch) { 578 case AUX_CH_B: 579 case AUX_CH_C: 580 case AUX_CH_D: 581 return DP_AUX_CH_CTL(aux_ch); 582 default: 583 MISSING_CASE(aux_ch); 584 return DP_AUX_CH_CTL(AUX_CH_B); 585 } 586 } 587 588 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 589 { 590 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 591 enum aux_ch aux_ch = dig_port->aux_ch; 592 593 switch (aux_ch) { 594 case AUX_CH_B: 595 case AUX_CH_C: 596 case AUX_CH_D: 597 return DP_AUX_CH_DATA(aux_ch, index); 598 default: 599 MISSING_CASE(aux_ch); 600 return DP_AUX_CH_DATA(AUX_CH_B, index); 601 } 602 } 603 604 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 605 { 606 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 607 enum aux_ch aux_ch = dig_port->aux_ch; 608 609 switch (aux_ch) { 610 case AUX_CH_A: 611 return DP_AUX_CH_CTL(aux_ch); 612 case AUX_CH_B: 613 case AUX_CH_C: 614 case AUX_CH_D: 615 return PCH_DP_AUX_CH_CTL(aux_ch); 616 default: 617 MISSING_CASE(aux_ch); 618 return DP_AUX_CH_CTL(AUX_CH_A); 619 } 620 } 621 622 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 623 { 624 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 625 enum aux_ch aux_ch = dig_port->aux_ch; 626 627 switch (aux_ch) { 628 case AUX_CH_A: 629 return DP_AUX_CH_DATA(aux_ch, index); 630 case AUX_CH_B: 631 case AUX_CH_C: 632 case AUX_CH_D: 633 return PCH_DP_AUX_CH_DATA(aux_ch, index); 634 default: 635 MISSING_CASE(aux_ch); 636 return DP_AUX_CH_DATA(AUX_CH_A, index); 637 } 638 } 639 640 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 641 { 642 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 643 enum aux_ch aux_ch = dig_port->aux_ch; 644 645 switch (aux_ch) { 646 case AUX_CH_A: 647 case AUX_CH_B: 648 case AUX_CH_C: 649 case AUX_CH_D: 650 case AUX_CH_E: 651 case AUX_CH_F: 652 return DP_AUX_CH_CTL(aux_ch); 653 default: 654 MISSING_CASE(aux_ch); 655 return DP_AUX_CH_CTL(AUX_CH_A); 656 } 657 } 658 659 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 660 { 661 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 662 enum aux_ch aux_ch = dig_port->aux_ch; 663 664 switch (aux_ch) { 665 case AUX_CH_A: 666 case AUX_CH_B: 667 case AUX_CH_C: 668 case AUX_CH_D: 669 case AUX_CH_E: 670 case AUX_CH_F: 671 return DP_AUX_CH_DATA(aux_ch, index); 672 default: 673 MISSING_CASE(aux_ch); 674 return DP_AUX_CH_DATA(AUX_CH_A, index); 675 } 676 } 677 678 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 679 { 680 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 681 enum aux_ch aux_ch = dig_port->aux_ch; 682 683 switch (aux_ch) { 684 case AUX_CH_A: 685 case AUX_CH_B: 686 case AUX_CH_C: 687 case AUX_CH_USBC1: 688 case AUX_CH_USBC2: 689 case AUX_CH_USBC3: 690 case AUX_CH_USBC4: 691 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 692 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 693 return DP_AUX_CH_CTL(aux_ch); 694 default: 695 MISSING_CASE(aux_ch); 696 return DP_AUX_CH_CTL(AUX_CH_A); 697 } 698 } 699 700 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 701 { 702 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 703 enum aux_ch aux_ch = dig_port->aux_ch; 704 705 switch (aux_ch) { 706 case AUX_CH_A: 707 case AUX_CH_B: 708 case AUX_CH_C: 709 case AUX_CH_USBC1: 710 case AUX_CH_USBC2: 711 case AUX_CH_USBC3: 712 case AUX_CH_USBC4: 713 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 714 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 715 return DP_AUX_CH_DATA(aux_ch, index); 716 default: 717 MISSING_CASE(aux_ch); 718 return DP_AUX_CH_DATA(AUX_CH_A, index); 719 } 720 } 721 722 static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) 723 { 724 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 725 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 726 enum aux_ch aux_ch = dig_port->aux_ch; 727 728 switch (aux_ch) { 729 case AUX_CH_A: 730 case AUX_CH_B: 731 case AUX_CH_USBC1: 732 case AUX_CH_USBC2: 733 case AUX_CH_USBC3: 734 case AUX_CH_USBC4: 735 return XELPDP_DP_AUX_CH_CTL(i915, aux_ch); 736 default: 737 MISSING_CASE(aux_ch); 738 return XELPDP_DP_AUX_CH_CTL(i915, AUX_CH_A); 739 } 740 } 741 742 static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) 743 { 744 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 745 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 746 enum aux_ch aux_ch = dig_port->aux_ch; 747 748 switch (aux_ch) { 749 case AUX_CH_A: 750 case AUX_CH_B: 751 case AUX_CH_USBC1: 752 case AUX_CH_USBC2: 753 case AUX_CH_USBC3: 754 case AUX_CH_USBC4: 755 return XELPDP_DP_AUX_CH_DATA(i915, aux_ch, index); 756 default: 757 MISSING_CASE(aux_ch); 758 return XELPDP_DP_AUX_CH_DATA(i915, AUX_CH_A, index); 759 } 760 } 761 762 void intel_dp_aux_fini(struct intel_dp *intel_dp) 763 { 764 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 765 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 766 767 kfree(intel_dp->aux.name); 768 } 769 770 void intel_dp_aux_init(struct intel_dp *intel_dp) 771 { 772 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 773 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 774 struct intel_encoder *encoder = &dig_port->base; 775 enum aux_ch aux_ch = dig_port->aux_ch; 776 char buf[AUX_CH_NAME_BUFSIZE]; 777 778 if (DISPLAY_VER(i915) >= 14) { 779 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; 780 intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; 781 } else if (DISPLAY_VER(i915) >= 12) { 782 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 783 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 784 } else if (DISPLAY_VER(i915) >= 9) { 785 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 786 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 787 } else if (HAS_PCH_SPLIT(i915)) { 788 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 789 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 790 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 791 intel_dp->aux_ch_ctl_reg = vlv_aux_ctl_reg; 792 intel_dp->aux_ch_data_reg = vlv_aux_data_reg; 793 } else { 794 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 795 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 796 } 797 798 if (DISPLAY_VER(i915) >= 9) 799 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 800 else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) 801 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 802 else if (HAS_PCH_SPLIT(i915)) 803 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 804 else 805 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 806 807 if (DISPLAY_VER(i915) >= 9) 808 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 809 else 810 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 811 812 intel_dp->aux.drm_dev = &i915->drm; 813 drm_dp_aux_init(&intel_dp->aux); 814 815 /* Failure to allocate our preferred name is not critical */ 816 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %s/%s", 817 aux_ch_name(i915, buf, sizeof(buf), aux_ch), 818 encoder->base.name); 819 820 intel_dp->aux.transfer = intel_dp_aux_transfer; 821 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 822 } 823 824 static enum aux_ch default_aux_ch(struct intel_encoder *encoder) 825 { 826 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 827 828 /* SKL has DDI E but no AUX E */ 829 if (DISPLAY_VER(i915) == 9 && encoder->port == PORT_E) 830 return AUX_CH_A; 831 832 return (enum aux_ch)encoder->port; 833 } 834 835 static struct intel_encoder * 836 get_encoder_by_aux_ch(struct intel_encoder *encoder, 837 enum aux_ch aux_ch) 838 { 839 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 840 struct intel_encoder *other; 841 842 for_each_intel_encoder(&i915->drm, other) { 843 if (other == encoder) 844 continue; 845 846 if (!intel_encoder_is_dig_port(other)) 847 continue; 848 849 if (enc_to_dig_port(other)->aux_ch == aux_ch) 850 return other; 851 } 852 853 return NULL; 854 } 855 856 enum aux_ch intel_dp_aux_ch(struct intel_encoder *encoder) 857 { 858 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 859 struct intel_encoder *other; 860 const char *source; 861 enum aux_ch aux_ch; 862 char buf[AUX_CH_NAME_BUFSIZE]; 863 864 aux_ch = intel_bios_dp_aux_ch(encoder->devdata); 865 source = "VBT"; 866 867 if (aux_ch == AUX_CH_NONE) { 868 aux_ch = default_aux_ch(encoder); 869 source = "platform default"; 870 } 871 872 if (aux_ch == AUX_CH_NONE) 873 return AUX_CH_NONE; 874 875 /* FIXME validate aux_ch against platform caps */ 876 877 other = get_encoder_by_aux_ch(encoder, aux_ch); 878 if (other) { 879 drm_dbg_kms(&i915->drm, 880 "[ENCODER:%d:%s] AUX CH %s already claimed by [ENCODER:%d:%s]\n", 881 encoder->base.base.id, encoder->base.name, 882 aux_ch_name(i915, buf, sizeof(buf), aux_ch), 883 other->base.base.id, other->base.name); 884 return AUX_CH_NONE; 885 } 886 887 drm_dbg_kms(&i915->drm, 888 "[ENCODER:%d:%s] Using AUX CH %s (%s)\n", 889 encoder->base.base.id, encoder->base.name, 890 aux_ch_name(i915, buf, sizeof(buf), aux_ch), source); 891 892 return aux_ch; 893 } 894 895 void intel_dp_aux_irq_handler(struct drm_i915_private *i915) 896 { 897 wake_up_all(&i915->display.gmbus.wait_queue); 898 } 899