1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020-2021 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "i915_trace.h" 9 #include "intel_bios.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_dp.h" 13 #include "intel_dp_aux.h" 14 #include "intel_dp_aux_regs.h" 15 #include "intel_pps.h" 16 #include "intel_tc.h" 17 18 #define AUX_CH_NAME_BUFSIZE 6 19 20 static const char *aux_ch_name(struct drm_i915_private *i915, 21 char *buf, int size, enum aux_ch aux_ch) 22 { 23 if (DISPLAY_VER(i915) >= 13 && aux_ch >= AUX_CH_D_XELPD) 24 snprintf(buf, size, "%c", 'A' + aux_ch - AUX_CH_D_XELPD + AUX_CH_D); 25 else if (DISPLAY_VER(i915) >= 12 && aux_ch >= AUX_CH_USBC1) 26 snprintf(buf, size, "USBC%c", '1' + aux_ch - AUX_CH_USBC1); 27 else 28 snprintf(buf, size, "%c", 'A' + aux_ch); 29 30 return buf; 31 } 32 33 u32 intel_dp_aux_pack(const u8 *src, int src_bytes) 34 { 35 int i; 36 u32 v = 0; 37 38 if (src_bytes > 4) 39 src_bytes = 4; 40 for (i = 0; i < src_bytes; i++) 41 v |= ((u32)src[i]) << ((3 - i) * 8); 42 return v; 43 } 44 45 static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes) 46 { 47 int i; 48 49 if (dst_bytes > 4) 50 dst_bytes = 4; 51 for (i = 0; i < dst_bytes; i++) 52 dst[i] = src >> ((3 - i) * 8); 53 } 54 55 static u32 56 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 57 { 58 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 59 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 60 const unsigned int timeout_ms = 10; 61 u32 status; 62 int ret; 63 64 ret = intel_de_wait_custom(i915, ch_ctl, DP_AUX_CH_CTL_SEND_BUSY, 0, 65 2, timeout_ms, &status); 66 67 if (ret == -ETIMEDOUT) 68 drm_err(&i915->drm, 69 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 70 intel_dp->aux.name, timeout_ms, status); 71 72 return status; 73 } 74 75 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 76 { 77 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 78 79 if (index) 80 return 0; 81 82 /* 83 * The clock divider is based off the hrawclk, and would like to run at 84 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 85 */ 86 return DIV_ROUND_CLOSEST(RUNTIME_INFO(i915)->rawclk_freq, 2000); 87 } 88 89 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 90 { 91 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 92 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 93 u32 freq; 94 95 if (index) 96 return 0; 97 98 /* 99 * The clock divider is based off the cdclk or PCH rawclk, and would 100 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 101 * divide by 2000 and use that 102 */ 103 if (dig_port->aux_ch == AUX_CH_A) 104 freq = i915->display.cdclk.hw.cdclk; 105 else 106 freq = RUNTIME_INFO(i915)->rawclk_freq; 107 return DIV_ROUND_CLOSEST(freq, 2000); 108 } 109 110 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 111 { 112 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 113 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 114 115 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(i915)) { 116 /* Workaround for non-ULT HSW */ 117 switch (index) { 118 case 0: return 63; 119 case 1: return 72; 120 default: return 0; 121 } 122 } 123 124 return ilk_get_aux_clock_divider(intel_dp, index); 125 } 126 127 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 128 { 129 /* 130 * SKL doesn't need us to program the AUX clock divider (Hardware will 131 * derive the clock from CDCLK automatically). We still implement the 132 * get_aux_clock_divider vfunc to plug-in into the existing code. 133 */ 134 return index ? 0 : 1; 135 } 136 137 static int intel_dp_aux_sync_len(void) 138 { 139 int precharge = 16; /* 10-16 */ 140 int preamble = 16; 141 142 return precharge + preamble; 143 } 144 145 int intel_dp_aux_fw_sync_len(void) 146 { 147 /* 148 * We faced some glitches on Dell Precision 5490 MTL laptop with panel: 149 * "Manufacturer: AUO, Model: 63898" when using HW default 18. Using 20 150 * is fixing these problems with the panel. It is still within range 151 * mentioned in eDP specification. 152 */ 153 int precharge = 12; /* 10-16 */ 154 int preamble = 8; 155 156 return precharge + preamble; 157 } 158 159 static int g4x_dp_aux_precharge_len(void) 160 { 161 int precharge_min = 10; 162 int preamble = 16; 163 164 /* HW wants the length of the extra precharge in 2us units */ 165 return (intel_dp_aux_sync_len() - 166 precharge_min - preamble) / 2; 167 } 168 169 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 170 int send_bytes, 171 u32 aux_clock_divider) 172 { 173 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 174 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 175 u32 timeout; 176 177 /* Max timeout value on G4x-BDW: 1.6ms */ 178 if (IS_BROADWELL(i915)) 179 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 180 else 181 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 182 183 return DP_AUX_CH_CTL_SEND_BUSY | 184 DP_AUX_CH_CTL_DONE | 185 DP_AUX_CH_CTL_INTERRUPT | 186 DP_AUX_CH_CTL_TIME_OUT_ERROR | 187 timeout | 188 DP_AUX_CH_CTL_RECEIVE_ERROR | 189 DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) | 190 DP_AUX_CH_CTL_PRECHARGE_2US(g4x_dp_aux_precharge_len()) | 191 DP_AUX_CH_CTL_BIT_CLOCK_2X(aux_clock_divider); 192 } 193 194 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 195 int send_bytes, 196 u32 unused) 197 { 198 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 199 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 200 u32 ret; 201 202 /* 203 * Max timeout values: 204 * SKL-GLK: 1.6ms 205 * ICL+: 4ms 206 */ 207 ret = DP_AUX_CH_CTL_SEND_BUSY | 208 DP_AUX_CH_CTL_DONE | 209 DP_AUX_CH_CTL_INTERRUPT | 210 DP_AUX_CH_CTL_TIME_OUT_ERROR | 211 DP_AUX_CH_CTL_TIME_OUT_MAX | 212 DP_AUX_CH_CTL_RECEIVE_ERROR | 213 DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) | 214 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len()) | 215 DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len()); 216 217 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 218 ret |= DP_AUX_CH_CTL_TBT_IO; 219 220 /* 221 * Power request bit is already set during aux power well enable. 222 * Preserve the bit across aux transactions. 223 */ 224 if (DISPLAY_VER(i915) >= 14) 225 ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; 226 227 return ret; 228 } 229 230 static int 231 intel_dp_aux_xfer(struct intel_dp *intel_dp, 232 const u8 *send, int send_bytes, 233 u8 *recv, int recv_size, 234 u32 aux_send_ctl_flags) 235 { 236 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 237 struct intel_encoder *encoder = &dig_port->base; 238 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 239 i915_reg_t ch_ctl, ch_data[5]; 240 u32 aux_clock_divider; 241 enum intel_display_power_domain aux_domain; 242 intel_wakeref_t aux_wakeref; 243 intel_wakeref_t pps_wakeref; 244 int i, ret, recv_bytes; 245 int try, clock = 0; 246 u32 status; 247 bool vdd; 248 249 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 250 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 251 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 252 253 intel_digital_port_lock(encoder); 254 /* 255 * Abort transfers on a disconnected port as required by 256 * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX 257 * timeouts that would otherwise happen. 258 */ 259 if (!intel_dp_is_edp(intel_dp) && 260 !intel_digital_port_connected_locked(&dig_port->base)) { 261 ret = -ENXIO; 262 goto out_unlock; 263 } 264 265 aux_domain = intel_aux_power_domain(dig_port); 266 267 aux_wakeref = intel_display_power_get(i915, aux_domain); 268 pps_wakeref = intel_pps_lock(intel_dp); 269 270 /* 271 * We will be called with VDD already enabled for dpcd/edid/oui reads. 272 * In such cases we want to leave VDD enabled and it's up to upper layers 273 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 274 * ourselves. 275 */ 276 vdd = intel_pps_vdd_on_unlocked(intel_dp); 277 278 /* 279 * dp aux is extremely sensitive to irq latency, hence request the 280 * lowest possible wakeup latency and so prevent the cpu from going into 281 * deep sleep states. 282 */ 283 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 284 285 intel_pps_check_power_unlocked(intel_dp); 286 287 /* 288 * FIXME PSR should be disabled here to prevent 289 * it using the same AUX CH simultaneously 290 */ 291 292 /* Try to wait for any previous AUX channel activity */ 293 for (try = 0; try < 3; try++) { 294 status = intel_de_read_notrace(i915, ch_ctl); 295 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 296 break; 297 msleep(1); 298 } 299 /* just trace the final value */ 300 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 301 302 if (try == 3) { 303 const u32 status = intel_de_read(i915, ch_ctl); 304 305 if (status != intel_dp->aux_busy_last_status) { 306 drm_WARN(&i915->drm, 1, 307 "%s: not started (status 0x%08x)\n", 308 intel_dp->aux.name, status); 309 intel_dp->aux_busy_last_status = status; 310 } 311 312 ret = -EBUSY; 313 goto out; 314 } 315 316 /* Only 5 data registers! */ 317 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { 318 ret = -E2BIG; 319 goto out; 320 } 321 322 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 323 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 324 send_bytes, 325 aux_clock_divider); 326 327 send_ctl |= aux_send_ctl_flags; 328 329 /* Must try at least 3 times according to DP spec */ 330 for (try = 0; try < 5; try++) { 331 /* Load the send data into the aux channel data registers */ 332 for (i = 0; i < send_bytes; i += 4) 333 intel_de_write(i915, ch_data[i >> 2], 334 intel_dp_aux_pack(send + i, 335 send_bytes - i)); 336 337 /* Send the command and wait for it to complete */ 338 intel_de_write(i915, ch_ctl, send_ctl); 339 340 status = intel_dp_aux_wait_done(intel_dp); 341 342 /* Clear done status and any errors */ 343 intel_de_write(i915, ch_ctl, 344 status | DP_AUX_CH_CTL_DONE | 345 DP_AUX_CH_CTL_TIME_OUT_ERROR | 346 DP_AUX_CH_CTL_RECEIVE_ERROR); 347 348 /* 349 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 350 * 400us delay required for errors and timeouts 351 * Timeout errors from the HW already meet this 352 * requirement so skip to next iteration 353 */ 354 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 355 continue; 356 357 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 358 usleep_range(400, 500); 359 continue; 360 } 361 if (status & DP_AUX_CH_CTL_DONE) 362 goto done; 363 } 364 } 365 366 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 367 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", 368 intel_dp->aux.name, status); 369 ret = -EBUSY; 370 goto out; 371 } 372 373 done: 374 /* 375 * Check for timeout or receive error. Timeouts occur when the sink is 376 * not connected. 377 */ 378 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 379 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", 380 intel_dp->aux.name, status); 381 ret = -EIO; 382 goto out; 383 } 384 385 /* 386 * Timeouts occur when the device isn't connected, so they're "normal" 387 * -- don't fill the kernel log with these 388 */ 389 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 390 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", 391 intel_dp->aux.name, status); 392 ret = -ETIMEDOUT; 393 goto out; 394 } 395 396 /* Unload any bytes sent back from the other side */ 397 recv_bytes = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, status); 398 399 /* 400 * By BSpec: "Message sizes of 0 or >20 are not allowed." 401 * We have no idea of what happened so we return -EBUSY so 402 * drm layer takes care for the necessary retries. 403 */ 404 if (recv_bytes == 0 || recv_bytes > 20) { 405 drm_dbg_kms(&i915->drm, 406 "%s: Forbidden recv_bytes = %d on aux transaction\n", 407 intel_dp->aux.name, recv_bytes); 408 ret = -EBUSY; 409 goto out; 410 } 411 412 if (recv_bytes > recv_size) 413 recv_bytes = recv_size; 414 415 for (i = 0; i < recv_bytes; i += 4) 416 intel_dp_aux_unpack(intel_de_read(i915, ch_data[i >> 2]), 417 recv + i, recv_bytes - i); 418 419 ret = recv_bytes; 420 out: 421 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 422 423 if (vdd) 424 intel_pps_vdd_off_unlocked(intel_dp, false); 425 426 intel_pps_unlock(intel_dp, pps_wakeref); 427 intel_display_power_put_async(i915, aux_domain, aux_wakeref); 428 out_unlock: 429 intel_digital_port_unlock(encoder); 430 431 return ret; 432 } 433 434 #define BARE_ADDRESS_SIZE 3 435 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 436 437 static void 438 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 439 const struct drm_dp_aux_msg *msg) 440 { 441 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 442 txbuf[1] = (msg->address >> 8) & 0xff; 443 txbuf[2] = msg->address & 0xff; 444 txbuf[3] = msg->size - 1; 445 } 446 447 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 448 { 449 /* 450 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 451 * select bit to inform the hardware to send the Aksv after our header 452 * since we can't access that data from software. 453 */ 454 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 455 msg->address == DP_AUX_HDCP_AKSV) 456 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 457 458 return 0; 459 } 460 461 static ssize_t 462 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 463 { 464 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 465 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 466 u8 txbuf[20], rxbuf[20]; 467 size_t txsize, rxsize; 468 u32 flags = intel_dp_aux_xfer_flags(msg); 469 int ret; 470 471 intel_dp_aux_header(txbuf, msg); 472 473 switch (msg->request & ~DP_AUX_I2C_MOT) { 474 case DP_AUX_NATIVE_WRITE: 475 case DP_AUX_I2C_WRITE: 476 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 477 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 478 rxsize = 2; /* 0 or 1 data bytes */ 479 480 if (drm_WARN_ON(&i915->drm, txsize > 20)) 481 return -E2BIG; 482 483 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size); 484 485 if (msg->buffer) 486 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 487 488 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 489 rxbuf, rxsize, flags); 490 if (ret > 0) { 491 msg->reply = rxbuf[0] >> 4; 492 493 if (ret > 1) { 494 /* Number of bytes written in a short write. */ 495 ret = clamp_t(int, rxbuf[1], 0, msg->size); 496 } else { 497 /* Return payload size. */ 498 ret = msg->size; 499 } 500 } 501 break; 502 503 case DP_AUX_NATIVE_READ: 504 case DP_AUX_I2C_READ: 505 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 506 rxsize = msg->size + 1; 507 508 if (drm_WARN_ON(&i915->drm, rxsize > 20)) 509 return -E2BIG; 510 511 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 512 rxbuf, rxsize, flags); 513 if (ret > 0) { 514 msg->reply = rxbuf[0] >> 4; 515 /* 516 * Assume happy day, and copy the data. The caller is 517 * expected to check msg->reply before touching it. 518 * 519 * Return payload size. 520 */ 521 ret--; 522 memcpy(msg->buffer, rxbuf + 1, ret); 523 } 524 break; 525 526 default: 527 ret = -EINVAL; 528 break; 529 } 530 531 return ret; 532 } 533 534 static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp) 535 { 536 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 537 enum aux_ch aux_ch = dig_port->aux_ch; 538 539 switch (aux_ch) { 540 case AUX_CH_B: 541 case AUX_CH_C: 542 case AUX_CH_D: 543 return VLV_DP_AUX_CH_CTL(aux_ch); 544 default: 545 MISSING_CASE(aux_ch); 546 return VLV_DP_AUX_CH_CTL(AUX_CH_B); 547 } 548 } 549 550 static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index) 551 { 552 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 553 enum aux_ch aux_ch = dig_port->aux_ch; 554 555 switch (aux_ch) { 556 case AUX_CH_B: 557 case AUX_CH_C: 558 case AUX_CH_D: 559 return VLV_DP_AUX_CH_DATA(aux_ch, index); 560 default: 561 MISSING_CASE(aux_ch); 562 return VLV_DP_AUX_CH_DATA(AUX_CH_B, index); 563 } 564 } 565 566 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 567 { 568 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 569 enum aux_ch aux_ch = dig_port->aux_ch; 570 571 switch (aux_ch) { 572 case AUX_CH_B: 573 case AUX_CH_C: 574 case AUX_CH_D: 575 return DP_AUX_CH_CTL(aux_ch); 576 default: 577 MISSING_CASE(aux_ch); 578 return DP_AUX_CH_CTL(AUX_CH_B); 579 } 580 } 581 582 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 583 { 584 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 585 enum aux_ch aux_ch = dig_port->aux_ch; 586 587 switch (aux_ch) { 588 case AUX_CH_B: 589 case AUX_CH_C: 590 case AUX_CH_D: 591 return DP_AUX_CH_DATA(aux_ch, index); 592 default: 593 MISSING_CASE(aux_ch); 594 return DP_AUX_CH_DATA(AUX_CH_B, index); 595 } 596 } 597 598 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 599 { 600 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 601 enum aux_ch aux_ch = dig_port->aux_ch; 602 603 switch (aux_ch) { 604 case AUX_CH_A: 605 return DP_AUX_CH_CTL(aux_ch); 606 case AUX_CH_B: 607 case AUX_CH_C: 608 case AUX_CH_D: 609 return PCH_DP_AUX_CH_CTL(aux_ch); 610 default: 611 MISSING_CASE(aux_ch); 612 return DP_AUX_CH_CTL(AUX_CH_A); 613 } 614 } 615 616 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 617 { 618 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 619 enum aux_ch aux_ch = dig_port->aux_ch; 620 621 switch (aux_ch) { 622 case AUX_CH_A: 623 return DP_AUX_CH_DATA(aux_ch, index); 624 case AUX_CH_B: 625 case AUX_CH_C: 626 case AUX_CH_D: 627 return PCH_DP_AUX_CH_DATA(aux_ch, index); 628 default: 629 MISSING_CASE(aux_ch); 630 return DP_AUX_CH_DATA(AUX_CH_A, index); 631 } 632 } 633 634 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 635 { 636 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 637 enum aux_ch aux_ch = dig_port->aux_ch; 638 639 switch (aux_ch) { 640 case AUX_CH_A: 641 case AUX_CH_B: 642 case AUX_CH_C: 643 case AUX_CH_D: 644 case AUX_CH_E: 645 case AUX_CH_F: 646 return DP_AUX_CH_CTL(aux_ch); 647 default: 648 MISSING_CASE(aux_ch); 649 return DP_AUX_CH_CTL(AUX_CH_A); 650 } 651 } 652 653 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 654 { 655 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 656 enum aux_ch aux_ch = dig_port->aux_ch; 657 658 switch (aux_ch) { 659 case AUX_CH_A: 660 case AUX_CH_B: 661 case AUX_CH_C: 662 case AUX_CH_D: 663 case AUX_CH_E: 664 case AUX_CH_F: 665 return DP_AUX_CH_DATA(aux_ch, index); 666 default: 667 MISSING_CASE(aux_ch); 668 return DP_AUX_CH_DATA(AUX_CH_A, index); 669 } 670 } 671 672 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 673 { 674 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 675 enum aux_ch aux_ch = dig_port->aux_ch; 676 677 switch (aux_ch) { 678 case AUX_CH_A: 679 case AUX_CH_B: 680 case AUX_CH_C: 681 case AUX_CH_USBC1: 682 case AUX_CH_USBC2: 683 case AUX_CH_USBC3: 684 case AUX_CH_USBC4: 685 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 686 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 687 return DP_AUX_CH_CTL(aux_ch); 688 default: 689 MISSING_CASE(aux_ch); 690 return DP_AUX_CH_CTL(AUX_CH_A); 691 } 692 } 693 694 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 695 { 696 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 697 enum aux_ch aux_ch = dig_port->aux_ch; 698 699 switch (aux_ch) { 700 case AUX_CH_A: 701 case AUX_CH_B: 702 case AUX_CH_C: 703 case AUX_CH_USBC1: 704 case AUX_CH_USBC2: 705 case AUX_CH_USBC3: 706 case AUX_CH_USBC4: 707 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 708 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 709 return DP_AUX_CH_DATA(aux_ch, index); 710 default: 711 MISSING_CASE(aux_ch); 712 return DP_AUX_CH_DATA(AUX_CH_A, index); 713 } 714 } 715 716 static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) 717 { 718 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 719 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 720 enum aux_ch aux_ch = dig_port->aux_ch; 721 722 switch (aux_ch) { 723 case AUX_CH_A: 724 case AUX_CH_B: 725 case AUX_CH_USBC1: 726 case AUX_CH_USBC2: 727 case AUX_CH_USBC3: 728 case AUX_CH_USBC4: 729 return XELPDP_DP_AUX_CH_CTL(i915, aux_ch); 730 default: 731 MISSING_CASE(aux_ch); 732 return XELPDP_DP_AUX_CH_CTL(i915, AUX_CH_A); 733 } 734 } 735 736 static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) 737 { 738 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 739 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 740 enum aux_ch aux_ch = dig_port->aux_ch; 741 742 switch (aux_ch) { 743 case AUX_CH_A: 744 case AUX_CH_B: 745 case AUX_CH_USBC1: 746 case AUX_CH_USBC2: 747 case AUX_CH_USBC3: 748 case AUX_CH_USBC4: 749 return XELPDP_DP_AUX_CH_DATA(i915, aux_ch, index); 750 default: 751 MISSING_CASE(aux_ch); 752 return XELPDP_DP_AUX_CH_DATA(i915, AUX_CH_A, index); 753 } 754 } 755 756 void intel_dp_aux_fini(struct intel_dp *intel_dp) 757 { 758 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 759 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 760 761 kfree(intel_dp->aux.name); 762 } 763 764 void intel_dp_aux_init(struct intel_dp *intel_dp) 765 { 766 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 767 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 768 struct intel_encoder *encoder = &dig_port->base; 769 enum aux_ch aux_ch = dig_port->aux_ch; 770 char buf[AUX_CH_NAME_BUFSIZE]; 771 772 if (DISPLAY_VER(i915) >= 14) { 773 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; 774 intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; 775 } else if (DISPLAY_VER(i915) >= 12) { 776 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 777 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 778 } else if (DISPLAY_VER(i915) >= 9) { 779 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 780 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 781 } else if (HAS_PCH_SPLIT(i915)) { 782 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 783 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 784 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 785 intel_dp->aux_ch_ctl_reg = vlv_aux_ctl_reg; 786 intel_dp->aux_ch_data_reg = vlv_aux_data_reg; 787 } else { 788 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 789 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 790 } 791 792 if (DISPLAY_VER(i915) >= 9) 793 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 794 else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) 795 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 796 else if (HAS_PCH_SPLIT(i915)) 797 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 798 else 799 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 800 801 if (DISPLAY_VER(i915) >= 9) 802 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 803 else 804 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 805 806 intel_dp->aux.drm_dev = &i915->drm; 807 drm_dp_aux_init(&intel_dp->aux); 808 809 /* Failure to allocate our preferred name is not critical */ 810 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %s/%s", 811 aux_ch_name(i915, buf, sizeof(buf), aux_ch), 812 encoder->base.name); 813 814 intel_dp->aux.transfer = intel_dp_aux_transfer; 815 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 816 } 817 818 static enum aux_ch default_aux_ch(struct intel_encoder *encoder) 819 { 820 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 821 822 /* SKL has DDI E but no AUX E */ 823 if (DISPLAY_VER(i915) == 9 && encoder->port == PORT_E) 824 return AUX_CH_A; 825 826 return (enum aux_ch)encoder->port; 827 } 828 829 static struct intel_encoder * 830 get_encoder_by_aux_ch(struct intel_encoder *encoder, 831 enum aux_ch aux_ch) 832 { 833 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 834 struct intel_encoder *other; 835 836 for_each_intel_encoder(&i915->drm, other) { 837 if (other == encoder) 838 continue; 839 840 if (!intel_encoder_is_dig_port(other)) 841 continue; 842 843 if (enc_to_dig_port(other)->aux_ch == aux_ch) 844 return other; 845 } 846 847 return NULL; 848 } 849 850 enum aux_ch intel_dp_aux_ch(struct intel_encoder *encoder) 851 { 852 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 853 struct intel_encoder *other; 854 const char *source; 855 enum aux_ch aux_ch; 856 char buf[AUX_CH_NAME_BUFSIZE]; 857 858 aux_ch = intel_bios_dp_aux_ch(encoder->devdata); 859 source = "VBT"; 860 861 if (aux_ch == AUX_CH_NONE) { 862 aux_ch = default_aux_ch(encoder); 863 source = "platform default"; 864 } 865 866 if (aux_ch == AUX_CH_NONE) 867 return AUX_CH_NONE; 868 869 /* FIXME validate aux_ch against platform caps */ 870 871 other = get_encoder_by_aux_ch(encoder, aux_ch); 872 if (other) { 873 drm_dbg_kms(&i915->drm, 874 "[ENCODER:%d:%s] AUX CH %s already claimed by [ENCODER:%d:%s]\n", 875 encoder->base.base.id, encoder->base.name, 876 aux_ch_name(i915, buf, sizeof(buf), aux_ch), 877 other->base.base.id, other->base.name); 878 return AUX_CH_NONE; 879 } 880 881 drm_dbg_kms(&i915->drm, 882 "[ENCODER:%d:%s] Using AUX CH %s (%s)\n", 883 encoder->base.base.id, encoder->base.name, 884 aux_ch_name(i915, buf, sizeof(buf), aux_ch), source); 885 886 return aux_ch; 887 } 888 889 void intel_dp_aux_irq_handler(struct drm_i915_private *i915) 890 { 891 wake_up_all(&i915->display.gmbus.wait_queue); 892 } 893