1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DP_H__ 7 #define __INTEL_DP_H__ 8 9 #include <linux/types.h> 10 11 enum intel_output_format; 12 enum pipe; 13 enum port; 14 struct drm_connector_state; 15 struct drm_dp_desc; 16 struct drm_dp_vsc_sdp; 17 struct drm_encoder; 18 struct drm_modeset_acquire_ctx; 19 struct intel_atomic_state; 20 struct intel_connector; 21 struct intel_crtc_state; 22 struct intel_digital_port; 23 struct intel_display; 24 struct intel_dp; 25 struct intel_encoder; 26 27 struct link_config_limits { 28 int min_rate, max_rate; 29 int min_lane_count, max_lane_count; 30 struct { 31 /* Uncompressed DSC input or link output bpp in 1 bpp units */ 32 int min_bpp, max_bpp; 33 } pipe; 34 struct { 35 /* Compressed or uncompressed link output bpp in 1/16 bpp units */ 36 int min_bpp_x16, max_bpp_x16; 37 } link; 38 }; 39 40 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); 41 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 42 const struct drm_connector_state *conn_state); 43 int intel_dp_min_bpp(enum intel_output_format output_format); 44 void intel_dp_init_modeset_retry_work(struct intel_connector *connector); 45 void 46 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, 47 struct intel_encoder *encoder, 48 const struct intel_crtc_state *crtc_state); 49 bool intel_dp_init_connector(struct intel_digital_port *dig_port, 50 struct intel_connector *intel_connector); 51 void intel_dp_cleanup_connector(struct intel_digital_port *dig_port, 52 struct intel_connector *connector); 53 54 void intel_dp_connector_sync_state(struct intel_connector *connector, 55 const struct intel_crtc_state *crtc_state); 56 void intel_dp_set_link_params(struct intel_dp *intel_dp, 57 int link_rate, int lane_count); 58 int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 59 struct drm_modeset_acquire_ctx *ctx, 60 u8 *pipe_mask); 61 void intel_dp_flush_connector_commits(struct intel_connector *connector); 62 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); 63 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 64 const struct intel_crtc_state *crtc_state); 65 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, 66 struct intel_connector *connector, 67 const struct intel_crtc_state *new_crtc_state); 68 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, 69 struct intel_connector *connector, 70 const struct intel_crtc_state *old_crtc_state); 71 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); 72 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder); 73 void intel_dp_encoder_flush_work(struct drm_encoder *encoder); 74 int intel_dp_compute_config(struct intel_atomic_state *state, 75 struct intel_encoder *encoder, 76 struct intel_crtc_state *pipe_config, 77 struct drm_connector_state *conn_state); 78 bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state, 79 bool dsc_enabled_on_crtc); 80 void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state); 81 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 82 struct intel_crtc_state *pipe_config, 83 struct drm_connector_state *conn_state, 84 const struct link_config_limits *limits, 85 int timeslots); 86 void intel_dp_audio_compute_config(struct intel_encoder *encoder, 87 struct intel_crtc_state *pipe_config, 88 struct drm_connector_state *conn_state); 89 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); 90 bool intel_dp_is_edp(struct intel_dp *intel_dp); 91 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); 92 bool intel_dp_has_dsc(const struct intel_connector *connector); 93 int intel_dp_link_symbol_size(int rate); 94 int intel_dp_link_symbol_clock(int rate); 95 bool intel_dp_is_port_edp(struct intel_display *display, enum port port); 96 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, 97 bool long_hpd); 98 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 99 const struct drm_connector_state *conn_state); 100 void intel_edp_backlight_off(const struct drm_connector_state *conn_state); 101 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); 102 void intel_dp_mst_suspend(struct intel_display *display); 103 void intel_dp_mst_resume(struct intel_display *display); 104 int intel_dp_rate_limit_len(const int *rates, int len, int max_rate); 105 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port); 106 int intel_dp_max_link_rate(struct intel_dp *intel_dp); 107 int intel_dp_max_lane_count(struct intel_dp *intel_dp); 108 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); 109 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); 110 int intel_dp_rate_index(const int *rates, int len, int rate); 111 void intel_dp_update_sink_caps(struct intel_dp *intel_dp); 112 void intel_dp_reset_link_params(struct intel_dp *intel_dp); 113 114 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 115 u8 *link_bw, u8 *rate_select); 116 bool intel_dp_source_supports_tps3(struct intel_display *display); 117 bool intel_dp_source_supports_tps4(struct intel_display *display); 118 119 int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, 120 int dsc_slice_count, int bpp_x16, unsigned long flags); 121 int intel_dp_link_required(int link_clock, int lane_count, 122 int mode_clock, int mode_hdisplay, 123 int link_bpp_x16, unsigned long bw_overhead_flags); 124 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 125 int bw_overhead); 126 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, 127 int max_dprx_rate, int max_dprx_lanes); 128 bool intel_dp_joiner_needs_dsc(struct intel_display *display, 129 int num_joined_pipes); 130 bool intel_dp_has_joiner(struct intel_dp *intel_dp); 131 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 132 const struct drm_connector_state *conn_state); 133 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, 134 const struct intel_crtc_state *crtc_state, 135 const struct drm_connector_state *conn_state); 136 void intel_read_dp_sdp(struct intel_encoder *encoder, 137 struct intel_crtc_state *crtc_state, 138 unsigned int type); 139 void intel_digital_port_lock(struct intel_encoder *encoder); 140 void intel_digital_port_unlock(struct intel_encoder *encoder); 141 bool intel_digital_port_connected(struct intel_encoder *encoder); 142 bool intel_digital_port_connected_locked(struct intel_encoder *encoder); 143 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 144 u8 dsc_max_bpc); 145 int intel_dp_compute_min_compressed_bpp_x16(struct intel_connector *connector, 146 enum intel_output_format output_format); 147 bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector, 148 int link_clock, int lane_count, 149 int mode_clock, int mode_hdisplay, 150 int num_joined_pipes, 151 enum intel_output_format output_format, 152 int pipe_bpp, unsigned long bw_overhead_flags); 153 bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16); 154 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 155 int mode_clock, int mode_hdisplay, 156 int num_joined_pipes); 157 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) 158 { 159 return ~((1 << lane_count) - 1) & 0xf; 160 } 161 162 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 163 const struct intel_connector *connector, 164 const struct intel_crtc_state *pipe_config); 165 u32 intel_dp_mode_to_fec_clock(u32 mode_clock); 166 int intel_dp_bw_fec_overhead(bool fec_enabled); 167 168 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 169 const struct intel_connector *connector, 170 const struct intel_crtc_state *pipe_config); 171 172 bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 173 const struct intel_connector *connector, 174 const struct intel_crtc_state *crtc_state); 175 176 void intel_ddi_update_pipe(struct intel_atomic_state *state, 177 struct intel_encoder *encoder, 178 const struct intel_crtc_state *crtc_state, 179 const struct drm_connector_state *conn_state); 180 181 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 182 struct intel_crtc_state *crtc_state); 183 void intel_dp_sync_state(struct intel_encoder *encoder, 184 const struct intel_crtc_state *crtc_state); 185 186 void intel_dp_check_frl_training(struct intel_dp *intel_dp); 187 void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 188 const struct intel_crtc_state *crtc_state); 189 190 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp); 191 void intel_dp_wait_source_oui(struct intel_dp *intel_dp); 192 int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, 193 int pipe_bpp); 194 195 bool intel_dp_compute_config_limits(struct intel_dp *intel_dp, 196 struct drm_connector_state *conn_state, 197 struct intel_crtc_state *crtc_state, 198 bool respect_downstream_limits, 199 bool dsc, 200 struct link_config_limits *limits); 201 202 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, 203 const struct drm_dp_desc *desc, bool is_branch, 204 struct intel_connector *connector); 205 bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder); 206 207 bool intel_dp_has_connector(struct intel_dp *intel_dp, 208 const struct drm_connector_state *conn_state); 209 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display); 210 int intel_dp_dsc_min_src_input_bpc(void); 211 int intel_dp_dsc_min_src_compressed_bpp(void); 212 int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, 213 const struct drm_connector_state *conn_state); 214 215 int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector); 216 void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external); 217 bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state); 218 int intel_dp_compute_config_late(struct intel_encoder *encoder, 219 struct intel_crtc_state *crtc_state, 220 struct drm_connector_state *conn_state); 221 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state, 222 bool assume_all_enabled); 223 int intel_dp_max_hdisplay_per_pipe(struct intel_display *display); 224 bool intel_dp_dotclk_valid(struct intel_display *display, 225 int target_clock, 226 int htotal, 227 int dsc_slice_count, 228 int num_joined_pipes); 229 bool intel_dp_joiner_candidate_valid(struct intel_connector *connector, 230 int hdisplay, 231 int num_joined_pipes); 232 233 #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \ 234 for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \ 235 for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes)) 236 237 u8 intel_dp_as_sdp_transmission_time(void); 238 239 int intel_dp_link_init(struct intel_dp *intel_dp); 240 void intel_dp_link_cleanup(struct intel_dp *intel_dp); 241 242 #endif /* __INTEL_DP_H__ */ 243