1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DP_H__ 7 #define __INTEL_DP_H__ 8 9 #include <linux/types.h> 10 11 enum intel_output_format; 12 enum pipe; 13 enum port; 14 struct drm_connector_state; 15 struct drm_dp_desc; 16 struct drm_dp_vsc_sdp; 17 struct drm_encoder; 18 struct drm_modeset_acquire_ctx; 19 struct intel_atomic_state; 20 struct intel_connector; 21 struct intel_crtc_state; 22 struct intel_digital_port; 23 struct intel_display; 24 struct intel_dp; 25 struct intel_encoder; 26 27 struct link_config_limits { 28 int min_rate, max_rate; 29 int min_lane_count, max_lane_count; 30 struct { 31 /* Uncompressed DSC input or link output bpp in 1 bpp units */ 32 int min_bpp, max_bpp; 33 } pipe; 34 struct { 35 /* Compressed or uncompressed link output bpp in 1/16 bpp units */ 36 int min_bpp_x16, max_bpp_x16; 37 } link; 38 }; 39 40 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); 41 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 42 const struct drm_connector_state *conn_state); 43 int intel_dp_min_bpp(enum intel_output_format output_format); 44 void intel_dp_init_modeset_retry_work(struct intel_connector *connector); 45 void 46 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, 47 struct intel_encoder *encoder, 48 const struct intel_crtc_state *crtc_state); 49 bool intel_dp_init_connector(struct intel_digital_port *dig_port, 50 struct intel_connector *intel_connector); 51 void intel_dp_connector_sync_state(struct intel_connector *connector, 52 const struct intel_crtc_state *crtc_state); 53 void intel_dp_set_link_params(struct intel_dp *intel_dp, 54 int link_rate, int lane_count); 55 int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 56 struct drm_modeset_acquire_ctx *ctx, 57 u8 *pipe_mask); 58 void intel_dp_flush_connector_commits(struct intel_connector *connector); 59 void intel_dp_link_check(struct intel_encoder *encoder); 60 void intel_dp_check_link_state(struct intel_dp *intel_dp); 61 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); 62 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 63 const struct intel_crtc_state *crtc_state); 64 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, 65 struct intel_connector *connector, 66 const struct intel_crtc_state *new_crtc_state); 67 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, 68 struct intel_connector *connector, 69 const struct intel_crtc_state *old_crtc_state); 70 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); 71 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder); 72 void intel_dp_encoder_flush_work(struct drm_encoder *encoder); 73 int intel_dp_compute_config(struct intel_encoder *encoder, 74 struct intel_crtc_state *pipe_config, 75 struct drm_connector_state *conn_state); 76 bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state, 77 bool dsc_enabled_on_crtc); 78 void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state); 79 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 80 struct intel_crtc_state *pipe_config, 81 struct drm_connector_state *conn_state, 82 const struct link_config_limits *limits, 83 int timeslots); 84 void intel_dp_audio_compute_config(struct intel_encoder *encoder, 85 struct intel_crtc_state *pipe_config, 86 struct drm_connector_state *conn_state); 87 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); 88 bool intel_dp_is_edp(struct intel_dp *intel_dp); 89 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); 90 bool intel_dp_has_dsc(const struct intel_connector *connector); 91 int intel_dp_link_symbol_size(int rate); 92 int intel_dp_link_symbol_clock(int rate); 93 bool intel_dp_is_port_edp(struct intel_display *display, enum port port); 94 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, 95 bool long_hpd); 96 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 97 const struct drm_connector_state *conn_state); 98 void intel_edp_backlight_off(const struct drm_connector_state *conn_state); 99 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); 100 void intel_dp_mst_suspend(struct intel_display *display); 101 void intel_dp_mst_resume(struct intel_display *display); 102 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port); 103 int intel_dp_max_link_rate(struct intel_dp *intel_dp); 104 int intel_dp_max_lane_count(struct intel_dp *intel_dp); 105 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); 106 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); 107 int intel_dp_max_common_rate(struct intel_dp *intel_dp); 108 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); 109 int intel_dp_common_rate(struct intel_dp *intel_dp, int index); 110 int intel_dp_rate_index(const int *rates, int len, int rate); 111 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count); 112 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count); 113 void intel_dp_update_sink_caps(struct intel_dp *intel_dp); 114 void intel_dp_reset_link_params(struct intel_dp *intel_dp); 115 116 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 117 u8 *link_bw, u8 *rate_select); 118 bool intel_dp_source_supports_tps3(struct intel_display *display); 119 bool intel_dp_source_supports_tps4(struct intel_display *display); 120 121 int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, 122 int dsc_slice_count, int bpp_x16, unsigned long flags); 123 int intel_dp_link_required(int link_clock, int lane_count, 124 int mode_clock, int mode_hdisplay, 125 int link_bpp_x16, unsigned long bw_overhead_flags); 126 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 127 int bw_overhead); 128 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, 129 int max_dprx_rate, int max_dprx_lanes); 130 bool intel_dp_joiner_needs_dsc(struct intel_display *display, 131 int num_joined_pipes); 132 bool intel_dp_has_joiner(struct intel_dp *intel_dp); 133 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 134 const struct drm_connector_state *conn_state); 135 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, 136 const struct intel_crtc_state *crtc_state, 137 const struct drm_connector_state *conn_state); 138 void intel_read_dp_sdp(struct intel_encoder *encoder, 139 struct intel_crtc_state *crtc_state, 140 unsigned int type); 141 void intel_digital_port_lock(struct intel_encoder *encoder); 142 void intel_digital_port_unlock(struct intel_encoder *encoder); 143 bool intel_digital_port_connected(struct intel_encoder *encoder); 144 bool intel_digital_port_connected_locked(struct intel_encoder *encoder); 145 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 146 u8 dsc_max_bpc); 147 int intel_dp_compute_min_compressed_bpp_x16(struct intel_connector *connector, 148 enum intel_output_format output_format); 149 bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector, 150 int link_clock, int lane_count, 151 int mode_clock, int mode_hdisplay, 152 int num_joined_pipes, 153 enum intel_output_format output_format, 154 int pipe_bpp, unsigned long bw_overhead_flags); 155 bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16); 156 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 157 int mode_clock, int mode_hdisplay, 158 int num_joined_pipes); 159 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) 160 { 161 return ~((1 << lane_count) - 1) & 0xf; 162 } 163 164 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 165 const struct intel_connector *connector, 166 const struct intel_crtc_state *pipe_config); 167 u32 intel_dp_mode_to_fec_clock(u32 mode_clock); 168 int intel_dp_bw_fec_overhead(bool fec_enabled); 169 170 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 171 const struct intel_connector *connector, 172 const struct intel_crtc_state *pipe_config); 173 174 bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 175 const struct intel_connector *connector, 176 const struct intel_crtc_state *crtc_state); 177 178 void intel_ddi_update_pipe(struct intel_atomic_state *state, 179 struct intel_encoder *encoder, 180 const struct intel_crtc_state *crtc_state, 181 const struct drm_connector_state *conn_state); 182 183 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 184 struct intel_crtc_state *crtc_state); 185 void intel_dp_sync_state(struct intel_encoder *encoder, 186 const struct intel_crtc_state *crtc_state); 187 188 void intel_dp_check_frl_training(struct intel_dp *intel_dp); 189 void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 190 const struct intel_crtc_state *crtc_state); 191 192 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp); 193 void intel_dp_wait_source_oui(struct intel_dp *intel_dp); 194 int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, 195 int pipe_bpp); 196 197 bool intel_dp_compute_config_limits(struct intel_dp *intel_dp, 198 struct drm_connector_state *conn_state, 199 struct intel_crtc_state *crtc_state, 200 bool respect_downstream_limits, 201 bool dsc, 202 struct link_config_limits *limits); 203 204 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, 205 const struct drm_dp_desc *desc, bool is_branch, 206 struct intel_connector *connector); 207 bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder); 208 209 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 210 u8 lane_count); 211 bool intel_dp_has_connector(struct intel_dp *intel_dp, 212 const struct drm_connector_state *conn_state); 213 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display); 214 int intel_dp_dsc_min_src_input_bpc(void); 215 int intel_dp_dsc_min_src_compressed_bpp(void); 216 int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, 217 const struct drm_connector_state *conn_state); 218 219 int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector); 220 void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external); 221 bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state); 222 int intel_dp_compute_config_late(struct intel_encoder *encoder, 223 struct intel_crtc_state *crtc_state, 224 struct drm_connector_state *conn_state); 225 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state, 226 bool assume_all_enabled); 227 int intel_dp_max_hdisplay_per_pipe(struct intel_display *display); 228 bool intel_dp_dotclk_valid(struct intel_display *display, 229 int target_clock, 230 int htotal, 231 int dsc_slice_count, 232 int num_joined_pipes); 233 bool intel_dp_joiner_candidate_valid(struct intel_connector *connector, 234 int hdisplay, 235 int num_joined_pipes); 236 237 #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \ 238 for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \ 239 for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes)) 240 241 #endif /* __INTEL_DP_H__ */ 242