1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DP_H__ 7 #define __INTEL_DP_H__ 8 9 #include <linux/types.h> 10 11 enum intel_output_format; 12 enum pipe; 13 enum port; 14 struct drm_connector_state; 15 struct drm_dp_desc; 16 struct drm_dp_vsc_sdp; 17 struct drm_encoder; 18 struct drm_modeset_acquire_ctx; 19 struct intel_atomic_state; 20 struct intel_connector; 21 struct intel_crtc_state; 22 struct intel_digital_port; 23 struct intel_display; 24 struct intel_dp; 25 struct intel_encoder; 26 27 struct link_config_limits { 28 int min_rate, max_rate; 29 int min_lane_count, max_lane_count; 30 struct { 31 /* Uncompressed DSC input or link output bpp in 1 bpp units */ 32 int min_bpp, max_bpp; 33 } pipe; 34 struct { 35 /* Compressed or uncompressed link output bpp in 1/16 bpp units */ 36 int min_bpp_x16, max_bpp_x16; 37 } link; 38 }; 39 40 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); 41 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 42 const struct drm_connector_state *conn_state); 43 int intel_dp_min_bpp(enum intel_output_format output_format); 44 void intel_dp_init_modeset_retry_work(struct intel_connector *connector); 45 void 46 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, 47 struct intel_encoder *encoder, 48 const struct intel_crtc_state *crtc_state); 49 bool intel_dp_init_connector(struct intel_digital_port *dig_port, 50 struct intel_connector *intel_connector); 51 void intel_dp_cleanup_connector(struct intel_digital_port *dig_port, 52 struct intel_connector *connector); 53 54 void intel_dp_connector_sync_state(struct intel_connector *connector, 55 const struct intel_crtc_state *crtc_state); 56 void intel_dp_set_link_params(struct intel_dp *intel_dp, 57 int link_rate, int lane_count); 58 int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 59 struct drm_modeset_acquire_ctx *ctx, 60 u8 *pipe_mask); 61 void intel_dp_flush_connector_commits(struct intel_connector *connector); 62 void intel_dp_link_check(struct intel_encoder *encoder); 63 void intel_dp_check_link_state(struct intel_dp *intel_dp); 64 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); 65 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 66 const struct intel_crtc_state *crtc_state); 67 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, 68 struct intel_connector *connector, 69 const struct intel_crtc_state *new_crtc_state); 70 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, 71 struct intel_connector *connector, 72 const struct intel_crtc_state *old_crtc_state); 73 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); 74 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder); 75 void intel_dp_encoder_flush_work(struct drm_encoder *encoder); 76 int intel_dp_compute_config(struct intel_encoder *encoder, 77 struct intel_crtc_state *pipe_config, 78 struct drm_connector_state *conn_state); 79 bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state, 80 bool dsc_enabled_on_crtc); 81 void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state); 82 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 83 struct intel_crtc_state *pipe_config, 84 struct drm_connector_state *conn_state, 85 const struct link_config_limits *limits, 86 int timeslots); 87 void intel_dp_audio_compute_config(struct intel_encoder *encoder, 88 struct intel_crtc_state *pipe_config, 89 struct drm_connector_state *conn_state); 90 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); 91 bool intel_dp_is_edp(struct intel_dp *intel_dp); 92 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); 93 bool intel_dp_has_dsc(const struct intel_connector *connector); 94 int intel_dp_link_symbol_size(int rate); 95 int intel_dp_link_symbol_clock(int rate); 96 bool intel_dp_is_port_edp(struct intel_display *display, enum port port); 97 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, 98 bool long_hpd); 99 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 100 const struct drm_connector_state *conn_state); 101 void intel_edp_backlight_off(const struct drm_connector_state *conn_state); 102 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); 103 void intel_dp_mst_suspend(struct intel_display *display); 104 void intel_dp_mst_resume(struct intel_display *display); 105 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port); 106 int intel_dp_max_link_rate(struct intel_dp *intel_dp); 107 int intel_dp_max_lane_count(struct intel_dp *intel_dp); 108 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); 109 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); 110 int intel_dp_max_common_rate(struct intel_dp *intel_dp); 111 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); 112 int intel_dp_common_rate(struct intel_dp *intel_dp, int index); 113 int intel_dp_rate_index(const int *rates, int len, int rate); 114 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count); 115 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count); 116 void intel_dp_update_sink_caps(struct intel_dp *intel_dp); 117 void intel_dp_reset_link_params(struct intel_dp *intel_dp); 118 119 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 120 u8 *link_bw, u8 *rate_select); 121 bool intel_dp_source_supports_tps3(struct intel_display *display); 122 bool intel_dp_source_supports_tps4(struct intel_display *display); 123 124 int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, 125 int dsc_slice_count, int bpp_x16, unsigned long flags); 126 int intel_dp_link_required(int link_clock, int lane_count, 127 int mode_clock, int mode_hdisplay, 128 int link_bpp_x16, unsigned long bw_overhead_flags); 129 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 130 int bw_overhead); 131 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, 132 int max_dprx_rate, int max_dprx_lanes); 133 bool intel_dp_joiner_needs_dsc(struct intel_display *display, 134 int num_joined_pipes); 135 bool intel_dp_has_joiner(struct intel_dp *intel_dp); 136 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 137 const struct drm_connector_state *conn_state); 138 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, 139 const struct intel_crtc_state *crtc_state, 140 const struct drm_connector_state *conn_state); 141 void intel_read_dp_sdp(struct intel_encoder *encoder, 142 struct intel_crtc_state *crtc_state, 143 unsigned int type); 144 void intel_digital_port_lock(struct intel_encoder *encoder); 145 void intel_digital_port_unlock(struct intel_encoder *encoder); 146 bool intel_digital_port_connected(struct intel_encoder *encoder); 147 bool intel_digital_port_connected_locked(struct intel_encoder *encoder); 148 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 149 u8 dsc_max_bpc); 150 int intel_dp_compute_min_compressed_bpp_x16(struct intel_connector *connector, 151 enum intel_output_format output_format); 152 bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector, 153 int link_clock, int lane_count, 154 int mode_clock, int mode_hdisplay, 155 int num_joined_pipes, 156 enum intel_output_format output_format, 157 int pipe_bpp, unsigned long bw_overhead_flags); 158 bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16); 159 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 160 int mode_clock, int mode_hdisplay, 161 int num_joined_pipes); 162 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) 163 { 164 return ~((1 << lane_count) - 1) & 0xf; 165 } 166 167 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 168 const struct intel_connector *connector, 169 const struct intel_crtc_state *pipe_config); 170 u32 intel_dp_mode_to_fec_clock(u32 mode_clock); 171 int intel_dp_bw_fec_overhead(bool fec_enabled); 172 173 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 174 const struct intel_connector *connector, 175 const struct intel_crtc_state *pipe_config); 176 177 bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 178 const struct intel_connector *connector, 179 const struct intel_crtc_state *crtc_state); 180 181 void intel_ddi_update_pipe(struct intel_atomic_state *state, 182 struct intel_encoder *encoder, 183 const struct intel_crtc_state *crtc_state, 184 const struct drm_connector_state *conn_state); 185 186 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 187 struct intel_crtc_state *crtc_state); 188 void intel_dp_sync_state(struct intel_encoder *encoder, 189 const struct intel_crtc_state *crtc_state); 190 191 void intel_dp_check_frl_training(struct intel_dp *intel_dp); 192 void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 193 const struct intel_crtc_state *crtc_state); 194 195 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp); 196 void intel_dp_wait_source_oui(struct intel_dp *intel_dp); 197 int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, 198 int pipe_bpp); 199 200 bool intel_dp_compute_config_limits(struct intel_dp *intel_dp, 201 struct drm_connector_state *conn_state, 202 struct intel_crtc_state *crtc_state, 203 bool respect_downstream_limits, 204 bool dsc, 205 struct link_config_limits *limits); 206 207 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, 208 const struct drm_dp_desc *desc, bool is_branch, 209 struct intel_connector *connector); 210 bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder); 211 212 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 213 u8 lane_count); 214 bool intel_dp_has_connector(struct intel_dp *intel_dp, 215 const struct drm_connector_state *conn_state); 216 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display); 217 int intel_dp_dsc_min_src_input_bpc(void); 218 int intel_dp_dsc_min_src_compressed_bpp(void); 219 int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, 220 const struct drm_connector_state *conn_state); 221 222 int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector); 223 void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external); 224 bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state); 225 int intel_dp_compute_config_late(struct intel_encoder *encoder, 226 struct intel_crtc_state *crtc_state, 227 struct drm_connector_state *conn_state); 228 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state, 229 bool assume_all_enabled); 230 int intel_dp_max_hdisplay_per_pipe(struct intel_display *display); 231 bool intel_dp_dotclk_valid(struct intel_display *display, 232 int target_clock, 233 int htotal, 234 int dsc_slice_count, 235 int num_joined_pipes); 236 bool intel_dp_joiner_candidate_valid(struct intel_connector *connector, 237 int hdisplay, 238 int num_joined_pipes); 239 240 #define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \ 241 for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \ 242 for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes)) 243 244 u8 intel_dp_as_sdp_transmission_time(void); 245 246 #endif /* __INTEL_DP_H__ */ 247