xref: /linux/drivers/gpu/drm/i915/display/intel_dp.h (revision 36f353a1ebf88280f58d1ebfe2731251d9159456)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __INTEL_DP_H__
7 #define __INTEL_DP_H__
8 
9 #include <linux/types.h>
10 
11 enum intel_output_format;
12 enum pipe;
13 enum port;
14 struct drm_connector_state;
15 struct drm_encoder;
16 struct drm_i915_private;
17 struct drm_modeset_acquire_ctx;
18 struct drm_dp_vsc_sdp;
19 struct intel_atomic_state;
20 struct intel_connector;
21 struct intel_crtc_state;
22 struct intel_digital_port;
23 struct intel_dp;
24 struct intel_encoder;
25 
26 struct link_config_limits {
27 	int min_rate, max_rate;
28 	int min_lane_count, max_lane_count;
29 	struct {
30 		/* Uncompressed DSC input or link output bpp in 1 bpp units */
31 		int min_bpp, max_bpp;
32 	} pipe;
33 	struct {
34 		/* Compressed or uncompressed link output bpp in 1/16 bpp units */
35 		int min_bpp_x16, max_bpp_x16;
36 	} link;
37 };
38 
39 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
40 void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
41 				       struct intel_crtc_state *pipe_config,
42 				       struct link_config_limits *limits);
43 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
44 				  const struct drm_connector_state *conn_state);
45 int intel_dp_min_bpp(enum intel_output_format output_format);
46 void intel_dp_init_modeset_retry_work(struct intel_connector *connector);
47 void intel_dp_queue_modeset_retry_work(struct intel_connector *connector);
48 void
49 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
50 				      struct intel_encoder *encoder,
51 				      const struct intel_crtc_state *crtc_state);
52 bool intel_dp_init_connector(struct intel_digital_port *dig_port,
53 			     struct intel_connector *intel_connector);
54 void intel_dp_connector_sync_state(struct intel_connector *connector,
55 				   const struct intel_crtc_state *crtc_state);
56 void intel_dp_set_link_params(struct intel_dp *intel_dp,
57 			      int link_rate, int lane_count);
58 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
59 					    int link_rate, u8 lane_count);
60 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
61 			      struct drm_modeset_acquire_ctx *ctx,
62 			      u8 *pipe_mask);
63 int intel_dp_retrain_link(struct intel_encoder *encoder,
64 			  struct drm_modeset_acquire_ctx *ctx);
65 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
66 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
67 					   const struct intel_crtc_state *crtc_state);
68 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
69 					struct intel_connector *connector,
70 					const struct intel_crtc_state *new_crtc_state);
71 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
72 					 struct intel_connector *connector,
73 					 const struct intel_crtc_state *old_crtc_state);
74 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
75 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);
76 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
77 int intel_dp_compute_config(struct intel_encoder *encoder,
78 			    struct intel_crtc_state *pipe_config,
79 			    struct drm_connector_state *conn_state);
80 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
81 				struct intel_crtc_state *pipe_config,
82 				struct drm_connector_state *conn_state,
83 				struct link_config_limits *limits,
84 				int timeslots,
85 				bool recompute_pipe_bpp);
86 void intel_dp_audio_compute_config(struct intel_encoder *encoder,
87 				   struct intel_crtc_state *pipe_config,
88 				   struct drm_connector_state *conn_state);
89 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
90 bool intel_dp_is_edp(struct intel_dp *intel_dp);
91 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
92 int intel_dp_link_symbol_size(int rate);
93 int intel_dp_link_symbol_clock(int rate);
94 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
95 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
96 				  bool long_hpd);
97 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
98 			    const struct drm_connector_state *conn_state);
99 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
100 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
101 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
102 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
103 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
104 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
105 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);
106 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
107 int intel_dp_max_common_rate(struct intel_dp *intel_dp);
108 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp);
109 void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
110 
111 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
112 			   u8 *link_bw, u8 *rate_select);
113 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915);
114 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);
115 
116 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
117 int intel_dp_link_required(int pixel_clock, int bpp);
118 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
119 				 int bw_overhead);
120 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
121 				int max_dprx_rate, int max_dprx_lanes);
122 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
123 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
124 			    const struct drm_connector_state *conn_state);
125 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
126 			     const struct intel_crtc_state *crtc_state,
127 			     const struct drm_connector_state *conn_state);
128 void intel_read_dp_sdp(struct intel_encoder *encoder,
129 		       struct intel_crtc_state *crtc_state,
130 		       unsigned int type);
131 void intel_digital_port_lock(struct intel_encoder *encoder);
132 void intel_digital_port_unlock(struct intel_encoder *encoder);
133 bool intel_digital_port_connected(struct intel_encoder *encoder);
134 bool intel_digital_port_connected_locked(struct intel_encoder *encoder);
135 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
136 				 u8 dsc_max_bpc);
137 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
138 					u32 link_clock, u32 lane_count,
139 					u32 mode_clock, u32 mode_hdisplay,
140 					bool bigjoiner,
141 					enum intel_output_format output_format,
142 					u32 pipe_bpp,
143 					u32 timeslots);
144 int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
145 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
146 					 struct intel_crtc_state *pipe_config,
147 					 int bpc);
148 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
149 				int mode_clock, int mode_hdisplay,
150 				bool bigjoiner);
151 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
152 			     int hdisplay, int clock);
153 
154 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
155 {
156 	return ~((1 << lane_count) - 1) & 0xf;
157 }
158 
159 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
160 			   const struct intel_connector *connector,
161 			   const struct intel_crtc_state *pipe_config);
162 u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
163 int intel_dp_bw_fec_overhead(bool fec_enabled);
164 
165 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
166 			   const struct intel_connector *connector,
167 			   const struct intel_crtc_state *pipe_config);
168 
169 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
170 
171 void intel_ddi_update_pipe(struct intel_atomic_state *state,
172 			   struct intel_encoder *encoder,
173 			   const struct intel_crtc_state *crtc_state,
174 			   const struct drm_connector_state *conn_state);
175 
176 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
177 				    struct intel_crtc_state *crtc_state);
178 void intel_dp_sync_state(struct intel_encoder *encoder,
179 			 const struct intel_crtc_state *crtc_state);
180 
181 void intel_dp_check_frl_training(struct intel_dp *intel_dp);
182 void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
183 				 const struct intel_crtc_state *crtc_state);
184 void intel_dp_phy_test(struct intel_encoder *encoder);
185 
186 void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
187 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
188 
189 bool
190 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
191 					const struct intel_crtc_state *crtc_state,
192 					bool dsc,
193 					struct link_config_limits *limits);
194 
195 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
196 
197 #endif /* __INTEL_DP_H__ */
198