1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DP_H__ 7 #define __INTEL_DP_H__ 8 9 #include <linux/types.h> 10 11 enum intel_output_format; 12 enum pipe; 13 enum port; 14 struct drm_connector_state; 15 struct drm_encoder; 16 struct drm_i915_private; 17 struct drm_modeset_acquire_ctx; 18 struct drm_dp_vsc_sdp; 19 struct intel_atomic_state; 20 struct intel_connector; 21 struct intel_crtc_state; 22 struct intel_digital_port; 23 struct intel_dp; 24 struct intel_encoder; 25 26 struct link_config_limits { 27 int min_rate, max_rate; 28 int min_lane_count, max_lane_count; 29 struct { 30 /* Uncompressed DSC input or link output bpp in 1 bpp units */ 31 int min_bpp, max_bpp; 32 } pipe; 33 struct { 34 /* Compressed or uncompressed link output bpp in 1/16 bpp units */ 35 int min_bpp_x16, max_bpp_x16; 36 } link; 37 }; 38 39 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); 40 void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, 41 struct intel_crtc_state *pipe_config, 42 struct link_config_limits *limits); 43 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 44 const struct drm_connector_state *conn_state); 45 int intel_dp_min_bpp(enum intel_output_format output_format); 46 bool intel_dp_init_connector(struct intel_digital_port *dig_port, 47 struct intel_connector *intel_connector); 48 void intel_dp_set_link_params(struct intel_dp *intel_dp, 49 int link_rate, int lane_count); 50 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 51 int link_rate, u8 lane_count); 52 int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 53 struct drm_modeset_acquire_ctx *ctx, 54 u8 *pipe_mask); 55 int intel_dp_retrain_link(struct intel_encoder *encoder, 56 struct drm_modeset_acquire_ctx *ctx); 57 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); 58 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 59 const struct intel_crtc_state *crtc_state); 60 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, 61 struct intel_connector *connector, 62 const struct intel_crtc_state *new_crtc_state); 63 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, 64 struct intel_connector *connector, 65 const struct intel_crtc_state *old_crtc_state); 66 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); 67 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder); 68 void intel_dp_encoder_flush_work(struct drm_encoder *encoder); 69 int intel_dp_compute_config(struct intel_encoder *encoder, 70 struct intel_crtc_state *pipe_config, 71 struct drm_connector_state *conn_state); 72 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 73 struct intel_crtc_state *pipe_config, 74 struct drm_connector_state *conn_state, 75 struct link_config_limits *limits, 76 int timeslots, 77 bool recompute_pipe_bpp); 78 void intel_dp_audio_compute_config(struct intel_encoder *encoder, 79 struct intel_crtc_state *pipe_config, 80 struct drm_connector_state *conn_state); 81 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); 82 bool intel_dp_is_edp(struct intel_dp *intel_dp); 83 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); 84 int intel_dp_link_symbol_size(int rate); 85 int intel_dp_link_symbol_clock(int rate); 86 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); 87 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, 88 bool long_hpd); 89 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 90 const struct drm_connector_state *conn_state); 91 void intel_edp_backlight_off(const struct drm_connector_state *conn_state); 92 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); 93 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv); 94 void intel_dp_mst_resume(struct drm_i915_private *dev_priv); 95 int intel_dp_max_link_rate(struct intel_dp *intel_dp); 96 int intel_dp_max_lane_count(struct intel_dp *intel_dp); 97 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); 98 99 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 100 u8 *link_bw, u8 *rate_select); 101 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915); 102 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915); 103 104 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp); 105 int intel_dp_link_required(int pixel_clock, int bpp); 106 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 107 int bw_overhead); 108 int intel_dp_max_data_rate(int max_link_rate, int max_lanes); 109 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp); 110 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 111 const struct drm_connector_state *conn_state); 112 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, 113 const struct intel_crtc_state *crtc_state, 114 const struct drm_connector_state *conn_state, 115 struct drm_dp_vsc_sdp *vsc); 116 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, 117 const struct intel_crtc_state *crtc_state, 118 const struct drm_dp_vsc_sdp *vsc); 119 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, 120 const struct intel_crtc_state *crtc_state, 121 const struct drm_connector_state *conn_state); 122 void intel_read_dp_sdp(struct intel_encoder *encoder, 123 struct intel_crtc_state *crtc_state, 124 unsigned int type); 125 bool intel_digital_port_connected(struct intel_encoder *encoder); 126 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 127 u8 dsc_max_bpc); 128 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, 129 u32 link_clock, u32 lane_count, 130 u32 mode_clock, u32 mode_hdisplay, 131 bool bigjoiner, 132 enum intel_output_format output_format, 133 u32 pipe_bpp, 134 u32 timeslots); 135 int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config); 136 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, 137 struct intel_crtc_state *pipe_config, 138 int bpc); 139 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 140 int mode_clock, int mode_hdisplay, 141 bool bigjoiner); 142 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, 143 int hdisplay, int clock); 144 145 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) 146 { 147 return ~((1 << lane_count) - 1) & 0xf; 148 } 149 150 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 151 const struct intel_connector *connector, 152 const struct intel_crtc_state *pipe_config); 153 u32 intel_dp_mode_to_fec_clock(u32 mode_clock); 154 int intel_dp_bw_fec_overhead(bool fec_enabled); 155 156 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 157 const struct intel_connector *connector, 158 const struct intel_crtc_state *pipe_config); 159 160 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp); 161 162 void intel_ddi_update_pipe(struct intel_atomic_state *state, 163 struct intel_encoder *encoder, 164 const struct intel_crtc_state *crtc_state, 165 const struct drm_connector_state *conn_state); 166 167 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 168 struct intel_crtc_state *crtc_state); 169 void intel_dp_sync_state(struct intel_encoder *encoder, 170 const struct intel_crtc_state *crtc_state); 171 172 void intel_dp_check_frl_training(struct intel_dp *intel_dp); 173 void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 174 const struct intel_crtc_state *crtc_state); 175 void intel_dp_phy_test(struct intel_encoder *encoder); 176 177 void intel_dp_wait_source_oui(struct intel_dp *intel_dp); 178 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp); 179 180 bool 181 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, 182 const struct intel_crtc_state *crtc_state, 183 bool dsc, 184 struct link_config_limits *limits); 185 186 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector); 187 188 #endif /* __INTEL_DP_H__ */ 189