1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/export.h> 29 #include <linux/i2c.h> 30 #include <linux/notifier.h> 31 #include <linux/seq_buf.h> 32 #include <linux/slab.h> 33 #include <linux/sort.h> 34 #include <linux/string_helpers.h> 35 #include <linux/timekeeping.h> 36 #include <linux/types.h> 37 38 #include <asm/byteorder.h> 39 40 #include <drm/display/drm_dp_helper.h> 41 #include <drm/display/drm_dp_tunnel.h> 42 #include <drm/display/drm_dsc_helper.h> 43 #include <drm/display/drm_hdmi_helper.h> 44 #include <drm/drm_atomic_helper.h> 45 #include <drm/drm_crtc.h> 46 #include <drm/drm_edid.h> 47 #include <drm/drm_fixed.h> 48 #include <drm/drm_probe_helper.h> 49 50 #include "g4x_dp.h" 51 #include "i915_drv.h" 52 #include "i915_irq.h" 53 #include "i915_reg.h" 54 #include "intel_alpm.h" 55 #include "intel_atomic.h" 56 #include "intel_audio.h" 57 #include "intel_backlight.h" 58 #include "intel_combo_phy_regs.h" 59 #include "intel_connector.h" 60 #include "intel_crtc.h" 61 #include "intel_cx0_phy.h" 62 #include "intel_ddi.h" 63 #include "intel_de.h" 64 #include "intel_display_driver.h" 65 #include "intel_display_types.h" 66 #include "intel_dp.h" 67 #include "intel_dp_aux.h" 68 #include "intel_dp_hdcp.h" 69 #include "intel_dp_link_training.h" 70 #include "intel_dp_mst.h" 71 #include "intel_dp_test.h" 72 #include "intel_dp_tunnel.h" 73 #include "intel_dpio_phy.h" 74 #include "intel_dpll.h" 75 #include "intel_drrs.h" 76 #include "intel_encoder.h" 77 #include "intel_fifo_underrun.h" 78 #include "intel_hdcp.h" 79 #include "intel_hdmi.h" 80 #include "intel_hotplug.h" 81 #include "intel_hotplug_irq.h" 82 #include "intel_lspcon.h" 83 #include "intel_lvds.h" 84 #include "intel_modeset_lock.h" 85 #include "intel_panel.h" 86 #include "intel_pch_display.h" 87 #include "intel_pfit.h" 88 #include "intel_pps.h" 89 #include "intel_psr.h" 90 #include "intel_runtime_pm.h" 91 #include "intel_quirks.h" 92 #include "intel_tc.h" 93 #include "intel_vdsc.h" 94 #include "intel_vrr.h" 95 #include "intel_crtc_state_dump.h" 96 97 /* DP DSC throughput values used for slice count calculations KPixels/s */ 98 #define DP_DSC_PEAK_PIXEL_RATE 2720000 99 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 100 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 101 102 /* Max DSC line buffer depth supported by HW. */ 103 #define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13 104 105 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ 106 #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530 107 108 /* Constants for DP DSC configurations */ 109 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 110 111 /* 112 * With Single pipe configuration, HW is capable of supporting maximum of: 113 * 2 slices per line for ICL, BMG 114 * 4 slices per line for other platforms. 115 * For now consider a max of 2 slices per line, which works for all platforms. 116 * With this we can have max of 4 DSC Slices per pipe. 117 * 118 * For higher resolutions where 12 slice support is required with 119 * ultrajoiner, only then each pipe can support 3 slices. 120 * 121 * #TODO Split this better to use 4 slices/dsc engine where supported. 122 */ 123 static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4}; 124 125 /** 126 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 127 * @intel_dp: DP struct 128 * 129 * If a CPU or PCH DP output is attached to an eDP panel, this function 130 * will return true, and false otherwise. 131 * 132 * This function is not safe to use prior to encoder type being set. 133 */ 134 bool intel_dp_is_edp(struct intel_dp *intel_dp) 135 { 136 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 137 138 return dig_port->base.type == INTEL_OUTPUT_EDP; 139 } 140 141 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 142 143 /* Is link rate UHBR and thus 128b/132b? */ 144 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) 145 { 146 return drm_dp_is_uhbr_rate(crtc_state->port_clock); 147 } 148 149 /** 150 * intel_dp_link_symbol_size - get the link symbol size for a given link rate 151 * @rate: link rate in 10kbit/s units 152 * 153 * Returns the link symbol size in bits/symbol units depending on the link 154 * rate -> channel coding. 155 */ 156 int intel_dp_link_symbol_size(int rate) 157 { 158 return drm_dp_is_uhbr_rate(rate) ? 32 : 10; 159 } 160 161 /** 162 * intel_dp_link_symbol_clock - convert link rate to link symbol clock 163 * @rate: link rate in 10kbit/s units 164 * 165 * Returns the link symbol clock frequency in kHz units depending on the 166 * link rate and channel coding. 167 */ 168 int intel_dp_link_symbol_clock(int rate) 169 { 170 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate)); 171 } 172 173 static int max_dprx_rate(struct intel_dp *intel_dp) 174 { 175 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 176 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); 177 178 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 179 } 180 181 static int max_dprx_lane_count(struct intel_dp *intel_dp) 182 { 183 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 184 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel); 185 186 return drm_dp_max_lane_count(intel_dp->dpcd); 187 } 188 189 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) 190 { 191 intel_dp->sink_rates[0] = 162000; 192 intel_dp->num_sink_rates = 1; 193 } 194 195 /* update sink rates from dpcd */ 196 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) 197 { 198 static const int dp_rates[] = { 199 162000, 270000, 540000, 810000 200 }; 201 int i, max_rate; 202 int max_lttpr_rate; 203 204 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { 205 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ 206 static const int quirk_rates[] = { 162000, 270000, 324000 }; 207 208 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); 209 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); 210 211 return; 212 } 213 214 /* 215 * Sink rates for 8b/10b. 216 */ 217 max_rate = max_dprx_rate(intel_dp); 218 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); 219 if (max_lttpr_rate) 220 max_rate = min(max_rate, max_lttpr_rate); 221 222 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { 223 if (dp_rates[i] > max_rate) 224 break; 225 intel_dp->sink_rates[i] = dp_rates[i]; 226 } 227 228 /* 229 * Sink rates for 128b/132b. If set, sink should support all 8b/10b 230 * rates and 10 Gbps. 231 */ 232 if (drm_dp_128b132b_supported(intel_dp->dpcd)) { 233 u8 uhbr_rates = 0; 234 235 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); 236 237 drm_dp_dpcd_readb(&intel_dp->aux, 238 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates); 239 240 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) { 241 /* We have a repeater */ 242 if (intel_dp->lttpr_common_caps[0] >= 0x20 && 243 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 244 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] & 245 DP_PHY_REPEATER_128B132B_SUPPORTED) { 246 /* Repeater supports 128b/132b, valid UHBR rates */ 247 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES - 248 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 249 } else { 250 /* Does not support 128b/132b */ 251 uhbr_rates = 0; 252 } 253 } 254 255 if (uhbr_rates & DP_UHBR10) 256 intel_dp->sink_rates[i++] = 1000000; 257 if (uhbr_rates & DP_UHBR13_5) 258 intel_dp->sink_rates[i++] = 1350000; 259 if (uhbr_rates & DP_UHBR20) 260 intel_dp->sink_rates[i++] = 2000000; 261 } 262 263 intel_dp->num_sink_rates = i; 264 } 265 266 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 267 { 268 struct intel_display *display = to_intel_display(intel_dp); 269 struct intel_connector *connector = intel_dp->attached_connector; 270 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 271 struct intel_encoder *encoder = &intel_dig_port->base; 272 273 intel_dp_set_dpcd_sink_rates(intel_dp); 274 275 if (intel_dp->num_sink_rates) 276 return; 277 278 drm_err(display->drm, 279 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", 280 connector->base.base.id, connector->base.name, 281 encoder->base.base.id, encoder->base.name); 282 283 intel_dp_set_default_sink_rates(intel_dp); 284 } 285 286 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp) 287 { 288 intel_dp->max_sink_lane_count = 1; 289 } 290 291 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp) 292 { 293 struct intel_display *display = to_intel_display(intel_dp); 294 struct intel_connector *connector = intel_dp->attached_connector; 295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 296 struct intel_encoder *encoder = &intel_dig_port->base; 297 298 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp); 299 300 switch (intel_dp->max_sink_lane_count) { 301 case 1: 302 case 2: 303 case 4: 304 return; 305 } 306 307 drm_err(display->drm, 308 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", 309 connector->base.base.id, connector->base.name, 310 encoder->base.base.id, encoder->base.name, 311 intel_dp->max_sink_lane_count); 312 313 intel_dp_set_default_max_sink_lane_count(intel_dp); 314 } 315 316 /* Get length of rates array potentially limited by max_rate. */ 317 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) 318 { 319 int i; 320 321 /* Limit results by potentially reduced max rate */ 322 for (i = 0; i < len; i++) { 323 if (rates[len - i - 1] <= max_rate) 324 return len - i; 325 } 326 327 return 0; 328 } 329 330 /* Get length of common rates array potentially limited by max_rate. */ 331 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, 332 int max_rate) 333 { 334 return intel_dp_rate_limit_len(intel_dp->common_rates, 335 intel_dp->num_common_rates, max_rate); 336 } 337 338 int intel_dp_common_rate(struct intel_dp *intel_dp, int index) 339 { 340 struct intel_display *display = to_intel_display(intel_dp); 341 342 if (drm_WARN_ON(display->drm, 343 index < 0 || index >= intel_dp->num_common_rates)) 344 return 162000; 345 346 return intel_dp->common_rates[index]; 347 } 348 349 /* Theoretical max between source and sink */ 350 int intel_dp_max_common_rate(struct intel_dp *intel_dp) 351 { 352 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); 353 } 354 355 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) 356 { 357 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); 358 int max_lanes = dig_port->max_lanes; 359 360 if (vbt_max_lanes) 361 max_lanes = min(max_lanes, vbt_max_lanes); 362 363 return max_lanes; 364 } 365 366 /* Theoretical max between source and sink */ 367 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) 368 { 369 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 370 int source_max = intel_dp_max_source_lane_count(dig_port); 371 int sink_max = intel_dp->max_sink_lane_count; 372 int lane_max = intel_tc_port_max_lane_count(dig_port); 373 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); 374 375 if (lttpr_max) 376 sink_max = min(sink_max, lttpr_max); 377 378 return min3(source_max, sink_max, lane_max); 379 } 380 381 static int forced_lane_count(struct intel_dp *intel_dp) 382 { 383 return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp)); 384 } 385 386 int intel_dp_max_lane_count(struct intel_dp *intel_dp) 387 { 388 int lane_count; 389 390 if (intel_dp->link.force_lane_count) 391 lane_count = forced_lane_count(intel_dp); 392 else 393 lane_count = intel_dp->link.max_lane_count; 394 395 switch (lane_count) { 396 case 1: 397 case 2: 398 case 4: 399 return lane_count; 400 default: 401 MISSING_CASE(lane_count); 402 return 1; 403 } 404 } 405 406 static int intel_dp_min_lane_count(struct intel_dp *intel_dp) 407 { 408 if (intel_dp->link.force_lane_count) 409 return forced_lane_count(intel_dp); 410 411 return 1; 412 } 413 414 /* 415 * The required data bandwidth for a mode with given pixel clock and bpp. This 416 * is the required net bandwidth independent of the data bandwidth efficiency. 417 * 418 * TODO: check if callers of this functions should use 419 * intel_dp_effective_data_rate() instead. 420 */ 421 int 422 intel_dp_link_required(int pixel_clock, int bpp) 423 { 424 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 425 return DIV_ROUND_UP(pixel_clock * bpp, 8); 426 } 427 428 /** 429 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead 430 * @pixel_clock: pixel clock in kHz 431 * @bpp_x16: bits per pixel .4 fixed point format 432 * @bw_overhead: BW allocation overhead in 1ppm units 433 * 434 * Return the effective pixel data rate in kB/sec units taking into account 435 * the provided SSC, FEC, DSC BW allocation overhead. 436 */ 437 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 438 int bw_overhead) 439 { 440 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead), 441 1000000 * 16 * 8); 442 } 443 444 /** 445 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params 446 * @intel_dp: Intel DP object 447 * @max_dprx_rate: Maximum data rate of the DPRX 448 * @max_dprx_lanes: Maximum lane count of the DPRX 449 * 450 * Calculate the maximum data rate for the provided link parameters taking into 451 * account any BW limitations by a DP tunnel attached to @intel_dp. 452 * 453 * Returns the maximum data rate in kBps units. 454 */ 455 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, 456 int max_dprx_rate, int max_dprx_lanes) 457 { 458 int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes); 459 460 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 461 max_rate = min(max_rate, 462 drm_dp_tunnel_available_bw(intel_dp->tunnel)); 463 464 return max_rate; 465 } 466 467 bool intel_dp_has_joiner(struct intel_dp *intel_dp) 468 { 469 struct intel_display *display = to_intel_display(intel_dp); 470 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 471 struct intel_encoder *encoder = &intel_dig_port->base; 472 473 /* eDP MSO is not compatible with joiner */ 474 if (intel_dp->mso_link_count) 475 return false; 476 477 return DISPLAY_VER(display) >= 12 || 478 (DISPLAY_VER(display) == 11 && 479 encoder->port != PORT_A); 480 } 481 482 static int dg2_max_source_rate(struct intel_dp *intel_dp) 483 { 484 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000; 485 } 486 487 static int icl_max_source_rate(struct intel_dp *intel_dp) 488 { 489 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 490 491 if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp)) 492 return 540000; 493 494 return 810000; 495 } 496 497 static int ehl_max_source_rate(struct intel_dp *intel_dp) 498 { 499 if (intel_dp_is_edp(intel_dp)) 500 return 540000; 501 502 return 810000; 503 } 504 505 static int mtl_max_source_rate(struct intel_dp *intel_dp) 506 { 507 struct intel_display *display = to_intel_display(intel_dp); 508 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 509 510 if (intel_encoder_is_c10phy(encoder)) 511 return 810000; 512 513 if (DISPLAY_VERx100(display) == 1401) 514 return 1350000; 515 516 return 2000000; 517 } 518 519 static int vbt_max_link_rate(struct intel_dp *intel_dp) 520 { 521 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 522 int max_rate; 523 524 max_rate = intel_bios_dp_max_link_rate(encoder->devdata); 525 526 if (intel_dp_is_edp(intel_dp)) { 527 struct intel_connector *connector = intel_dp->attached_connector; 528 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; 529 530 if (max_rate && edp_max_rate) 531 max_rate = min(max_rate, edp_max_rate); 532 else if (edp_max_rate) 533 max_rate = edp_max_rate; 534 } 535 536 return max_rate; 537 } 538 539 static void 540 intel_dp_set_source_rates(struct intel_dp *intel_dp) 541 { 542 /* The values must be in increasing order */ 543 static const int bmg_rates[] = { 544 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 545 810000, 1000000, 1350000, 546 }; 547 static const int mtl_rates[] = { 548 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 549 810000, 1000000, 2000000, 550 }; 551 static const int icl_rates[] = { 552 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000, 553 1000000, 1350000, 554 }; 555 static const int bxt_rates[] = { 556 162000, 216000, 243000, 270000, 324000, 432000, 540000 557 }; 558 static const int skl_rates[] = { 559 162000, 216000, 270000, 324000, 432000, 540000 560 }; 561 static const int hsw_rates[] = { 562 162000, 270000, 540000 563 }; 564 static const int g4x_rates[] = { 565 162000, 270000 566 }; 567 struct intel_display *display = to_intel_display(intel_dp); 568 const int *source_rates; 569 int size, max_rate = 0, vbt_max_rate; 570 571 /* This should only be done once */ 572 drm_WARN_ON(display->drm, 573 intel_dp->source_rates || intel_dp->num_source_rates); 574 575 if (DISPLAY_VER(display) >= 14) { 576 if (display->platform.battlemage) { 577 source_rates = bmg_rates; 578 size = ARRAY_SIZE(bmg_rates); 579 } else { 580 source_rates = mtl_rates; 581 size = ARRAY_SIZE(mtl_rates); 582 } 583 max_rate = mtl_max_source_rate(intel_dp); 584 } else if (DISPLAY_VER(display) >= 11) { 585 source_rates = icl_rates; 586 size = ARRAY_SIZE(icl_rates); 587 if (display->platform.dg2) 588 max_rate = dg2_max_source_rate(intel_dp); 589 else if (display->platform.alderlake_p || display->platform.alderlake_s || 590 display->platform.dg1 || display->platform.rocketlake) 591 max_rate = 810000; 592 else if (display->platform.jasperlake || display->platform.elkhartlake) 593 max_rate = ehl_max_source_rate(intel_dp); 594 else 595 max_rate = icl_max_source_rate(intel_dp); 596 } else if (display->platform.geminilake || display->platform.broxton) { 597 source_rates = bxt_rates; 598 size = ARRAY_SIZE(bxt_rates); 599 } else if (DISPLAY_VER(display) == 9) { 600 source_rates = skl_rates; 601 size = ARRAY_SIZE(skl_rates); 602 } else if ((display->platform.haswell && !display->platform.haswell_ulx) || 603 display->platform.broadwell) { 604 source_rates = hsw_rates; 605 size = ARRAY_SIZE(hsw_rates); 606 } else { 607 source_rates = g4x_rates; 608 size = ARRAY_SIZE(g4x_rates); 609 } 610 611 vbt_max_rate = vbt_max_link_rate(intel_dp); 612 if (max_rate && vbt_max_rate) 613 max_rate = min(max_rate, vbt_max_rate); 614 else if (vbt_max_rate) 615 max_rate = vbt_max_rate; 616 617 if (max_rate) 618 size = intel_dp_rate_limit_len(source_rates, size, max_rate); 619 620 intel_dp->source_rates = source_rates; 621 intel_dp->num_source_rates = size; 622 } 623 624 static int intersect_rates(const int *source_rates, int source_len, 625 const int *sink_rates, int sink_len, 626 int *common_rates) 627 { 628 int i = 0, j = 0, k = 0; 629 630 while (i < source_len && j < sink_len) { 631 if (source_rates[i] == sink_rates[j]) { 632 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 633 return k; 634 common_rates[k] = source_rates[i]; 635 ++k; 636 ++i; 637 ++j; 638 } else if (source_rates[i] < sink_rates[j]) { 639 ++i; 640 } else { 641 ++j; 642 } 643 } 644 return k; 645 } 646 647 /* return index of rate in rates array, or -1 if not found */ 648 int intel_dp_rate_index(const int *rates, int len, int rate) 649 { 650 int i; 651 652 for (i = 0; i < len; i++) 653 if (rate == rates[i]) 654 return i; 655 656 return -1; 657 } 658 659 static int intel_dp_link_config_rate(struct intel_dp *intel_dp, 660 const struct intel_dp_link_config *lc) 661 { 662 return intel_dp_common_rate(intel_dp, lc->link_rate_idx); 663 } 664 665 static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc) 666 { 667 return 1 << lc->lane_count_exp; 668 } 669 670 static int intel_dp_link_config_bw(struct intel_dp *intel_dp, 671 const struct intel_dp_link_config *lc) 672 { 673 return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc), 674 intel_dp_link_config_lane_count(lc)); 675 } 676 677 static int link_config_cmp_by_bw(const void *a, const void *b, const void *p) 678 { 679 struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */ 680 const struct intel_dp_link_config *lc_a = a; 681 const struct intel_dp_link_config *lc_b = b; 682 int bw_a = intel_dp_link_config_bw(intel_dp, lc_a); 683 int bw_b = intel_dp_link_config_bw(intel_dp, lc_b); 684 685 if (bw_a != bw_b) 686 return bw_a - bw_b; 687 688 return intel_dp_link_config_rate(intel_dp, lc_a) - 689 intel_dp_link_config_rate(intel_dp, lc_b); 690 } 691 692 static void intel_dp_link_config_init(struct intel_dp *intel_dp) 693 { 694 struct intel_display *display = to_intel_display(intel_dp); 695 struct intel_dp_link_config *lc; 696 int num_common_lane_configs; 697 int i; 698 int j; 699 700 if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp)))) 701 return; 702 703 num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1; 704 705 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs > 706 ARRAY_SIZE(intel_dp->link.configs))) 707 return; 708 709 intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs; 710 711 lc = &intel_dp->link.configs[0]; 712 for (i = 0; i < intel_dp->num_common_rates; i++) { 713 for (j = 0; j < num_common_lane_configs; j++) { 714 lc->lane_count_exp = j; 715 lc->link_rate_idx = i; 716 717 lc++; 718 } 719 } 720 721 sort_r(intel_dp->link.configs, intel_dp->link.num_configs, 722 sizeof(intel_dp->link.configs[0]), 723 link_config_cmp_by_bw, NULL, 724 intel_dp); 725 } 726 727 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) 728 { 729 struct intel_display *display = to_intel_display(intel_dp); 730 const struct intel_dp_link_config *lc; 731 732 if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs)) 733 idx = 0; 734 735 lc = &intel_dp->link.configs[idx]; 736 737 *link_rate = intel_dp_link_config_rate(intel_dp, lc); 738 *lane_count = intel_dp_link_config_lane_count(lc); 739 } 740 741 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) 742 { 743 int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, 744 link_rate); 745 int lane_count_exp = ilog2(lane_count); 746 int i; 747 748 for (i = 0; i < intel_dp->link.num_configs; i++) { 749 const struct intel_dp_link_config *lc = &intel_dp->link.configs[i]; 750 751 if (lc->lane_count_exp == lane_count_exp && 752 lc->link_rate_idx == link_rate_idx) 753 return i; 754 } 755 756 return -1; 757 } 758 759 static void intel_dp_set_common_rates(struct intel_dp *intel_dp) 760 { 761 struct intel_display *display = to_intel_display(intel_dp); 762 763 drm_WARN_ON(display->drm, 764 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); 765 766 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, 767 intel_dp->num_source_rates, 768 intel_dp->sink_rates, 769 intel_dp->num_sink_rates, 770 intel_dp->common_rates); 771 772 /* Paranoia, there should always be something in common. */ 773 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) { 774 intel_dp->common_rates[0] = 162000; 775 intel_dp->num_common_rates = 1; 776 } 777 778 intel_dp_link_config_init(intel_dp); 779 } 780 781 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 782 u8 lane_count) 783 { 784 /* 785 * FIXME: we need to synchronize the current link parameters with 786 * hardware readout. Currently fast link training doesn't work on 787 * boot-up. 788 */ 789 if (link_rate == 0 || 790 link_rate > intel_dp->link.max_rate) 791 return false; 792 793 if (lane_count == 0 || 794 lane_count > intel_dp_max_lane_count(intel_dp)) 795 return false; 796 797 return true; 798 } 799 800 u32 intel_dp_mode_to_fec_clock(u32 mode_clock) 801 { 802 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), 803 1000000U); 804 } 805 806 int intel_dp_bw_fec_overhead(bool fec_enabled) 807 { 808 /* 809 * TODO: Calculate the actual overhead for a given mode. 810 * The hard-coded 1/0.972261=2.853% overhead factor 811 * corresponds (for instance) to the 8b/10b DP FEC 2.4% + 812 * 0.453% DSC overhead. This is enough for a 3840 width mode, 813 * which has a DSC overhead of up to ~0.2%, but may not be 814 * enough for a 1024 width mode where this is ~0.8% (on a 4 815 * lane DP link, with 2 DSC slices and 8 bpp color depth). 816 */ 817 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000; 818 } 819 820 static int 821 small_joiner_ram_size_bits(struct intel_display *display) 822 { 823 if (DISPLAY_VER(display) >= 13) 824 return 17280 * 8; 825 else if (DISPLAY_VER(display) >= 11) 826 return 7680 * 8; 827 else 828 return 6144 * 8; 829 } 830 831 u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) 832 { 833 u32 bits_per_pixel = bpp; 834 int i; 835 836 /* Error out if the max bpp is less than smallest allowed valid bpp */ 837 if (bits_per_pixel < valid_dsc_bpp[0]) { 838 drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n", 839 bits_per_pixel, valid_dsc_bpp[0]); 840 return 0; 841 } 842 843 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ 844 if (DISPLAY_VER(display) >= 13) { 845 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); 846 847 /* 848 * According to BSpec, 27 is the max DSC output bpp, 849 * 8 is the min DSC output bpp. 850 * While we can still clamp higher bpp values to 27, saving bandwidth, 851 * if it is required to oompress up to bpp < 8, means we can't do 852 * that and probably means we can't fit the required mode, even with 853 * DSC enabled. 854 */ 855 if (bits_per_pixel < 8) { 856 drm_dbg_kms(display->drm, 857 "Unsupported BPP %u, min 8\n", 858 bits_per_pixel); 859 return 0; 860 } 861 bits_per_pixel = min_t(u32, bits_per_pixel, 27); 862 } else { 863 /* Find the nearest match in the array of known BPPs from VESA */ 864 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { 865 if (bits_per_pixel < valid_dsc_bpp[i + 1]) 866 break; 867 } 868 drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n", 869 bits_per_pixel, valid_dsc_bpp[i]); 870 871 bits_per_pixel = valid_dsc_bpp[i]; 872 } 873 874 return bits_per_pixel; 875 } 876 877 static int bigjoiner_interface_bits(struct intel_display *display) 878 { 879 return DISPLAY_VER(display) >= 14 ? 36 : 24; 880 } 881 882 static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock, 883 int num_joined_pipes) 884 { 885 u32 max_bpp; 886 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ 887 int ppc = 2; 888 int num_big_joiners = num_joined_pipes / 2; 889 890 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) / 891 intel_dp_mode_to_fec_clock(mode_clock); 892 893 max_bpp *= num_big_joiners; 894 895 return max_bpp; 896 897 } 898 899 static u32 small_joiner_ram_max_bpp(struct intel_display *display, 900 u32 mode_hdisplay, 901 int num_joined_pipes) 902 { 903 u32 max_bpp; 904 905 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ 906 max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay; 907 908 max_bpp *= num_joined_pipes; 909 910 return max_bpp; 911 } 912 913 static int ultrajoiner_ram_bits(void) 914 { 915 return 4 * 72 * 512; 916 } 917 918 static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay) 919 { 920 return ultrajoiner_ram_bits() / mode_hdisplay; 921 } 922 923 static 924 u32 get_max_compressed_bpp_with_joiner(struct intel_display *display, 925 u32 mode_clock, u32 mode_hdisplay, 926 int num_joined_pipes) 927 { 928 u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes); 929 930 if (num_joined_pipes > 1) 931 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock, 932 num_joined_pipes)); 933 if (num_joined_pipes == 4) 934 max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay)); 935 936 return max_bpp; 937 } 938 939 u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display, 940 u32 link_clock, u32 lane_count, 941 u32 mode_clock, u32 mode_hdisplay, 942 int num_joined_pipes, 943 enum intel_output_format output_format, 944 u32 pipe_bpp, 945 u32 timeslots) 946 { 947 u32 bits_per_pixel, joiner_max_bpp; 948 949 /* 950 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* 951 * (LinkSymbolClock)* 8 * (TimeSlots / 64) 952 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) 953 * for MST -> TimeSlots has to be calculated, based on mode requirements 954 * 955 * Due to FEC overhead, the available bw is reduced to 97.2261%. 956 * To support the given mode: 957 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead 958 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead 959 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock 960 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) / 961 * (ModeClock / FEC Overhead) 962 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) / 963 * (ModeClock / FEC Overhead * 8) 964 */ 965 bits_per_pixel = ((link_clock * lane_count) * timeslots) / 966 (intel_dp_mode_to_fec_clock(mode_clock) * 8); 967 968 /* Bandwidth required for 420 is half, that of 444 format */ 969 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 970 bits_per_pixel *= 2; 971 972 /* 973 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum 974 * supported PPS value can be 63.9375 and with the further 975 * mention that for 420, 422 formats, bpp should be programmed double 976 * the target bpp restricting our target bpp to be 31.9375 at max. 977 */ 978 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 979 bits_per_pixel = min_t(u32, bits_per_pixel, 31); 980 981 drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots " 982 "total bw %u pixel clock %u\n", 983 bits_per_pixel, timeslots, 984 (link_clock * lane_count * 8), 985 intel_dp_mode_to_fec_clock(mode_clock)); 986 987 joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock, 988 mode_hdisplay, num_joined_pipes); 989 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); 990 991 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp); 992 993 return bits_per_pixel; 994 } 995 996 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 997 int mode_clock, int mode_hdisplay, 998 int num_joined_pipes) 999 { 1000 struct intel_display *display = to_intel_display(connector); 1001 u8 min_slice_count, i; 1002 int max_slice_width; 1003 1004 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) 1005 min_slice_count = DIV_ROUND_UP(mode_clock, 1006 DP_DSC_MAX_ENC_THROUGHPUT_0); 1007 else 1008 min_slice_count = DIV_ROUND_UP(mode_clock, 1009 DP_DSC_MAX_ENC_THROUGHPUT_1); 1010 1011 /* 1012 * Due to some DSC engine BW limitations, we need to enable second 1013 * slice and VDSC engine, whenever we approach close enough to max CDCLK 1014 */ 1015 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100)) 1016 min_slice_count = max_t(u8, min_slice_count, 2); 1017 1018 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); 1019 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { 1020 drm_dbg_kms(display->drm, 1021 "Unsupported slice width %d by DP DSC Sink device\n", 1022 max_slice_width); 1023 return 0; 1024 } 1025 /* Also take into account max slice width */ 1026 min_slice_count = max_t(u8, min_slice_count, 1027 DIV_ROUND_UP(mode_hdisplay, 1028 max_slice_width)); 1029 1030 /* Find the closest match to the valid slice count values */ 1031 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { 1032 u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes; 1033 1034 /* 1035 * 3 DSC Slices per pipe need 3 DSC engines, 1036 * which is supported only with Ultrajoiner. 1037 */ 1038 if (valid_dsc_slicecount[i] == 3 && num_joined_pipes != 4) 1039 continue; 1040 1041 if (test_slice_count > 1042 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) 1043 break; 1044 1045 /* 1046 * Bigjoiner needs small joiner to be enabled. 1047 * So there should be at least 2 dsc slices per pipe, 1048 * whenever bigjoiner is enabled. 1049 */ 1050 if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2) 1051 continue; 1052 1053 if (mode_hdisplay % test_slice_count) 1054 continue; 1055 1056 if (min_slice_count <= test_slice_count) 1057 return test_slice_count; 1058 } 1059 1060 drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n", 1061 min_slice_count); 1062 return 0; 1063 } 1064 1065 static bool source_can_output(struct intel_dp *intel_dp, 1066 enum intel_output_format format) 1067 { 1068 struct intel_display *display = to_intel_display(intel_dp); 1069 1070 switch (format) { 1071 case INTEL_OUTPUT_FORMAT_RGB: 1072 return true; 1073 1074 case INTEL_OUTPUT_FORMAT_YCBCR444: 1075 /* 1076 * No YCbCr output support on gmch platforms. 1077 * Also, ILK doesn't seem capable of DP YCbCr output. 1078 * The displayed image is severly corrupted. SNB+ is fine. 1079 */ 1080 return !HAS_GMCH(display) && !display->platform.ironlake; 1081 1082 case INTEL_OUTPUT_FORMAT_YCBCR420: 1083 /* Platform < Gen 11 cannot output YCbCr420 format */ 1084 return DISPLAY_VER(display) >= 11; 1085 1086 default: 1087 MISSING_CASE(format); 1088 return false; 1089 } 1090 } 1091 1092 static bool 1093 dfp_can_convert_from_rgb(struct intel_dp *intel_dp, 1094 enum intel_output_format sink_format) 1095 { 1096 if (!drm_dp_is_branch(intel_dp->dpcd)) 1097 return false; 1098 1099 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1100 return intel_dp->dfp.rgb_to_ycbcr; 1101 1102 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1103 return intel_dp->dfp.rgb_to_ycbcr && 1104 intel_dp->dfp.ycbcr_444_to_420; 1105 1106 return false; 1107 } 1108 1109 static bool 1110 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, 1111 enum intel_output_format sink_format) 1112 { 1113 if (!drm_dp_is_branch(intel_dp->dpcd)) 1114 return false; 1115 1116 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1117 return intel_dp->dfp.ycbcr_444_to_420; 1118 1119 return false; 1120 } 1121 1122 static bool 1123 dfp_can_convert(struct intel_dp *intel_dp, 1124 enum intel_output_format output_format, 1125 enum intel_output_format sink_format) 1126 { 1127 switch (output_format) { 1128 case INTEL_OUTPUT_FORMAT_RGB: 1129 return dfp_can_convert_from_rgb(intel_dp, sink_format); 1130 case INTEL_OUTPUT_FORMAT_YCBCR444: 1131 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format); 1132 default: 1133 MISSING_CASE(output_format); 1134 return false; 1135 } 1136 1137 return false; 1138 } 1139 1140 static enum intel_output_format 1141 intel_dp_output_format(struct intel_connector *connector, 1142 enum intel_output_format sink_format) 1143 { 1144 struct intel_display *display = to_intel_display(connector); 1145 struct intel_dp *intel_dp = intel_attached_dp(connector); 1146 enum intel_output_format force_dsc_output_format = 1147 intel_dp->force_dsc_output_format; 1148 enum intel_output_format output_format; 1149 if (force_dsc_output_format) { 1150 if (source_can_output(intel_dp, force_dsc_output_format) && 1151 (!drm_dp_is_branch(intel_dp->dpcd) || 1152 sink_format != force_dsc_output_format || 1153 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format))) 1154 return force_dsc_output_format; 1155 1156 drm_dbg_kms(display->drm, "Cannot force DSC output format\n"); 1157 } 1158 1159 if (sink_format == INTEL_OUTPUT_FORMAT_RGB || 1160 dfp_can_convert_from_rgb(intel_dp, sink_format)) 1161 output_format = INTEL_OUTPUT_FORMAT_RGB; 1162 1163 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 1164 dfp_can_convert_from_ycbcr444(intel_dp, sink_format)) 1165 output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 1166 1167 else 1168 output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1169 1170 drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format)); 1171 1172 return output_format; 1173 } 1174 1175 int intel_dp_min_bpp(enum intel_output_format output_format) 1176 { 1177 if (output_format == INTEL_OUTPUT_FORMAT_RGB) 1178 return 6 * 3; 1179 else 1180 return 8 * 3; 1181 } 1182 1183 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) 1184 { 1185 /* 1186 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output 1187 * format of the number of bytes per pixel will be half the number 1188 * of bytes of RGB pixel. 1189 */ 1190 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1191 bpp /= 2; 1192 1193 return bpp; 1194 } 1195 1196 static enum intel_output_format 1197 intel_dp_sink_format(struct intel_connector *connector, 1198 const struct drm_display_mode *mode) 1199 { 1200 const struct drm_display_info *info = &connector->base.display_info; 1201 1202 if (drm_mode_is_420_only(info, mode)) 1203 return INTEL_OUTPUT_FORMAT_YCBCR420; 1204 1205 return INTEL_OUTPUT_FORMAT_RGB; 1206 } 1207 1208 static int 1209 intel_dp_mode_min_output_bpp(struct intel_connector *connector, 1210 const struct drm_display_mode *mode) 1211 { 1212 enum intel_output_format output_format, sink_format; 1213 1214 sink_format = intel_dp_sink_format(connector, mode); 1215 1216 output_format = intel_dp_output_format(connector, sink_format); 1217 1218 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); 1219 } 1220 1221 static bool intel_dp_hdisplay_bad(struct intel_display *display, 1222 int hdisplay) 1223 { 1224 /* 1225 * Older platforms don't like hdisplay==4096 with DP. 1226 * 1227 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline 1228 * and frame counter increment), but we don't get vblank interrupts, 1229 * and the pipe underruns immediately. The link also doesn't seem 1230 * to get trained properly. 1231 * 1232 * On CHV the vblank interrupts don't seem to disappear but 1233 * otherwise the symptoms are similar. 1234 * 1235 * TODO: confirm the behaviour on HSW+ 1236 */ 1237 return hdisplay == 4096 && !HAS_DDI(display); 1238 } 1239 1240 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp) 1241 { 1242 struct intel_connector *connector = intel_dp->attached_connector; 1243 const struct drm_display_info *info = &connector->base.display_info; 1244 int max_tmds_clock = intel_dp->dfp.max_tmds_clock; 1245 1246 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */ 1247 if (max_tmds_clock && info->max_tmds_clock) 1248 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); 1249 1250 return max_tmds_clock; 1251 } 1252 1253 static enum drm_mode_status 1254 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, 1255 int clock, int bpc, 1256 enum intel_output_format sink_format, 1257 bool respect_downstream_limits) 1258 { 1259 int tmds_clock, min_tmds_clock, max_tmds_clock; 1260 1261 if (!respect_downstream_limits) 1262 return MODE_OK; 1263 1264 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1265 1266 min_tmds_clock = intel_dp->dfp.min_tmds_clock; 1267 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp); 1268 1269 if (min_tmds_clock && tmds_clock < min_tmds_clock) 1270 return MODE_CLOCK_LOW; 1271 1272 if (max_tmds_clock && tmds_clock > max_tmds_clock) 1273 return MODE_CLOCK_HIGH; 1274 1275 return MODE_OK; 1276 } 1277 1278 static enum drm_mode_status 1279 intel_dp_mode_valid_downstream(struct intel_connector *connector, 1280 const struct drm_display_mode *mode, 1281 int target_clock) 1282 { 1283 struct intel_dp *intel_dp = intel_attached_dp(connector); 1284 const struct drm_display_info *info = &connector->base.display_info; 1285 enum drm_mode_status status; 1286 enum intel_output_format sink_format; 1287 1288 /* If PCON supports FRL MODE, check FRL bandwidth constraints */ 1289 if (intel_dp->dfp.pcon_max_frl_bw) { 1290 int target_bw; 1291 int max_frl_bw; 1292 int bpp = intel_dp_mode_min_output_bpp(connector, mode); 1293 1294 target_bw = bpp * target_clock; 1295 1296 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 1297 1298 /* converting bw from Gbps to Kbps*/ 1299 max_frl_bw = max_frl_bw * 1000000; 1300 1301 if (target_bw > max_frl_bw) 1302 return MODE_CLOCK_HIGH; 1303 1304 return MODE_OK; 1305 } 1306 1307 if (intel_dp->dfp.max_dotclock && 1308 target_clock > intel_dp->dfp.max_dotclock) 1309 return MODE_CLOCK_HIGH; 1310 1311 sink_format = intel_dp_sink_format(connector, mode); 1312 1313 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ 1314 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1315 8, sink_format, true); 1316 1317 if (status != MODE_OK) { 1318 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 1319 !connector->base.ycbcr_420_allowed || 1320 !drm_mode_is_420_also(info, mode)) 1321 return status; 1322 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1323 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1324 8, sink_format, true); 1325 if (status != MODE_OK) 1326 return status; 1327 } 1328 1329 return MODE_OK; 1330 } 1331 1332 static 1333 bool intel_dp_needs_joiner(struct intel_dp *intel_dp, 1334 struct intel_connector *connector, 1335 int hdisplay, int clock, 1336 int num_joined_pipes) 1337 { 1338 struct intel_display *display = to_intel_display(intel_dp); 1339 int hdisplay_limit; 1340 1341 if (!intel_dp_has_joiner(intel_dp)) 1342 return false; 1343 1344 num_joined_pipes /= 2; 1345 1346 hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120; 1347 1348 return clock > num_joined_pipes * display->cdclk.max_dotclk_freq || 1349 hdisplay > num_joined_pipes * hdisplay_limit; 1350 } 1351 1352 int intel_dp_num_joined_pipes(struct intel_dp *intel_dp, 1353 struct intel_connector *connector, 1354 int hdisplay, int clock) 1355 { 1356 struct intel_display *display = to_intel_display(intel_dp); 1357 1358 if (connector->force_joined_pipes) 1359 return connector->force_joined_pipes; 1360 1361 if (HAS_ULTRAJOINER(display) && 1362 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4)) 1363 return 4; 1364 1365 if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) && 1366 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2)) 1367 return 2; 1368 1369 return 1; 1370 } 1371 1372 bool intel_dp_has_dsc(const struct intel_connector *connector) 1373 { 1374 struct intel_display *display = to_intel_display(connector); 1375 1376 if (!HAS_DSC(display)) 1377 return false; 1378 1379 if (connector->mst_port && !HAS_DSC_MST(display)) 1380 return false; 1381 1382 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && 1383 connector->panel.vbt.edp.dsc_disable) 1384 return false; 1385 1386 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) 1387 return false; 1388 1389 return true; 1390 } 1391 1392 static enum drm_mode_status 1393 intel_dp_mode_valid(struct drm_connector *_connector, 1394 struct drm_display_mode *mode) 1395 { 1396 struct intel_display *display = to_intel_display(_connector->dev); 1397 struct intel_connector *connector = to_intel_connector(_connector); 1398 struct intel_dp *intel_dp = intel_attached_dp(connector); 1399 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1400 const struct drm_display_mode *fixed_mode; 1401 int target_clock = mode->clock; 1402 int max_rate, mode_rate, max_lanes, max_link_clock; 1403 int max_dotclk = display->cdclk.max_dotclk_freq; 1404 u16 dsc_max_compressed_bpp = 0; 1405 u8 dsc_slice_count = 0; 1406 enum drm_mode_status status; 1407 bool dsc = false; 1408 int num_joined_pipes; 1409 1410 status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 1411 if (status != MODE_OK) 1412 return status; 1413 1414 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1415 return MODE_H_ILLEGAL; 1416 1417 if (mode->clock < 10000) 1418 return MODE_CLOCK_LOW; 1419 1420 fixed_mode = intel_panel_fixed_mode(connector, mode); 1421 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 1422 status = intel_panel_mode_valid(connector, mode); 1423 if (status != MODE_OK) 1424 return status; 1425 1426 target_clock = fixed_mode->clock; 1427 } 1428 1429 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, 1430 mode->hdisplay, target_clock); 1431 max_dotclk *= num_joined_pipes; 1432 1433 if (target_clock > max_dotclk) 1434 return MODE_CLOCK_HIGH; 1435 1436 if (intel_dp_hdisplay_bad(display, mode->hdisplay)) 1437 return MODE_H_ILLEGAL; 1438 1439 max_link_clock = intel_dp_max_link_rate(intel_dp); 1440 max_lanes = intel_dp_max_lane_count(intel_dp); 1441 1442 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); 1443 1444 mode_rate = intel_dp_link_required(target_clock, 1445 intel_dp_mode_min_output_bpp(connector, mode)); 1446 1447 if (intel_dp_has_dsc(connector)) { 1448 enum intel_output_format sink_format, output_format; 1449 int pipe_bpp; 1450 1451 sink_format = intel_dp_sink_format(connector, mode); 1452 output_format = intel_dp_output_format(connector, sink_format); 1453 /* 1454 * TBD pass the connector BPC, 1455 * for now U8_MAX so that max BPC on that platform would be picked 1456 */ 1457 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); 1458 1459 /* 1460 * Output bpp is stored in 6.4 format so right shift by 4 to get the 1461 * integer value since we support only integer values of bpp. 1462 */ 1463 if (intel_dp_is_edp(intel_dp)) { 1464 dsc_max_compressed_bpp = 1465 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; 1466 dsc_slice_count = 1467 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 1468 true); 1469 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { 1470 dsc_max_compressed_bpp = 1471 intel_dp_dsc_get_max_compressed_bpp(display, 1472 max_link_clock, 1473 max_lanes, 1474 target_clock, 1475 mode->hdisplay, 1476 num_joined_pipes, 1477 output_format, 1478 pipe_bpp, 64); 1479 dsc_slice_count = 1480 intel_dp_dsc_get_slice_count(connector, 1481 target_clock, 1482 mode->hdisplay, 1483 num_joined_pipes); 1484 } 1485 1486 dsc = dsc_max_compressed_bpp && dsc_slice_count; 1487 } 1488 1489 if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) 1490 return MODE_CLOCK_HIGH; 1491 1492 if (mode_rate > max_rate && !dsc) 1493 return MODE_CLOCK_HIGH; 1494 1495 status = intel_dp_mode_valid_downstream(connector, mode, target_clock); 1496 if (status != MODE_OK) 1497 return status; 1498 1499 return intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes); 1500 } 1501 1502 bool intel_dp_source_supports_tps3(struct intel_display *display) 1503 { 1504 return DISPLAY_VER(display) >= 9 || 1505 display->platform.broadwell || display->platform.haswell; 1506 } 1507 1508 bool intel_dp_source_supports_tps4(struct intel_display *display) 1509 { 1510 return DISPLAY_VER(display) >= 10; 1511 } 1512 1513 static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem) 1514 { 1515 int i; 1516 1517 for (i = 0; i < nelem; i++) 1518 seq_buf_printf(s, "%s%d", i ? ", " : "", array[i]); 1519 } 1520 1521 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1522 { 1523 struct intel_display *display = to_intel_display(intel_dp); 1524 DECLARE_SEQ_BUF(s, 128); /* FIXME: too big for stack? */ 1525 1526 if (!drm_debug_enabled(DRM_UT_KMS)) 1527 return; 1528 1529 seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates); 1530 drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s)); 1531 1532 seq_buf_clear(&s); 1533 seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates); 1534 drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s)); 1535 1536 seq_buf_clear(&s); 1537 seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates); 1538 drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s)); 1539 } 1540 1541 static int forced_link_rate(struct intel_dp *intel_dp) 1542 { 1543 int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate); 1544 1545 if (len == 0) 1546 return intel_dp_common_rate(intel_dp, 0); 1547 1548 return intel_dp_common_rate(intel_dp, len - 1); 1549 } 1550 1551 int 1552 intel_dp_max_link_rate(struct intel_dp *intel_dp) 1553 { 1554 int len; 1555 1556 if (intel_dp->link.force_rate) 1557 return forced_link_rate(intel_dp); 1558 1559 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate); 1560 1561 return intel_dp_common_rate(intel_dp, len - 1); 1562 } 1563 1564 static int 1565 intel_dp_min_link_rate(struct intel_dp *intel_dp) 1566 { 1567 if (intel_dp->link.force_rate) 1568 return forced_link_rate(intel_dp); 1569 1570 return intel_dp_common_rate(intel_dp, 0); 1571 } 1572 1573 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1574 { 1575 struct intel_display *display = to_intel_display(intel_dp); 1576 int i = intel_dp_rate_index(intel_dp->sink_rates, 1577 intel_dp->num_sink_rates, rate); 1578 1579 if (drm_WARN_ON(display->drm, i < 0)) 1580 i = 0; 1581 1582 return i; 1583 } 1584 1585 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1586 u8 *link_bw, u8 *rate_select) 1587 { 1588 /* eDP 1.4 rate select method. */ 1589 if (intel_dp->use_rate_select) { 1590 *link_bw = 0; 1591 *rate_select = 1592 intel_dp_rate_select(intel_dp, port_clock); 1593 } else { 1594 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1595 *rate_select = 0; 1596 } 1597 } 1598 1599 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp) 1600 { 1601 struct intel_connector *connector = intel_dp->attached_connector; 1602 1603 return connector->base.display_info.is_hdmi; 1604 } 1605 1606 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 1607 const struct intel_crtc_state *pipe_config) 1608 { 1609 struct intel_display *display = to_intel_display(intel_dp); 1610 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1611 1612 if (DISPLAY_VER(display) >= 12) 1613 return true; 1614 1615 if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A && 1616 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) 1617 return true; 1618 1619 return false; 1620 } 1621 1622 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 1623 const struct intel_connector *connector, 1624 const struct intel_crtc_state *pipe_config) 1625 { 1626 return intel_dp_source_supports_fec(intel_dp, pipe_config) && 1627 drm_dp_sink_supports_fec(connector->dp.fec_capability); 1628 } 1629 1630 bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 1631 const struct intel_connector *connector, 1632 const struct intel_crtc_state *crtc_state) 1633 { 1634 if (!intel_dp_has_dsc(connector)) 1635 return false; 1636 1637 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && 1638 !intel_dp_supports_fec(intel_dp, connector, crtc_state)) 1639 return false; 1640 1641 return intel_dsc_source_support(crtc_state); 1642 } 1643 1644 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, 1645 const struct intel_crtc_state *crtc_state, 1646 int bpc, bool respect_downstream_limits) 1647 { 1648 int clock = crtc_state->hw.adjusted_mode.crtc_clock; 1649 1650 /* 1651 * Current bpc could already be below 8bpc due to 1652 * FDI bandwidth constraints or other limits. 1653 * HDMI minimum is 8bpc however. 1654 */ 1655 bpc = max(bpc, 8); 1656 1657 /* 1658 * We will never exceed downstream TMDS clock limits while 1659 * attempting deep color. If the user insists on forcing an 1660 * out of spec mode they will have to be satisfied with 8bpc. 1661 */ 1662 if (!respect_downstream_limits) 1663 bpc = 8; 1664 1665 for (; bpc >= 8; bpc -= 2) { 1666 if (intel_hdmi_bpc_possible(crtc_state, bpc, 1667 intel_dp_has_hdmi_sink(intel_dp)) && 1668 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, 1669 respect_downstream_limits) == MODE_OK) 1670 return bpc; 1671 } 1672 1673 return -EINVAL; 1674 } 1675 1676 static int intel_dp_max_bpp(struct intel_dp *intel_dp, 1677 const struct intel_crtc_state *crtc_state, 1678 bool respect_downstream_limits) 1679 { 1680 struct intel_display *display = to_intel_display(intel_dp); 1681 struct intel_connector *connector = intel_dp->attached_connector; 1682 int bpp, bpc; 1683 1684 bpc = crtc_state->pipe_bpp / 3; 1685 1686 if (intel_dp->dfp.max_bpc) 1687 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); 1688 1689 if (intel_dp->dfp.min_tmds_clock) { 1690 int max_hdmi_bpc; 1691 1692 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc, 1693 respect_downstream_limits); 1694 if (max_hdmi_bpc < 0) 1695 return 0; 1696 1697 bpc = min(bpc, max_hdmi_bpc); 1698 } 1699 1700 bpp = bpc * 3; 1701 if (intel_dp_is_edp(intel_dp)) { 1702 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1703 if (connector->base.display_info.bpc == 0 && 1704 connector->panel.vbt.edp.bpp && 1705 connector->panel.vbt.edp.bpp < bpp) { 1706 drm_dbg_kms(display->drm, 1707 "clamping bpp for eDP panel to BIOS-provided %i\n", 1708 connector->panel.vbt.edp.bpp); 1709 bpp = connector->panel.vbt.edp.bpp; 1710 } 1711 } 1712 1713 return bpp; 1714 } 1715 1716 static bool has_seamless_m_n(struct intel_connector *connector) 1717 { 1718 struct intel_display *display = to_intel_display(connector); 1719 1720 /* 1721 * Seamless M/N reprogramming only implemented 1722 * for BDW+ double buffered M/N registers so far. 1723 */ 1724 return HAS_DOUBLE_BUFFERED_M_N(display) && 1725 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 1726 } 1727 1728 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state, 1729 const struct drm_connector_state *conn_state) 1730 { 1731 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1732 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1733 1734 /* FIXME a bit of a mess wrt clock vs. crtc_clock */ 1735 if (has_seamless_m_n(connector)) 1736 return intel_panel_highest_mode(connector, adjusted_mode)->clock; 1737 else 1738 return adjusted_mode->crtc_clock; 1739 } 1740 1741 /* Optimize link config in order: max bpp, min clock, min lanes */ 1742 static int 1743 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 1744 struct intel_crtc_state *pipe_config, 1745 const struct drm_connector_state *conn_state, 1746 const struct link_config_limits *limits) 1747 { 1748 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); 1749 int mode_rate, link_rate, link_avail; 1750 1751 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 1752 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); 1753 bpp -= 2 * 3) { 1754 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 1755 1756 mode_rate = intel_dp_link_required(clock, link_bpp); 1757 1758 for (i = 0; i < intel_dp->num_common_rates; i++) { 1759 link_rate = intel_dp_common_rate(intel_dp, i); 1760 if (link_rate < limits->min_rate || 1761 link_rate > limits->max_rate) 1762 continue; 1763 1764 for (lane_count = limits->min_lane_count; 1765 lane_count <= limits->max_lane_count; 1766 lane_count <<= 1) { 1767 link_avail = intel_dp_max_link_data_rate(intel_dp, 1768 link_rate, 1769 lane_count); 1770 1771 1772 if (mode_rate <= link_avail) { 1773 pipe_config->lane_count = lane_count; 1774 pipe_config->pipe_bpp = bpp; 1775 pipe_config->port_clock = link_rate; 1776 1777 return 0; 1778 } 1779 } 1780 } 1781 } 1782 1783 return -EINVAL; 1784 } 1785 1786 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display) 1787 { 1788 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 1789 if (DISPLAY_VER(display) >= 12) 1790 return 12; 1791 if (DISPLAY_VER(display) == 11) 1792 return 10; 1793 1794 return 0; 1795 } 1796 1797 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 1798 u8 max_req_bpc) 1799 { 1800 struct intel_display *display = to_intel_display(connector); 1801 int i, num_bpc; 1802 u8 dsc_bpc[3] = {}; 1803 int dsc_max_bpc; 1804 1805 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 1806 1807 if (!dsc_max_bpc) 1808 return dsc_max_bpc; 1809 1810 dsc_max_bpc = min(dsc_max_bpc, max_req_bpc); 1811 1812 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, 1813 dsc_bpc); 1814 for (i = 0; i < num_bpc; i++) { 1815 if (dsc_max_bpc >= dsc_bpc[i]) 1816 return dsc_bpc[i] * 3; 1817 } 1818 1819 return 0; 1820 } 1821 1822 static int intel_dp_source_dsc_version_minor(struct intel_display *display) 1823 { 1824 return DISPLAY_VER(display) >= 14 ? 2 : 1; 1825 } 1826 1827 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 1828 { 1829 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> 1830 DP_DSC_MINOR_SHIFT; 1831 } 1832 1833 static int intel_dp_get_slice_height(int vactive) 1834 { 1835 int slice_height; 1836 1837 /* 1838 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108 1839 * lines is an optimal slice height, but any size can be used as long as 1840 * vertical active integer multiple and maximum vertical slice count 1841 * requirements are met. 1842 */ 1843 for (slice_height = 108; slice_height <= vactive; slice_height += 2) 1844 if (vactive % slice_height == 0) 1845 return slice_height; 1846 1847 /* 1848 * Highly unlikely we reach here as most of the resolutions will end up 1849 * finding appropriate slice_height in above loop but returning 1850 * slice_height as 2 here as it should work with all resolutions. 1851 */ 1852 return 2; 1853 } 1854 1855 static int intel_dp_dsc_compute_params(const struct intel_connector *connector, 1856 struct intel_crtc_state *crtc_state) 1857 { 1858 struct intel_display *display = to_intel_display(connector); 1859 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1860 int ret; 1861 1862 /* 1863 * RC_MODEL_SIZE is currently a constant across all configurations. 1864 * 1865 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and 1866 * DP_DSC_RC_BUF_SIZE for this. 1867 */ 1868 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1869 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1870 1871 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); 1872 1873 ret = intel_dsc_compute_params(crtc_state); 1874 if (ret) 1875 return ret; 1876 1877 vdsc_cfg->dsc_version_major = 1878 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 1879 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; 1880 vdsc_cfg->dsc_version_minor = 1881 min(intel_dp_source_dsc_version_minor(display), 1882 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)); 1883 if (vdsc_cfg->convert_rgb) 1884 vdsc_cfg->convert_rgb = 1885 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & 1886 DP_DSC_RGB; 1887 1888 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, 1889 drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd)); 1890 if (!vdsc_cfg->line_buf_depth) { 1891 drm_dbg_kms(display->drm, 1892 "DSC Sink Line Buffer Depth invalid\n"); 1893 return -EINVAL; 1894 } 1895 1896 vdsc_cfg->block_pred_enable = 1897 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & 1898 DP_DSC_BLK_PREDICTION_IS_SUPPORTED; 1899 1900 return drm_dsc_compute_rc_parameters(vdsc_cfg); 1901 } 1902 1903 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, 1904 enum intel_output_format output_format) 1905 { 1906 struct intel_display *display = to_intel_display(connector); 1907 u8 sink_dsc_format; 1908 1909 switch (output_format) { 1910 case INTEL_OUTPUT_FORMAT_RGB: 1911 sink_dsc_format = DP_DSC_RGB; 1912 break; 1913 case INTEL_OUTPUT_FORMAT_YCBCR444: 1914 sink_dsc_format = DP_DSC_YCbCr444; 1915 break; 1916 case INTEL_OUTPUT_FORMAT_YCBCR420: 1917 if (min(intel_dp_source_dsc_version_minor(display), 1918 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2) 1919 return false; 1920 sink_dsc_format = DP_DSC_YCbCr420_Native; 1921 break; 1922 default: 1923 return false; 1924 } 1925 1926 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); 1927 } 1928 1929 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock, 1930 u32 lane_count, u32 mode_clock, 1931 enum intel_output_format output_format, 1932 int timeslots) 1933 { 1934 u32 available_bw, required_bw; 1935 1936 available_bw = (link_clock * lane_count * timeslots * 16) / 8; 1937 required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock)); 1938 1939 return available_bw > required_bw; 1940 } 1941 1942 static int dsc_compute_link_config(struct intel_dp *intel_dp, 1943 struct intel_crtc_state *pipe_config, 1944 struct link_config_limits *limits, 1945 u16 compressed_bppx16, 1946 int timeslots) 1947 { 1948 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1949 int link_rate, lane_count; 1950 int i; 1951 1952 for (i = 0; i < intel_dp->num_common_rates; i++) { 1953 link_rate = intel_dp_common_rate(intel_dp, i); 1954 if (link_rate < limits->min_rate || link_rate > limits->max_rate) 1955 continue; 1956 1957 for (lane_count = limits->min_lane_count; 1958 lane_count <= limits->max_lane_count; 1959 lane_count <<= 1) { 1960 if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate, 1961 lane_count, adjusted_mode->clock, 1962 pipe_config->output_format, 1963 timeslots)) 1964 continue; 1965 1966 pipe_config->lane_count = lane_count; 1967 pipe_config->port_clock = link_rate; 1968 1969 return 0; 1970 } 1971 } 1972 1973 return -EINVAL; 1974 } 1975 1976 static 1977 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, 1978 const struct intel_crtc_state *pipe_config, 1979 int bpc) 1980 { 1981 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); 1982 1983 if (max_bppx16) 1984 return max_bppx16; 1985 /* 1986 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate 1987 * values as given in spec Table 2-157 DP v2.0 1988 */ 1989 switch (pipe_config->output_format) { 1990 case INTEL_OUTPUT_FORMAT_RGB: 1991 case INTEL_OUTPUT_FORMAT_YCBCR444: 1992 return (3 * bpc) << 4; 1993 case INTEL_OUTPUT_FORMAT_YCBCR420: 1994 return (3 * (bpc / 2)) << 4; 1995 default: 1996 MISSING_CASE(pipe_config->output_format); 1997 break; 1998 } 1999 2000 return 0; 2001 } 2002 2003 int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config) 2004 { 2005 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ 2006 switch (pipe_config->output_format) { 2007 case INTEL_OUTPUT_FORMAT_RGB: 2008 case INTEL_OUTPUT_FORMAT_YCBCR444: 2009 return 8; 2010 case INTEL_OUTPUT_FORMAT_YCBCR420: 2011 return 6; 2012 default: 2013 MISSING_CASE(pipe_config->output_format); 2014 break; 2015 } 2016 2017 return 0; 2018 } 2019 2020 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, 2021 const struct intel_crtc_state *pipe_config, 2022 int bpc) 2023 { 2024 return intel_dp_dsc_max_sink_compressed_bppx16(connector, 2025 pipe_config, bpc) >> 4; 2026 } 2027 2028 static int dsc_src_min_compressed_bpp(void) 2029 { 2030 /* Min Compressed bpp supported by source is 8 */ 2031 return 8; 2032 } 2033 2034 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) 2035 { 2036 struct intel_display *display = to_intel_display(intel_dp); 2037 2038 /* 2039 * Forcing DSC and using the platform's max compressed bpp is seen to cause 2040 * underruns. Since DSC isn't needed in these cases, limit the 2041 * max compressed bpp to 18, which is a safe value across platforms with different 2042 * pipe bpps. 2043 */ 2044 if (intel_dp->force_dsc_en) 2045 return 18; 2046 2047 /* 2048 * Max Compressed bpp for Gen 13+ is 27bpp. 2049 * For earlier platform is 23bpp. (Bspec:49259). 2050 */ 2051 if (DISPLAY_VER(display) < 13) 2052 return 23; 2053 else 2054 return 27; 2055 } 2056 2057 /* 2058 * From a list of valid compressed bpps try different compressed bpp and find a 2059 * suitable link configuration that can support it. 2060 */ 2061 static int 2062 icl_dsc_compute_link_config(struct intel_dp *intel_dp, 2063 struct intel_crtc_state *pipe_config, 2064 struct link_config_limits *limits, 2065 int dsc_max_bpp, 2066 int dsc_min_bpp, 2067 int pipe_bpp, 2068 int timeslots) 2069 { 2070 int i, ret; 2071 2072 /* Compressed BPP should be less than the Input DSC bpp */ 2073 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 2074 2075 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { 2076 if (valid_dsc_bpp[i] < dsc_min_bpp) 2077 continue; 2078 if (valid_dsc_bpp[i] > dsc_max_bpp) 2079 break; 2080 2081 ret = dsc_compute_link_config(intel_dp, 2082 pipe_config, 2083 limits, 2084 valid_dsc_bpp[i] << 4, 2085 timeslots); 2086 if (ret == 0) { 2087 pipe_config->dsc.compressed_bpp_x16 = 2088 fxp_q4_from_int(valid_dsc_bpp[i]); 2089 return 0; 2090 } 2091 } 2092 2093 return -EINVAL; 2094 } 2095 2096 /* 2097 * From XE_LPD onwards we supports compression bpps in steps of 1 up to 2098 * uncompressed bpp-1. So we start from max compressed bpp and see if any 2099 * link configuration is able to support that compressed bpp, if not we 2100 * step down and check for lower compressed bpp. 2101 */ 2102 static int 2103 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, 2104 const struct intel_connector *connector, 2105 struct intel_crtc_state *pipe_config, 2106 struct link_config_limits *limits, 2107 int dsc_max_bpp, 2108 int dsc_min_bpp, 2109 int pipe_bpp, 2110 int timeslots) 2111 { 2112 struct intel_display *display = to_intel_display(intel_dp); 2113 u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); 2114 u16 compressed_bppx16; 2115 u8 bppx16_step; 2116 int ret; 2117 2118 if (DISPLAY_VER(display) < 14 || bppx16_incr <= 1) 2119 bppx16_step = 16; 2120 else 2121 bppx16_step = 16 / bppx16_incr; 2122 2123 /* Compressed BPP should be less than the Input DSC bpp */ 2124 dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step); 2125 dsc_min_bpp = dsc_min_bpp << 4; 2126 2127 for (compressed_bppx16 = dsc_max_bpp; 2128 compressed_bppx16 >= dsc_min_bpp; 2129 compressed_bppx16 -= bppx16_step) { 2130 if (intel_dp->force_dsc_fractional_bpp_en && 2131 !fxp_q4_to_frac(compressed_bppx16)) 2132 continue; 2133 ret = dsc_compute_link_config(intel_dp, 2134 pipe_config, 2135 limits, 2136 compressed_bppx16, 2137 timeslots); 2138 if (ret == 0) { 2139 pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16; 2140 if (intel_dp->force_dsc_fractional_bpp_en && 2141 fxp_q4_to_frac(compressed_bppx16)) 2142 drm_dbg_kms(display->drm, 2143 "Forcing DSC fractional bpp\n"); 2144 2145 return 0; 2146 } 2147 } 2148 return -EINVAL; 2149 } 2150 2151 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, 2152 const struct intel_connector *connector, 2153 struct intel_crtc_state *pipe_config, 2154 struct link_config_limits *limits, 2155 int pipe_bpp, 2156 int timeslots) 2157 { 2158 struct intel_display *display = to_intel_display(intel_dp); 2159 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2160 int dsc_min_bpp; 2161 int dsc_max_bpp; 2162 int dsc_joiner_max_bpp; 2163 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2164 2165 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); 2166 2167 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock, 2168 adjusted_mode->hdisplay, 2169 num_joined_pipes); 2170 dsc_max_bpp = min(dsc_joiner_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16)); 2171 2172 if (DISPLAY_VER(display) >= 13) 2173 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits, 2174 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); 2175 return icl_dsc_compute_link_config(intel_dp, pipe_config, limits, 2176 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); 2177 } 2178 2179 int intel_dp_dsc_min_src_input_bpc(void) 2180 { 2181 /* Min DSC Input BPC for ICL+ is 8 */ 2182 return 8; 2183 } 2184 2185 static 2186 bool is_dsc_pipe_bpp_sufficient(struct link_config_limits *limits, 2187 int pipe_bpp) 2188 { 2189 return pipe_bpp >= limits->pipe.min_bpp && 2190 pipe_bpp <= limits->pipe.max_bpp; 2191 } 2192 2193 static 2194 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, 2195 struct link_config_limits *limits) 2196 { 2197 struct intel_display *display = to_intel_display(intel_dp); 2198 int forced_bpp; 2199 2200 if (!intel_dp->force_dsc_bpc) 2201 return 0; 2202 2203 forced_bpp = intel_dp->force_dsc_bpc * 3; 2204 2205 if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) { 2206 drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n", 2207 intel_dp->force_dsc_bpc); 2208 return forced_bpp; 2209 } 2210 2211 drm_dbg_kms(display->drm, 2212 "Cannot force DSC BPC:%d, due to DSC BPC limits\n", 2213 intel_dp->force_dsc_bpc); 2214 2215 return 0; 2216 } 2217 2218 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2219 struct intel_crtc_state *pipe_config, 2220 struct drm_connector_state *conn_state, 2221 struct link_config_limits *limits, 2222 int timeslots) 2223 { 2224 const struct intel_connector *connector = 2225 to_intel_connector(conn_state->connector); 2226 int dsc_max_bpp; 2227 int dsc_min_bpp; 2228 u8 dsc_bpc[3] = {}; 2229 int forced_bpp, pipe_bpp; 2230 int num_bpc, i, ret; 2231 2232 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); 2233 2234 if (forced_bpp) { 2235 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, 2236 limits, forced_bpp, timeslots); 2237 if (ret == 0) { 2238 pipe_config->pipe_bpp = forced_bpp; 2239 return 0; 2240 } 2241 } 2242 2243 dsc_max_bpp = limits->pipe.max_bpp; 2244 dsc_min_bpp = limits->pipe.min_bpp; 2245 2246 /* 2247 * Get the maximum DSC bpc that will be supported by any valid 2248 * link configuration and compressed bpp. 2249 */ 2250 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); 2251 for (i = 0; i < num_bpc; i++) { 2252 pipe_bpp = dsc_bpc[i] * 3; 2253 if (pipe_bpp < dsc_min_bpp) 2254 break; 2255 if (pipe_bpp > dsc_max_bpp) 2256 continue; 2257 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, 2258 limits, pipe_bpp, timeslots); 2259 if (ret == 0) { 2260 pipe_config->pipe_bpp = pipe_bpp; 2261 return 0; 2262 } 2263 } 2264 2265 return -EINVAL; 2266 } 2267 2268 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2269 struct intel_crtc_state *pipe_config, 2270 struct drm_connector_state *conn_state, 2271 struct link_config_limits *limits) 2272 { 2273 struct intel_display *display = to_intel_display(intel_dp); 2274 struct intel_connector *connector = 2275 to_intel_connector(conn_state->connector); 2276 int pipe_bpp, forced_bpp; 2277 int dsc_min_bpp; 2278 int dsc_max_bpp; 2279 2280 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); 2281 2282 if (forced_bpp) { 2283 pipe_bpp = forced_bpp; 2284 } else { 2285 int max_bpc = limits->pipe.max_bpp / 3; 2286 2287 /* For eDP use max bpp that can be supported with DSC. */ 2288 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); 2289 if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) { 2290 drm_dbg_kms(display->drm, 2291 "Computed BPC is not in DSC BPC limits\n"); 2292 return -EINVAL; 2293 } 2294 } 2295 pipe_config->port_clock = limits->max_rate; 2296 pipe_config->lane_count = limits->max_lane_count; 2297 2298 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); 2299 2300 dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 2301 2302 /* Compressed BPP should be less than the Input DSC bpp */ 2303 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 2304 2305 pipe_config->dsc.compressed_bpp_x16 = 2306 fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp)); 2307 2308 pipe_config->pipe_bpp = pipe_bpp; 2309 2310 return 0; 2311 } 2312 2313 static void intel_dp_fec_compute_config(struct intel_dp *intel_dp, 2314 struct intel_crtc_state *crtc_state) 2315 { 2316 if (crtc_state->fec_enable) 2317 return; 2318 2319 /* 2320 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional. 2321 * Since, FEC is a bandwidth overhead, continue to not enable it for 2322 * eDP. Until, there is a good reason to do so. 2323 */ 2324 if (intel_dp_is_edp(intel_dp)) 2325 return; 2326 2327 if (intel_dp_is_uhbr(crtc_state)) 2328 return; 2329 2330 crtc_state->fec_enable = true; 2331 } 2332 2333 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 2334 struct intel_crtc_state *pipe_config, 2335 struct drm_connector_state *conn_state, 2336 struct link_config_limits *limits, 2337 int timeslots, 2338 bool compute_pipe_bpp) 2339 { 2340 struct intel_display *display = to_intel_display(intel_dp); 2341 const struct intel_connector *connector = 2342 to_intel_connector(conn_state->connector); 2343 const struct drm_display_mode *adjusted_mode = 2344 &pipe_config->hw.adjusted_mode; 2345 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2346 int ret; 2347 2348 intel_dp_fec_compute_config(intel_dp, pipe_config); 2349 2350 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format)) 2351 return -EINVAL; 2352 2353 /* 2354 * compute pipe bpp is set to false for DP MST DSC case 2355 * and compressed_bpp is calculated same time once 2356 * vpci timeslots are allocated, because overall bpp 2357 * calculation procedure is bit different for MST case. 2358 */ 2359 if (compute_pipe_bpp) { 2360 if (intel_dp_is_edp(intel_dp)) 2361 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2362 conn_state, limits); 2363 else 2364 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2365 conn_state, limits, timeslots); 2366 if (ret) { 2367 drm_dbg_kms(display->drm, 2368 "No Valid pipe bpp for given mode ret = %d\n", ret); 2369 return ret; 2370 } 2371 } 2372 2373 /* Calculate Slice count */ 2374 if (intel_dp_is_edp(intel_dp)) { 2375 pipe_config->dsc.slice_count = 2376 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 2377 true); 2378 if (!pipe_config->dsc.slice_count) { 2379 drm_dbg_kms(display->drm, 2380 "Unsupported Slice Count %d\n", 2381 pipe_config->dsc.slice_count); 2382 return -EINVAL; 2383 } 2384 } else { 2385 u8 dsc_dp_slice_count; 2386 2387 dsc_dp_slice_count = 2388 intel_dp_dsc_get_slice_count(connector, 2389 adjusted_mode->crtc_clock, 2390 adjusted_mode->crtc_hdisplay, 2391 num_joined_pipes); 2392 if (!dsc_dp_slice_count) { 2393 drm_dbg_kms(display->drm, 2394 "Compressed Slice Count not supported\n"); 2395 return -EINVAL; 2396 } 2397 2398 pipe_config->dsc.slice_count = dsc_dp_slice_count; 2399 } 2400 /* 2401 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate 2402 * is greater than the maximum Cdclock and if slice count is even 2403 * then we need to use 2 VDSC instances. 2404 * In case of Ultrajoiner along with 12 slices we need to use 3 2405 * VDSC instances. 2406 */ 2407 if (pipe_config->joiner_pipes && num_joined_pipes == 4 && 2408 pipe_config->dsc.slice_count == 12) 2409 pipe_config->dsc.num_streams = 3; 2410 else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) 2411 pipe_config->dsc.num_streams = 2; 2412 else 2413 pipe_config->dsc.num_streams = 1; 2414 2415 ret = intel_dp_dsc_compute_params(connector, pipe_config); 2416 if (ret < 0) { 2417 drm_dbg_kms(display->drm, 2418 "Cannot compute valid DSC parameters for Input Bpp = %d" 2419 "Compressed BPP = " FXP_Q4_FMT "\n", 2420 pipe_config->pipe_bpp, 2421 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16)); 2422 return ret; 2423 } 2424 2425 pipe_config->dsc.compression_enable = true; 2426 drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d " 2427 "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n", 2428 pipe_config->pipe_bpp, 2429 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2430 pipe_config->dsc.slice_count); 2431 2432 return 0; 2433 } 2434 2435 /* 2436 * Calculate the output link min, max bpp values in limits based on the pipe bpp 2437 * range, crtc_state and dsc mode. Return true on success. 2438 */ 2439 static bool 2440 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, 2441 const struct intel_connector *connector, 2442 const struct intel_crtc_state *crtc_state, 2443 bool dsc, 2444 struct link_config_limits *limits) 2445 { 2446 struct intel_display *display = to_intel_display(intel_dp); 2447 const struct drm_display_mode *adjusted_mode = 2448 &crtc_state->hw.adjusted_mode; 2449 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2450 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2451 int max_link_bpp_x16; 2452 2453 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, 2454 fxp_q4_from_int(limits->pipe.max_bpp)); 2455 2456 if (!dsc) { 2457 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3)); 2458 2459 if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp)) 2460 return false; 2461 2462 limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp); 2463 } else { 2464 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; 2465 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; 2466 2467 dsc_src_min_bpp = dsc_src_min_compressed_bpp(); 2468 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state); 2469 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 2470 limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); 2471 2472 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2473 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, 2474 crtc_state, 2475 limits->pipe.max_bpp / 3); 2476 dsc_max_bpp = dsc_sink_max_bpp ? 2477 min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; 2478 2479 max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp)); 2480 } 2481 2482 limits->link.max_bpp_x16 = max_link_bpp_x16; 2483 2484 drm_dbg_kms(display->drm, 2485 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n", 2486 encoder->base.base.id, encoder->base.name, 2487 crtc->base.base.id, crtc->base.name, 2488 adjusted_mode->crtc_clock, 2489 str_on_off(dsc), 2490 limits->max_lane_count, 2491 limits->max_rate, 2492 limits->pipe.max_bpp, 2493 FXP_Q4_ARGS(limits->link.max_bpp_x16)); 2494 2495 return true; 2496 } 2497 2498 static void 2499 intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp, 2500 struct link_config_limits *limits) 2501 { 2502 struct intel_display *display = to_intel_display(intel_dp); 2503 int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(); 2504 int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 2505 2506 limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); 2507 limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); 2508 } 2509 2510 bool 2511 intel_dp_compute_config_limits(struct intel_dp *intel_dp, 2512 struct intel_crtc_state *crtc_state, 2513 bool respect_downstream_limits, 2514 bool dsc, 2515 struct link_config_limits *limits) 2516 { 2517 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2518 2519 limits->min_rate = intel_dp_min_link_rate(intel_dp); 2520 limits->max_rate = intel_dp_max_link_rate(intel_dp); 2521 2522 /* FIXME 128b/132b SST+DSC support missing */ 2523 if (!is_mst && dsc) 2524 limits->max_rate = min(limits->max_rate, 810000); 2525 limits->min_rate = min(limits->min_rate, limits->max_rate); 2526 2527 limits->min_lane_count = intel_dp_min_lane_count(intel_dp); 2528 limits->max_lane_count = intel_dp_max_lane_count(intel_dp); 2529 2530 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); 2531 if (is_mst) { 2532 /* 2533 * FIXME: If all the streams can't fit into the link with their 2534 * current pipe_bpp we should reduce pipe_bpp across the board 2535 * until things start to fit. Until then we limit to <= 8bpc 2536 * since that's what was hardcoded for all MST streams 2537 * previously. This hack should be removed once we have the 2538 * proper retry logic in place. 2539 */ 2540 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24); 2541 } else { 2542 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, 2543 respect_downstream_limits); 2544 } 2545 2546 if (dsc) 2547 intel_dp_dsc_compute_pipe_bpp_limits(intel_dp, limits); 2548 2549 if (is_mst || intel_dp->use_max_params) { 2550 /* 2551 * For MST we always configure max link bw - the spec doesn't 2552 * seem to suggest we should do otherwise. 2553 * 2554 * Use the maximum clock and number of lanes the eDP panel 2555 * advertizes being capable of in case the initial fast 2556 * optimal params failed us. The panels are generally 2557 * designed to support only a single clock and lane 2558 * configuration, and typically on older panels these 2559 * values correspond to the native resolution of the panel. 2560 */ 2561 limits->min_lane_count = limits->max_lane_count; 2562 limits->min_rate = limits->max_rate; 2563 } 2564 2565 intel_dp_test_compute_config(intel_dp, crtc_state, limits); 2566 2567 return intel_dp_compute_config_link_bpp_limits(intel_dp, 2568 intel_dp->attached_connector, 2569 crtc_state, 2570 dsc, 2571 limits); 2572 } 2573 2574 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state) 2575 { 2576 const struct drm_display_mode *adjusted_mode = 2577 &crtc_state->hw.adjusted_mode; 2578 int bpp = crtc_state->dsc.compression_enable ? 2579 fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) : 2580 crtc_state->pipe_bpp; 2581 2582 return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); 2583 } 2584 2585 bool intel_dp_joiner_needs_dsc(struct intel_display *display, 2586 int num_joined_pipes) 2587 { 2588 /* 2589 * Pipe joiner needs compression up to display 12 due to bandwidth 2590 * limitation. DG2 onwards pipe joiner can be enabled without 2591 * compression. 2592 * Ultrajoiner always needs compression. 2593 */ 2594 return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) || 2595 num_joined_pipes == 4; 2596 } 2597 2598 static int 2599 intel_dp_compute_link_config(struct intel_encoder *encoder, 2600 struct intel_crtc_state *pipe_config, 2601 struct drm_connector_state *conn_state, 2602 bool respect_downstream_limits) 2603 { 2604 struct intel_display *display = to_intel_display(encoder); 2605 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2606 struct intel_connector *connector = 2607 to_intel_connector(conn_state->connector); 2608 const struct drm_display_mode *adjusted_mode = 2609 &pipe_config->hw.adjusted_mode; 2610 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2611 struct link_config_limits limits; 2612 bool dsc_needed, joiner_needs_dsc; 2613 int num_joined_pipes; 2614 int ret = 0; 2615 2616 if (pipe_config->fec_enable && 2617 !intel_dp_supports_fec(intel_dp, connector, pipe_config)) 2618 return -EINVAL; 2619 2620 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, 2621 adjusted_mode->crtc_hdisplay, 2622 adjusted_mode->crtc_clock); 2623 if (num_joined_pipes > 1) 2624 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe); 2625 2626 joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes); 2627 2628 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || 2629 !intel_dp_compute_config_limits(intel_dp, pipe_config, 2630 respect_downstream_limits, 2631 false, 2632 &limits); 2633 2634 if (!dsc_needed) { 2635 /* 2636 * Optimize for slow and wide for everything, because there are some 2637 * eDP 1.3 and 1.4 panels don't work well with fast and narrow. 2638 */ 2639 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, 2640 conn_state, &limits); 2641 if (!ret && intel_dp_is_uhbr(pipe_config)) 2642 ret = intel_dp_mtp_tu_compute_config(intel_dp, 2643 pipe_config, 2644 pipe_config->pipe_bpp, 2645 pipe_config->pipe_bpp, 2646 conn_state, 2647 0, false); 2648 if (ret) 2649 dsc_needed = true; 2650 } 2651 2652 if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) { 2653 drm_dbg_kms(display->drm, "DSC required but not available\n"); 2654 return -EINVAL; 2655 } 2656 2657 if (dsc_needed) { 2658 drm_dbg_kms(display->drm, 2659 "Try DSC (fallback=%s, joiner=%s, force=%s)\n", 2660 str_yes_no(ret), str_yes_no(joiner_needs_dsc), 2661 str_yes_no(intel_dp->force_dsc_en)); 2662 2663 if (!intel_dp_compute_config_limits(intel_dp, pipe_config, 2664 respect_downstream_limits, 2665 true, 2666 &limits)) 2667 return -EINVAL; 2668 2669 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 2670 conn_state, &limits, 64, true); 2671 if (ret < 0) 2672 return ret; 2673 } 2674 2675 drm_dbg_kms(display->drm, 2676 "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n", 2677 pipe_config->lane_count, pipe_config->port_clock, 2678 pipe_config->pipe_bpp, 2679 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2680 intel_dp_config_required_rate(pipe_config), 2681 intel_dp_max_link_data_rate(intel_dp, 2682 pipe_config->port_clock, 2683 pipe_config->lane_count)); 2684 2685 return 0; 2686 } 2687 2688 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 2689 const struct drm_connector_state *conn_state) 2690 { 2691 const struct intel_digital_connector_state *intel_conn_state = 2692 to_intel_digital_connector_state(conn_state); 2693 const struct drm_display_mode *adjusted_mode = 2694 &crtc_state->hw.adjusted_mode; 2695 2696 /* 2697 * Our YCbCr output is always limited range. 2698 * crtc_state->limited_color_range only applies to RGB, 2699 * and it must never be set for YCbCr or we risk setting 2700 * some conflicting bits in TRANSCONF which will mess up 2701 * the colors on the monitor. 2702 */ 2703 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2704 return false; 2705 2706 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2707 /* 2708 * See: 2709 * CEA-861-E - 5.1 Default Encoding Parameters 2710 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 2711 */ 2712 return crtc_state->pipe_bpp != 18 && 2713 drm_default_rgb_quant_range(adjusted_mode) == 2714 HDMI_QUANTIZATION_RANGE_LIMITED; 2715 } else { 2716 return intel_conn_state->broadcast_rgb == 2717 INTEL_BROADCAST_RGB_LIMITED; 2718 } 2719 } 2720 2721 static bool intel_dp_port_has_audio(struct intel_display *display, enum port port) 2722 { 2723 if (display->platform.g4x) 2724 return false; 2725 if (DISPLAY_VER(display) < 12 && port == PORT_A) 2726 return false; 2727 2728 return true; 2729 } 2730 2731 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, 2732 const struct drm_connector_state *conn_state, 2733 struct drm_dp_vsc_sdp *vsc) 2734 { 2735 struct intel_display *display = to_intel_display(crtc_state); 2736 2737 if (crtc_state->has_panel_replay) { 2738 /* 2739 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2740 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel 2741 * Encoding/Colorimetry Format indication. 2742 */ 2743 vsc->revision = 0x7; 2744 } else { 2745 /* 2746 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2747 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ 2748 * Colorimetry Format indication. 2749 */ 2750 vsc->revision = 0x5; 2751 } 2752 2753 vsc->length = 0x13; 2754 2755 /* DP 1.4a spec, Table 2-120 */ 2756 switch (crtc_state->output_format) { 2757 case INTEL_OUTPUT_FORMAT_YCBCR444: 2758 vsc->pixelformat = DP_PIXELFORMAT_YUV444; 2759 break; 2760 case INTEL_OUTPUT_FORMAT_YCBCR420: 2761 vsc->pixelformat = DP_PIXELFORMAT_YUV420; 2762 break; 2763 case INTEL_OUTPUT_FORMAT_RGB: 2764 default: 2765 vsc->pixelformat = DP_PIXELFORMAT_RGB; 2766 } 2767 2768 switch (conn_state->colorspace) { 2769 case DRM_MODE_COLORIMETRY_BT709_YCC: 2770 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2771 break; 2772 case DRM_MODE_COLORIMETRY_XVYCC_601: 2773 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; 2774 break; 2775 case DRM_MODE_COLORIMETRY_XVYCC_709: 2776 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; 2777 break; 2778 case DRM_MODE_COLORIMETRY_SYCC_601: 2779 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; 2780 break; 2781 case DRM_MODE_COLORIMETRY_OPYCC_601: 2782 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; 2783 break; 2784 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 2785 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; 2786 break; 2787 case DRM_MODE_COLORIMETRY_BT2020_RGB: 2788 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; 2789 break; 2790 case DRM_MODE_COLORIMETRY_BT2020_YCC: 2791 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; 2792 break; 2793 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 2794 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 2795 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; 2796 break; 2797 default: 2798 /* 2799 * RGB->YCBCR color conversion uses the BT.709 2800 * color space. 2801 */ 2802 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2803 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2804 else 2805 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; 2806 break; 2807 } 2808 2809 vsc->bpc = crtc_state->pipe_bpp / 3; 2810 2811 /* only RGB pixelformat supports 6 bpc */ 2812 drm_WARN_ON(display->drm, 2813 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); 2814 2815 /* all YCbCr are always limited range */ 2816 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; 2817 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; 2818 } 2819 2820 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, 2821 struct intel_crtc_state *crtc_state) 2822 { 2823 struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; 2824 const struct drm_display_mode *adjusted_mode = 2825 &crtc_state->hw.adjusted_mode; 2826 2827 if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported) 2828 return; 2829 2830 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); 2831 2832 /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */ 2833 as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; 2834 as_sdp->length = 0x9; 2835 as_sdp->duration_incr_ms = 0; 2836 2837 if (crtc_state->cmrr.enable) { 2838 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; 2839 as_sdp->vtotal = adjusted_mode->vtotal; 2840 as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode); 2841 as_sdp->target_rr_divider = true; 2842 } else { 2843 as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; 2844 as_sdp->vtotal = adjusted_mode->vtotal; 2845 as_sdp->target_rr = 0; 2846 } 2847 } 2848 2849 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, 2850 struct intel_crtc_state *crtc_state, 2851 const struct drm_connector_state *conn_state) 2852 { 2853 struct drm_dp_vsc_sdp *vsc; 2854 2855 if ((!intel_dp->colorimetry_support || 2856 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) && 2857 !crtc_state->has_psr) 2858 return; 2859 2860 vsc = &crtc_state->infoframes.vsc; 2861 2862 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 2863 vsc->sdp_type = DP_SDP_VSC; 2864 2865 /* Needs colorimetry */ 2866 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { 2867 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 2868 vsc); 2869 } else if (crtc_state->has_panel_replay) { 2870 /* 2871 * [Panel Replay without colorimetry info] 2872 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2873 * VSC SDP supporting 3D stereo + Panel Replay. 2874 */ 2875 vsc->revision = 0x6; 2876 vsc->length = 0x10; 2877 } else if (crtc_state->has_sel_update) { 2878 /* 2879 * [PSR2 without colorimetry] 2880 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 2881 * 3D stereo + PSR/PSR2 + Y-coordinate. 2882 */ 2883 vsc->revision = 0x4; 2884 vsc->length = 0xe; 2885 } else { 2886 /* 2887 * [PSR1] 2888 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2889 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or 2890 * higher). 2891 */ 2892 vsc->revision = 0x2; 2893 vsc->length = 0x8; 2894 } 2895 } 2896 2897 static void 2898 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, 2899 struct intel_crtc_state *crtc_state, 2900 const struct drm_connector_state *conn_state) 2901 { 2902 struct intel_display *display = to_intel_display(intel_dp); 2903 int ret; 2904 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; 2905 2906 if (!conn_state->hdr_output_metadata) 2907 return; 2908 2909 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); 2910 2911 if (ret) { 2912 drm_dbg_kms(display->drm, 2913 "couldn't set HDR metadata in infoframe\n"); 2914 return; 2915 } 2916 2917 crtc_state->infoframes.enable |= 2918 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 2919 } 2920 2921 static bool can_enable_drrs(struct intel_connector *connector, 2922 const struct intel_crtc_state *pipe_config, 2923 const struct drm_display_mode *downclock_mode) 2924 { 2925 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2926 2927 if (pipe_config->vrr.enable) 2928 return false; 2929 2930 /* 2931 * DRRS and PSR can't be enable together, so giving preference to PSR 2932 * as it allows more power-savings by complete shutting down display, 2933 * so to guarantee this, intel_drrs_compute_config() must be called 2934 * after intel_psr_compute_config(). 2935 */ 2936 if (pipe_config->has_psr) 2937 return false; 2938 2939 /* FIXME missing FDI M2/N2 etc. */ 2940 if (pipe_config->has_pch_encoder) 2941 return false; 2942 2943 if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder)) 2944 return false; 2945 2946 return downclock_mode && 2947 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 2948 } 2949 2950 static void 2951 intel_dp_drrs_compute_config(struct intel_connector *connector, 2952 struct intel_crtc_state *pipe_config, 2953 int link_bpp_x16) 2954 { 2955 struct intel_display *display = to_intel_display(connector); 2956 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2957 const struct drm_display_mode *downclock_mode = 2958 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 2959 int pixel_clock; 2960 2961 /* 2962 * FIXME all joined pipes share the same transcoder. 2963 * Need to account for that when updating M/N live. 2964 */ 2965 if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes) 2966 pipe_config->update_m_n = true; 2967 2968 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { 2969 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) 2970 intel_zero_m_n(&pipe_config->dp_m2_n2); 2971 return; 2972 } 2973 2974 if (display->platform.ironlake || display->platform.sandybridge || 2975 display->platform.ivybridge) 2976 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; 2977 2978 pipe_config->has_drrs = true; 2979 2980 pixel_clock = downclock_mode->clock; 2981 if (pipe_config->splitter.enable) 2982 pixel_clock /= pipe_config->splitter.link_count; 2983 2984 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock, 2985 pipe_config->port_clock, 2986 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 2987 &pipe_config->dp_m2_n2); 2988 2989 /* FIXME: abstract this better */ 2990 if (pipe_config->splitter.enable) 2991 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 2992 } 2993 2994 static bool intel_dp_has_audio(struct intel_encoder *encoder, 2995 const struct drm_connector_state *conn_state) 2996 { 2997 struct intel_display *display = to_intel_display(encoder); 2998 const struct intel_digital_connector_state *intel_conn_state = 2999 to_intel_digital_connector_state(conn_state); 3000 struct intel_connector *connector = 3001 to_intel_connector(conn_state->connector); 3002 3003 if (!intel_dp_port_has_audio(display, encoder->port)) 3004 return false; 3005 3006 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 3007 return connector->base.display_info.has_audio; 3008 else 3009 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 3010 } 3011 3012 static int 3013 intel_dp_compute_output_format(struct intel_encoder *encoder, 3014 struct intel_crtc_state *crtc_state, 3015 struct drm_connector_state *conn_state, 3016 bool respect_downstream_limits) 3017 { 3018 struct intel_display *display = to_intel_display(encoder); 3019 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3020 struct intel_connector *connector = intel_dp->attached_connector; 3021 const struct drm_display_info *info = &connector->base.display_info; 3022 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3023 bool ycbcr_420_only; 3024 int ret; 3025 3026 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 3027 3028 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { 3029 drm_dbg_kms(display->drm, 3030 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 3031 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 3032 } else { 3033 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode); 3034 } 3035 3036 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); 3037 3038 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 3039 respect_downstream_limits); 3040 if (ret) { 3041 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3042 !connector->base.ycbcr_420_allowed || 3043 !drm_mode_is_420_also(info, adjusted_mode)) 3044 return ret; 3045 3046 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 3047 crtc_state->output_format = intel_dp_output_format(connector, 3048 crtc_state->sink_format); 3049 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 3050 respect_downstream_limits); 3051 } 3052 3053 return ret; 3054 } 3055 3056 void 3057 intel_dp_audio_compute_config(struct intel_encoder *encoder, 3058 struct intel_crtc_state *pipe_config, 3059 struct drm_connector_state *conn_state) 3060 { 3061 pipe_config->has_audio = 3062 intel_dp_has_audio(encoder, conn_state) && 3063 intel_audio_compute_config(encoder, pipe_config, conn_state); 3064 3065 pipe_config->sdp_split_enable = pipe_config->has_audio && 3066 intel_dp_is_uhbr(pipe_config); 3067 } 3068 3069 static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) 3070 { 3071 struct drm_i915_private *i915 = to_i915(connector->base.dev); 3072 3073 drm_connector_get(&connector->base); 3074 if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work)) 3075 drm_connector_put(&connector->base); 3076 } 3077 3078 void 3079 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, 3080 struct intel_encoder *encoder, 3081 const struct intel_crtc_state *crtc_state) 3082 { 3083 struct intel_connector *connector; 3084 struct intel_digital_connector_state *conn_state; 3085 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3086 int i; 3087 3088 if (intel_dp->needs_modeset_retry) 3089 return; 3090 3091 intel_dp->needs_modeset_retry = true; 3092 3093 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3094 intel_dp_queue_modeset_retry_work(intel_dp->attached_connector); 3095 3096 return; 3097 } 3098 3099 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { 3100 if (!conn_state->base.crtc) 3101 continue; 3102 3103 if (connector->mst_port == intel_dp) 3104 intel_dp_queue_modeset_retry_work(connector); 3105 } 3106 } 3107 3108 int 3109 intel_dp_compute_config(struct intel_encoder *encoder, 3110 struct intel_crtc_state *pipe_config, 3111 struct drm_connector_state *conn_state) 3112 { 3113 struct intel_display *display = to_intel_display(encoder); 3114 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); 3115 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 3116 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3117 const struct drm_display_mode *fixed_mode; 3118 struct intel_connector *connector = intel_dp->attached_connector; 3119 int ret = 0, link_bpp_x16; 3120 3121 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode); 3122 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 3123 ret = intel_panel_compute_config(connector, adjusted_mode); 3124 if (ret) 3125 return ret; 3126 } 3127 3128 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 3129 return -EINVAL; 3130 3131 if (!connector->base.interlace_allowed && 3132 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 3133 return -EINVAL; 3134 3135 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 3136 return -EINVAL; 3137 3138 if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay)) 3139 return -EINVAL; 3140 3141 /* 3142 * Try to respect downstream TMDS clock limits first, if 3143 * that fails assume the user might know something we don't. 3144 */ 3145 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true); 3146 if (ret) 3147 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false); 3148 if (ret) 3149 return ret; 3150 3151 if ((intel_dp_is_edp(intel_dp) && fixed_mode) || 3152 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3153 ret = intel_panel_fitting(pipe_config, conn_state); 3154 if (ret) 3155 return ret; 3156 } 3157 3158 pipe_config->limited_color_range = 3159 intel_dp_limited_color_range(pipe_config, conn_state); 3160 3161 if (intel_dp_is_uhbr(pipe_config)) { 3162 /* 128b/132b SST also needs this */ 3163 pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder; 3164 } else { 3165 pipe_config->enhanced_framing = 3166 drm_dp_enhanced_frame_cap(intel_dp->dpcd); 3167 } 3168 3169 if (pipe_config->dsc.compression_enable) 3170 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; 3171 else 3172 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format, 3173 pipe_config->pipe_bpp)); 3174 3175 if (intel_dp->mso_link_count) { 3176 int n = intel_dp->mso_link_count; 3177 int overlap = intel_dp->mso_pixel_overlap; 3178 3179 pipe_config->splitter.enable = true; 3180 pipe_config->splitter.link_count = n; 3181 pipe_config->splitter.pixel_overlap = overlap; 3182 3183 drm_dbg_kms(display->drm, 3184 "MSO link count %d, pixel overlap %d\n", 3185 n, overlap); 3186 3187 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; 3188 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; 3189 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; 3190 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; 3191 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; 3192 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; 3193 adjusted_mode->crtc_clock /= n; 3194 } 3195 3196 intel_dp_audio_compute_config(encoder, pipe_config, conn_state); 3197 3198 if (!intel_dp_is_uhbr(pipe_config)) { 3199 intel_link_compute_m_n(link_bpp_x16, 3200 pipe_config->lane_count, 3201 adjusted_mode->crtc_clock, 3202 pipe_config->port_clock, 3203 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 3204 &pipe_config->dp_m_n); 3205 } 3206 3207 /* FIXME: abstract this better */ 3208 if (pipe_config->splitter.enable) 3209 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; 3210 3211 intel_vrr_compute_config(pipe_config, conn_state); 3212 intel_dp_compute_as_sdp(intel_dp, pipe_config); 3213 intel_psr_compute_config(intel_dp, pipe_config, conn_state); 3214 intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state); 3215 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); 3216 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); 3217 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); 3218 3219 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector, 3220 pipe_config); 3221 } 3222 3223 void intel_dp_set_link_params(struct intel_dp *intel_dp, 3224 int link_rate, int lane_count) 3225 { 3226 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 3227 intel_dp->link_trained = false; 3228 intel_dp->needs_modeset_retry = false; 3229 intel_dp->link_rate = link_rate; 3230 intel_dp->lane_count = lane_count; 3231 } 3232 3233 void intel_dp_reset_link_params(struct intel_dp *intel_dp) 3234 { 3235 intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); 3236 intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); 3237 intel_dp->link.mst_probed_lane_count = 0; 3238 intel_dp->link.mst_probed_rate = 0; 3239 intel_dp->link.retrain_disabled = false; 3240 intel_dp->link.seq_train_failures = 0; 3241 } 3242 3243 /* Enable backlight PWM and backlight PP control. */ 3244 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 3245 const struct drm_connector_state *conn_state) 3246 { 3247 struct intel_display *display = to_intel_display(crtc_state); 3248 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); 3249 3250 if (!intel_dp_is_edp(intel_dp)) 3251 return; 3252 3253 drm_dbg_kms(display->drm, "\n"); 3254 3255 intel_backlight_enable(crtc_state, conn_state); 3256 intel_pps_backlight_on(intel_dp); 3257 } 3258 3259 /* Disable backlight PP control and backlight PWM. */ 3260 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) 3261 { 3262 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); 3263 struct intel_display *display = to_intel_display(intel_dp); 3264 3265 if (!intel_dp_is_edp(intel_dp)) 3266 return; 3267 3268 drm_dbg_kms(display->drm, "\n"); 3269 3270 intel_pps_backlight_off(intel_dp); 3271 intel_backlight_disable(old_conn_state); 3272 } 3273 3274 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) 3275 { 3276 /* 3277 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus 3278 * be capable of signalling downstream hpd with a long pulse. 3279 * Whether or not that means D3 is safe to use is not clear, 3280 * but let's assume so until proven otherwise. 3281 * 3282 * FIXME should really check all downstream ports... 3283 */ 3284 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 3285 drm_dp_is_branch(intel_dp->dpcd) && 3286 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; 3287 } 3288 3289 static int 3290 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set) 3291 { 3292 int err; 3293 u8 val; 3294 3295 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val); 3296 if (err < 0) 3297 return err; 3298 3299 if (set) 3300 val |= flag; 3301 else 3302 val &= ~flag; 3303 3304 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val); 3305 } 3306 3307 static void 3308 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, 3309 bool enable) 3310 { 3311 struct intel_display *display = to_intel_display(connector); 3312 3313 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux, 3314 DP_DECOMPRESSION_EN, enable) < 0) 3315 drm_dbg_kms(display->drm, 3316 "Failed to %s sink decompression state\n", 3317 str_enable_disable(enable)); 3318 } 3319 3320 static void 3321 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, 3322 bool enable) 3323 { 3324 struct intel_display *display = to_intel_display(connector); 3325 struct drm_dp_aux *aux = connector->port ? 3326 connector->port->passthrough_aux : NULL; 3327 3328 if (!aux) 3329 return; 3330 3331 if (write_dsc_decompression_flag(aux, 3332 DP_DSC_PASSTHROUGH_EN, enable) < 0) 3333 drm_dbg_kms(display->drm, 3334 "Failed to %s sink compression passthrough state\n", 3335 str_enable_disable(enable)); 3336 } 3337 3338 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, 3339 const struct intel_connector *connector, 3340 bool for_get_ref) 3341 { 3342 struct intel_display *display = to_intel_display(state); 3343 struct drm_connector *_connector_iter; 3344 struct drm_connector_state *old_conn_state; 3345 struct drm_connector_state *new_conn_state; 3346 int ref_count = 0; 3347 int i; 3348 3349 /* 3350 * On SST the decompression AUX device won't be shared, each connector 3351 * uses for this its own AUX targeting the sink device. 3352 */ 3353 if (!connector->mst_port) 3354 return connector->dp.dsc_decompression_enabled ? 1 : 0; 3355 3356 for_each_oldnew_connector_in_state(&state->base, _connector_iter, 3357 old_conn_state, new_conn_state, i) { 3358 const struct intel_connector * 3359 connector_iter = to_intel_connector(_connector_iter); 3360 3361 if (connector_iter->mst_port != connector->mst_port) 3362 continue; 3363 3364 if (!connector_iter->dp.dsc_decompression_enabled) 3365 continue; 3366 3367 drm_WARN_ON(display->drm, 3368 (for_get_ref && !new_conn_state->crtc) || 3369 (!for_get_ref && !old_conn_state->crtc)); 3370 3371 if (connector_iter->dp.dsc_decompression_aux == 3372 connector->dp.dsc_decompression_aux) 3373 ref_count++; 3374 } 3375 3376 return ref_count; 3377 } 3378 3379 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state, 3380 struct intel_connector *connector) 3381 { 3382 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0; 3383 3384 connector->dp.dsc_decompression_enabled = true; 3385 3386 return ret; 3387 } 3388 3389 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state, 3390 struct intel_connector *connector) 3391 { 3392 connector->dp.dsc_decompression_enabled = false; 3393 3394 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0; 3395 } 3396 3397 /** 3398 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device 3399 * @state: atomic state 3400 * @connector: connector to enable the decompression for 3401 * @new_crtc_state: new state for the CRTC driving @connector 3402 * 3403 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3404 * register of the appropriate sink/branch device. On SST this is always the 3405 * sink device, whereas on MST based on each device's DSC capabilities it's 3406 * either the last branch device (enabling decompression in it) or both the 3407 * last branch device (enabling passthrough in it) and the sink device 3408 * (enabling decompression in it). 3409 */ 3410 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, 3411 struct intel_connector *connector, 3412 const struct intel_crtc_state *new_crtc_state) 3413 { 3414 struct intel_display *display = to_intel_display(state); 3415 3416 if (!new_crtc_state->dsc.compression_enable) 3417 return; 3418 3419 if (drm_WARN_ON(display->drm, 3420 !connector->dp.dsc_decompression_aux || 3421 connector->dp.dsc_decompression_enabled)) 3422 return; 3423 3424 if (!intel_dp_dsc_aux_get_ref(state, connector)) 3425 return; 3426 3427 intel_dp_sink_set_dsc_passthrough(connector, true); 3428 intel_dp_sink_set_dsc_decompression(connector, true); 3429 } 3430 3431 /** 3432 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device 3433 * @state: atomic state 3434 * @connector: connector to disable the decompression for 3435 * @old_crtc_state: old state for the CRTC driving @connector 3436 * 3437 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3438 * register of the appropriate sink/branch device, corresponding to the 3439 * sequence in intel_dp_sink_enable_decompression(). 3440 */ 3441 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, 3442 struct intel_connector *connector, 3443 const struct intel_crtc_state *old_crtc_state) 3444 { 3445 struct intel_display *display = to_intel_display(state); 3446 3447 if (!old_crtc_state->dsc.compression_enable) 3448 return; 3449 3450 if (drm_WARN_ON(display->drm, 3451 !connector->dp.dsc_decompression_aux || 3452 !connector->dp.dsc_decompression_enabled)) 3453 return; 3454 3455 if (!intel_dp_dsc_aux_put_ref(state, connector)) 3456 return; 3457 3458 intel_dp_sink_set_dsc_decompression(connector, false); 3459 intel_dp_sink_set_dsc_passthrough(connector, false); 3460 } 3461 3462 static void 3463 intel_dp_init_source_oui(struct intel_dp *intel_dp) 3464 { 3465 struct intel_display *display = to_intel_display(intel_dp); 3466 u8 oui[] = { 0x00, 0xaa, 0x01 }; 3467 u8 buf[3] = {}; 3468 3469 if (READ_ONCE(intel_dp->oui_valid)) 3470 return; 3471 3472 WRITE_ONCE(intel_dp->oui_valid, true); 3473 3474 /* 3475 * During driver init, we want to be careful and avoid changing the source OUI if it's 3476 * already set to what we want, so as to avoid clearing any state by accident 3477 */ 3478 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) 3479 drm_dbg_kms(display->drm, "Failed to read source OUI\n"); 3480 3481 if (memcmp(oui, buf, sizeof(oui)) == 0) { 3482 /* Assume the OUI was written now. */ 3483 intel_dp->last_oui_write = jiffies; 3484 return; 3485 } 3486 3487 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) { 3488 drm_dbg_kms(display->drm, "Failed to write source OUI\n"); 3489 WRITE_ONCE(intel_dp->oui_valid, false); 3490 } 3491 3492 intel_dp->last_oui_write = jiffies; 3493 } 3494 3495 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp) 3496 { 3497 WRITE_ONCE(intel_dp->oui_valid, false); 3498 } 3499 3500 void intel_dp_wait_source_oui(struct intel_dp *intel_dp) 3501 { 3502 struct intel_display *display = to_intel_display(intel_dp); 3503 struct intel_connector *connector = intel_dp->attached_connector; 3504 3505 drm_dbg_kms(display->drm, 3506 "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n", 3507 connector->base.base.id, connector->base.name, 3508 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3509 3510 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 3511 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3512 } 3513 3514 /* If the device supports it, try to set the power state appropriately */ 3515 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) 3516 { 3517 struct intel_display *display = to_intel_display(intel_dp); 3518 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3519 int ret, i; 3520 3521 /* Should have a valid DPCD by this point */ 3522 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 3523 return; 3524 3525 if (mode != DP_SET_POWER_D0) { 3526 if (downstream_hpd_needs_d0(intel_dp)) 3527 return; 3528 3529 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3530 } else { 3531 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); 3532 3533 lspcon_resume(dp_to_dig_port(intel_dp)); 3534 3535 /* Write the source OUI as early as possible */ 3536 intel_dp_init_source_oui(intel_dp); 3537 3538 /* 3539 * When turning on, we need to retry for 1ms to give the sink 3540 * time to wake up. 3541 */ 3542 for (i = 0; i < 3; i++) { 3543 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3544 if (ret == 1) 3545 break; 3546 msleep(1); 3547 } 3548 3549 if (ret == 1 && lspcon->active) 3550 lspcon_wait_pcon_mode(lspcon); 3551 } 3552 3553 if (ret != 1) 3554 drm_dbg_kms(display->drm, 3555 "[ENCODER:%d:%s] Set power to %s failed\n", 3556 encoder->base.base.id, encoder->base.name, 3557 mode == DP_SET_POWER_D0 ? "D0" : "D3"); 3558 } 3559 3560 static bool 3561 intel_dp_get_dpcd(struct intel_dp *intel_dp); 3562 3563 /** 3564 * intel_dp_sync_state - sync the encoder state during init/resume 3565 * @encoder: intel encoder to sync 3566 * @crtc_state: state for the CRTC connected to the encoder 3567 * 3568 * Sync any state stored in the encoder wrt. HW state during driver init 3569 * and system resume. 3570 */ 3571 void intel_dp_sync_state(struct intel_encoder *encoder, 3572 const struct intel_crtc_state *crtc_state) 3573 { 3574 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3575 bool dpcd_updated = false; 3576 3577 /* 3578 * Don't clobber DPCD if it's been already read out during output 3579 * setup (eDP) or detect. 3580 */ 3581 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) { 3582 intel_dp_get_dpcd(intel_dp); 3583 dpcd_updated = true; 3584 } 3585 3586 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); 3587 3588 if (crtc_state) { 3589 intel_dp_reset_link_params(intel_dp); 3590 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 3591 intel_dp->link_trained = true; 3592 } 3593 } 3594 3595 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 3596 struct intel_crtc_state *crtc_state) 3597 { 3598 struct intel_display *display = to_intel_display(encoder); 3599 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3600 bool fastset = true; 3601 3602 /* 3603 * If BIOS has set an unsupported or non-standard link rate for some 3604 * reason force an encoder recompute and full modeset. 3605 */ 3606 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, 3607 crtc_state->port_clock) < 0) { 3608 drm_dbg_kms(display->drm, 3609 "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n", 3610 encoder->base.base.id, encoder->base.name); 3611 crtc_state->uapi.connectors_changed = true; 3612 fastset = false; 3613 } 3614 3615 /* 3616 * FIXME hack to force full modeset when DSC is being used. 3617 * 3618 * As long as we do not have full state readout and config comparison 3619 * of crtc_state->dsc, we have no way to ensure reliable fastset. 3620 * Remove once we have readout for DSC. 3621 */ 3622 if (crtc_state->dsc.compression_enable) { 3623 drm_dbg_kms(display->drm, 3624 "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n", 3625 encoder->base.base.id, encoder->base.name); 3626 crtc_state->uapi.mode_changed = true; 3627 fastset = false; 3628 } 3629 3630 if (CAN_PANEL_REPLAY(intel_dp)) { 3631 drm_dbg_kms(display->drm, 3632 "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n", 3633 encoder->base.base.id, encoder->base.name); 3634 crtc_state->uapi.mode_changed = true; 3635 fastset = false; 3636 } 3637 3638 return fastset; 3639 } 3640 3641 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) 3642 { 3643 struct intel_display *display = to_intel_display(intel_dp); 3644 3645 /* Clear the cached register set to avoid using stale values */ 3646 3647 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); 3648 3649 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, 3650 intel_dp->pcon_dsc_dpcd, 3651 sizeof(intel_dp->pcon_dsc_dpcd)) < 0) 3652 drm_err(display->drm, "Failed to read DPCD register 0x%x\n", 3653 DP_PCON_DSC_ENCODER); 3654 3655 drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n", 3656 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); 3657 } 3658 3659 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) 3660 { 3661 static const int bw_gbps[] = {9, 18, 24, 32, 40, 48}; 3662 int i; 3663 3664 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { 3665 if (frl_bw_mask & (1 << i)) 3666 return bw_gbps[i]; 3667 } 3668 return 0; 3669 } 3670 3671 static int intel_dp_pcon_set_frl_mask(int max_frl) 3672 { 3673 switch (max_frl) { 3674 case 48: 3675 return DP_PCON_FRL_BW_MASK_48GBPS; 3676 case 40: 3677 return DP_PCON_FRL_BW_MASK_40GBPS; 3678 case 32: 3679 return DP_PCON_FRL_BW_MASK_32GBPS; 3680 case 24: 3681 return DP_PCON_FRL_BW_MASK_24GBPS; 3682 case 18: 3683 return DP_PCON_FRL_BW_MASK_18GBPS; 3684 case 9: 3685 return DP_PCON_FRL_BW_MASK_9GBPS; 3686 } 3687 3688 return 0; 3689 } 3690 3691 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) 3692 { 3693 struct intel_connector *connector = intel_dp->attached_connector; 3694 const struct drm_display_info *info = &connector->base.display_info; 3695 int max_frl_rate; 3696 int max_lanes, rate_per_lane; 3697 int max_dsc_lanes, dsc_rate_per_lane; 3698 3699 max_lanes = info->hdmi.max_lanes; 3700 rate_per_lane = info->hdmi.max_frl_rate_per_lane; 3701 max_frl_rate = max_lanes * rate_per_lane; 3702 3703 if (info->hdmi.dsc_cap.v_1p2) { 3704 max_dsc_lanes = info->hdmi.dsc_cap.max_lanes; 3705 dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane; 3706 if (max_dsc_lanes && dsc_rate_per_lane) 3707 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane); 3708 } 3709 3710 return max_frl_rate; 3711 } 3712 3713 static bool 3714 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp, 3715 u8 max_frl_bw_mask, u8 *frl_trained_mask) 3716 { 3717 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) && 3718 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL && 3719 *frl_trained_mask >= max_frl_bw_mask) 3720 return true; 3721 3722 return false; 3723 } 3724 3725 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) 3726 { 3727 struct intel_display *display = to_intel_display(intel_dp); 3728 #define TIMEOUT_FRL_READY_MS 500 3729 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 3730 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret; 3731 u8 max_frl_bw_mask = 0, frl_trained_mask; 3732 bool is_active; 3733 3734 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 3735 drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); 3736 3737 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp); 3738 drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n", 3739 max_edid_frl_bw); 3740 3741 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw); 3742 3743 if (max_frl_bw <= 0) 3744 return -EINVAL; 3745 3746 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); 3747 drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask); 3748 3749 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask)) 3750 goto frl_trained; 3751 3752 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); 3753 if (ret < 0) 3754 return ret; 3755 /* Wait for PCON to be FRL Ready */ 3756 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS); 3757 3758 if (!is_active) 3759 return -ETIMEDOUT; 3760 3761 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, 3762 DP_PCON_ENABLE_SEQUENTIAL_LINK); 3763 if (ret < 0) 3764 return ret; 3765 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, 3766 DP_PCON_FRL_LINK_TRAIN_NORMAL); 3767 if (ret < 0) 3768 return ret; 3769 ret = drm_dp_pcon_frl_enable(&intel_dp->aux); 3770 if (ret < 0) 3771 return ret; 3772 /* 3773 * Wait for FRL to be completed 3774 * Check if the HDMI Link is up and active. 3775 */ 3776 wait_for(is_active = 3777 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask), 3778 TIMEOUT_HDMI_LINK_ACTIVE_MS); 3779 3780 if (!is_active) 3781 return -ETIMEDOUT; 3782 3783 frl_trained: 3784 drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask); 3785 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); 3786 intel_dp->frl.is_trained = true; 3787 drm_dbg(display->drm, "FRL trained with : %d Gbps\n", 3788 intel_dp->frl.trained_rate_gbps); 3789 3790 return 0; 3791 } 3792 3793 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) 3794 { 3795 if (drm_dp_is_branch(intel_dp->dpcd) && 3796 intel_dp_has_hdmi_sink(intel_dp) && 3797 intel_dp_hdmi_sink_max_frl(intel_dp) > 0) 3798 return true; 3799 3800 return false; 3801 } 3802 3803 static 3804 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp) 3805 { 3806 int ret; 3807 u8 buf = 0; 3808 3809 /* Set PCON source control mode */ 3810 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE; 3811 3812 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3813 if (ret < 0) 3814 return ret; 3815 3816 /* Set HDMI LINK ENABLE */ 3817 buf |= DP_PCON_ENABLE_HDMI_LINK; 3818 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3819 if (ret < 0) 3820 return ret; 3821 3822 return 0; 3823 } 3824 3825 void intel_dp_check_frl_training(struct intel_dp *intel_dp) 3826 { 3827 struct intel_display *display = to_intel_display(intel_dp); 3828 3829 /* 3830 * Always go for FRL training if: 3831 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) 3832 * -sink is HDMI2.1 3833 */ 3834 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || 3835 !intel_dp_is_hdmi_2_1_sink(intel_dp) || 3836 intel_dp->frl.is_trained) 3837 return; 3838 3839 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) { 3840 int ret, mode; 3841 3842 drm_dbg(display->drm, 3843 "Couldn't set FRL mode, continuing with TMDS mode\n"); 3844 ret = intel_dp_pcon_set_tmds_mode(intel_dp); 3845 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); 3846 3847 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS) 3848 drm_dbg(display->drm, 3849 "Issue with PCON, cannot set TMDS mode\n"); 3850 } else { 3851 drm_dbg(display->drm, "FRL training Completed\n"); 3852 } 3853 } 3854 3855 static int 3856 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state) 3857 { 3858 int vactive = crtc_state->hw.adjusted_mode.vdisplay; 3859 3860 return intel_hdmi_dsc_get_slice_height(vactive); 3861 } 3862 3863 static int 3864 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, 3865 const struct intel_crtc_state *crtc_state) 3866 { 3867 struct intel_connector *connector = intel_dp->attached_connector; 3868 const struct drm_display_info *info = &connector->base.display_info; 3869 int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice; 3870 int hdmi_max_slices = info->hdmi.dsc_cap.max_slices; 3871 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); 3872 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); 3873 3874 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, 3875 pcon_max_slice_width, 3876 hdmi_max_slices, hdmi_throughput); 3877 } 3878 3879 static int 3880 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, 3881 const struct intel_crtc_state *crtc_state, 3882 int num_slices, int slice_width) 3883 { 3884 struct intel_connector *connector = intel_dp->attached_connector; 3885 const struct drm_display_info *info = &connector->base.display_info; 3886 int output_format = crtc_state->output_format; 3887 bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp; 3888 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); 3889 int hdmi_max_chunk_bytes = 3890 info->hdmi.dsc_cap.total_chunk_kbytes * 1024; 3891 3892 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, 3893 num_slices, output_format, hdmi_all_bpp, 3894 hdmi_max_chunk_bytes); 3895 } 3896 3897 void 3898 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 3899 const struct intel_crtc_state *crtc_state) 3900 { 3901 struct intel_display *display = to_intel_display(intel_dp); 3902 struct intel_connector *connector = intel_dp->attached_connector; 3903 const struct drm_display_info *info; 3904 u8 pps_param[6]; 3905 int slice_height; 3906 int slice_width; 3907 int num_slices; 3908 int bits_per_pixel; 3909 int ret; 3910 bool hdmi_is_dsc_1_2; 3911 3912 if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) 3913 return; 3914 3915 if (!connector) 3916 return; 3917 3918 info = &connector->base.display_info; 3919 3920 hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2; 3921 3922 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || 3923 !hdmi_is_dsc_1_2) 3924 return; 3925 3926 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); 3927 if (!slice_height) 3928 return; 3929 3930 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); 3931 if (!num_slices) 3932 return; 3933 3934 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, 3935 num_slices); 3936 3937 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, 3938 num_slices, slice_width); 3939 if (!bits_per_pixel) 3940 return; 3941 3942 pps_param[0] = slice_height & 0xFF; 3943 pps_param[1] = slice_height >> 8; 3944 pps_param[2] = slice_width & 0xFF; 3945 pps_param[3] = slice_width >> 8; 3946 pps_param[4] = bits_per_pixel & 0xFF; 3947 pps_param[5] = (bits_per_pixel >> 8) & 0x3; 3948 3949 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); 3950 if (ret < 0) 3951 drm_dbg_kms(display->drm, "Failed to set pcon DSC\n"); 3952 } 3953 3954 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 3955 const struct intel_crtc_state *crtc_state) 3956 { 3957 struct intel_display *display = to_intel_display(intel_dp); 3958 bool ycbcr444_to_420 = false; 3959 bool rgb_to_ycbcr = false; 3960 u8 tmp; 3961 3962 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) 3963 return; 3964 3965 if (!drm_dp_is_branch(intel_dp->dpcd)) 3966 return; 3967 3968 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0; 3969 3970 if (drm_dp_dpcd_writeb(&intel_dp->aux, 3971 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) 3972 drm_dbg_kms(display->drm, 3973 "Failed to %s protocol converter HDMI mode\n", 3974 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp))); 3975 3976 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3977 switch (crtc_state->output_format) { 3978 case INTEL_OUTPUT_FORMAT_YCBCR420: 3979 break; 3980 case INTEL_OUTPUT_FORMAT_YCBCR444: 3981 ycbcr444_to_420 = true; 3982 break; 3983 case INTEL_OUTPUT_FORMAT_RGB: 3984 rgb_to_ycbcr = true; 3985 ycbcr444_to_420 = true; 3986 break; 3987 default: 3988 MISSING_CASE(crtc_state->output_format); 3989 break; 3990 } 3991 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 3992 switch (crtc_state->output_format) { 3993 case INTEL_OUTPUT_FORMAT_YCBCR444: 3994 break; 3995 case INTEL_OUTPUT_FORMAT_RGB: 3996 rgb_to_ycbcr = true; 3997 break; 3998 default: 3999 MISSING_CASE(crtc_state->output_format); 4000 break; 4001 } 4002 } 4003 4004 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; 4005 4006 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4007 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) 4008 drm_dbg_kms(display->drm, 4009 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", 4010 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); 4011 4012 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; 4013 4014 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) 4015 drm_dbg_kms(display->drm, 4016 "Failed to %s protocol converter RGB->YCbCr conversion mode\n", 4017 str_enable_disable(tmp)); 4018 } 4019 4020 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) 4021 { 4022 u8 dprx = 0; 4023 4024 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 4025 &dprx) != 1) 4026 return false; 4027 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; 4028 } 4029 4030 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, 4031 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 4032 { 4033 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, 4034 DP_DSC_RECEIVER_CAP_SIZE) < 0) { 4035 drm_err(aux->drm_dev, 4036 "Failed to read DPCD register 0x%x\n", 4037 DP_DSC_SUPPORT); 4038 return; 4039 } 4040 4041 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", 4042 DP_DSC_RECEIVER_CAP_SIZE, 4043 dsc_dpcd); 4044 } 4045 4046 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector) 4047 { 4048 struct intel_display *display = to_intel_display(connector); 4049 4050 /* 4051 * Clear the cached register set to avoid using stale values 4052 * for the sinks that do not support DSC. 4053 */ 4054 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 4055 4056 /* Clear fec_capable to avoid using stale values */ 4057 connector->dp.fec_capability = 0; 4058 4059 if (dpcd_rev < DP_DPCD_REV_14) 4060 return; 4061 4062 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, 4063 connector->dp.dsc_dpcd); 4064 4065 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, 4066 &connector->dp.fec_capability) < 0) { 4067 drm_err(display->drm, "Failed to read FEC DPCD register\n"); 4068 return; 4069 } 4070 4071 drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n", 4072 connector->dp.fec_capability); 4073 } 4074 4075 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) 4076 { 4077 if (edp_dpcd_rev < DP_EDP_14) 4078 return; 4079 4080 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); 4081 } 4082 4083 static void 4084 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) 4085 { 4086 struct intel_display *display = to_intel_display(intel_dp); 4087 4088 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ 4089 if (!HAS_DSC(display)) 4090 return; 4091 4092 if (intel_dp_is_edp(intel_dp)) 4093 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], 4094 connector); 4095 else 4096 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], 4097 connector); 4098 } 4099 4100 static void intel_edp_mso_mode_fixup(struct intel_connector *connector, 4101 struct drm_display_mode *mode) 4102 { 4103 struct intel_display *display = to_intel_display(connector); 4104 struct intel_dp *intel_dp = intel_attached_dp(connector); 4105 int n = intel_dp->mso_link_count; 4106 int overlap = intel_dp->mso_pixel_overlap; 4107 4108 if (!mode || !n) 4109 return; 4110 4111 mode->hdisplay = (mode->hdisplay - overlap) * n; 4112 mode->hsync_start = (mode->hsync_start - overlap) * n; 4113 mode->hsync_end = (mode->hsync_end - overlap) * n; 4114 mode->htotal = (mode->htotal - overlap) * n; 4115 mode->clock *= n; 4116 4117 drm_mode_set_name(mode); 4118 4119 drm_dbg_kms(display->drm, 4120 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n", 4121 connector->base.base.id, connector->base.name, 4122 DRM_MODE_ARG(mode)); 4123 } 4124 4125 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) 4126 { 4127 struct intel_display *display = to_intel_display(encoder); 4128 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4129 struct intel_connector *connector = intel_dp->attached_connector; 4130 4131 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { 4132 /* 4133 * This is a big fat ugly hack. 4134 * 4135 * Some machines in UEFI boot mode provide us a VBT that has 18 4136 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4137 * unknown we fail to light up. Yet the same BIOS boots up with 4138 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4139 * max, not what it tells us to use. 4140 * 4141 * Note: This will still be broken if the eDP panel is not lit 4142 * up by the BIOS, and thus we can't get the mode at module 4143 * load. 4144 */ 4145 drm_dbg_kms(display->drm, 4146 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4147 pipe_bpp, connector->panel.vbt.edp.bpp); 4148 connector->panel.vbt.edp.bpp = pipe_bpp; 4149 } 4150 } 4151 4152 static void intel_edp_mso_init(struct intel_dp *intel_dp) 4153 { 4154 struct intel_display *display = to_intel_display(intel_dp); 4155 struct intel_connector *connector = intel_dp->attached_connector; 4156 struct drm_display_info *info = &connector->base.display_info; 4157 u8 mso; 4158 4159 if (intel_dp->edp_dpcd[0] < DP_EDP_14) 4160 return; 4161 4162 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { 4163 drm_err(display->drm, "Failed to read MSO cap\n"); 4164 return; 4165 } 4166 4167 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ 4168 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; 4169 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { 4170 drm_err(display->drm, "Invalid MSO link count cap %u\n", mso); 4171 mso = 0; 4172 } 4173 4174 if (mso) { 4175 drm_dbg_kms(display->drm, 4176 "Sink MSO %ux%u configuration, pixel overlap %u\n", 4177 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, 4178 info->mso_pixel_overlap); 4179 if (!HAS_MSO(display)) { 4180 drm_err(display->drm, 4181 "No source MSO support, disabling\n"); 4182 mso = 0; 4183 } 4184 } 4185 4186 intel_dp->mso_link_count = mso; 4187 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; 4188 } 4189 4190 static void 4191 intel_edp_set_sink_rates(struct intel_dp *intel_dp) 4192 { 4193 intel_dp->num_sink_rates = 0; 4194 4195 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { 4196 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 4197 int i; 4198 4199 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 4200 sink_rates, sizeof(sink_rates)); 4201 4202 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 4203 int val = le16_to_cpu(sink_rates[i]); 4204 4205 if (val == 0) 4206 break; 4207 4208 /* Value read multiplied by 200kHz gives the per-lane 4209 * link rate in kHz. The source rates are, however, 4210 * stored in terms of LS_Clk kHz. The full conversion 4211 * back to symbols is 4212 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) 4213 */ 4214 intel_dp->sink_rates[i] = (val * 200) / 10; 4215 } 4216 intel_dp->num_sink_rates = i; 4217 } 4218 4219 /* 4220 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, 4221 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. 4222 */ 4223 if (intel_dp->num_sink_rates) 4224 intel_dp->use_rate_select = true; 4225 else 4226 intel_dp_set_sink_rates(intel_dp); 4227 } 4228 4229 static bool 4230 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 4231 { 4232 struct intel_display *display = to_intel_display(intel_dp); 4233 4234 /* this function is meant to be called only once */ 4235 drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); 4236 4237 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) 4238 return false; 4239 4240 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4241 drm_dp_is_branch(intel_dp->dpcd)); 4242 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4243 4244 intel_dp->colorimetry_support = 4245 intel_dp_get_colorimetry_status(intel_dp); 4246 4247 /* 4248 * Read the eDP display control registers. 4249 * 4250 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in 4251 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it 4252 * set, but require eDP 1.4+ detection (e.g. for supported link rates 4253 * method). The display control registers should read zero if they're 4254 * not supported anyway. 4255 */ 4256 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 4257 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 4258 sizeof(intel_dp->edp_dpcd)) { 4259 drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n", 4260 (int)sizeof(intel_dp->edp_dpcd), 4261 intel_dp->edp_dpcd); 4262 4263 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; 4264 } 4265 4266 /* 4267 * If needed, program our source OUI so we can make various Intel-specific AUX services 4268 * available (such as HDR backlight controls) 4269 */ 4270 intel_dp_init_source_oui(intel_dp); 4271 4272 /* 4273 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 4274 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 4275 */ 4276 intel_psr_init_dpcd(intel_dp); 4277 4278 intel_edp_set_sink_rates(intel_dp); 4279 intel_dp_set_max_sink_lane_count(intel_dp); 4280 4281 /* Read the eDP DSC DPCD registers */ 4282 intel_dp_detect_dsc_caps(intel_dp, connector); 4283 4284 return true; 4285 } 4286 4287 static bool 4288 intel_dp_has_sink_count(struct intel_dp *intel_dp) 4289 { 4290 if (!intel_dp->attached_connector) 4291 return false; 4292 4293 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, 4294 intel_dp->dpcd, 4295 &intel_dp->desc); 4296 } 4297 4298 void intel_dp_update_sink_caps(struct intel_dp *intel_dp) 4299 { 4300 intel_dp_set_sink_rates(intel_dp); 4301 intel_dp_set_max_sink_lane_count(intel_dp); 4302 intel_dp_set_common_rates(intel_dp); 4303 } 4304 4305 static bool 4306 intel_dp_get_dpcd(struct intel_dp *intel_dp) 4307 { 4308 int ret; 4309 4310 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) 4311 return false; 4312 4313 /* 4314 * Don't clobber cached eDP rates. Also skip re-reading 4315 * the OUI/ID since we know it won't change. 4316 */ 4317 if (!intel_dp_is_edp(intel_dp)) { 4318 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4319 drm_dp_is_branch(intel_dp->dpcd)); 4320 4321 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4322 4323 intel_dp->colorimetry_support = 4324 intel_dp_get_colorimetry_status(intel_dp); 4325 4326 intel_dp_update_sink_caps(intel_dp); 4327 } 4328 4329 if (intel_dp_has_sink_count(intel_dp)) { 4330 ret = drm_dp_read_sink_count(&intel_dp->aux); 4331 if (ret < 0) 4332 return false; 4333 4334 /* 4335 * Sink count can change between short pulse hpd hence 4336 * a member variable in intel_dp will track any changes 4337 * between short pulse interrupts. 4338 */ 4339 intel_dp->sink_count = ret; 4340 4341 /* 4342 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 4343 * a dongle is present but no display. Unless we require to know 4344 * if a dongle is present or not, we don't need to update 4345 * downstream port information. So, an early return here saves 4346 * time from performing other operations which are not required. 4347 */ 4348 if (!intel_dp->sink_count) 4349 return false; 4350 } 4351 4352 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, 4353 intel_dp->downstream_ports) == 0; 4354 } 4355 4356 static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode) 4357 { 4358 if (mst_mode == DRM_DP_MST) 4359 return "MST"; 4360 else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG) 4361 return "SST w/ sideband messaging"; 4362 else 4363 return "SST"; 4364 } 4365 4366 static enum drm_dp_mst_mode 4367 intel_dp_mst_mode_choose(struct intel_dp *intel_dp, 4368 enum drm_dp_mst_mode sink_mst_mode) 4369 { 4370 struct intel_display *display = to_intel_display(intel_dp); 4371 4372 if (!display->params.enable_dp_mst) 4373 return DRM_DP_SST; 4374 4375 if (!intel_dp_mst_source_support(intel_dp)) 4376 return DRM_DP_SST; 4377 4378 if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG && 4379 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)) 4380 return DRM_DP_SST; 4381 4382 return sink_mst_mode; 4383 } 4384 4385 static enum drm_dp_mst_mode 4386 intel_dp_mst_detect(struct intel_dp *intel_dp) 4387 { 4388 struct intel_display *display = to_intel_display(intel_dp); 4389 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4390 enum drm_dp_mst_mode sink_mst_mode; 4391 enum drm_dp_mst_mode mst_detect; 4392 4393 sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 4394 4395 mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode); 4396 4397 drm_dbg_kms(display->drm, 4398 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n", 4399 encoder->base.base.id, encoder->base.name, 4400 str_yes_no(intel_dp_mst_source_support(intel_dp)), 4401 intel_dp_mst_mode_str(sink_mst_mode), 4402 str_yes_no(display->params.enable_dp_mst), 4403 intel_dp_mst_mode_str(mst_detect)); 4404 4405 return mst_detect; 4406 } 4407 4408 static void 4409 intel_dp_mst_configure(struct intel_dp *intel_dp) 4410 { 4411 if (!intel_dp_mst_source_support(intel_dp)) 4412 return; 4413 4414 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST; 4415 4416 if (intel_dp->is_mst) 4417 intel_dp_mst_prepare_probe(intel_dp); 4418 4419 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 4420 4421 /* Avoid stale info on the next detect cycle. */ 4422 intel_dp->mst_detect = DRM_DP_SST; 4423 } 4424 4425 static void 4426 intel_dp_mst_disconnect(struct intel_dp *intel_dp) 4427 { 4428 struct intel_display *display = to_intel_display(intel_dp); 4429 4430 if (!intel_dp->is_mst) 4431 return; 4432 4433 drm_dbg_kms(display->drm, 4434 "MST device may have disappeared %d vs %d\n", 4435 intel_dp->is_mst, intel_dp->mst_mgr.mst_state); 4436 intel_dp->is_mst = false; 4437 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 4438 } 4439 4440 static bool 4441 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi) 4442 { 4443 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; 4444 } 4445 4446 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4]) 4447 { 4448 int retry; 4449 4450 for (retry = 0; retry < 3; retry++) { 4451 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1, 4452 &esi[1], 3) == 3) 4453 return true; 4454 } 4455 4456 return false; 4457 } 4458 4459 bool 4460 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 4461 const struct drm_connector_state *conn_state) 4462 { 4463 /* 4464 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 4465 * of Color Encoding Format and Content Color Gamut], in order to 4466 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. 4467 */ 4468 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 4469 return true; 4470 4471 switch (conn_state->colorspace) { 4472 case DRM_MODE_COLORIMETRY_SYCC_601: 4473 case DRM_MODE_COLORIMETRY_OPYCC_601: 4474 case DRM_MODE_COLORIMETRY_BT2020_YCC: 4475 case DRM_MODE_COLORIMETRY_BT2020_RGB: 4476 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 4477 return true; 4478 default: 4479 break; 4480 } 4481 4482 return false; 4483 } 4484 4485 static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, 4486 struct dp_sdp *sdp, size_t size) 4487 { 4488 size_t length = sizeof(struct dp_sdp); 4489 4490 if (size < length) 4491 return -ENOSPC; 4492 4493 memset(sdp, 0, size); 4494 4495 /* Prepare AS (Adaptive Sync) SDP Header */ 4496 sdp->sdp_header.HB0 = 0; 4497 sdp->sdp_header.HB1 = as_sdp->sdp_type; 4498 sdp->sdp_header.HB2 = 0x02; 4499 sdp->sdp_header.HB3 = as_sdp->length; 4500 4501 /* Fill AS (Adaptive Sync) SDP Payload */ 4502 sdp->db[0] = as_sdp->mode; 4503 sdp->db[1] = as_sdp->vtotal & 0xFF; 4504 sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF; 4505 sdp->db[3] = as_sdp->target_rr & 0xFF; 4506 sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; 4507 4508 if (as_sdp->target_rr_divider) 4509 sdp->db[4] |= 0x20; 4510 4511 return length; 4512 } 4513 4514 static ssize_t 4515 intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display, 4516 const struct hdmi_drm_infoframe *drm_infoframe, 4517 struct dp_sdp *sdp, 4518 size_t size) 4519 { 4520 size_t length = sizeof(struct dp_sdp); 4521 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; 4522 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; 4523 ssize_t len; 4524 4525 if (size < length) 4526 return -ENOSPC; 4527 4528 memset(sdp, 0, size); 4529 4530 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); 4531 if (len < 0) { 4532 drm_dbg_kms(display->drm, 4533 "buffer size is smaller than hdr metadata infoframe\n"); 4534 return -ENOSPC; 4535 } 4536 4537 if (len != infoframe_size) { 4538 drm_dbg_kms(display->drm, "wrong static hdr metadata size\n"); 4539 return -ENOSPC; 4540 } 4541 4542 /* 4543 * Set up the infoframe sdp packet for HDR static metadata. 4544 * Prepare VSC Header for SU as per DP 1.4a spec, 4545 * Table 2-100 and Table 2-101 4546 */ 4547 4548 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ 4549 sdp->sdp_header.HB0 = 0; 4550 /* 4551 * Packet Type 80h + Non-audio INFOFRAME Type value 4552 * HDMI_INFOFRAME_TYPE_DRM: 0x87 4553 * - 80h + Non-audio INFOFRAME Type value 4554 * - InfoFrame Type: 0x07 4555 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] 4556 */ 4557 sdp->sdp_header.HB1 = drm_infoframe->type; 4558 /* 4559 * Least Significant Eight Bits of (Data Byte Count – 1) 4560 * infoframe_size - 1 4561 */ 4562 sdp->sdp_header.HB2 = 0x1D; 4563 /* INFOFRAME SDP Version Number */ 4564 sdp->sdp_header.HB3 = (0x13 << 2); 4565 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4566 sdp->db[0] = drm_infoframe->version; 4567 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4568 sdp->db[1] = drm_infoframe->length; 4569 /* 4570 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after 4571 * HDMI_INFOFRAME_HEADER_SIZE 4572 */ 4573 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); 4574 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], 4575 HDMI_DRM_INFOFRAME_SIZE); 4576 4577 /* 4578 * Size of DP infoframe sdp packet for HDR static metadata consists of 4579 * - DP SDP Header(struct dp_sdp_header): 4 bytes 4580 * - Two Data Blocks: 2 bytes 4581 * CTA Header Byte2 (INFOFRAME Version Number) 4582 * CTA Header Byte3 (Length of INFOFRAME) 4583 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes 4584 * 4585 * Prior to GEN11's GMP register size is identical to DP HDR static metadata 4586 * infoframe size. But GEN11+ has larger than that size, write_infoframe 4587 * will pad rest of the size. 4588 */ 4589 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; 4590 } 4591 4592 static void intel_write_dp_sdp(struct intel_encoder *encoder, 4593 const struct intel_crtc_state *crtc_state, 4594 unsigned int type) 4595 { 4596 struct intel_display *display = to_intel_display(encoder); 4597 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4598 struct dp_sdp sdp = {}; 4599 ssize_t len; 4600 4601 if ((crtc_state->infoframes.enable & 4602 intel_hdmi_infoframe_enable(type)) == 0) 4603 return; 4604 4605 switch (type) { 4606 case DP_SDP_VSC: 4607 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp); 4608 break; 4609 case HDMI_PACKET_TYPE_GAMUT_METADATA: 4610 len = intel_dp_hdr_metadata_infoframe_sdp_pack(display, 4611 &crtc_state->infoframes.drm.drm, 4612 &sdp, sizeof(sdp)); 4613 break; 4614 case DP_SDP_ADAPTIVE_SYNC: 4615 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp, 4616 sizeof(sdp)); 4617 break; 4618 default: 4619 MISSING_CASE(type); 4620 return; 4621 } 4622 4623 if (drm_WARN_ON(display->drm, len < 0)) 4624 return; 4625 4626 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); 4627 } 4628 4629 void intel_dp_set_infoframes(struct intel_encoder *encoder, 4630 bool enable, 4631 const struct intel_crtc_state *crtc_state, 4632 const struct drm_connector_state *conn_state) 4633 { 4634 struct intel_display *display = to_intel_display(encoder); 4635 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); 4636 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 4637 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | 4638 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; 4639 4640 if (HAS_AS_SDP(display)) 4641 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL; 4642 4643 u32 val = intel_de_read(display, reg) & ~dip_enable; 4644 4645 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ 4646 if (!enable && HAS_DSC(display)) 4647 val &= ~VDIP_ENABLE_PPS; 4648 4649 /* 4650 * This routine disables VSC DIP if the function is called 4651 * to disable SDP or if it does not have PSR 4652 */ 4653 if (!enable || !crtc_state->has_psr) 4654 val &= ~VIDEO_DIP_ENABLE_VSC_HSW; 4655 4656 intel_de_write(display, reg, val); 4657 intel_de_posting_read(display, reg); 4658 4659 if (!enable) 4660 return; 4661 4662 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); 4663 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); 4664 4665 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); 4666 } 4667 4668 static 4669 int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, 4670 const void *buffer, size_t size) 4671 { 4672 const struct dp_sdp *sdp = buffer; 4673 4674 if (size < sizeof(struct dp_sdp)) 4675 return -EINVAL; 4676 4677 memset(as_sdp, 0, sizeof(*as_sdp)); 4678 4679 if (sdp->sdp_header.HB0 != 0) 4680 return -EINVAL; 4681 4682 if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC) 4683 return -EINVAL; 4684 4685 if (sdp->sdp_header.HB2 != 0x02) 4686 return -EINVAL; 4687 4688 if ((sdp->sdp_header.HB3 & 0x3F) != 9) 4689 return -EINVAL; 4690 4691 as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH; 4692 as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; 4693 as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; 4694 as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); 4695 as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; 4696 4697 return 0; 4698 } 4699 4700 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, 4701 const void *buffer, size_t size) 4702 { 4703 const struct dp_sdp *sdp = buffer; 4704 4705 if (size < sizeof(struct dp_sdp)) 4706 return -EINVAL; 4707 4708 memset(vsc, 0, sizeof(*vsc)); 4709 4710 if (sdp->sdp_header.HB0 != 0) 4711 return -EINVAL; 4712 4713 if (sdp->sdp_header.HB1 != DP_SDP_VSC) 4714 return -EINVAL; 4715 4716 vsc->sdp_type = sdp->sdp_header.HB1; 4717 vsc->revision = sdp->sdp_header.HB2; 4718 vsc->length = sdp->sdp_header.HB3; 4719 4720 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || 4721 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) || 4722 (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) { 4723 /* 4724 * - HB2 = 0x2, HB3 = 0x8 4725 * VSC SDP supporting 3D stereo + PSR 4726 * - HB2 = 0x4, HB3 = 0xe 4727 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of 4728 * first scan line of the SU region (applies to eDP v1.4b 4729 * and higher). 4730 * - HB2 = 0x6, HB3 = 0x10 4731 * VSC SDP supporting 3D stereo + Panel Replay. 4732 */ 4733 return 0; 4734 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { 4735 /* 4736 * - HB2 = 0x5, HB3 = 0x13 4737 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry 4738 * Format. 4739 */ 4740 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; 4741 vsc->colorimetry = sdp->db[16] & 0xf; 4742 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; 4743 4744 switch (sdp->db[17] & 0x7) { 4745 case 0x0: 4746 vsc->bpc = 6; 4747 break; 4748 case 0x1: 4749 vsc->bpc = 8; 4750 break; 4751 case 0x2: 4752 vsc->bpc = 10; 4753 break; 4754 case 0x3: 4755 vsc->bpc = 12; 4756 break; 4757 case 0x4: 4758 vsc->bpc = 16; 4759 break; 4760 default: 4761 MISSING_CASE(sdp->db[17] & 0x7); 4762 return -EINVAL; 4763 } 4764 4765 vsc->content_type = sdp->db[18] & 0x7; 4766 } else { 4767 return -EINVAL; 4768 } 4769 4770 return 0; 4771 } 4772 4773 static void 4774 intel_read_dp_as_sdp(struct intel_encoder *encoder, 4775 struct intel_crtc_state *crtc_state, 4776 struct drm_dp_as_sdp *as_sdp) 4777 { 4778 struct intel_display *display = to_intel_display(encoder); 4779 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4780 unsigned int type = DP_SDP_ADAPTIVE_SYNC; 4781 struct dp_sdp sdp = {}; 4782 int ret; 4783 4784 if ((crtc_state->infoframes.enable & 4785 intel_hdmi_infoframe_enable(type)) == 0) 4786 return; 4787 4788 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 4789 sizeof(sdp)); 4790 4791 ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp)); 4792 if (ret) 4793 drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n"); 4794 } 4795 4796 static int 4797 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, 4798 const void *buffer, size_t size) 4799 { 4800 int ret; 4801 4802 const struct dp_sdp *sdp = buffer; 4803 4804 if (size < sizeof(struct dp_sdp)) 4805 return -EINVAL; 4806 4807 if (sdp->sdp_header.HB0 != 0) 4808 return -EINVAL; 4809 4810 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) 4811 return -EINVAL; 4812 4813 /* 4814 * Least Significant Eight Bits of (Data Byte Count – 1) 4815 * 1Dh (i.e., Data Byte Count = 30 bytes). 4816 */ 4817 if (sdp->sdp_header.HB2 != 0x1D) 4818 return -EINVAL; 4819 4820 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ 4821 if ((sdp->sdp_header.HB3 & 0x3) != 0) 4822 return -EINVAL; 4823 4824 /* INFOFRAME SDP Version Number */ 4825 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) 4826 return -EINVAL; 4827 4828 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4829 if (sdp->db[0] != 1) 4830 return -EINVAL; 4831 4832 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4833 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) 4834 return -EINVAL; 4835 4836 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], 4837 HDMI_DRM_INFOFRAME_SIZE); 4838 4839 return ret; 4840 } 4841 4842 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, 4843 struct intel_crtc_state *crtc_state, 4844 struct drm_dp_vsc_sdp *vsc) 4845 { 4846 struct intel_display *display = to_intel_display(encoder); 4847 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4848 unsigned int type = DP_SDP_VSC; 4849 struct dp_sdp sdp = {}; 4850 int ret; 4851 4852 if ((crtc_state->infoframes.enable & 4853 intel_hdmi_infoframe_enable(type)) == 0) 4854 return; 4855 4856 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); 4857 4858 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); 4859 4860 if (ret) 4861 drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n"); 4862 } 4863 4864 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, 4865 struct intel_crtc_state *crtc_state, 4866 struct hdmi_drm_infoframe *drm_infoframe) 4867 { 4868 struct intel_display *display = to_intel_display(encoder); 4869 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4870 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; 4871 struct dp_sdp sdp = {}; 4872 int ret; 4873 4874 if ((crtc_state->infoframes.enable & 4875 intel_hdmi_infoframe_enable(type)) == 0) 4876 return; 4877 4878 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 4879 sizeof(sdp)); 4880 4881 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, 4882 sizeof(sdp)); 4883 4884 if (ret) 4885 drm_dbg_kms(display->drm, 4886 "Failed to unpack DP HDR Metadata Infoframe SDP\n"); 4887 } 4888 4889 void intel_read_dp_sdp(struct intel_encoder *encoder, 4890 struct intel_crtc_state *crtc_state, 4891 unsigned int type) 4892 { 4893 switch (type) { 4894 case DP_SDP_VSC: 4895 intel_read_dp_vsc_sdp(encoder, crtc_state, 4896 &crtc_state->infoframes.vsc); 4897 break; 4898 case HDMI_PACKET_TYPE_GAMUT_METADATA: 4899 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, 4900 &crtc_state->infoframes.drm.drm); 4901 break; 4902 case DP_SDP_ADAPTIVE_SYNC: 4903 intel_read_dp_as_sdp(encoder, crtc_state, 4904 &crtc_state->infoframes.as_sdp); 4905 break; 4906 default: 4907 MISSING_CASE(type); 4908 break; 4909 } 4910 } 4911 4912 static bool intel_dp_link_ok(struct intel_dp *intel_dp, 4913 u8 link_status[DP_LINK_STATUS_SIZE]) 4914 { 4915 struct intel_display *display = to_intel_display(intel_dp); 4916 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4917 bool uhbr = intel_dp->link_rate >= 1000000; 4918 bool ok; 4919 4920 if (uhbr) 4921 ok = drm_dp_128b132b_lane_channel_eq_done(link_status, 4922 intel_dp->lane_count); 4923 else 4924 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); 4925 4926 if (ok) 4927 return true; 4928 4929 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 4930 drm_dbg_kms(display->drm, 4931 "[ENCODER:%d:%s] %s link not ok, retraining\n", 4932 encoder->base.base.id, encoder->base.name, 4933 uhbr ? "128b/132b" : "8b/10b"); 4934 4935 return false; 4936 } 4937 4938 static void 4939 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) 4940 { 4941 bool handled = false; 4942 4943 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled); 4944 4945 if (esi[1] & DP_CP_IRQ) { 4946 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 4947 ack[1] |= DP_CP_IRQ; 4948 } 4949 } 4950 4951 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp) 4952 { 4953 struct intel_display *display = to_intel_display(intel_dp); 4954 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4955 u8 link_status[DP_LINK_STATUS_SIZE] = {}; 4956 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2; 4957 4958 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status, 4959 esi_link_status_size) != esi_link_status_size) { 4960 drm_err(display->drm, 4961 "[ENCODER:%d:%s] Failed to read link status\n", 4962 encoder->base.base.id, encoder->base.name); 4963 return false; 4964 } 4965 4966 return intel_dp_link_ok(intel_dp, link_status); 4967 } 4968 4969 /** 4970 * intel_dp_check_mst_status - service any pending MST interrupts, check link status 4971 * @intel_dp: Intel DP struct 4972 * 4973 * Read any pending MST interrupts, call MST core to handle these and ack the 4974 * interrupts. Check if the main and AUX link state is ok. 4975 * 4976 * Returns: 4977 * - %true if pending interrupts were serviced (or no interrupts were 4978 * pending) w/o detecting an error condition. 4979 * - %false if an error condition - like AUX failure or a loss of link - is 4980 * detected, or another condition - like a DP tunnel BW state change - needs 4981 * servicing from the hotplug work. 4982 */ 4983 static bool 4984 intel_dp_check_mst_status(struct intel_dp *intel_dp) 4985 { 4986 struct intel_display *display = to_intel_display(intel_dp); 4987 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4988 struct intel_encoder *encoder = &dig_port->base; 4989 bool link_ok = true; 4990 bool reprobe_needed = false; 4991 4992 drm_WARN_ON_ONCE(display->drm, intel_dp->active_mst_links < 0); 4993 4994 for (;;) { 4995 u8 esi[4] = {}; 4996 u8 ack[4] = {}; 4997 4998 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { 4999 drm_dbg_kms(display->drm, 5000 "failed to get ESI - device may have failed\n"); 5001 link_ok = false; 5002 5003 break; 5004 } 5005 5006 drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi); 5007 5008 if (intel_dp->active_mst_links > 0 && link_ok && 5009 esi[3] & LINK_STATUS_CHANGED) { 5010 if (!intel_dp_mst_link_status(intel_dp)) 5011 link_ok = false; 5012 ack[3] |= LINK_STATUS_CHANGED; 5013 } 5014 5015 intel_dp_mst_hpd_irq(intel_dp, esi, ack); 5016 5017 if (esi[3] & DP_TUNNELING_IRQ) { 5018 if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr, 5019 &intel_dp->aux)) 5020 reprobe_needed = true; 5021 ack[3] |= DP_TUNNELING_IRQ; 5022 } 5023 5024 if (mem_is_zero(ack, sizeof(ack))) 5025 break; 5026 5027 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack)) 5028 drm_dbg_kms(display->drm, "Failed to ack ESI\n"); 5029 5030 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY)) 5031 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); 5032 } 5033 5034 if (!link_ok || intel_dp->link.force_retrain) 5035 intel_encoder_link_check_queue_work(encoder, 0); 5036 5037 return !reprobe_needed; 5038 } 5039 5040 static void 5041 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) 5042 { 5043 bool is_active; 5044 u8 buf = 0; 5045 5046 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); 5047 if (intel_dp->frl.is_trained && !is_active) { 5048 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) 5049 return; 5050 5051 buf &= ~DP_PCON_ENABLE_HDMI_LINK; 5052 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) 5053 return; 5054 5055 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); 5056 5057 intel_dp->frl.is_trained = false; 5058 5059 /* Restart FRL training or fall back to TMDS mode */ 5060 intel_dp_check_frl_training(intel_dp); 5061 } 5062 } 5063 5064 static bool 5065 intel_dp_needs_link_retrain(struct intel_dp *intel_dp) 5066 { 5067 u8 link_status[DP_LINK_STATUS_SIZE]; 5068 5069 if (!intel_dp->link_trained) 5070 return false; 5071 5072 /* 5073 * While PSR source HW is enabled, it will control main-link sending 5074 * frames, enabling and disabling it so trying to do a retrain will fail 5075 * as the link would or not be on or it could mix training patterns 5076 * and frame data at the same time causing retrain to fail. 5077 * Also when exiting PSR, HW will retrain the link anyways fixing 5078 * any link status error. 5079 */ 5080 if (intel_psr_enabled(intel_dp)) 5081 return false; 5082 5083 if (intel_dp->link.force_retrain) 5084 return true; 5085 5086 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 5087 link_status) < 0) 5088 return false; 5089 5090 /* 5091 * Validate the cached values of intel_dp->link_rate and 5092 * intel_dp->lane_count before attempting to retrain. 5093 * 5094 * FIXME would be nice to user the crtc state here, but since 5095 * we need to call this from the short HPD handler that seems 5096 * a bit hard. 5097 */ 5098 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, 5099 intel_dp->lane_count)) 5100 return false; 5101 5102 if (intel_dp->link.retrain_disabled) 5103 return false; 5104 5105 if (intel_dp->link.seq_train_failures) 5106 return true; 5107 5108 /* Retrain if link not ok */ 5109 return !intel_dp_link_ok(intel_dp, link_status) && 5110 !intel_psr_link_ok(intel_dp); 5111 } 5112 5113 bool intel_dp_has_connector(struct intel_dp *intel_dp, 5114 const struct drm_connector_state *conn_state) 5115 { 5116 struct intel_display *display = to_intel_display(intel_dp); 5117 struct intel_encoder *encoder; 5118 enum pipe pipe; 5119 5120 if (!conn_state->best_encoder) 5121 return false; 5122 5123 /* SST */ 5124 encoder = &dp_to_dig_port(intel_dp)->base; 5125 if (conn_state->best_encoder == &encoder->base) 5126 return true; 5127 5128 /* MST */ 5129 for_each_pipe(display, pipe) { 5130 encoder = &intel_dp->mst_encoders[pipe]->base; 5131 if (conn_state->best_encoder == &encoder->base) 5132 return true; 5133 } 5134 5135 return false; 5136 } 5137 5138 static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state) 5139 { 5140 struct intel_connector *connector = to_intel_connector(conn_state->connector); 5141 struct intel_display *display = to_intel_display(connector); 5142 5143 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); 5144 5145 if (!conn_state->commit) 5146 return; 5147 5148 drm_WARN_ON(display->drm, 5149 !wait_for_completion_timeout(&conn_state->commit->hw_done, 5150 msecs_to_jiffies(5000))); 5151 } 5152 5153 int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 5154 struct drm_modeset_acquire_ctx *ctx, 5155 u8 *pipe_mask) 5156 { 5157 struct intel_display *display = to_intel_display(intel_dp); 5158 struct drm_connector_list_iter conn_iter; 5159 struct intel_connector *connector; 5160 int ret = 0; 5161 5162 *pipe_mask = 0; 5163 5164 drm_connector_list_iter_begin(display->drm, &conn_iter); 5165 for_each_intel_connector_iter(connector, &conn_iter) { 5166 struct drm_connector_state *conn_state = 5167 connector->base.state; 5168 struct intel_crtc_state *crtc_state; 5169 struct intel_crtc *crtc; 5170 5171 if (!intel_dp_has_connector(intel_dp, conn_state)) 5172 continue; 5173 5174 crtc = to_intel_crtc(conn_state->crtc); 5175 if (!crtc) 5176 continue; 5177 5178 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 5179 if (ret) 5180 break; 5181 5182 crtc_state = to_intel_crtc_state(crtc->base.state); 5183 5184 drm_WARN_ON(display->drm, 5185 !intel_crtc_has_dp_encoder(crtc_state)); 5186 5187 if (!crtc_state->hw.active) 5188 continue; 5189 5190 wait_for_connector_hw_done(conn_state); 5191 5192 *pipe_mask |= BIT(crtc->pipe); 5193 } 5194 drm_connector_list_iter_end(&conn_iter); 5195 5196 return ret; 5197 } 5198 5199 void intel_dp_flush_connector_commits(struct intel_connector *connector) 5200 { 5201 wait_for_connector_hw_done(connector->base.state); 5202 } 5203 5204 static bool intel_dp_is_connected(struct intel_dp *intel_dp) 5205 { 5206 struct intel_connector *connector = intel_dp->attached_connector; 5207 5208 return connector->base.status == connector_status_connected || 5209 intel_dp->is_mst; 5210 } 5211 5212 static int intel_dp_retrain_link(struct intel_encoder *encoder, 5213 struct drm_modeset_acquire_ctx *ctx) 5214 { 5215 struct intel_display *display = to_intel_display(encoder); 5216 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5217 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5218 u8 pipe_mask; 5219 int ret; 5220 5221 if (!intel_dp_is_connected(intel_dp)) 5222 return 0; 5223 5224 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 5225 ctx); 5226 if (ret) 5227 return ret; 5228 5229 if (!intel_dp_needs_link_retrain(intel_dp)) 5230 return 0; 5231 5232 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); 5233 if (ret) 5234 return ret; 5235 5236 if (pipe_mask == 0) 5237 return 0; 5238 5239 if (!intel_dp_needs_link_retrain(intel_dp)) 5240 return 0; 5241 5242 drm_dbg_kms(display->drm, 5243 "[ENCODER:%d:%s] retraining link (forced %s)\n", 5244 encoder->base.base.id, encoder->base.name, 5245 str_yes_no(intel_dp->link.force_retrain)); 5246 5247 ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx); 5248 if (ret == -EDEADLK) 5249 return ret; 5250 5251 intel_dp->link.force_retrain = false; 5252 5253 if (ret) 5254 drm_dbg_kms(display->drm, 5255 "[ENCODER:%d:%s] link retraining failed: %pe\n", 5256 encoder->base.base.id, encoder->base.name, 5257 ERR_PTR(ret)); 5258 5259 return ret; 5260 } 5261 5262 void intel_dp_link_check(struct intel_encoder *encoder) 5263 { 5264 struct drm_modeset_acquire_ctx ctx; 5265 int ret; 5266 5267 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 5268 ret = intel_dp_retrain_link(encoder, &ctx); 5269 } 5270 5271 void intel_dp_check_link_state(struct intel_dp *intel_dp) 5272 { 5273 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5274 struct intel_encoder *encoder = &dig_port->base; 5275 5276 if (!intel_dp_is_connected(intel_dp)) 5277 return; 5278 5279 if (!intel_dp_needs_link_retrain(intel_dp)) 5280 return; 5281 5282 intel_encoder_link_check_queue_work(encoder, 0); 5283 } 5284 5285 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp) 5286 { 5287 struct intel_display *display = to_intel_display(intel_dp); 5288 u8 val; 5289 5290 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5291 return; 5292 5293 if (drm_dp_dpcd_readb(&intel_dp->aux, 5294 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) 5295 return; 5296 5297 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); 5298 5299 if (val & DP_AUTOMATED_TEST_REQUEST) 5300 intel_dp_test_request(intel_dp); 5301 5302 if (val & DP_CP_IRQ) 5303 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5304 5305 if (val & DP_SINK_SPECIFIC_IRQ) 5306 drm_dbg_kms(display->drm, "Sink specific irq unhandled\n"); 5307 } 5308 5309 static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp) 5310 { 5311 struct intel_display *display = to_intel_display(intel_dp); 5312 bool reprobe_needed = false; 5313 u8 val; 5314 5315 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5316 return false; 5317 5318 if (drm_dp_dpcd_readb(&intel_dp->aux, 5319 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) 5320 return false; 5321 5322 if ((val & DP_TUNNELING_IRQ) && 5323 drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr, 5324 &intel_dp->aux)) 5325 reprobe_needed = true; 5326 5327 if (drm_dp_dpcd_writeb(&intel_dp->aux, 5328 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) 5329 return reprobe_needed; 5330 5331 if (val & HDMI_LINK_STATUS_CHANGED) 5332 intel_dp_handle_hdmi_link_status_change(intel_dp); 5333 5334 return reprobe_needed; 5335 } 5336 5337 /* 5338 * According to DP spec 5339 * 5.1.2: 5340 * 1. Read DPCD 5341 * 2. Configure link according to Receiver Capabilities 5342 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 5343 * 4. Check link status on receipt of hot-plug interrupt 5344 * 5345 * intel_dp_short_pulse - handles short pulse interrupts 5346 * when full detection is not required. 5347 * Returns %true if short pulse is handled and full detection 5348 * is NOT required and %false otherwise. 5349 */ 5350 static bool 5351 intel_dp_short_pulse(struct intel_dp *intel_dp) 5352 { 5353 u8 old_sink_count = intel_dp->sink_count; 5354 bool reprobe_needed = false; 5355 bool ret; 5356 5357 intel_dp_test_reset(intel_dp); 5358 5359 /* 5360 * Now read the DPCD to see if it's actually running 5361 * If the current value of sink count doesn't match with 5362 * the value that was stored earlier or dpcd read failed 5363 * we need to do full detection 5364 */ 5365 ret = intel_dp_get_dpcd(intel_dp); 5366 5367 if ((old_sink_count != intel_dp->sink_count) || !ret) { 5368 /* No need to proceed if we are going to do full detect */ 5369 return false; 5370 } 5371 5372 intel_dp_check_device_service_irq(intel_dp); 5373 reprobe_needed = intel_dp_check_link_service_irq(intel_dp); 5374 5375 /* Handle CEC interrupts, if any */ 5376 drm_dp_cec_irq(&intel_dp->aux); 5377 5378 intel_dp_check_link_state(intel_dp); 5379 5380 intel_psr_short_pulse(intel_dp); 5381 5382 if (intel_dp_test_short_pulse(intel_dp)) 5383 reprobe_needed = true; 5384 5385 return !reprobe_needed; 5386 } 5387 5388 /* XXX this is probably wrong for multiple downstream ports */ 5389 static enum drm_connector_status 5390 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 5391 { 5392 struct intel_display *display = to_intel_display(intel_dp); 5393 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5394 u8 *dpcd = intel_dp->dpcd; 5395 u8 type; 5396 5397 if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp))) 5398 return connector_status_connected; 5399 5400 lspcon_resume(dig_port); 5401 5402 if (!intel_dp_get_dpcd(intel_dp)) 5403 return connector_status_disconnected; 5404 5405 intel_dp->mst_detect = intel_dp_mst_detect(intel_dp); 5406 5407 /* if there's no downstream port, we're done */ 5408 if (!drm_dp_is_branch(dpcd)) 5409 return connector_status_connected; 5410 5411 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 5412 if (intel_dp_has_sink_count(intel_dp) && 5413 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 5414 return intel_dp->sink_count ? 5415 connector_status_connected : connector_status_disconnected; 5416 } 5417 5418 if (intel_dp->mst_detect == DRM_DP_MST) 5419 return connector_status_connected; 5420 5421 /* If no HPD, poke DDC gently */ 5422 if (drm_probe_ddc(&intel_dp->aux.ddc)) 5423 return connector_status_connected; 5424 5425 /* Well we tried, say unknown for unreliable port types */ 5426 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 5427 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 5428 if (type == DP_DS_PORT_TYPE_VGA || 5429 type == DP_DS_PORT_TYPE_NON_EDID) 5430 return connector_status_unknown; 5431 } else { 5432 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 5433 DP_DWN_STRM_PORT_TYPE_MASK; 5434 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 5435 type == DP_DWN_STRM_PORT_TYPE_OTHER) 5436 return connector_status_unknown; 5437 } 5438 5439 /* Anything else is out of spec, warn and ignore */ 5440 drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n"); 5441 return connector_status_disconnected; 5442 } 5443 5444 static enum drm_connector_status 5445 edp_detect(struct intel_dp *intel_dp) 5446 { 5447 return connector_status_connected; 5448 } 5449 5450 void intel_digital_port_lock(struct intel_encoder *encoder) 5451 { 5452 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5453 5454 if (dig_port->lock) 5455 dig_port->lock(dig_port); 5456 } 5457 5458 void intel_digital_port_unlock(struct intel_encoder *encoder) 5459 { 5460 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5461 5462 if (dig_port->unlock) 5463 dig_port->unlock(dig_port); 5464 } 5465 5466 /* 5467 * intel_digital_port_connected_locked - is the specified port connected? 5468 * @encoder: intel_encoder 5469 * 5470 * In cases where there's a connector physically connected but it can't be used 5471 * by our hardware we also return false, since the rest of the driver should 5472 * pretty much treat the port as disconnected. This is relevant for type-C 5473 * (starting on ICL) where there's ownership involved. 5474 * 5475 * The caller must hold the lock acquired by calling intel_digital_port_lock() 5476 * when calling this function. 5477 * 5478 * Return %true if port is connected, %false otherwise. 5479 */ 5480 bool intel_digital_port_connected_locked(struct intel_encoder *encoder) 5481 { 5482 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5483 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5484 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); 5485 bool is_connected = false; 5486 intel_wakeref_t wakeref; 5487 5488 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) { 5489 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4); 5490 5491 do { 5492 is_connected = dig_port->connected(encoder); 5493 if (is_connected || is_glitch_free) 5494 break; 5495 usleep_range(10, 30); 5496 } while (time_before(jiffies, wait_expires)); 5497 } 5498 5499 return is_connected; 5500 } 5501 5502 bool intel_digital_port_connected(struct intel_encoder *encoder) 5503 { 5504 bool ret; 5505 5506 intel_digital_port_lock(encoder); 5507 ret = intel_digital_port_connected_locked(encoder); 5508 intel_digital_port_unlock(encoder); 5509 5510 return ret; 5511 } 5512 5513 static const struct drm_edid * 5514 intel_dp_get_edid(struct intel_dp *intel_dp) 5515 { 5516 struct intel_connector *connector = intel_dp->attached_connector; 5517 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 5518 5519 /* Use panel fixed edid if we have one */ 5520 if (fixed_edid) { 5521 /* invalid edid */ 5522 if (IS_ERR(fixed_edid)) 5523 return NULL; 5524 5525 return drm_edid_dup(fixed_edid); 5526 } 5527 5528 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc); 5529 } 5530 5531 static void 5532 intel_dp_update_dfp(struct intel_dp *intel_dp, 5533 const struct drm_edid *drm_edid) 5534 { 5535 struct intel_display *display = to_intel_display(intel_dp); 5536 struct intel_connector *connector = intel_dp->attached_connector; 5537 5538 intel_dp->dfp.max_bpc = 5539 drm_dp_downstream_max_bpc(intel_dp->dpcd, 5540 intel_dp->downstream_ports, drm_edid); 5541 5542 intel_dp->dfp.max_dotclock = 5543 drm_dp_downstream_max_dotclock(intel_dp->dpcd, 5544 intel_dp->downstream_ports); 5545 5546 intel_dp->dfp.min_tmds_clock = 5547 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, 5548 intel_dp->downstream_ports, 5549 drm_edid); 5550 intel_dp->dfp.max_tmds_clock = 5551 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, 5552 intel_dp->downstream_ports, 5553 drm_edid); 5554 5555 intel_dp->dfp.pcon_max_frl_bw = 5556 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, 5557 intel_dp->downstream_ports); 5558 5559 drm_dbg_kms(display->drm, 5560 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", 5561 connector->base.base.id, connector->base.name, 5562 intel_dp->dfp.max_bpc, 5563 intel_dp->dfp.max_dotclock, 5564 intel_dp->dfp.min_tmds_clock, 5565 intel_dp->dfp.max_tmds_clock, 5566 intel_dp->dfp.pcon_max_frl_bw); 5567 5568 intel_dp_get_pcon_dsc_cap(intel_dp); 5569 } 5570 5571 static bool 5572 intel_dp_can_ycbcr420(struct intel_dp *intel_dp) 5573 { 5574 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) && 5575 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough)) 5576 return true; 5577 5578 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) && 5579 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5580 return true; 5581 5582 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) && 5583 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5584 return true; 5585 5586 return false; 5587 } 5588 5589 static void 5590 intel_dp_update_420(struct intel_dp *intel_dp) 5591 { 5592 struct intel_display *display = to_intel_display(intel_dp); 5593 struct intel_connector *connector = intel_dp->attached_connector; 5594 5595 intel_dp->dfp.ycbcr420_passthrough = 5596 drm_dp_downstream_420_passthrough(intel_dp->dpcd, 5597 intel_dp->downstream_ports); 5598 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ 5599 intel_dp->dfp.ycbcr_444_to_420 = 5600 dp_to_dig_port(intel_dp)->lspcon.active || 5601 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, 5602 intel_dp->downstream_ports); 5603 intel_dp->dfp.rgb_to_ycbcr = 5604 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, 5605 intel_dp->downstream_ports, 5606 DP_DS_HDMI_BT709_RGB_YCBCR_CONV); 5607 5608 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp); 5609 5610 drm_dbg_kms(display->drm, 5611 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", 5612 connector->base.base.id, connector->base.name, 5613 str_yes_no(intel_dp->dfp.rgb_to_ycbcr), 5614 str_yes_no(connector->base.ycbcr_420_allowed), 5615 str_yes_no(intel_dp->dfp.ycbcr_444_to_420)); 5616 } 5617 5618 static void 5619 intel_dp_set_edid(struct intel_dp *intel_dp) 5620 { 5621 struct intel_display *display = to_intel_display(intel_dp); 5622 struct intel_connector *connector = intel_dp->attached_connector; 5623 const struct drm_edid *drm_edid; 5624 bool vrr_capable; 5625 5626 intel_dp_unset_edid(intel_dp); 5627 drm_edid = intel_dp_get_edid(intel_dp); 5628 connector->detect_edid = drm_edid; 5629 5630 /* Below we depend on display info having been updated */ 5631 drm_edid_connector_update(&connector->base, drm_edid); 5632 5633 vrr_capable = intel_vrr_is_capable(connector); 5634 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n", 5635 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable)); 5636 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable); 5637 5638 intel_dp_update_dfp(intel_dp, drm_edid); 5639 intel_dp_update_420(intel_dp); 5640 5641 drm_dp_cec_attach(&intel_dp->aux, 5642 connector->base.display_info.source_physical_address); 5643 } 5644 5645 static void 5646 intel_dp_unset_edid(struct intel_dp *intel_dp) 5647 { 5648 struct intel_connector *connector = intel_dp->attached_connector; 5649 5650 drm_dp_cec_unset_edid(&intel_dp->aux); 5651 drm_edid_free(connector->detect_edid); 5652 connector->detect_edid = NULL; 5653 5654 intel_dp->dfp.max_bpc = 0; 5655 intel_dp->dfp.max_dotclock = 0; 5656 intel_dp->dfp.min_tmds_clock = 0; 5657 intel_dp->dfp.max_tmds_clock = 0; 5658 5659 intel_dp->dfp.pcon_max_frl_bw = 0; 5660 5661 intel_dp->dfp.ycbcr_444_to_420 = false; 5662 connector->base.ycbcr_420_allowed = false; 5663 5664 drm_connector_set_vrr_capable_property(&connector->base, 5665 false); 5666 } 5667 5668 static void 5669 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) 5670 { 5671 struct intel_display *display = to_intel_display(intel_dp); 5672 5673 intel_dp->as_sdp_supported = HAS_AS_SDP(display) && 5674 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); 5675 } 5676 5677 static int 5678 intel_dp_detect(struct drm_connector *_connector, 5679 struct drm_modeset_acquire_ctx *ctx, 5680 bool force) 5681 { 5682 struct intel_display *display = to_intel_display(_connector->dev); 5683 struct intel_connector *connector = to_intel_connector(_connector); 5684 struct intel_dp *intel_dp = intel_attached_dp(connector); 5685 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5686 struct intel_encoder *encoder = &dig_port->base; 5687 enum drm_connector_status status; 5688 int ret; 5689 5690 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 5691 connector->base.base.id, connector->base.name); 5692 drm_WARN_ON(display->drm, 5693 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 5694 5695 if (!intel_display_device_enabled(display)) 5696 return connector_status_disconnected; 5697 5698 if (!intel_display_driver_check_access(display)) 5699 return connector->base.status; 5700 5701 intel_dp_flush_connector_commits(connector); 5702 5703 intel_pps_vdd_on(intel_dp); 5704 5705 /* Can't disconnect eDP */ 5706 if (intel_dp_is_edp(intel_dp)) 5707 status = edp_detect(intel_dp); 5708 else if (intel_digital_port_connected(encoder)) 5709 status = intel_dp_detect_dpcd(intel_dp); 5710 else 5711 status = connector_status_disconnected; 5712 5713 if (status != connector_status_disconnected && 5714 !intel_dp_mst_verify_dpcd_state(intel_dp)) 5715 /* 5716 * This requires retrying detection for instance to re-enable 5717 * the MST mode that got reset via a long HPD pulse. The retry 5718 * will happen either via the hotplug handler's retry logic, 5719 * ensured by setting the connector here to SST/disconnected, 5720 * or via a userspace connector probing in response to the 5721 * hotplug uevent sent when removing the MST connectors. 5722 */ 5723 status = connector_status_disconnected; 5724 5725 if (status == connector_status_disconnected) { 5726 intel_dp_test_reset(intel_dp); 5727 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 5728 intel_dp->psr.sink_panel_replay_support = false; 5729 intel_dp->psr.sink_panel_replay_su_support = false; 5730 5731 intel_dp_mst_disconnect(intel_dp); 5732 5733 intel_dp_tunnel_disconnect(intel_dp); 5734 5735 goto out_unset_edid; 5736 } 5737 5738 intel_dp_init_source_oui(intel_dp); 5739 5740 ret = intel_dp_tunnel_detect(intel_dp, ctx); 5741 if (ret == -EDEADLK) { 5742 status = ret; 5743 5744 goto out_vdd_off; 5745 } 5746 5747 if (ret == 1) 5748 connector->base.epoch_counter++; 5749 5750 if (!intel_dp_is_edp(intel_dp)) 5751 intel_psr_init_dpcd(intel_dp); 5752 5753 intel_dp_detect_dsc_caps(intel_dp, connector); 5754 5755 intel_dp_detect_sdp_caps(intel_dp); 5756 5757 if (intel_dp->reset_link_params) { 5758 intel_dp_reset_link_params(intel_dp); 5759 intel_dp->reset_link_params = false; 5760 } 5761 5762 intel_dp_mst_configure(intel_dp); 5763 5764 intel_dp_print_rates(intel_dp); 5765 5766 if (intel_dp->is_mst) { 5767 /* 5768 * If we are in MST mode then this connector 5769 * won't appear connected or have anything 5770 * with EDID on it 5771 */ 5772 status = connector_status_disconnected; 5773 goto out_unset_edid; 5774 } 5775 5776 /* 5777 * Some external monitors do not signal loss of link synchronization 5778 * with an IRQ_HPD, so force a link status check. 5779 * 5780 * TODO: this probably became redundant, so remove it: the link state 5781 * is rechecked/recovered now after modesets, where the loss of 5782 * synchronization tends to occur. 5783 */ 5784 if (!intel_dp_is_edp(intel_dp)) 5785 intel_dp_check_link_state(intel_dp); 5786 5787 /* 5788 * Clearing NACK and defer counts to get their exact values 5789 * while reading EDID which are required by Compliance tests 5790 * 4.2.2.4 and 4.2.2.5 5791 */ 5792 intel_dp->aux.i2c_nack_count = 0; 5793 intel_dp->aux.i2c_defer_count = 0; 5794 5795 intel_dp_set_edid(intel_dp); 5796 if (intel_dp_is_edp(intel_dp) || connector->detect_edid) 5797 status = connector_status_connected; 5798 5799 intel_dp_check_device_service_irq(intel_dp); 5800 5801 out_unset_edid: 5802 if (status != connector_status_connected && !intel_dp->is_mst) 5803 intel_dp_unset_edid(intel_dp); 5804 5805 if (!intel_dp_is_edp(intel_dp)) 5806 drm_dp_set_subconnector_property(&connector->base, 5807 status, 5808 intel_dp->dpcd, 5809 intel_dp->downstream_ports); 5810 out_vdd_off: 5811 intel_pps_vdd_off(intel_dp); 5812 5813 return status; 5814 } 5815 5816 static void 5817 intel_dp_force(struct drm_connector *connector) 5818 { 5819 struct intel_display *display = to_intel_display(connector->dev); 5820 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 5821 5822 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 5823 connector->base.id, connector->name); 5824 5825 if (!intel_display_driver_check_access(display)) 5826 return; 5827 5828 intel_dp_unset_edid(intel_dp); 5829 5830 if (connector->status != connector_status_connected) 5831 return; 5832 5833 intel_dp_set_edid(intel_dp); 5834 } 5835 5836 static int intel_dp_get_modes(struct drm_connector *_connector) 5837 { 5838 struct intel_display *display = to_intel_display(_connector->dev); 5839 struct intel_connector *connector = to_intel_connector(_connector); 5840 struct intel_dp *intel_dp = intel_attached_dp(connector); 5841 int num_modes; 5842 5843 /* drm_edid_connector_update() done in ->detect() or ->force() */ 5844 num_modes = drm_edid_connector_add_modes(&connector->base); 5845 5846 /* Also add fixed mode, which may or may not be present in EDID */ 5847 if (intel_dp_is_edp(intel_dp)) 5848 num_modes += intel_panel_get_modes(connector); 5849 5850 if (num_modes) 5851 return num_modes; 5852 5853 if (!connector->detect_edid) { 5854 struct drm_display_mode *mode; 5855 5856 mode = drm_dp_downstream_mode(display->drm, 5857 intel_dp->dpcd, 5858 intel_dp->downstream_ports); 5859 if (mode) { 5860 drm_mode_probed_add(&connector->base, mode); 5861 num_modes++; 5862 } 5863 } 5864 5865 return num_modes; 5866 } 5867 5868 static int 5869 intel_dp_connector_register(struct drm_connector *connector) 5870 { 5871 struct intel_display *display = to_intel_display(connector->dev); 5872 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 5873 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5874 struct intel_lspcon *lspcon = &dig_port->lspcon; 5875 int ret; 5876 5877 ret = intel_connector_register(connector); 5878 if (ret) 5879 return ret; 5880 5881 drm_dbg_kms(display->drm, "registering %s bus for %s\n", 5882 intel_dp->aux.name, connector->kdev->kobj.name); 5883 5884 intel_dp->aux.dev = connector->kdev; 5885 ret = drm_dp_aux_register(&intel_dp->aux); 5886 if (!ret) 5887 drm_dp_cec_register_connector(&intel_dp->aux, connector); 5888 5889 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) 5890 return ret; 5891 5892 /* 5893 * ToDo: Clean this up to handle lspcon init and resume more 5894 * efficiently and streamlined. 5895 */ 5896 if (lspcon_init(dig_port)) { 5897 lspcon_detect_hdr_capability(lspcon); 5898 if (lspcon->hdr_supported) 5899 drm_connector_attach_hdr_output_metadata_property(connector); 5900 } 5901 5902 return ret; 5903 } 5904 5905 static void 5906 intel_dp_connector_unregister(struct drm_connector *connector) 5907 { 5908 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 5909 5910 drm_dp_cec_unregister_connector(&intel_dp->aux); 5911 drm_dp_aux_unregister(&intel_dp->aux); 5912 intel_connector_unregister(connector); 5913 } 5914 5915 void intel_dp_connector_sync_state(struct intel_connector *connector, 5916 const struct intel_crtc_state *crtc_state) 5917 { 5918 struct intel_display *display = to_intel_display(connector); 5919 5920 if (crtc_state && crtc_state->dsc.compression_enable) { 5921 drm_WARN_ON(display->drm, 5922 !connector->dp.dsc_decompression_aux); 5923 connector->dp.dsc_decompression_enabled = true; 5924 } else { 5925 connector->dp.dsc_decompression_enabled = false; 5926 } 5927 } 5928 5929 void intel_dp_encoder_flush_work(struct drm_encoder *_encoder) 5930 { 5931 struct intel_encoder *encoder = to_intel_encoder(_encoder); 5932 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5933 struct intel_dp *intel_dp = &dig_port->dp; 5934 5935 intel_encoder_link_check_flush_work(encoder); 5936 5937 intel_dp_mst_encoder_cleanup(dig_port); 5938 5939 intel_dp_tunnel_destroy(intel_dp); 5940 5941 intel_pps_vdd_off_sync(intel_dp); 5942 5943 /* 5944 * Ensure power off delay is respected on module remove, so that we can 5945 * reduce delays at driver probe. See pps_init_timestamps(). 5946 */ 5947 intel_pps_wait_power_cycle(intel_dp); 5948 5949 intel_dp_aux_fini(intel_dp); 5950 } 5951 5952 void intel_dp_encoder_suspend(struct intel_encoder *encoder) 5953 { 5954 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5955 5956 intel_pps_vdd_off_sync(intel_dp); 5957 5958 intel_dp_tunnel_suspend(intel_dp); 5959 } 5960 5961 void intel_dp_encoder_shutdown(struct intel_encoder *encoder) 5962 { 5963 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5964 5965 intel_pps_wait_power_cycle(intel_dp); 5966 } 5967 5968 static int intel_modeset_tile_group(struct intel_atomic_state *state, 5969 int tile_group_id) 5970 { 5971 struct intel_display *display = to_intel_display(state); 5972 struct drm_connector_list_iter conn_iter; 5973 struct drm_connector *connector; 5974 int ret = 0; 5975 5976 drm_connector_list_iter_begin(display->drm, &conn_iter); 5977 drm_for_each_connector_iter(connector, &conn_iter) { 5978 struct drm_connector_state *conn_state; 5979 struct intel_crtc_state *crtc_state; 5980 struct intel_crtc *crtc; 5981 5982 if (!connector->has_tile || 5983 connector->tile_group->id != tile_group_id) 5984 continue; 5985 5986 conn_state = drm_atomic_get_connector_state(&state->base, 5987 connector); 5988 if (IS_ERR(conn_state)) { 5989 ret = PTR_ERR(conn_state); 5990 break; 5991 } 5992 5993 crtc = to_intel_crtc(conn_state->crtc); 5994 5995 if (!crtc) 5996 continue; 5997 5998 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 5999 crtc_state->uapi.mode_changed = true; 6000 6001 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6002 if (ret) 6003 break; 6004 } 6005 drm_connector_list_iter_end(&conn_iter); 6006 6007 return ret; 6008 } 6009 6010 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) 6011 { 6012 struct intel_display *display = to_intel_display(state); 6013 struct intel_crtc *crtc; 6014 6015 if (transcoders == 0) 6016 return 0; 6017 6018 for_each_intel_crtc(display->drm, crtc) { 6019 struct intel_crtc_state *crtc_state; 6020 int ret; 6021 6022 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6023 if (IS_ERR(crtc_state)) 6024 return PTR_ERR(crtc_state); 6025 6026 if (!crtc_state->hw.enable) 6027 continue; 6028 6029 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) 6030 continue; 6031 6032 crtc_state->uapi.mode_changed = true; 6033 6034 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6035 if (ret) 6036 return ret; 6037 6038 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6039 if (ret) 6040 return ret; 6041 6042 transcoders &= ~BIT(crtc_state->cpu_transcoder); 6043 } 6044 6045 drm_WARN_ON(display->drm, transcoders != 0); 6046 6047 return 0; 6048 } 6049 6050 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, 6051 struct drm_connector *connector) 6052 { 6053 const struct drm_connector_state *old_conn_state = 6054 drm_atomic_get_old_connector_state(&state->base, connector); 6055 const struct intel_crtc_state *old_crtc_state; 6056 struct intel_crtc *crtc; 6057 u8 transcoders; 6058 6059 crtc = to_intel_crtc(old_conn_state->crtc); 6060 if (!crtc) 6061 return 0; 6062 6063 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6064 6065 if (!old_crtc_state->hw.active) 6066 return 0; 6067 6068 transcoders = old_crtc_state->sync_mode_slaves_mask; 6069 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) 6070 transcoders |= BIT(old_crtc_state->master_transcoder); 6071 6072 return intel_modeset_affected_transcoders(state, 6073 transcoders); 6074 } 6075 6076 static int intel_dp_connector_atomic_check(struct drm_connector *conn, 6077 struct drm_atomic_state *_state) 6078 { 6079 struct intel_display *display = to_intel_display(conn->dev); 6080 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6081 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn); 6082 struct intel_connector *intel_conn = to_intel_connector(conn); 6083 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder); 6084 int ret; 6085 6086 ret = intel_digital_connector_atomic_check(conn, &state->base); 6087 if (ret) 6088 return ret; 6089 6090 if (intel_dp_mst_source_support(intel_dp)) { 6091 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr); 6092 if (ret) 6093 return ret; 6094 } 6095 6096 if (!intel_connector_needs_modeset(state, conn)) 6097 return 0; 6098 6099 ret = intel_dp_tunnel_atomic_check_state(state, 6100 intel_dp, 6101 intel_conn); 6102 if (ret) 6103 return ret; 6104 6105 /* 6106 * We don't enable port sync on BDW due to missing w/as and 6107 * due to not having adjusted the modeset sequence appropriately. 6108 */ 6109 if (DISPLAY_VER(display) < 9) 6110 return 0; 6111 6112 if (conn->has_tile) { 6113 ret = intel_modeset_tile_group(state, conn->tile_group->id); 6114 if (ret) 6115 return ret; 6116 } 6117 6118 return intel_modeset_synced_crtcs(state, conn); 6119 } 6120 6121 static void intel_dp_oob_hotplug_event(struct drm_connector *connector, 6122 enum drm_connector_status hpd_state) 6123 { 6124 struct intel_display *display = to_intel_display(connector->dev); 6125 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 6126 struct drm_i915_private *i915 = to_i915(connector->dev); 6127 bool hpd_high = hpd_state == connector_status_connected; 6128 unsigned int hpd_pin = encoder->hpd_pin; 6129 bool need_work = false; 6130 6131 spin_lock_irq(&i915->irq_lock); 6132 if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) { 6133 display->hotplug.event_bits |= BIT(hpd_pin); 6134 6135 __assign_bit(hpd_pin, 6136 &display->hotplug.oob_hotplug_last_state, 6137 hpd_high); 6138 need_work = true; 6139 } 6140 spin_unlock_irq(&i915->irq_lock); 6141 6142 if (need_work) 6143 intel_hpd_schedule_detection(i915); 6144 } 6145 6146 static const struct drm_connector_funcs intel_dp_connector_funcs = { 6147 .force = intel_dp_force, 6148 .fill_modes = drm_helper_probe_single_connector_modes, 6149 .atomic_get_property = intel_digital_connector_atomic_get_property, 6150 .atomic_set_property = intel_digital_connector_atomic_set_property, 6151 .late_register = intel_dp_connector_register, 6152 .early_unregister = intel_dp_connector_unregister, 6153 .destroy = intel_connector_destroy, 6154 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6155 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 6156 .oob_hotplug_event = intel_dp_oob_hotplug_event, 6157 }; 6158 6159 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 6160 .detect_ctx = intel_dp_detect, 6161 .get_modes = intel_dp_get_modes, 6162 .mode_valid = intel_dp_mode_valid, 6163 .atomic_check = intel_dp_connector_atomic_check, 6164 }; 6165 6166 enum irqreturn 6167 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) 6168 { 6169 struct intel_display *display = to_intel_display(dig_port); 6170 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 6171 struct intel_dp *intel_dp = &dig_port->dp; 6172 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 6173 6174 if (dig_port->base.type == INTEL_OUTPUT_EDP && 6175 (long_hpd || 6176 intel_runtime_pm_suspended(&i915->runtime_pm) || 6177 !intel_pps_have_panel_power_or_vdd(intel_dp))) { 6178 /* 6179 * vdd off can generate a long/short pulse on eDP which 6180 * would require vdd on to handle it, and thus we 6181 * would end up in an endless cycle of 6182 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." 6183 */ 6184 drm_dbg_kms(display->drm, 6185 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", 6186 long_hpd ? "long" : "short", 6187 dig_port->base.base.base.id, 6188 dig_port->base.base.name); 6189 return IRQ_HANDLED; 6190 } 6191 6192 drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", 6193 dig_port->base.base.base.id, 6194 dig_port->base.base.name, 6195 long_hpd ? "long" : "short"); 6196 6197 /* 6198 * TBT DP tunnels require the GFX driver to read out the DPRX caps in 6199 * response to long HPD pulses. The DP hotplug handler does that, 6200 * however the hotplug handler may be blocked by another 6201 * connector's/encoder's hotplug handler. Since the TBT CM may not 6202 * complete the DP tunnel BW request for the latter connector/encoder 6203 * waiting for this encoder's DPRX read, perform a dummy read here. 6204 */ 6205 if (long_hpd) 6206 intel_dp_read_dprx_caps(intel_dp, dpcd); 6207 6208 if (long_hpd) { 6209 intel_dp->reset_link_params = true; 6210 intel_dp_invalidate_source_oui(intel_dp); 6211 6212 return IRQ_NONE; 6213 } 6214 6215 if (intel_dp->is_mst) { 6216 if (!intel_dp_check_mst_status(intel_dp)) 6217 return IRQ_NONE; 6218 } else if (!intel_dp_short_pulse(intel_dp)) { 6219 return IRQ_NONE; 6220 } 6221 6222 return IRQ_HANDLED; 6223 } 6224 6225 static bool _intel_dp_is_port_edp(struct intel_display *display, 6226 const struct intel_bios_encoder_data *devdata, 6227 enum port port) 6228 { 6229 /* 6230 * eDP not supported on g4x. so bail out early just 6231 * for a bit extra safety in case the VBT is bonkers. 6232 */ 6233 if (DISPLAY_VER(display) < 5) 6234 return false; 6235 6236 if (DISPLAY_VER(display) < 9 && port == PORT_A) 6237 return true; 6238 6239 return devdata && intel_bios_encoder_supports_edp(devdata); 6240 } 6241 6242 bool intel_dp_is_port_edp(struct intel_display *display, enum port port) 6243 { 6244 const struct intel_bios_encoder_data *devdata = 6245 intel_bios_encoder_data_lookup(display, port); 6246 6247 return _intel_dp_is_port_edp(display, devdata, port); 6248 } 6249 6250 bool 6251 intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder) 6252 { 6253 struct intel_display *display = to_intel_display(encoder); 6254 enum port port = encoder->port; 6255 6256 if (intel_bios_encoder_is_lspcon(encoder->devdata)) 6257 return false; 6258 6259 if (DISPLAY_VER(display) >= 11) 6260 return true; 6261 6262 if (port == PORT_A) 6263 return false; 6264 6265 if (display->platform.haswell || display->platform.broadwell || 6266 DISPLAY_VER(display) >= 9) 6267 return true; 6268 6269 return false; 6270 } 6271 6272 static void 6273 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 6274 { 6275 struct intel_display *display = to_intel_display(intel_dp); 6276 enum port port = dp_to_dig_port(intel_dp)->base.port; 6277 6278 if (!intel_dp_is_edp(intel_dp)) 6279 drm_connector_attach_dp_subconnector_property(connector); 6280 6281 if (!display->platform.g4x && port != PORT_A) 6282 intel_attach_force_audio_property(connector); 6283 6284 intel_attach_broadcast_rgb_property(connector); 6285 if (HAS_GMCH(display)) 6286 drm_connector_attach_max_bpc_property(connector, 6, 10); 6287 else if (DISPLAY_VER(display) >= 5) 6288 drm_connector_attach_max_bpc_property(connector, 6, 12); 6289 6290 /* Register HDMI colorspace for case of lspcon */ 6291 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) { 6292 drm_connector_attach_content_type_property(connector); 6293 intel_attach_hdmi_colorspace_property(connector); 6294 } else { 6295 intel_attach_dp_colorspace_property(connector); 6296 } 6297 6298 if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) 6299 drm_connector_attach_hdr_output_metadata_property(connector); 6300 6301 if (HAS_VRR(display)) 6302 drm_connector_attach_vrr_capable_property(connector); 6303 } 6304 6305 static void 6306 intel_edp_add_properties(struct intel_dp *intel_dp) 6307 { 6308 struct intel_display *display = to_intel_display(intel_dp); 6309 struct intel_connector *connector = intel_dp->attached_connector; 6310 const struct drm_display_mode *fixed_mode = 6311 intel_panel_preferred_fixed_mode(connector); 6312 6313 intel_attach_scaling_mode_property(&connector->base); 6314 6315 drm_connector_set_panel_orientation_with_quirk(&connector->base, 6316 display->vbt.orientation, 6317 fixed_mode->hdisplay, 6318 fixed_mode->vdisplay); 6319 } 6320 6321 static void intel_edp_backlight_setup(struct intel_dp *intel_dp, 6322 struct intel_connector *connector) 6323 { 6324 struct intel_display *display = to_intel_display(intel_dp); 6325 enum pipe pipe = INVALID_PIPE; 6326 6327 if (display->platform.valleyview || display->platform.cherryview) 6328 pipe = vlv_pps_backlight_initial_pipe(intel_dp); 6329 6330 intel_backlight_setup(connector, pipe); 6331 } 6332 6333 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 6334 struct intel_connector *connector) 6335 { 6336 struct intel_display *display = to_intel_display(intel_dp); 6337 struct drm_i915_private *dev_priv = to_i915(display->drm); 6338 struct drm_display_mode *fixed_mode; 6339 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 6340 bool has_dpcd; 6341 const struct drm_edid *drm_edid; 6342 6343 if (!intel_dp_is_edp(intel_dp)) 6344 return true; 6345 6346 /* 6347 * On IBX/CPT we may get here with LVDS already registered. Since the 6348 * driver uses the only internal power sequencer available for both 6349 * eDP and LVDS bail out early in this case to prevent interfering 6350 * with an already powered-on LVDS power sequencer. 6351 */ 6352 if (intel_get_lvds_encoder(dev_priv)) { 6353 drm_WARN_ON(display->drm, 6354 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 6355 drm_info(display->drm, 6356 "LVDS was detected, not registering eDP\n"); 6357 6358 return false; 6359 } 6360 6361 intel_bios_init_panel_early(display, &connector->panel, 6362 encoder->devdata); 6363 6364 if (!intel_pps_init(intel_dp)) { 6365 drm_info(display->drm, 6366 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n", 6367 encoder->base.base.id, encoder->base.name); 6368 /* 6369 * The BIOS may have still enabled VDD on the PPS even 6370 * though it's unusable. Make sure we turn it back off 6371 * and to release the power domain references/etc. 6372 */ 6373 goto out_vdd_off; 6374 } 6375 6376 /* 6377 * Enable HPD sense for live status check. 6378 * intel_hpd_irq_setup() will turn it off again 6379 * if it's no longer needed later. 6380 * 6381 * The DPCD probe below will make sure VDD is on. 6382 */ 6383 intel_hpd_enable_detection(encoder); 6384 6385 intel_alpm_init_dpcd(intel_dp); 6386 6387 /* Cache DPCD and EDID for edp. */ 6388 has_dpcd = intel_edp_init_dpcd(intel_dp, connector); 6389 6390 if (!has_dpcd) { 6391 /* if this fails, presume the device is a ghost */ 6392 drm_info(display->drm, 6393 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n", 6394 encoder->base.base.id, encoder->base.name); 6395 goto out_vdd_off; 6396 } 6397 6398 /* 6399 * VBT and straps are liars. Also check HPD as that seems 6400 * to be the most reliable piece of information available. 6401 * 6402 * ... expect on devices that forgot to hook HPD up for eDP 6403 * (eg. Acer Chromebook C710), so we'll check it only if multiple 6404 * ports are attempting to use the same AUX CH, according to VBT. 6405 */ 6406 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) { 6407 /* 6408 * If this fails, presume the DPCD answer came 6409 * from some other port using the same AUX CH. 6410 * 6411 * FIXME maybe cleaner to check this before the 6412 * DPCD read? Would need sort out the VDD handling... 6413 */ 6414 if (!intel_digital_port_connected(encoder)) { 6415 drm_info(display->drm, 6416 "[ENCODER:%d:%s] HPD is down, disabling eDP\n", 6417 encoder->base.base.id, encoder->base.name); 6418 goto out_vdd_off; 6419 } 6420 6421 /* 6422 * Unfortunately even the HPD based detection fails on 6423 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall 6424 * back to checking for a VGA branch device. Only do this 6425 * on known affected platforms to minimize false positives. 6426 */ 6427 if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) && 6428 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) == 6429 DP_DWN_STRM_PORT_TYPE_ANALOG) { 6430 drm_info(display->drm, 6431 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n", 6432 encoder->base.base.id, encoder->base.name); 6433 goto out_vdd_off; 6434 } 6435 } 6436 6437 mutex_lock(&display->drm->mode_config.mutex); 6438 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc); 6439 if (!drm_edid) { 6440 /* Fallback to EDID from ACPI OpRegion, if any */ 6441 drm_edid = intel_opregion_get_edid(connector); 6442 if (drm_edid) 6443 drm_dbg_kms(display->drm, 6444 "[CONNECTOR:%d:%s] Using OpRegion EDID\n", 6445 connector->base.base.id, connector->base.name); 6446 } 6447 if (drm_edid) { 6448 if (drm_edid_connector_update(&connector->base, drm_edid) || 6449 !drm_edid_connector_add_modes(&connector->base)) { 6450 drm_edid_connector_update(&connector->base, NULL); 6451 drm_edid_free(drm_edid); 6452 drm_edid = ERR_PTR(-EINVAL); 6453 } 6454 } else { 6455 drm_edid = ERR_PTR(-ENOENT); 6456 } 6457 6458 intel_bios_init_panel_late(display, &connector->panel, encoder->devdata, 6459 IS_ERR(drm_edid) ? NULL : drm_edid); 6460 6461 intel_panel_add_edid_fixed_modes(connector, true); 6462 6463 /* MSO requires information from the EDID */ 6464 intel_edp_mso_init(intel_dp); 6465 6466 /* multiply the mode clock and horizontal timings for MSO */ 6467 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) 6468 intel_edp_mso_mode_fixup(connector, fixed_mode); 6469 6470 /* fallback to VBT if available for eDP */ 6471 if (!intel_panel_preferred_fixed_mode(connector)) 6472 intel_panel_add_vbt_lfp_fixed_mode(connector); 6473 6474 mutex_unlock(&display->drm->mode_config.mutex); 6475 6476 if (!intel_panel_preferred_fixed_mode(connector)) { 6477 drm_info(display->drm, 6478 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n", 6479 encoder->base.base.id, encoder->base.name); 6480 goto out_vdd_off; 6481 } 6482 6483 intel_panel_init(connector, drm_edid); 6484 6485 intel_edp_backlight_setup(intel_dp, connector); 6486 6487 intel_edp_add_properties(intel_dp); 6488 6489 intel_pps_init_late(intel_dp); 6490 6491 return true; 6492 6493 out_vdd_off: 6494 intel_pps_vdd_off_sync(intel_dp); 6495 intel_bios_fini_panel(&connector->panel); 6496 6497 return false; 6498 } 6499 6500 static void intel_dp_modeset_retry_work_fn(struct work_struct *work) 6501 { 6502 struct intel_connector *connector = container_of(work, typeof(*connector), 6503 modeset_retry_work); 6504 struct intel_display *display = to_intel_display(connector); 6505 6506 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id, 6507 connector->base.name); 6508 6509 /* Grab the locks before changing connector property*/ 6510 mutex_lock(&display->drm->mode_config.mutex); 6511 /* Set connector link status to BAD and send a Uevent to notify 6512 * userspace to do a modeset. 6513 */ 6514 drm_connector_set_link_status_property(&connector->base, 6515 DRM_MODE_LINK_STATUS_BAD); 6516 mutex_unlock(&display->drm->mode_config.mutex); 6517 /* Send Hotplug uevent so userspace can reprobe */ 6518 drm_kms_helper_connector_hotplug_event(&connector->base); 6519 6520 drm_connector_put(&connector->base); 6521 } 6522 6523 void intel_dp_init_modeset_retry_work(struct intel_connector *connector) 6524 { 6525 INIT_WORK(&connector->modeset_retry_work, 6526 intel_dp_modeset_retry_work_fn); 6527 } 6528 6529 bool 6530 intel_dp_init_connector(struct intel_digital_port *dig_port, 6531 struct intel_connector *connector) 6532 { 6533 struct intel_display *display = to_intel_display(dig_port); 6534 struct intel_dp *intel_dp = &dig_port->dp; 6535 struct intel_encoder *encoder = &dig_port->base; 6536 struct drm_device *dev = encoder->base.dev; 6537 struct drm_i915_private *dev_priv = to_i915(dev); 6538 enum port port = encoder->port; 6539 int type; 6540 6541 /* Initialize the work for modeset in case of link train failure */ 6542 intel_dp_init_modeset_retry_work(connector); 6543 6544 if (drm_WARN(dev, dig_port->max_lanes < 1, 6545 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", 6546 dig_port->max_lanes, encoder->base.base.id, 6547 encoder->base.name)) 6548 return false; 6549 6550 intel_dp->reset_link_params = true; 6551 6552 /* Preserve the current hw state. */ 6553 intel_dp->DP = intel_de_read(display, intel_dp->output_reg); 6554 intel_dp->attached_connector = connector; 6555 6556 if (_intel_dp_is_port_edp(display, encoder->devdata, port)) { 6557 /* 6558 * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30, 6559 * although in theory it could work on TypeC legacy ports. 6560 */ 6561 drm_WARN_ON(dev, intel_encoder_is_tc(encoder) && 6562 DISPLAY_VER(display) < 30); 6563 type = DRM_MODE_CONNECTOR_eDP; 6564 encoder->type = INTEL_OUTPUT_EDP; 6565 6566 /* eDP only on port B and/or C on vlv/chv */ 6567 if (drm_WARN_ON(dev, (display->platform.valleyview || 6568 display->platform.cherryview) && 6569 port != PORT_B && port != PORT_C)) 6570 return false; 6571 } else { 6572 type = DRM_MODE_CONNECTOR_DisplayPort; 6573 } 6574 6575 intel_dp_set_default_sink_rates(intel_dp); 6576 intel_dp_set_default_max_sink_lane_count(intel_dp); 6577 6578 if (display->platform.valleyview || display->platform.cherryview) 6579 vlv_pps_pipe_init(intel_dp); 6580 6581 intel_dp_aux_init(intel_dp); 6582 connector->dp.dsc_decompression_aux = &intel_dp->aux; 6583 6584 drm_dbg_kms(display->drm, 6585 "Adding %s connector on [ENCODER:%d:%s]\n", 6586 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 6587 encoder->base.base.id, encoder->base.name); 6588 6589 drm_connector_init_with_ddc(dev, &connector->base, &intel_dp_connector_funcs, 6590 type, &intel_dp->aux.ddc); 6591 drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs); 6592 6593 if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12) 6594 connector->base.interlace_allowed = true; 6595 6596 if (type != DRM_MODE_CONNECTOR_eDP) 6597 connector->polled = DRM_CONNECTOR_POLL_HPD; 6598 connector->base.polled = connector->polled; 6599 6600 intel_connector_attach_encoder(connector, encoder); 6601 6602 if (HAS_DDI(display)) 6603 connector->get_hw_state = intel_ddi_connector_get_hw_state; 6604 else 6605 connector->get_hw_state = intel_connector_get_hw_state; 6606 connector->sync_state = intel_dp_connector_sync_state; 6607 6608 if (!intel_edp_init_connector(intel_dp, connector)) { 6609 intel_dp_aux_fini(intel_dp); 6610 goto fail; 6611 } 6612 6613 intel_dp_set_source_rates(intel_dp); 6614 intel_dp_set_common_rates(intel_dp); 6615 intel_dp_reset_link_params(intel_dp); 6616 6617 /* init MST on ports that can support it */ 6618 intel_dp_mst_encoder_init(dig_port, connector->base.base.id); 6619 6620 intel_dp_add_properties(intel_dp, &connector->base); 6621 6622 if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) { 6623 int ret = intel_dp_hdcp_init(dig_port, connector); 6624 if (ret) 6625 drm_dbg_kms(display->drm, 6626 "HDCP init failed, skipping.\n"); 6627 } 6628 6629 intel_dp->frl.is_trained = false; 6630 intel_dp->frl.trained_rate_gbps = 0; 6631 6632 intel_psr_init(intel_dp); 6633 6634 return true; 6635 6636 fail: 6637 intel_display_power_flush_work(dev_priv); 6638 drm_connector_cleanup(&connector->base); 6639 6640 return false; 6641 } 6642 6643 void intel_dp_mst_suspend(struct intel_display *display) 6644 { 6645 struct intel_encoder *encoder; 6646 6647 if (!HAS_DISPLAY(display)) 6648 return; 6649 6650 for_each_intel_encoder(display->drm, encoder) { 6651 struct intel_dp *intel_dp; 6652 6653 if (encoder->type != INTEL_OUTPUT_DDI) 6654 continue; 6655 6656 intel_dp = enc_to_intel_dp(encoder); 6657 6658 if (!intel_dp_mst_source_support(intel_dp)) 6659 continue; 6660 6661 if (intel_dp->is_mst) 6662 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); 6663 } 6664 } 6665 6666 void intel_dp_mst_resume(struct intel_display *display) 6667 { 6668 struct intel_encoder *encoder; 6669 6670 if (!HAS_DISPLAY(display)) 6671 return; 6672 6673 for_each_intel_encoder(display->drm, encoder) { 6674 struct intel_dp *intel_dp; 6675 int ret; 6676 6677 if (encoder->type != INTEL_OUTPUT_DDI) 6678 continue; 6679 6680 intel_dp = enc_to_intel_dp(encoder); 6681 6682 if (!intel_dp_mst_source_support(intel_dp)) 6683 continue; 6684 6685 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, 6686 true); 6687 if (ret) { 6688 intel_dp->is_mst = false; 6689 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 6690 false); 6691 } 6692 } 6693 } 6694