1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/export.h> 29 #include <linux/i2c.h> 30 #include <linux/iopoll.h> 31 #include <linux/log2.h> 32 #include <linux/math.h> 33 #include <linux/notifier.h> 34 #include <linux/seq_buf.h> 35 #include <linux/slab.h> 36 #include <linux/string_helpers.h> 37 #include <linux/timekeeping.h> 38 #include <linux/types.h> 39 #include <asm/byteorder.h> 40 41 #include <drm/display/drm_dp_helper.h> 42 #include <drm/display/drm_dp_tunnel.h> 43 #include <drm/display/drm_dsc_helper.h> 44 #include <drm/display/drm_hdmi_helper.h> 45 #include <drm/drm_atomic_helper.h> 46 #include <drm/drm_crtc.h> 47 #include <drm/drm_edid.h> 48 #include <drm/drm_fixed.h> 49 #include <drm/drm_print.h> 50 #include <drm/drm_probe_helper.h> 51 52 #include "g4x_dp.h" 53 #include "intel_alpm.h" 54 #include "intel_atomic.h" 55 #include "intel_audio.h" 56 #include "intel_backlight.h" 57 #include "intel_combo_phy_regs.h" 58 #include "intel_connector.h" 59 #include "intel_crtc.h" 60 #include "intel_crtc_state_dump.h" 61 #include "intel_cx0_phy.h" 62 #include "intel_ddi.h" 63 #include "intel_de.h" 64 #include "intel_display_driver.h" 65 #include "intel_display_jiffies.h" 66 #include "intel_display_utils.h" 67 #include "intel_display_regs.h" 68 #include "intel_display_rpm.h" 69 #include "intel_display_types.h" 70 #include "intel_dp.h" 71 #include "intel_dp_aux.h" 72 #include "intel_dp_hdcp.h" 73 #include "intel_dp_link_caps.h" 74 #include "intel_dp_link_training.h" 75 #include "intel_dp_mst.h" 76 #include "intel_dp_test.h" 77 #include "intel_dp_tunnel.h" 78 #include "intel_dpio_phy.h" 79 #include "intel_dpll.h" 80 #include "intel_drrs.h" 81 #include "intel_encoder.h" 82 #include "intel_fifo_underrun.h" 83 #include "intel_hdcp.h" 84 #include "intel_hdmi.h" 85 #include "intel_hotplug.h" 86 #include "intel_hotplug_irq.h" 87 #include "intel_lspcon.h" 88 #include "intel_lvds.h" 89 #include "intel_modeset_lock.h" 90 #include "intel_panel.h" 91 #include "intel_pch_display.h" 92 #include "intel_pfit.h" 93 #include "intel_pps.h" 94 #include "intel_psr.h" 95 #include "intel_quirks.h" 96 #include "intel_tc.h" 97 #include "intel_vblank.h" 98 #include "intel_vdsc.h" 99 #include "intel_vrr.h" 100 101 /* Max DSC line buffer depth supported by HW. */ 102 #define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13 103 104 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ 105 #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530 106 107 /* Constants for DP DSC configurations */ 108 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 109 110 /** 111 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 112 * @intel_dp: DP struct 113 * 114 * If a CPU or PCH DP output is attached to an eDP panel, this function 115 * will return true, and false otherwise. 116 * 117 * This function is not safe to use prior to encoder type being set. 118 */ 119 bool intel_dp_is_edp(struct intel_dp *intel_dp) 120 { 121 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 122 123 return dig_port->base.type == INTEL_OUTPUT_EDP; 124 } 125 126 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 127 128 /* Is link rate UHBR and thus 128b/132b? */ 129 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) 130 { 131 return drm_dp_is_uhbr_rate(crtc_state->port_clock); 132 } 133 134 /** 135 * intel_dp_link_symbol_size - get the link symbol size for a given link rate 136 * @rate: link rate in 10kbit/s units 137 * 138 * Returns the link symbol size in bits/symbol units depending on the link 139 * rate -> channel coding. 140 */ 141 int intel_dp_link_symbol_size(int rate) 142 { 143 return drm_dp_is_uhbr_rate(rate) ? 32 : 10; 144 } 145 146 /** 147 * intel_dp_link_symbol_clock - convert link rate to link symbol clock 148 * @rate: link rate in 10kbit/s units 149 * 150 * Returns the link symbol clock frequency in kHz units depending on the 151 * link rate and channel coding. 152 */ 153 int intel_dp_link_symbol_clock(int rate) 154 { 155 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate)); 156 } 157 158 static int max_dprx_rate(struct intel_dp *intel_dp) 159 { 160 struct intel_display *display = to_intel_display(intel_dp); 161 int max_rate; 162 163 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 164 max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); 165 else 166 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 167 168 /* 169 * Some platforms + eDP panels may not reliably support HBR3 170 * due to signal integrity limitations, despite advertising it. 171 * Cap the link rate to HBR2 to avoid unstable configurations for the 172 * known machines. 173 */ 174 if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2)) 175 max_rate = min(max_rate, 540000); 176 177 return max_rate; 178 } 179 180 static int max_dprx_lane_count(struct intel_dp *intel_dp) 181 { 182 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 183 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel); 184 185 return drm_dp_max_lane_count(intel_dp->dpcd); 186 } 187 188 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) 189 { 190 intel_dp->sink_rates[0] = 162000; 191 intel_dp->num_sink_rates = 1; 192 } 193 194 /* update sink rates from dpcd */ 195 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) 196 { 197 static const int dp_rates[] = { 198 162000, 270000, 540000, 810000 199 }; 200 int i, max_rate; 201 int max_lttpr_rate; 202 203 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { 204 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ 205 static const int quirk_rates[] = { 162000, 270000, 324000 }; 206 207 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); 208 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); 209 210 return; 211 } 212 213 /* 214 * Sink rates for 8b/10b. 215 */ 216 max_rate = max_dprx_rate(intel_dp); 217 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); 218 if (max_lttpr_rate) 219 max_rate = min(max_rate, max_lttpr_rate); 220 221 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { 222 if (dp_rates[i] > max_rate) 223 break; 224 intel_dp->sink_rates[i] = dp_rates[i]; 225 } 226 227 /* 228 * Sink rates for 128b/132b. If set, sink should support all 8b/10b 229 * rates and 10 Gbps. 230 */ 231 if (drm_dp_128b132b_supported(intel_dp->dpcd)) { 232 u8 uhbr_rates = 0; 233 234 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); 235 236 drm_dp_dpcd_readb(&intel_dp->aux, 237 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates); 238 239 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) { 240 /* We have a repeater */ 241 if (intel_dp->lttpr_common_caps[0] >= 0x20 && 242 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 243 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] & 244 DP_PHY_REPEATER_128B132B_SUPPORTED) { 245 /* Repeater supports 128b/132b, valid UHBR rates */ 246 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES - 247 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 248 } else { 249 /* Does not support 128b/132b */ 250 uhbr_rates = 0; 251 } 252 } 253 254 if (uhbr_rates & DP_UHBR10) 255 intel_dp->sink_rates[i++] = 1000000; 256 if (uhbr_rates & DP_UHBR13_5) 257 intel_dp->sink_rates[i++] = 1350000; 258 if (uhbr_rates & DP_UHBR20) 259 intel_dp->sink_rates[i++] = 2000000; 260 } 261 262 intel_dp->num_sink_rates = i; 263 } 264 265 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 266 { 267 struct intel_display *display = to_intel_display(intel_dp); 268 struct intel_connector *connector = intel_dp->attached_connector; 269 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 270 struct intel_encoder *encoder = &intel_dig_port->base; 271 272 intel_dp_set_dpcd_sink_rates(intel_dp); 273 274 if (intel_dp->num_sink_rates) 275 return; 276 277 drm_err(display->drm, 278 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", 279 connector->base.base.id, connector->base.name, 280 encoder->base.base.id, encoder->base.name); 281 282 intel_dp_set_default_sink_rates(intel_dp); 283 } 284 285 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp) 286 { 287 intel_dp->max_sink_lane_count = 1; 288 } 289 290 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp) 291 { 292 struct intel_display *display = to_intel_display(intel_dp); 293 struct intel_connector *connector = intel_dp->attached_connector; 294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 295 struct intel_encoder *encoder = &intel_dig_port->base; 296 297 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp); 298 299 switch (intel_dp->max_sink_lane_count) { 300 case 1: 301 case 2: 302 case 4: 303 return; 304 } 305 306 drm_err(display->drm, 307 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", 308 connector->base.base.id, connector->base.name, 309 encoder->base.base.id, encoder->base.name, 310 intel_dp->max_sink_lane_count); 311 312 intel_dp_set_default_max_sink_lane_count(intel_dp); 313 } 314 315 /* Get length of rates array potentially limited by max_rate. */ 316 int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) 317 { 318 int i; 319 320 /* Limit results by potentially reduced max rate */ 321 for (i = 0; i < len; i++) { 322 if (rates[len - i - 1] <= max_rate) 323 return len - i; 324 } 325 326 return 0; 327 } 328 329 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) 330 { 331 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); 332 int max_lanes = dig_port->max_lanes; 333 334 if (vbt_max_lanes) 335 max_lanes = min(max_lanes, vbt_max_lanes); 336 337 return max_lanes; 338 } 339 340 /* 341 * Theoretical max between source and sink. 342 */ 343 static int intel_dp_get_max_common_lane_count(struct intel_dp *intel_dp) 344 { 345 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 346 int source_max = intel_dp_max_source_lane_count(dig_port); 347 int sink_max = intel_dp->max_sink_lane_count; 348 int lane_max = intel_tc_port_max_lane_count(dig_port); 349 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); 350 351 if (lttpr_max) 352 sink_max = min(sink_max, lttpr_max); 353 354 return min3(source_max, sink_max, lane_max); 355 } 356 357 int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, 358 int dsc_slice_count, int bpp_x16, unsigned long flags) 359 { 360 int overhead; 361 362 WARN_ON(flags & ~(DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK | 363 DRM_DP_BW_OVERHEAD_FEC)); 364 365 if (drm_dp_is_uhbr_rate(link_clock)) 366 flags |= DRM_DP_BW_OVERHEAD_UHBR; 367 368 if (dsc_slice_count) 369 flags |= DRM_DP_BW_OVERHEAD_DSC; 370 371 overhead = drm_dp_bw_overhead(lane_count, hdisplay, 372 dsc_slice_count, 373 bpp_x16, 374 flags); 375 376 /* 377 * TODO: clarify whether a minimum required by the fixed FEC overhead 378 * in the bspec audio programming sequence is required here. 379 */ 380 return max(overhead, intel_dp_bw_fec_overhead(flags & DRM_DP_BW_OVERHEAD_FEC)); 381 } 382 383 /* 384 * The required data bandwidth for a mode with given pixel clock and bpp. This 385 * is the required net bandwidth independent of the data bandwidth efficiency. 386 */ 387 int intel_dp_link_required(int link_clock, int lane_count, 388 int mode_clock, int mode_hdisplay, 389 int link_bpp_x16, unsigned long bw_overhead_flags) 390 { 391 int bw_overhead = intel_dp_link_bw_overhead(link_clock, lane_count, mode_hdisplay, 392 0, link_bpp_x16, bw_overhead_flags); 393 394 return intel_dp_effective_data_rate(mode_clock, link_bpp_x16, bw_overhead); 395 } 396 397 /** 398 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead 399 * @pixel_clock: pixel clock in kHz 400 * @bpp_x16: bits per pixel .4 fixed point format 401 * @bw_overhead: BW allocation overhead in 1ppm units 402 * 403 * Return the effective pixel data rate in kB/sec units taking into account 404 * the provided SSC, FEC, DSC BW allocation overhead. 405 */ 406 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 407 int bw_overhead) 408 { 409 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead), 410 1000000 * 16 * 8); 411 } 412 413 /** 414 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params 415 * @intel_dp: Intel DP object 416 * @max_dprx_rate: Maximum data rate of the DPRX 417 * @max_dprx_lanes: Maximum lane count of the DPRX 418 * 419 * Calculate the maximum data rate for the provided link parameters taking into 420 * account any BW limitations by a DP tunnel attached to @intel_dp. 421 * 422 * Returns the maximum data rate in kBps units. 423 */ 424 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, 425 int max_dprx_rate, int max_dprx_lanes) 426 { 427 int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes); 428 429 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 430 max_rate = min(max_rate, 431 drm_dp_tunnel_available_bw(intel_dp->tunnel)); 432 433 return max_rate; 434 } 435 436 bool intel_dp_has_joiner(struct intel_dp *intel_dp) 437 { 438 struct intel_display *display = to_intel_display(intel_dp); 439 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 440 struct intel_encoder *encoder = &intel_dig_port->base; 441 struct intel_connector *connector = intel_dp->attached_connector; 442 443 /* eDP MSO is not compatible with joiner */ 444 if (intel_dp->mso_link_count) 445 return false; 446 447 if (intel_dp_is_edp(intel_dp) && 448 !connector->panel.vbt.edp.pipe_joiner_enable) 449 return false; 450 451 return DISPLAY_VER(display) >= 12 || 452 (DISPLAY_VER(display) == 11 && 453 encoder->port != PORT_A); 454 } 455 456 static int dg2_max_source_rate(struct intel_dp *intel_dp) 457 { 458 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000; 459 } 460 461 static int icl_max_source_rate(struct intel_dp *intel_dp) 462 { 463 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 464 465 if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp)) 466 return 540000; 467 468 return 810000; 469 } 470 471 static int ehl_max_source_rate(struct intel_dp *intel_dp) 472 { 473 if (intel_dp_is_edp(intel_dp)) 474 return 540000; 475 476 return 810000; 477 } 478 479 static int mtl_max_source_rate(struct intel_dp *intel_dp) 480 { 481 struct intel_display *display = to_intel_display(intel_dp); 482 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 483 484 if (intel_encoder_is_c10phy(encoder) || 485 display->platform.pantherlake_wildcatlake) 486 return 810000; 487 488 if (DISPLAY_VERx100(display) == 1401) 489 return 1350000; 490 491 return 2000000; 492 } 493 494 static int vbt_max_link_rate(struct intel_dp *intel_dp) 495 { 496 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 497 int max_rate; 498 499 max_rate = intel_bios_dp_max_link_rate(encoder->devdata); 500 501 if (intel_dp_is_edp(intel_dp)) { 502 struct intel_connector *connector = intel_dp->attached_connector; 503 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; 504 505 if (max_rate && edp_max_rate) 506 max_rate = min(max_rate, edp_max_rate); 507 else if (edp_max_rate) 508 max_rate = edp_max_rate; 509 } 510 511 return max_rate; 512 } 513 514 static void 515 intel_dp_set_source_rates(struct intel_dp *intel_dp) 516 { 517 /* The values must be in increasing order */ 518 static const int bmg_rates[] = { 519 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 520 810000, 1000000, 1350000, 521 }; 522 static const int mtl_rates[] = { 523 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 524 810000, 1000000, 2000000, 525 }; 526 static const int icl_rates[] = { 527 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000, 528 1000000, 1350000, 529 }; 530 static const int bxt_rates[] = { 531 162000, 216000, 243000, 270000, 324000, 432000, 540000 532 }; 533 static const int skl_rates[] = { 534 162000, 216000, 270000, 324000, 432000, 540000 535 }; 536 static const int hsw_rates[] = { 537 162000, 270000, 540000 538 }; 539 static const int g4x_rates[] = { 540 162000, 270000 541 }; 542 struct intel_display *display = to_intel_display(intel_dp); 543 const int *source_rates; 544 int size, max_rate = 0, vbt_max_rate; 545 546 /* This should only be done once */ 547 drm_WARN_ON(display->drm, 548 intel_dp->source_rates || intel_dp->num_source_rates); 549 550 if (DISPLAY_VER(display) >= 14) { 551 if (display->platform.battlemage) { 552 source_rates = bmg_rates; 553 size = ARRAY_SIZE(bmg_rates); 554 } else { 555 source_rates = mtl_rates; 556 size = ARRAY_SIZE(mtl_rates); 557 } 558 max_rate = mtl_max_source_rate(intel_dp); 559 } else if (DISPLAY_VER(display) >= 11) { 560 source_rates = icl_rates; 561 size = ARRAY_SIZE(icl_rates); 562 if (display->platform.dg2) 563 max_rate = dg2_max_source_rate(intel_dp); 564 else if (display->platform.alderlake_p || display->platform.alderlake_s || 565 display->platform.dg1 || display->platform.rocketlake) 566 max_rate = 810000; 567 else if (display->platform.jasperlake || display->platform.elkhartlake) 568 max_rate = ehl_max_source_rate(intel_dp); 569 else 570 max_rate = icl_max_source_rate(intel_dp); 571 } else if (display->platform.geminilake || display->platform.broxton) { 572 source_rates = bxt_rates; 573 size = ARRAY_SIZE(bxt_rates); 574 } else if (DISPLAY_VER(display) == 9) { 575 source_rates = skl_rates; 576 size = ARRAY_SIZE(skl_rates); 577 } else if ((display->platform.haswell && !display->platform.haswell_ulx) || 578 display->platform.broadwell) { 579 source_rates = hsw_rates; 580 size = ARRAY_SIZE(hsw_rates); 581 } else { 582 source_rates = g4x_rates; 583 size = ARRAY_SIZE(g4x_rates); 584 } 585 586 vbt_max_rate = vbt_max_link_rate(intel_dp); 587 if (max_rate && vbt_max_rate) 588 max_rate = min(max_rate, vbt_max_rate); 589 else if (vbt_max_rate) 590 max_rate = vbt_max_rate; 591 592 if (max_rate) 593 size = intel_dp_rate_limit_len(source_rates, size, max_rate); 594 595 intel_dp->source_rates = source_rates; 596 intel_dp->num_source_rates = size; 597 } 598 599 static int intersect_rates(const int *source_rates, int source_len, 600 const int *sink_rates, int sink_len, 601 int *common_rates) 602 { 603 int i = 0, j = 0, k = 0; 604 605 while (i < source_len && j < sink_len) { 606 if (source_rates[i] == sink_rates[j]) { 607 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 608 return k; 609 common_rates[k] = source_rates[i]; 610 ++k; 611 ++i; 612 ++j; 613 } else if (source_rates[i] < sink_rates[j]) { 614 ++i; 615 } else { 616 ++j; 617 } 618 } 619 return k; 620 } 621 622 /* return index of rate in rates array, or -1 if not found */ 623 int intel_dp_rate_index(const int *rates, int len, int rate) 624 { 625 int i; 626 627 for (i = 0; i < len; i++) 628 if (rate == rates[i]) 629 return i; 630 631 return -1; 632 } 633 634 static void intel_dp_get_common_rates(struct intel_dp *intel_dp, 635 int common_rates[DP_MAX_SUPPORTED_RATES], 636 int *num_common_rates) 637 { 638 struct intel_display *display = to_intel_display(intel_dp); 639 640 drm_WARN_ON(display->drm, 641 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); 642 643 *num_common_rates = intersect_rates(intel_dp->source_rates, 644 intel_dp->num_source_rates, 645 intel_dp->sink_rates, 646 intel_dp->num_sink_rates, 647 common_rates); 648 649 /* Paranoia, there should always be something in common. */ 650 if (drm_WARN_ON(display->drm, *num_common_rates == 0)) { 651 common_rates[0] = 162000; 652 *num_common_rates = 1; 653 } 654 } 655 656 /* Return %true if any common link param changed. */ 657 static bool intel_dp_set_common_link_params(struct intel_dp *intel_dp) 658 { 659 int num_common_rates; 660 int common_rates[DP_MAX_SUPPORTED_RATES]; 661 bool params_changed = false; 662 663 intel_dp_get_common_rates(intel_dp, common_rates, &num_common_rates); 664 if (intel_dp_link_caps_update(intel_dp->link.caps, 665 common_rates, num_common_rates, 666 intel_dp_get_max_common_lane_count(intel_dp), 667 intel_dp->reset_link_params)) 668 params_changed = true; 669 670 return params_changed; 671 } 672 673 u32 intel_dp_mode_to_fec_clock(u32 mode_clock) 674 { 675 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), 676 1000000U); 677 } 678 679 int intel_dp_bw_fec_overhead(bool fec_enabled) 680 { 681 /* 682 * TODO: Calculate the actual overhead for a given mode. 683 * The hard-coded 1/0.972261=2.853% overhead factor 684 * corresponds (for instance) to the 8b/10b DP FEC 2.4% + 685 * 0.453% DSC overhead. This is enough for a 3840 width mode, 686 * which has a DSC overhead of up to ~0.2%, but may not be 687 * enough for a 1024 width mode where this is ~0.8% (on a 4 688 * lane DP link, with 2 DSC slices and 8 bpp color depth). 689 */ 690 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000; 691 } 692 693 static int 694 small_joiner_ram_size_bits(struct intel_display *display) 695 { 696 if (DISPLAY_VER(display) >= 13) 697 return 17280 * 8; 698 else if (DISPLAY_VER(display) >= 11) 699 return 7680 * 8; 700 else 701 return 6144 * 8; 702 } 703 704 static int align_min_vesa_compressed_bpp_x16(int min_link_bpp_x16) 705 { 706 int i; 707 708 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { 709 int vesa_bpp_x16 = fxp_q4_from_int(valid_dsc_bpp[i]); 710 711 if (vesa_bpp_x16 >= min_link_bpp_x16) 712 return vesa_bpp_x16; 713 } 714 715 return 0; 716 } 717 718 static int align_max_vesa_compressed_bpp_x16(int max_link_bpp_x16) 719 { 720 int i; 721 722 for (i = ARRAY_SIZE(valid_dsc_bpp) - 1; i >= 0; i--) { 723 int vesa_bpp_x16 = fxp_q4_from_int(valid_dsc_bpp[i]); 724 725 if (vesa_bpp_x16 <= max_link_bpp_x16) 726 return vesa_bpp_x16; 727 } 728 729 return 0; 730 } 731 732 static int bigjoiner_interface_bits(struct intel_display *display) 733 { 734 return DISPLAY_VER(display) >= 14 ? 36 : 24; 735 } 736 737 static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock, 738 int num_joined_pipes) 739 { 740 u32 max_bpp; 741 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ 742 int ppc = 2; 743 int num_big_joiners = num_joined_pipes / 2; 744 745 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) / 746 intel_dp_mode_to_fec_clock(mode_clock); 747 748 max_bpp *= num_big_joiners; 749 750 return max_bpp; 751 752 } 753 754 static u32 small_joiner_ram_max_bpp(struct intel_display *display, 755 u32 mode_hdisplay, 756 int num_joined_pipes) 757 { 758 u32 max_bpp; 759 760 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ 761 max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay; 762 763 max_bpp *= num_joined_pipes; 764 765 return max_bpp; 766 } 767 768 static int ultrajoiner_ram_bits(void) 769 { 770 return 4 * 72 * 512; 771 } 772 773 static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay) 774 { 775 return ultrajoiner_ram_bits() / mode_hdisplay; 776 } 777 778 /* TODO: return a bpp_x16 value */ 779 static 780 u32 get_max_compressed_bpp_with_joiner(struct intel_display *display, 781 u32 mode_clock, u32 mode_hdisplay, 782 int num_joined_pipes) 783 { 784 u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes); 785 786 if (num_joined_pipes > 1) 787 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock, 788 num_joined_pipes)); 789 if (num_joined_pipes == 4) 790 max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay)); 791 792 return max_bpp; 793 } 794 795 static int intel_dp_dsc_min_slice_count(const struct intel_connector *connector, 796 int mode_clock, int mode_hdisplay) 797 { 798 struct intel_display *display = to_intel_display(connector); 799 bool is_edp = 800 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP; 801 int min_slice_count; 802 int max_slice_width; 803 int tp_rgb_yuv444; 804 int tp_yuv422_420; 805 806 /* 807 * TODO: allow using less than the maximum number of slices 808 * supported by the eDP sink, to allow using fewer DSC engines. 809 */ 810 if (is_edp) 811 return drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, true); 812 813 /* 814 * TODO: Use the throughput value specific to the actual RGB/YUV 815 * format of the output. 816 * The RGB/YUV444 throughput value should be always either equal 817 * or smaller than the YUV422/420 value, but let's not depend on 818 * this assumption. 819 */ 820 if (mode_clock > max(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444, 821 connector->dp.dsc_branch_caps.overall_throughput.yuv422_420)) 822 return 0; 823 824 if (mode_hdisplay > connector->dp.dsc_branch_caps.max_line_width) 825 return 0; 826 827 /* 828 * TODO: Pass the total pixel rate of all the streams transferred to 829 * an MST tiled display, calculate the total slice count for all tiles 830 * from this and the per-tile slice count from the total slice count. 831 */ 832 tp_rgb_yuv444 = drm_dp_dsc_sink_max_slice_throughput(connector->dp.dsc_dpcd, 833 mode_clock, true); 834 tp_yuv422_420 = drm_dp_dsc_sink_max_slice_throughput(connector->dp.dsc_dpcd, 835 mode_clock, false); 836 837 /* 838 * TODO: Use the throughput value specific to the actual RGB/YUV 839 * format of the output. 840 * For now use the smaller of these, which is ok, potentially 841 * resulting in a higher than required minimum slice count. 842 * The RGB/YUV444 throughput value should be always either equal 843 * or smaller than the YUV422/420 value, but let's not depend on 844 * this assumption. 845 */ 846 min_slice_count = DIV_ROUND_UP(mode_clock, min(tp_rgb_yuv444, tp_yuv422_420)); 847 848 /* 849 * Due to some DSC engine BW limitations, we need to enable second 850 * slice and VDSC engine, whenever we approach close enough to max CDCLK 851 */ 852 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100)) 853 min_slice_count = max(min_slice_count, 2); 854 855 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); 856 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { 857 drm_dbg_kms(display->drm, 858 "Unsupported slice width %d by DP DSC Sink device\n", 859 max_slice_width); 860 return 0; 861 } 862 /* Also take into account max slice width */ 863 min_slice_count = max(min_slice_count, 864 DIV_ROUND_UP(mode_hdisplay, max_slice_width)); 865 866 return min_slice_count; 867 } 868 869 static bool 870 intel_dp_dsc_get_slice_config(const struct intel_connector *connector, 871 int mode_clock, int mode_hdisplay, 872 int num_joined_pipes, 873 struct intel_dsc_slice_config *config_ret) 874 { 875 struct intel_display *display = to_intel_display(connector); 876 int min_slice_count = 877 intel_dp_dsc_min_slice_count(connector, mode_clock, mode_hdisplay); 878 bool is_edp = 879 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP; 880 u32 sink_slice_count_mask = 881 drm_dp_dsc_sink_slice_count_mask(connector->dp.dsc_dpcd, is_edp); 882 int slices_per_pipe; 883 884 /* 885 * Find the closest match to the valid slice count values 886 * 887 * Max HW DSC-per-pipe x slice-per-DSC (= slice-per-pipe) capability: 888 * ICL: 2x2 889 * BMG: 2x2, or for ultrajoined 4 pipes: 3x1 890 * TGL+: 2x4 (TODO: Add support for this) 891 * 892 * TODO: Explore if it's worth increasing the number of slices (from 1 893 * to 2 or 3), so that multiple VDSC engines can be used, thus 894 * reducing the minimum CDCLK requirement, which in turn is determined 895 * by the 1 pixel per clock VDSC engine throughput in 896 * intel_vdsc_min_cdclk(). 897 */ 898 for (slices_per_pipe = 1; slices_per_pipe <= 4; slices_per_pipe++) { 899 struct intel_dsc_slice_config config; 900 int slices_per_line; 901 902 if (!intel_dsc_get_slice_config(display, 903 num_joined_pipes, slices_per_pipe, 904 &config)) 905 continue; 906 907 slices_per_line = intel_dsc_line_slice_count(&config); 908 909 if (!(drm_dp_dsc_slice_count_to_mask(slices_per_line) & 910 sink_slice_count_mask)) 911 continue; 912 913 if (mode_hdisplay % slices_per_line) 914 continue; 915 916 if (min_slice_count <= slices_per_line) { 917 *config_ret = config; 918 919 return true; 920 } 921 } 922 923 /* Print slice count 1,2,4,..24 if bit#0,1,3,..23 is set in the mask. */ 924 sink_slice_count_mask <<= 1; 925 drm_dbg_kms(display->drm, 926 "[CONNECTOR:%d:%s] Unsupported slice count (min: %d, sink supported: %*pbl)\n", 927 connector->base.base.id, connector->base.name, 928 min_slice_count, 929 (int)BITS_PER_TYPE(sink_slice_count_mask), &sink_slice_count_mask); 930 931 return false; 932 } 933 934 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 935 int mode_clock, int mode_hdisplay, 936 int num_joined_pipes) 937 { 938 struct intel_dsc_slice_config config; 939 940 if (!intel_dp_dsc_get_slice_config(connector, 941 mode_clock, mode_hdisplay, 942 num_joined_pipes, &config)) 943 return 0; 944 945 return intel_dsc_line_slice_count(&config); 946 } 947 948 static bool source_can_output(struct intel_dp *intel_dp, 949 enum intel_output_format format) 950 { 951 struct intel_display *display = to_intel_display(intel_dp); 952 953 switch (format) { 954 case INTEL_OUTPUT_FORMAT_RGB: 955 return true; 956 957 case INTEL_OUTPUT_FORMAT_YCBCR444: 958 /* 959 * No YCbCr output support on gmch platforms. 960 * Also, ILK doesn't seem capable of DP YCbCr output. 961 * The displayed image is severely corrupted. SNB+ is fine. 962 */ 963 return !HAS_GMCH(display) && !display->platform.ironlake; 964 965 case INTEL_OUTPUT_FORMAT_YCBCR420: 966 /* Platform < Gen 11 cannot output YCbCr420 format */ 967 return DISPLAY_VER(display) >= 11; 968 969 default: 970 MISSING_CASE(format); 971 return false; 972 } 973 } 974 975 static bool 976 dfp_can_convert_from_rgb(struct intel_dp *intel_dp, 977 enum intel_output_format sink_format) 978 { 979 if (!drm_dp_is_branch(intel_dp->dpcd)) 980 return false; 981 982 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) 983 return intel_dp->dfp.rgb_to_ycbcr; 984 985 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 986 return intel_dp->dfp.rgb_to_ycbcr && 987 intel_dp->dfp.ycbcr_444_to_420; 988 989 return false; 990 } 991 992 static bool 993 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, 994 enum intel_output_format sink_format) 995 { 996 if (!drm_dp_is_branch(intel_dp->dpcd)) 997 return false; 998 999 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1000 return intel_dp->dfp.ycbcr_444_to_420; 1001 1002 return false; 1003 } 1004 1005 static bool 1006 dfp_can_convert(struct intel_dp *intel_dp, 1007 enum intel_output_format output_format, 1008 enum intel_output_format sink_format) 1009 { 1010 switch (output_format) { 1011 case INTEL_OUTPUT_FORMAT_RGB: 1012 return dfp_can_convert_from_rgb(intel_dp, sink_format); 1013 case INTEL_OUTPUT_FORMAT_YCBCR444: 1014 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format); 1015 default: 1016 MISSING_CASE(output_format); 1017 return false; 1018 } 1019 1020 return false; 1021 } 1022 1023 static enum intel_output_format 1024 intel_dp_output_format(struct intel_connector *connector, 1025 enum intel_output_format sink_format) 1026 { 1027 struct intel_display *display = to_intel_display(connector); 1028 struct intel_dp *intel_dp = intel_attached_dp(connector); 1029 enum intel_output_format force_dsc_output_format = 1030 intel_dp->force_dsc_output_format; 1031 enum intel_output_format output_format; 1032 if (force_dsc_output_format) { 1033 if (source_can_output(intel_dp, force_dsc_output_format) && 1034 (!drm_dp_is_branch(intel_dp->dpcd) || 1035 sink_format != force_dsc_output_format || 1036 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format))) 1037 return force_dsc_output_format; 1038 1039 drm_dbg_kms(display->drm, "Cannot force DSC output format\n"); 1040 } 1041 1042 if (sink_format == INTEL_OUTPUT_FORMAT_RGB || 1043 dfp_can_convert_from_rgb(intel_dp, sink_format)) 1044 output_format = INTEL_OUTPUT_FORMAT_RGB; 1045 1046 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 1047 dfp_can_convert_from_ycbcr444(intel_dp, sink_format)) 1048 output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 1049 1050 else 1051 output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1052 1053 drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format)); 1054 1055 return output_format; 1056 } 1057 1058 int intel_dp_min_bpp(enum intel_output_format output_format) 1059 { 1060 if (output_format == INTEL_OUTPUT_FORMAT_RGB) 1061 return intel_display_min_pipe_bpp(); 1062 else 1063 return 8 * 3; 1064 } 1065 1066 int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, int pipe_bpp) 1067 { 1068 /* 1069 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output 1070 * format of the number of bytes per pixel will be half the number 1071 * of bytes of RGB pixel. 1072 */ 1073 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1074 pipe_bpp /= 2; 1075 1076 return fxp_q4_from_int(pipe_bpp); 1077 } 1078 1079 static int 1080 intel_dp_mode_min_link_bpp_x16(struct intel_connector *connector, 1081 const struct drm_display_mode *mode, 1082 enum intel_output_format output_format) 1083 { 1084 return intel_dp_output_format_link_bpp_x16(output_format, 1085 intel_dp_min_bpp(output_format)); 1086 } 1087 1088 static bool intel_dp_hdisplay_bad(struct intel_display *display, 1089 int hdisplay) 1090 { 1091 /* 1092 * Older platforms don't like hdisplay==4096 with DP. 1093 * 1094 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline 1095 * and frame counter increment), but we don't get vblank interrupts, 1096 * and the pipe underruns immediately. The link also doesn't seem 1097 * to get trained properly. 1098 * 1099 * On CHV the vblank interrupts don't seem to disappear but 1100 * otherwise the symptoms are similar. 1101 * 1102 * TODO: confirm the behaviour on HSW+ 1103 */ 1104 return hdisplay == 4096 && !HAS_DDI(display); 1105 } 1106 1107 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp) 1108 { 1109 struct intel_connector *connector = intel_dp->attached_connector; 1110 const struct drm_display_info *info = &connector->base.display_info; 1111 int max_tmds_clock = intel_dp->dfp.max_tmds_clock; 1112 1113 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */ 1114 if (max_tmds_clock && info->max_tmds_clock) 1115 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); 1116 1117 return max_tmds_clock; 1118 } 1119 1120 static enum drm_mode_status 1121 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, 1122 int clock, int bpc, 1123 enum intel_output_format sink_format, 1124 bool respect_downstream_limits) 1125 { 1126 int tmds_clock, min_tmds_clock, max_tmds_clock; 1127 1128 if (!respect_downstream_limits) 1129 return MODE_OK; 1130 1131 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1132 1133 min_tmds_clock = intel_dp->dfp.min_tmds_clock; 1134 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp); 1135 1136 if (min_tmds_clock && tmds_clock < min_tmds_clock) 1137 return MODE_CLOCK_LOW; 1138 1139 if (max_tmds_clock && tmds_clock > max_tmds_clock) 1140 return MODE_CLOCK_HIGH; 1141 1142 return MODE_OK; 1143 } 1144 1145 static int frl_required_bw(int clock, int bpc, 1146 enum intel_output_format sink_format) 1147 { 1148 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1149 clock /= 2; 1150 1151 return clock * bpc * 3; 1152 } 1153 1154 static enum drm_mode_status 1155 intel_dp_mode_valid_downstream(struct intel_connector *connector, 1156 const struct drm_display_mode *mode, 1157 int target_clock, 1158 enum intel_output_format sink_format) 1159 { 1160 struct intel_dp *intel_dp = intel_attached_dp(connector); 1161 1162 /* If PCON supports FRL MODE, check FRL bandwidth constraints */ 1163 if (intel_dp->dfp.pcon_max_frl_bw) { 1164 int target_bw, max_frl_bw; 1165 1166 /* Assume 8bpc for the FRL bandwidth check */ 1167 target_bw = frl_required_bw(target_clock, 8, sink_format); 1168 1169 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 1170 1171 /* converting bw from Gbps to Kbps*/ 1172 max_frl_bw = max_frl_bw * 1000000; 1173 1174 if (target_bw > max_frl_bw) 1175 return MODE_CLOCK_HIGH; 1176 1177 return MODE_OK; 1178 } 1179 1180 if (intel_dp->dfp.max_dotclock && 1181 target_clock > intel_dp->dfp.max_dotclock) 1182 return MODE_CLOCK_HIGH; 1183 1184 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ 1185 return intel_dp_tmds_clock_valid(intel_dp, target_clock, 1186 8, sink_format, true); 1187 } 1188 1189 static enum drm_mode_status 1190 intel_dp_sink_format_valid(struct intel_connector *connector, 1191 const struct drm_display_mode *mode, 1192 enum intel_output_format sink_format) 1193 { 1194 struct intel_dp *intel_dp = intel_attached_dp(connector); 1195 const struct drm_display_info *info = &connector->base.display_info; 1196 1197 switch (sink_format) { 1198 case INTEL_OUTPUT_FORMAT_YCBCR420: 1199 if (intel_dp->dfp.min_tmds_clock && 1200 !intel_dp_has_hdmi_sink(intel_dp)) 1201 return MODE_NO_420; 1202 1203 if (!connector->base.ycbcr_420_allowed || 1204 !drm_mode_is_420(info, mode)) 1205 return MODE_NO_420; 1206 1207 return MODE_OK; 1208 case INTEL_OUTPUT_FORMAT_RGB: 1209 return MODE_OK; 1210 default: 1211 MISSING_CASE(sink_format); 1212 return MODE_BAD; 1213 } 1214 } 1215 1216 int intel_dp_max_hdisplay_per_pipe(struct intel_display *display) 1217 { 1218 return DISPLAY_VER(display) >= 30 ? 6144 : 5120; 1219 } 1220 1221 bool intel_dp_has_dsc(const struct intel_connector *connector) 1222 { 1223 struct intel_display *display = to_intel_display(connector); 1224 1225 if (!HAS_DSC(display)) 1226 return false; 1227 1228 if (connector->mst.dp && !HAS_DSC_MST(display)) 1229 return false; 1230 1231 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && 1232 connector->panel.vbt.edp.dsc_disable) 1233 return false; 1234 1235 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) 1236 return false; 1237 1238 return true; 1239 } 1240 1241 static 1242 bool intel_dp_can_join(struct intel_dp *intel_dp, 1243 int num_joined_pipes) 1244 { 1245 struct intel_display *display = to_intel_display(intel_dp); 1246 1247 if (num_joined_pipes > 1 && !intel_dp_has_joiner(intel_dp)) 1248 return false; 1249 1250 switch (num_joined_pipes) { 1251 case 1: 1252 return true; 1253 case 2: 1254 return HAS_BIGJOINER(display) || 1255 HAS_UNCOMPRESSED_JOINER(display); 1256 case 4: 1257 return HAS_ULTRAJOINER(display); 1258 default: 1259 return false; 1260 } 1261 } 1262 1263 bool intel_dp_dotclk_valid(struct intel_display *display, 1264 int target_clock, 1265 int htotal, 1266 int dsc_slice_count, 1267 int num_joined_pipes) 1268 { 1269 int max_dotclk = display->cdclk.max_dotclk_freq; 1270 int effective_dotclk_limit; 1271 1272 effective_dotclk_limit = max_dotclk * num_joined_pipes; 1273 1274 if (dsc_slice_count) 1275 target_clock = intel_dsc_get_pixel_rate_with_dsc_bubbles(display, 1276 target_clock, 1277 htotal, 1278 dsc_slice_count); 1279 else 1280 effective_dotclk_limit = 1281 intel_max_uncompressed_dotclock(display) * num_joined_pipes; 1282 1283 return target_clock <= effective_dotclk_limit; 1284 } 1285 1286 static enum drm_mode_status 1287 intel_dp_mode_valid_format(struct intel_connector *connector, 1288 const struct drm_display_mode *mode, 1289 int target_clock, 1290 enum intel_output_format sink_format) 1291 { 1292 struct intel_display *display = to_intel_display(connector); 1293 struct intel_dp *intel_dp = intel_attached_dp(connector); 1294 enum intel_output_format output_format; 1295 int max_rate, mode_rate, max_lanes, max_link_clock; 1296 struct intel_dp_link_config max_bw_config; 1297 u16 dsc_max_compressed_bpp = 0; 1298 enum drm_mode_status status; 1299 bool dsc = false; 1300 int num_joined_pipes; 1301 int link_bpp_x16; 1302 1303 status = intel_dp_sink_format_valid(connector, mode, sink_format); 1304 if (status != MODE_OK) 1305 return status; 1306 1307 output_format = intel_dp_output_format(connector, sink_format); 1308 1309 intel_dp_link_caps_get_max_bw_config(intel_dp->link.caps, &max_bw_config); 1310 max_link_clock = max_bw_config.rate; 1311 max_lanes = max_bw_config.lane_count; 1312 1313 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); 1314 1315 link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode, 1316 output_format); 1317 mode_rate = intel_dp_link_required(max_link_clock, max_lanes, 1318 target_clock, mode->hdisplay, 1319 link_bpp_x16, 0); 1320 1321 /* 1322 * We cannot determine the required pipe‑join count before knowing whether 1323 * DSC is needed, nor can we determine DSC need without knowing the pipe 1324 * count. 1325 * Because of this dependency cycle, the only correct approach is to iterate 1326 * over candidate pipe counts and evaluate each combination. 1327 */ 1328 status = MODE_CLOCK_HIGH; 1329 for_each_joiner_candidate(connector, mode, num_joined_pipes) { 1330 int dsc_slice_count = 0; 1331 1332 status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes); 1333 if (status != MODE_OK) 1334 continue; 1335 1336 if (intel_dp_has_dsc(connector)) { 1337 int pipe_bpp; 1338 1339 dsc_slice_count = intel_dp_dsc_get_slice_count(connector, 1340 target_clock, 1341 mode->hdisplay, 1342 num_joined_pipes); 1343 1344 /* 1345 * TBD pass the connector BPC, 1346 * for now U8_MAX so that max BPC on that platform would be picked 1347 */ 1348 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); 1349 1350 /* 1351 * Output bpp is stored in 6.4 format so right shift by 4 to get the 1352 * integer value since we support only integer values of bpp. 1353 */ 1354 if (intel_dp_is_edp(intel_dp)) { 1355 dsc_max_compressed_bpp = 1356 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; 1357 1358 dsc = dsc_max_compressed_bpp && dsc_slice_count; 1359 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { 1360 unsigned long bw_overhead_flags = 0; 1361 1362 if (!drm_dp_is_uhbr_rate(max_link_clock)) 1363 bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC; 1364 1365 dsc = intel_dp_mode_valid_with_dsc(connector, 1366 max_link_clock, max_lanes, 1367 target_clock, mode->hdisplay, 1368 num_joined_pipes, 1369 output_format, pipe_bpp, 1370 bw_overhead_flags); 1371 } 1372 } 1373 1374 if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) { 1375 status = MODE_CLOCK_HIGH; 1376 continue; 1377 } 1378 1379 if (mode_rate > max_rate && !dsc) { 1380 status = MODE_CLOCK_HIGH; 1381 continue; 1382 } 1383 1384 status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes); 1385 if (status != MODE_OK) 1386 continue; 1387 1388 if (!dsc) 1389 dsc_slice_count = 0; 1390 1391 if (!intel_dp_dotclk_valid(display, 1392 target_clock, 1393 mode->htotal, 1394 dsc_slice_count, 1395 num_joined_pipes)) { 1396 status = MODE_CLOCK_HIGH; 1397 continue; 1398 } 1399 1400 break; 1401 } 1402 1403 if (status != MODE_OK) 1404 return status; 1405 1406 return intel_dp_mode_valid_downstream(connector, mode, 1407 target_clock, sink_format); 1408 } 1409 1410 static enum drm_mode_status 1411 intel_dp_mode_valid(struct drm_connector *_connector, 1412 const struct drm_display_mode *mode) 1413 { 1414 struct intel_display *display = to_intel_display(_connector->dev); 1415 struct intel_connector *connector = to_intel_connector(_connector); 1416 const struct drm_display_info *info = &connector->base.display_info; 1417 struct intel_dp *intel_dp = intel_attached_dp(connector); 1418 int target_clock = mode->clock; 1419 enum drm_mode_status status; 1420 1421 status = intel_cpu_transcoder_mode_valid(display, mode); 1422 if (status != MODE_OK) 1423 return status; 1424 1425 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1426 return MODE_H_ILLEGAL; 1427 1428 if (mode->clock < 10000) 1429 return MODE_CLOCK_LOW; 1430 1431 if (intel_dp_hdisplay_bad(display, mode->hdisplay)) 1432 return MODE_H_ILLEGAL; 1433 1434 if (intel_dp_is_edp(intel_dp)) { 1435 status = intel_panel_mode_valid(connector, mode, &target_clock); 1436 if (status != MODE_OK) 1437 return status; 1438 } 1439 1440 /* 1441 * TODO: Even when using a 4:2:0 sink_format intel_dp_output_format() 1442 * will always choose a 4:4:4 output_format if the DFP can do the 1443 * 4:4:4->4:2:0 conversion for us. Thus a mode may still be rejected 1444 * if we only have enough DP link bandwidth for 4:2:0 but not for 1445 * 4:4:4. Another attempt with an explicit 4:2:0 output_format might 1446 * be needed here. intel_dp_compute_config() would need the same 1447 * logic, or else the actual modeset would still fail. 1448 * 1449 * Also a lot of the checks only depend on output_format but not 1450 * sink_format, so we are potentially doing redundant work by 1451 * testing the same output_format for two different sink_formats. 1452 */ 1453 if (drm_mode_is_420_only(info, mode)) { 1454 status = intel_dp_mode_valid_format(connector, mode, target_clock, 1455 INTEL_OUTPUT_FORMAT_YCBCR420); 1456 } else { 1457 status = intel_dp_mode_valid_format(connector, mode, target_clock, 1458 INTEL_OUTPUT_FORMAT_RGB); 1459 1460 if (status != MODE_OK && drm_mode_is_420_also(info, mode)) 1461 status = intel_dp_mode_valid_format(connector, mode, target_clock, 1462 INTEL_OUTPUT_FORMAT_YCBCR420); 1463 } 1464 1465 return status; 1466 } 1467 1468 bool intel_dp_source_supports_tps3(struct intel_display *display) 1469 { 1470 return DISPLAY_VER(display) >= 9 || 1471 display->platform.broadwell || display->platform.haswell; 1472 } 1473 1474 bool intel_dp_source_supports_tps4(struct intel_display *display) 1475 { 1476 return DISPLAY_VER(display) >= 10; 1477 } 1478 1479 static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem) 1480 { 1481 int i; 1482 1483 for (i = 0; i < nelem; i++) 1484 seq_buf_printf(s, "%s%d", i ? ", " : "", array[i]); 1485 } 1486 1487 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1488 { 1489 struct intel_display *display = to_intel_display(intel_dp); 1490 DECLARE_SEQ_BUF(s, 128); /* FIXME: too big for stack? */ 1491 1492 if (!drm_debug_enabled(DRM_UT_KMS)) 1493 return; 1494 1495 seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates); 1496 drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s)); 1497 1498 seq_buf_clear(&s); 1499 seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates); 1500 drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s)); 1501 1502 intel_dp_link_caps_print_common_rates(intel_dp->link.caps); 1503 } 1504 1505 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1506 { 1507 struct intel_display *display = to_intel_display(intel_dp); 1508 int i = intel_dp_rate_index(intel_dp->sink_rates, 1509 intel_dp->num_sink_rates, rate); 1510 1511 if (drm_WARN_ON(display->drm, i < 0)) 1512 i = 0; 1513 1514 return i; 1515 } 1516 1517 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1518 u8 *link_bw, u8 *rate_select) 1519 { 1520 struct intel_display *display = to_intel_display(intel_dp); 1521 1522 /* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */ 1523 if (display->platform.g4x && port_clock == 268800) 1524 port_clock = 270000; 1525 1526 /* eDP 1.4 rate select method. */ 1527 if (intel_dp->use_rate_select) { 1528 *link_bw = 0; 1529 *rate_select = 1530 intel_dp_rate_select(intel_dp, port_clock); 1531 } else { 1532 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1533 *rate_select = 0; 1534 } 1535 } 1536 1537 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp) 1538 { 1539 struct intel_connector *connector = intel_dp->attached_connector; 1540 1541 return connector->base.display_info.is_hdmi; 1542 } 1543 1544 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 1545 const struct intel_crtc_state *pipe_config) 1546 { 1547 struct intel_display *display = to_intel_display(intel_dp); 1548 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1549 1550 if (DISPLAY_VER(display) >= 12) 1551 return true; 1552 1553 if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A && 1554 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) 1555 return true; 1556 1557 return false; 1558 } 1559 1560 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 1561 const struct intel_connector *connector, 1562 const struct intel_crtc_state *pipe_config) 1563 { 1564 return intel_dp_source_supports_fec(intel_dp, pipe_config) && 1565 drm_dp_sink_supports_fec(connector->dp.fec_capability); 1566 } 1567 1568 bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 1569 const struct intel_connector *connector, 1570 const struct intel_crtc_state *crtc_state) 1571 { 1572 if (!intel_dp_has_dsc(connector)) 1573 return false; 1574 1575 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && 1576 !intel_dp_supports_fec(intel_dp, connector, crtc_state)) 1577 return false; 1578 1579 return intel_dsc_source_support(crtc_state); 1580 } 1581 1582 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, 1583 const struct intel_crtc_state *crtc_state, 1584 int bpc, bool respect_downstream_limits) 1585 { 1586 int clock = crtc_state->hw.adjusted_mode.crtc_clock; 1587 1588 /* 1589 * Current bpc could already be below 8bpc due to 1590 * FDI bandwidth constraints or other limits. 1591 * HDMI minimum is 8bpc however. 1592 */ 1593 bpc = max(bpc, 8); 1594 1595 /* 1596 * We will never exceed downstream TMDS clock limits while 1597 * attempting deep color. If the user insists on forcing an 1598 * out of spec mode they will have to be satisfied with 8bpc. 1599 */ 1600 if (!respect_downstream_limits) 1601 bpc = 8; 1602 1603 for (; bpc >= 8; bpc -= 2) { 1604 if (intel_hdmi_bpc_possible(crtc_state, bpc, 1605 intel_dp_has_hdmi_sink(intel_dp)) && 1606 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, 1607 respect_downstream_limits) == MODE_OK) 1608 return bpc; 1609 } 1610 1611 return -EINVAL; 1612 } 1613 1614 static int intel_dp_max_bpp(struct intel_dp *intel_dp, 1615 const struct intel_crtc_state *crtc_state, 1616 bool respect_downstream_limits) 1617 { 1618 struct intel_display *display = to_intel_display(intel_dp); 1619 struct intel_connector *connector = intel_dp->attached_connector; 1620 int bpp, bpc; 1621 1622 bpc = crtc_state->max_pipe_bpp / 3; 1623 1624 if (intel_dp->dfp.max_bpc) 1625 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); 1626 1627 if (intel_dp->dfp.min_tmds_clock) { 1628 int max_hdmi_bpc; 1629 1630 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc, 1631 respect_downstream_limits); 1632 if (max_hdmi_bpc < 0) 1633 return 0; 1634 1635 bpc = min(bpc, max_hdmi_bpc); 1636 } 1637 1638 bpp = bpc * 3; 1639 if (intel_dp_is_edp(intel_dp)) { 1640 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1641 if (connector->base.display_info.bpc == 0 && 1642 connector->panel.vbt.edp.bpp && 1643 connector->panel.vbt.edp.bpp < bpp) { 1644 drm_dbg_kms(display->drm, 1645 "clamping bpp for eDP panel to BIOS-provided %i\n", 1646 connector->panel.vbt.edp.bpp); 1647 bpp = connector->panel.vbt.edp.bpp; 1648 } 1649 } 1650 1651 return bpp; 1652 } 1653 1654 static bool has_seamless_m_n(struct intel_connector *connector) 1655 { 1656 struct intel_display *display = to_intel_display(connector); 1657 1658 /* 1659 * Seamless M/N reprogramming only implemented 1660 * for BDW+ double buffered M/N registers so far. 1661 */ 1662 return HAS_DOUBLE_BUFFERED_M_N(display) && 1663 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 1664 } 1665 1666 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state, 1667 const struct drm_connector_state *conn_state) 1668 { 1669 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1670 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1671 1672 /* FIXME a bit of a mess wrt clock vs. crtc_clock */ 1673 if (has_seamless_m_n(connector)) 1674 return intel_panel_highest_mode(connector, adjusted_mode)->clock; 1675 else 1676 return adjusted_mode->crtc_clock; 1677 } 1678 1679 /* Optimize link config in order: max bpp, min clock, min lanes */ 1680 static int 1681 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 1682 struct intel_crtc_state *pipe_config, 1683 const struct drm_connector_state *conn_state, 1684 const struct link_config_limits *limits) 1685 { 1686 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1687 int bpp, clock = intel_dp_mode_clock(pipe_config, conn_state); 1688 struct intel_dp_link_caps *link_caps = intel_dp->link.caps; 1689 struct intel_dp_link_caps_order order = 1690 intel_dp_link_caps_connector_compute_order(connector); 1691 int err = -EINVAL; 1692 int link_avail; 1693 1694 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 1695 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); 1696 bpp -= 2 * 3) { 1697 int link_bpp_x16 = 1698 intel_dp_output_format_link_bpp_x16(pipe_config->output_format, bpp); 1699 struct intel_dp_link_config link_config; 1700 struct intel_dp_link_caps_iter iter; 1701 1702 intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter); 1703 for_each_dp_link_config(&iter, &link_config) { 1704 const struct drm_display_mode *adjusted_mode = 1705 &pipe_config->hw.adjusted_mode; 1706 int mode_rate; 1707 1708 mode_rate = intel_dp_link_required(link_config.rate, 1709 link_config.lane_count, 1710 clock, adjusted_mode->hdisplay, 1711 link_bpp_x16, 0); 1712 1713 link_avail = intel_dp_max_link_data_rate(intel_dp, 1714 link_config.rate, 1715 link_config.lane_count); 1716 1717 if (mode_rate <= link_avail) { 1718 pipe_config->lane_count = link_config.lane_count; 1719 pipe_config->pipe_bpp = bpp; 1720 pipe_config->port_clock = link_config.rate; 1721 1722 err = 0; 1723 1724 break; 1725 } 1726 } 1727 intel_dp_link_caps_iter_end(&iter); 1728 1729 if (!err) 1730 break; 1731 } 1732 1733 return err; 1734 } 1735 1736 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display) 1737 { 1738 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 1739 if (DISPLAY_VER(display) >= 12) 1740 return 12; 1741 if (DISPLAY_VER(display) == 11) 1742 return 10; 1743 1744 return intel_dp_dsc_min_src_input_bpc(); 1745 } 1746 1747 static int align_min_sink_dsc_input_bpp(const struct intel_connector *connector, 1748 int min_pipe_bpp) 1749 { 1750 u8 dsc_bpc[3]; 1751 int num_bpc; 1752 int i; 1753 1754 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, 1755 dsc_bpc); 1756 for (i = num_bpc - 1; i >= 0; i--) { 1757 if (dsc_bpc[i] * 3 >= min_pipe_bpp) 1758 return dsc_bpc[i] * 3; 1759 } 1760 1761 return 0; 1762 } 1763 1764 static int align_max_sink_dsc_input_bpp(const struct intel_connector *connector, 1765 int max_pipe_bpp) 1766 { 1767 u8 dsc_bpc[3]; 1768 int num_bpc; 1769 int i; 1770 1771 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, 1772 dsc_bpc); 1773 for (i = 0; i < num_bpc; i++) { 1774 if (dsc_bpc[i] * 3 <= max_pipe_bpp) 1775 return dsc_bpc[i] * 3; 1776 } 1777 1778 return 0; 1779 } 1780 1781 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 1782 u8 max_req_bpc) 1783 { 1784 struct intel_display *display = to_intel_display(connector); 1785 int dsc_max_bpc; 1786 1787 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 1788 1789 if (!dsc_max_bpc) 1790 return dsc_max_bpc; 1791 1792 dsc_max_bpc = min(dsc_max_bpc, max_req_bpc); 1793 1794 return align_max_sink_dsc_input_bpp(connector, dsc_max_bpc * 3); 1795 } 1796 1797 static int intel_dp_source_dsc_version_minor(struct intel_display *display) 1798 { 1799 return DISPLAY_VER(display) >= 14 ? 2 : 1; 1800 } 1801 1802 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 1803 { 1804 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> 1805 DP_DSC_MINOR_SHIFT; 1806 } 1807 1808 static int intel_dp_get_slice_height(int vactive) 1809 { 1810 int slice_height; 1811 1812 /* 1813 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108 1814 * lines is an optimal slice height, but any size can be used as long as 1815 * vertical active integer multiple and maximum vertical slice count 1816 * requirements are met. 1817 */ 1818 for (slice_height = 108; slice_height <= vactive; slice_height += 2) 1819 if (vactive % slice_height == 0) 1820 return slice_height; 1821 1822 /* 1823 * Highly unlikely we reach here as most of the resolutions will end up 1824 * finding appropriate slice_height in above loop but returning 1825 * slice_height as 2 here as it should work with all resolutions. 1826 */ 1827 return 2; 1828 } 1829 1830 static int intel_dp_dsc_compute_params(const struct intel_connector *connector, 1831 struct intel_crtc_state *crtc_state) 1832 { 1833 struct intel_display *display = to_intel_display(connector); 1834 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1835 int ret; 1836 1837 /* 1838 * RC_MODEL_SIZE is currently a constant across all configurations. 1839 * 1840 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and 1841 * DP_DSC_RC_BUF_SIZE for this. 1842 */ 1843 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1844 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1845 1846 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); 1847 1848 ret = intel_dsc_compute_params(crtc_state); 1849 if (ret) 1850 return ret; 1851 1852 vdsc_cfg->dsc_version_major = 1853 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 1854 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; 1855 vdsc_cfg->dsc_version_minor = 1856 min(intel_dp_source_dsc_version_minor(display), 1857 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)); 1858 if (vdsc_cfg->convert_rgb) 1859 vdsc_cfg->convert_rgb = 1860 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & 1861 DP_DSC_RGB; 1862 1863 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, 1864 drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd)); 1865 if (!vdsc_cfg->line_buf_depth) { 1866 drm_dbg_kms(display->drm, 1867 "DSC Sink Line Buffer Depth invalid\n"); 1868 return -EINVAL; 1869 } 1870 1871 vdsc_cfg->block_pred_enable = 1872 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & 1873 DP_DSC_BLK_PREDICTION_IS_SUPPORTED; 1874 1875 return drm_dsc_compute_rc_parameters(vdsc_cfg); 1876 } 1877 1878 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, 1879 enum intel_output_format output_format) 1880 { 1881 struct intel_display *display = to_intel_display(connector); 1882 u8 sink_dsc_format; 1883 1884 switch (output_format) { 1885 case INTEL_OUTPUT_FORMAT_RGB: 1886 sink_dsc_format = DP_DSC_RGB; 1887 break; 1888 case INTEL_OUTPUT_FORMAT_YCBCR444: 1889 sink_dsc_format = DP_DSC_YCbCr444; 1890 break; 1891 case INTEL_OUTPUT_FORMAT_YCBCR420: 1892 if (min(intel_dp_source_dsc_version_minor(display), 1893 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2) 1894 return false; 1895 sink_dsc_format = DP_DSC_YCbCr420_Native; 1896 break; 1897 default: 1898 return false; 1899 } 1900 1901 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); 1902 } 1903 1904 static bool is_bw_sufficient_for_dsc_config(struct intel_dp *intel_dp, 1905 int link_clock, int lane_count, 1906 int mode_clock, int mode_hdisplay, 1907 int dsc_slice_count, int link_bpp_x16, 1908 unsigned long bw_overhead_flags) 1909 { 1910 int available_bw; 1911 int required_bw; 1912 1913 available_bw = intel_dp_max_link_data_rate(intel_dp, link_clock, lane_count); 1914 required_bw = intel_dp_link_required(link_clock, lane_count, 1915 mode_clock, mode_hdisplay, 1916 link_bpp_x16, bw_overhead_flags); 1917 1918 return available_bw >= required_bw; 1919 } 1920 1921 static int dsc_compute_link_config(struct intel_dp *intel_dp, 1922 struct intel_crtc_state *pipe_config, 1923 struct drm_connector_state *conn_state, 1924 const struct link_config_limits *limits, 1925 int dsc_bpp_x16) 1926 { 1927 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1928 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1929 struct intel_dp_link_caps *link_caps = intel_dp->link.caps; 1930 struct intel_dp_link_caps_order order = 1931 intel_dp_link_caps_connector_compute_order(connector); 1932 struct intel_dp_link_config link_config; 1933 struct intel_dp_link_caps_iter iter; 1934 int err = -EINVAL; 1935 1936 intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter); 1937 for_each_dp_link_config(&iter, &link_config) { 1938 /* 1939 * FIXME: intel_dp_mtp_tu_compute_config() requires 1940 * ->lane_count and ->port_clock set before we know 1941 * they'll work. If we end up failing altogether, 1942 * they'll remain in crtc state. This shouldn't matter, 1943 * as we'd then bail out from compute config, but it's 1944 * just ugly. 1945 */ 1946 pipe_config->lane_count = link_config.lane_count; 1947 pipe_config->port_clock = link_config.rate; 1948 1949 if (drm_dp_is_uhbr_rate(link_config.rate)) { 1950 int ret; 1951 1952 ret = intel_dp_mtp_tu_compute_config(intel_dp, 1953 pipe_config, 1954 conn_state, 1955 dsc_bpp_x16, 1956 dsc_bpp_x16, 1957 0, true); 1958 if (ret) 1959 continue; 1960 } else { 1961 unsigned long bw_overhead_flags = 1962 pipe_config->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; 1963 int line_slice_count = 1964 intel_dsc_line_slice_count(&pipe_config->dsc.slice_config); 1965 1966 if (!is_bw_sufficient_for_dsc_config(intel_dp, 1967 link_config.rate, 1968 link_config.lane_count, 1969 adjusted_mode->crtc_clock, 1970 adjusted_mode->hdisplay, 1971 line_slice_count, 1972 dsc_bpp_x16, 1973 bw_overhead_flags)) 1974 continue; 1975 } 1976 1977 err = 0; 1978 1979 break; 1980 } 1981 intel_dp_link_caps_iter_end(&iter); 1982 1983 return err; 1984 } 1985 1986 static 1987 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, 1988 enum intel_output_format output_format, 1989 int bpc) 1990 { 1991 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); 1992 1993 if (max_bppx16) 1994 return max_bppx16; 1995 /* 1996 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate 1997 * values as given in spec Table 2-157 DP v2.0 1998 */ 1999 switch (output_format) { 2000 case INTEL_OUTPUT_FORMAT_RGB: 2001 case INTEL_OUTPUT_FORMAT_YCBCR444: 2002 return (3 * bpc) << 4; 2003 case INTEL_OUTPUT_FORMAT_YCBCR420: 2004 return (3 * (bpc / 2)) << 4; 2005 default: 2006 MISSING_CASE(output_format); 2007 break; 2008 } 2009 2010 return 0; 2011 } 2012 2013 static int intel_dp_dsc_sink_min_compressed_bpp(enum intel_output_format output_format) 2014 { 2015 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ 2016 switch (output_format) { 2017 case INTEL_OUTPUT_FORMAT_RGB: 2018 case INTEL_OUTPUT_FORMAT_YCBCR444: 2019 return 8; 2020 case INTEL_OUTPUT_FORMAT_YCBCR420: 2021 return 6; 2022 default: 2023 MISSING_CASE(output_format); 2024 break; 2025 } 2026 2027 return 0; 2028 } 2029 2030 static int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, 2031 enum intel_output_format output_format, 2032 int bpc) 2033 { 2034 return intel_dp_dsc_max_sink_compressed_bppx16(connector, 2035 output_format, bpc) >> 4; 2036 } 2037 2038 int intel_dp_dsc_min_src_compressed_bpp(void) 2039 { 2040 /* Min Compressed bpp supported by source is 8 */ 2041 return 8; 2042 } 2043 2044 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) 2045 { 2046 struct intel_display *display = to_intel_display(intel_dp); 2047 2048 /* 2049 * Forcing DSC and using the platform's max compressed bpp is seen to cause 2050 * underruns. Since DSC isn't needed in these cases, limit the 2051 * max compressed bpp to 18, which is a safe value across platforms with different 2052 * pipe bpps. 2053 */ 2054 if (intel_dp->force_dsc_en) 2055 return 18; 2056 2057 /* 2058 * Max Compressed bpp for Gen 13+ is 27bpp. 2059 * For earlier platform is 23bpp. (Bspec:49259). 2060 */ 2061 if (DISPLAY_VER(display) < 13) 2062 return 23; 2063 else 2064 return 27; 2065 } 2066 2067 /* 2068 * Note: for pre-13 display you still need to check the validity of each step. 2069 */ 2070 int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) 2071 { 2072 struct intel_display *display = to_intel_display(connector); 2073 u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); 2074 2075 if (DISPLAY_VER(display) < 14 || !incr) 2076 return fxp_q4_from_int(1); 2077 2078 if (connector->mst.dp && 2079 !connector->link.force_bpp_x16 && !connector->mst.dp->force_dsc_fractional_bpp_en) 2080 return fxp_q4_from_int(1); 2081 2082 /* fxp q4 */ 2083 return fxp_q4_from_int(1) / incr; 2084 } 2085 2086 /* 2087 * Note: for bpp_x16 to be valid it must be also within the source/sink's 2088 * min..max bpp capability range. 2089 */ 2090 bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16) 2091 { 2092 struct intel_display *display = to_intel_display(intel_dp); 2093 2094 if (DISPLAY_VER(display) >= 13) { 2095 if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16)) 2096 return false; 2097 2098 return true; 2099 } 2100 2101 if (fxp_q4_to_frac(bpp_x16)) 2102 return false; 2103 2104 return align_max_vesa_compressed_bpp_x16(bpp_x16) == bpp_x16; 2105 } 2106 2107 static int align_min_compressed_bpp_x16(const struct intel_connector *connector, int min_bpp_x16) 2108 { 2109 struct intel_display *display = to_intel_display(connector); 2110 2111 if (DISPLAY_VER(display) >= 13) { 2112 int bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); 2113 2114 drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); 2115 2116 return round_up(min_bpp_x16, bpp_step_x16); 2117 } else { 2118 return align_min_vesa_compressed_bpp_x16(min_bpp_x16); 2119 } 2120 } 2121 2122 static int align_max_compressed_bpp_x16(const struct intel_connector *connector, 2123 enum intel_output_format output_format, 2124 int pipe_bpp, int max_bpp_x16) 2125 { 2126 struct intel_display *display = to_intel_display(connector); 2127 int link_bpp_x16 = intel_dp_output_format_link_bpp_x16(output_format, pipe_bpp); 2128 int bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); 2129 2130 max_bpp_x16 = min(max_bpp_x16, link_bpp_x16 - bpp_step_x16); 2131 2132 if (DISPLAY_VER(display) >= 13) { 2133 drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); 2134 2135 return round_down(max_bpp_x16, bpp_step_x16); 2136 } else { 2137 return align_max_vesa_compressed_bpp_x16(max_bpp_x16); 2138 } 2139 } 2140 2141 /* 2142 * Find the max compressed BPP we can find a link configuration for. The BPPs to 2143 * try depend on the source (platform) and sink. 2144 */ 2145 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, 2146 struct intel_crtc_state *pipe_config, 2147 struct drm_connector_state *conn_state, 2148 const struct link_config_limits *limits, 2149 int pipe_bpp) 2150 { 2151 struct intel_display *display = to_intel_display(intel_dp); 2152 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2153 int min_bpp_x16, max_bpp_x16, bpp_step_x16; 2154 int bpp_x16; 2155 int ret; 2156 2157 min_bpp_x16 = limits->link.min_bpp_x16; 2158 max_bpp_x16 = limits->link.max_bpp_x16; 2159 bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); 2160 2161 max_bpp_x16 = align_max_compressed_bpp_x16(connector, pipe_config->output_format, 2162 pipe_bpp, max_bpp_x16); 2163 if (intel_dp_is_edp(intel_dp)) { 2164 struct intel_dp_link_config max_link_config; 2165 2166 /* 2167 * FIXME: Clarify why eDP does not use the regular SST BW 2168 * check and instead always uses the maximum link config, 2169 * regardless of intel_dp::use_max_params. Then unify this eDP 2170 * path with the regular DP path. 2171 */ 2172 if (!intel_dp_get_connector_max_link_config(connector, limits, &max_link_config)) 2173 return -EINVAL; 2174 2175 pipe_config->port_clock = max_link_config.rate; 2176 pipe_config->lane_count = max_link_config.lane_count; 2177 2178 pipe_config->dsc.compressed_bpp_x16 = max_bpp_x16; 2179 2180 return 0; 2181 } 2182 2183 for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { 2184 if (!intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) 2185 continue; 2186 2187 ret = dsc_compute_link_config(intel_dp, 2188 pipe_config, 2189 conn_state, 2190 limits, 2191 bpp_x16); 2192 if (ret == 0) { 2193 pipe_config->dsc.compressed_bpp_x16 = bpp_x16; 2194 if (intel_dp->force_dsc_fractional_bpp_en && 2195 fxp_q4_to_frac(bpp_x16)) 2196 drm_dbg_kms(display->drm, 2197 "Forcing DSC fractional bpp\n"); 2198 2199 return 0; 2200 } 2201 } 2202 2203 return -EINVAL; 2204 } 2205 2206 int intel_dp_dsc_min_src_input_bpc(void) 2207 { 2208 /* Min DSC Input BPC for ICL+ is 8 */ 2209 return 8; 2210 } 2211 2212 static 2213 bool is_dsc_pipe_bpp_sufficient(const struct link_config_limits *limits, 2214 int pipe_bpp) 2215 { 2216 return pipe_bpp >= limits->pipe.min_bpp && 2217 pipe_bpp <= limits->pipe.max_bpp; 2218 } 2219 2220 static 2221 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, 2222 const struct link_config_limits *limits) 2223 { 2224 struct intel_display *display = to_intel_display(intel_dp); 2225 int forced_bpp; 2226 2227 if (!intel_dp->force_dsc_bpc) 2228 return 0; 2229 2230 forced_bpp = intel_dp->force_dsc_bpc * 3; 2231 2232 if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) { 2233 drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n", 2234 intel_dp->force_dsc_bpc); 2235 return forced_bpp; 2236 } 2237 2238 drm_dbg_kms(display->drm, 2239 "Cannot force DSC BPC:%d, due to DSC BPC limits\n", 2240 intel_dp->force_dsc_bpc); 2241 2242 return 0; 2243 } 2244 2245 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2246 struct intel_crtc_state *pipe_config, 2247 struct drm_connector_state *conn_state, 2248 const struct link_config_limits *limits) 2249 { 2250 int forced_bpp, pipe_bpp; 2251 int ret; 2252 2253 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); 2254 if (forced_bpp) 2255 pipe_bpp = forced_bpp; 2256 else 2257 pipe_bpp = limits->pipe.max_bpp; 2258 2259 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, 2260 limits, pipe_bpp); 2261 if (ret) 2262 return -EINVAL; 2263 2264 pipe_config->pipe_bpp = pipe_bpp; 2265 2266 return 0; 2267 } 2268 2269 /* 2270 * Return whether FEC must be enabled for 8b10b SST or MST links. On 128b132b 2271 * links FEC is always enabled implicitly by the HW, so this function returns 2272 * false for that case. 2273 */ 2274 bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state, 2275 bool dsc_enabled_on_crtc) 2276 { 2277 if (intel_dp_is_uhbr(crtc_state)) 2278 return false; 2279 2280 /* 2281 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional. 2282 * Since, FEC is a bandwidth overhead, continue to not enable it for 2283 * eDP. Until, there is a good reason to do so. 2284 */ 2285 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2286 return false; 2287 2288 return dsc_enabled_on_crtc || intel_dsc_enabled_on_link(crtc_state); 2289 } 2290 2291 void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state) 2292 { 2293 crtc_state->fec_enable = false; 2294 2295 crtc_state->dsc.compression_enable = false; 2296 crtc_state->dsc.compressed_bpp_x16 = 0; 2297 2298 memset(&crtc_state->dsc.slice_config, 0, sizeof(crtc_state->dsc.slice_config)); 2299 memset(&crtc_state->dsc.config, 0, sizeof(crtc_state->dsc.config)); 2300 } 2301 2302 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 2303 struct intel_crtc_state *pipe_config, 2304 struct drm_connector_state *conn_state, 2305 const struct link_config_limits *limits, 2306 int timeslots) 2307 { 2308 struct intel_display *display = to_intel_display(intel_dp); 2309 const struct intel_connector *connector = 2310 to_intel_connector(conn_state->connector); 2311 const struct drm_display_mode *adjusted_mode = 2312 &pipe_config->hw.adjusted_mode; 2313 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2314 bool is_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST); 2315 int ret; 2316 2317 /* 2318 * FIXME: set the FEC enabled state once pipe_config->port_clock is 2319 * already known, so the UHBR/non-UHBR mode can be determined. 2320 */ 2321 pipe_config->fec_enable = intel_dp_needs_8b10b_fec(pipe_config, true); 2322 2323 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format)) 2324 return -EINVAL; 2325 2326 /* 2327 * Link parameters, pipe bpp and compressed bpp have already been 2328 * figured out for DP MST DSC. 2329 */ 2330 if (!is_mst) { 2331 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2332 conn_state, limits); 2333 if (ret) { 2334 drm_dbg_kms(display->drm, 2335 "No Valid pipe bpp for given mode ret = %d\n", ret); 2336 return ret; 2337 } 2338 } 2339 2340 if (!intel_dp_dsc_get_slice_config(connector, adjusted_mode->crtc_clock, 2341 adjusted_mode->crtc_hdisplay, num_joined_pipes, 2342 &pipe_config->dsc.slice_config)) 2343 return -EINVAL; 2344 2345 ret = intel_dp_dsc_compute_params(connector, pipe_config); 2346 if (ret < 0) { 2347 drm_dbg_kms(display->drm, 2348 "Cannot compute valid DSC parameters for Input Bpp = %d" 2349 "Compressed BPP = " FXP_Q4_FMT "\n", 2350 pipe_config->pipe_bpp, 2351 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16)); 2352 return ret; 2353 } 2354 2355 intel_dsc_enable_on_crtc(pipe_config); 2356 2357 drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d " 2358 "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n", 2359 pipe_config->pipe_bpp, 2360 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2361 intel_dsc_line_slice_count(&pipe_config->dsc.slice_config)); 2362 2363 return 0; 2364 } 2365 2366 static int 2367 dsc_throughput_quirk_max_bpp_x16(const struct intel_connector *connector, 2368 int mode_clock) 2369 { 2370 if (!connector->dp.dsc_throughput_quirk) 2371 return INT_MAX; 2372 2373 /* 2374 * Synaptics Panamera branch devices have a problem decompressing a 2375 * stream with a compressed link-bpp higher than 12, if the pixel 2376 * clock is higher than ~50 % of the maximum overall throughput 2377 * reported by the branch device. Work around this by limiting the 2378 * maximum link bpp for such pixel clocks. 2379 * 2380 * TODO: Use the throughput value specific to the actual RGB/YUV 2381 * format of the output, after determining the pixel clock limit for 2382 * YUV modes. For now use the smaller of the throughput values, which 2383 * may result in limiting the link-bpp value already at a lower than 2384 * required mode clock in case of native YUV422/420 output formats. 2385 * The RGB/YUV444 throughput value should be always either equal or 2386 * smaller than the YUV422/420 value, but let's not depend on this 2387 * assumption. 2388 */ 2389 if (mode_clock < 2390 min(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444, 2391 connector->dp.dsc_branch_caps.overall_throughput.yuv422_420) / 2) 2392 return INT_MAX; 2393 2394 return fxp_q4_from_int(12); 2395 } 2396 2397 int intel_dp_compute_min_compressed_bpp_x16(struct intel_connector *connector, 2398 enum intel_output_format output_format) 2399 { 2400 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; 2401 int min_bpp_x16; 2402 2403 dsc_src_min_bpp = intel_dp_dsc_min_src_compressed_bpp(); 2404 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(output_format); 2405 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 2406 2407 min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); 2408 2409 min_bpp_x16 = align_min_compressed_bpp_x16(connector, min_bpp_x16); 2410 2411 return min_bpp_x16; 2412 } 2413 2414 static int compute_max_compressed_bpp_x16(struct intel_connector *connector, 2415 int mode_clock, int mode_hdisplay, 2416 int num_joined_pipes, 2417 enum intel_output_format output_format, 2418 int pipe_max_bpp, int max_link_bpp_x16) 2419 { 2420 struct intel_display *display = to_intel_display(connector); 2421 struct intel_dp *intel_dp = intel_attached_dp(connector); 2422 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; 2423 int throughput_max_bpp_x16; 2424 int joiner_max_bpp; 2425 2426 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2427 joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, 2428 mode_clock, 2429 mode_hdisplay, 2430 num_joined_pipes); 2431 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, 2432 output_format, 2433 pipe_max_bpp / 3); 2434 dsc_max_bpp = min(dsc_sink_max_bpp, dsc_src_max_bpp); 2435 dsc_max_bpp = min(dsc_max_bpp, joiner_max_bpp); 2436 2437 max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp)); 2438 2439 throughput_max_bpp_x16 = dsc_throughput_quirk_max_bpp_x16(connector, 2440 mode_clock); 2441 if (throughput_max_bpp_x16 < max_link_bpp_x16) { 2442 max_link_bpp_x16 = throughput_max_bpp_x16; 2443 2444 drm_dbg_kms(display->drm, 2445 "[CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n", 2446 connector->base.base.id, connector->base.name, 2447 FXP_Q4_ARGS(max_link_bpp_x16)); 2448 } 2449 2450 max_link_bpp_x16 = align_max_compressed_bpp_x16(connector, output_format, 2451 pipe_max_bpp, max_link_bpp_x16); 2452 2453 return max_link_bpp_x16; 2454 } 2455 2456 bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector, 2457 int link_clock, int lane_count, 2458 int mode_clock, int mode_hdisplay, 2459 int num_joined_pipes, 2460 enum intel_output_format output_format, 2461 int pipe_bpp, unsigned long bw_overhead_flags) 2462 { 2463 struct intel_dp *intel_dp = intel_attached_dp(connector); 2464 int min_bpp_x16 = intel_dp_compute_min_compressed_bpp_x16(connector, 2465 output_format); 2466 int max_bpp_x16 = compute_max_compressed_bpp_x16(connector, 2467 mode_clock, mode_hdisplay, 2468 num_joined_pipes, 2469 output_format, 2470 pipe_bpp, INT_MAX); 2471 int dsc_slice_count = intel_dp_dsc_get_slice_count(connector, 2472 mode_clock, 2473 mode_hdisplay, 2474 num_joined_pipes); 2475 2476 if (min_bpp_x16 <= 0 || min_bpp_x16 > max_bpp_x16) 2477 return false; 2478 2479 if (dsc_slice_count == 0) 2480 return false; 2481 2482 return is_bw_sufficient_for_dsc_config(intel_dp, 2483 link_clock, lane_count, 2484 mode_clock, mode_hdisplay, 2485 dsc_slice_count, min_bpp_x16, 2486 bw_overhead_flags); 2487 } 2488 2489 bool 2490 intel_dp_get_connector_max_link_config(struct intel_connector *connector, 2491 const struct link_config_limits *limits, 2492 struct intel_dp_link_config *max_link_config) 2493 { 2494 struct intel_dp *intel_dp = intel_attached_dp(connector); 2495 struct intel_dp_link_caps *link_caps = intel_dp->link.caps; 2496 struct intel_dp_link_caps_order order = 2497 intel_dp_link_caps_connector_compute_order(connector); 2498 2499 return intel_dp_link_caps_get_max_config(link_caps, order.key, limits->link_config_filter, 2500 max_link_config); 2501 } 2502 2503 /* 2504 * Calculate the output link min, max bpp values in limits based on the pipe bpp 2505 * range, crtc_state and dsc mode. Return true on success. 2506 */ 2507 static bool 2508 intel_dp_compute_config_link_bpp_limits(struct intel_connector *connector, 2509 const struct intel_crtc_state *crtc_state, 2510 bool dsc, 2511 struct link_config_limits *limits) 2512 { 2513 struct intel_display *display = to_intel_display(connector); 2514 struct intel_dp *intel_dp = intel_attached_dp(connector); 2515 const struct drm_display_mode *adjusted_mode = 2516 &crtc_state->hw.adjusted_mode; 2517 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2518 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2519 struct intel_dp_link_config max_link_config; 2520 int max_link_bpp_x16; 2521 2522 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, 2523 fxp_q4_from_int(limits->pipe.max_bpp)); 2524 2525 if (!dsc) { 2526 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3)); 2527 2528 if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp)) 2529 return false; 2530 2531 limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp); 2532 } else { 2533 limits->link.min_bpp_x16 = 2534 intel_dp_compute_min_compressed_bpp_x16(connector, 2535 crtc_state->output_format); 2536 2537 max_link_bpp_x16 = 2538 compute_max_compressed_bpp_x16(connector, 2539 adjusted_mode->crtc_clock, 2540 adjusted_mode->hdisplay, 2541 intel_crtc_num_joined_pipes(crtc_state), 2542 crtc_state->output_format, 2543 limits->pipe.max_bpp, 2544 max_link_bpp_x16); 2545 } 2546 2547 limits->link.max_bpp_x16 = max_link_bpp_x16; 2548 2549 if (!intel_dp_get_connector_max_link_config(connector, limits, &max_link_config)) 2550 return false; 2551 2552 drm_dbg_kms(display->drm, 2553 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max link %dx%d max pipe_bpp %d min link_bpp " FXP_Q4_FMT " max link_bpp " FXP_Q4_FMT "\n", 2554 encoder->base.base.id, encoder->base.name, 2555 crtc->base.base.id, crtc->base.name, 2556 adjusted_mode->crtc_clock, 2557 str_on_off(dsc), 2558 max_link_config.lane_count, 2559 max_link_config.rate, 2560 limits->pipe.max_bpp, 2561 FXP_Q4_ARGS(limits->link.min_bpp_x16), 2562 FXP_Q4_ARGS(limits->link.max_bpp_x16)); 2563 2564 if (limits->link.min_bpp_x16 <= 0 || 2565 limits->link.min_bpp_x16 > limits->link.max_bpp_x16) 2566 return false; 2567 2568 return true; 2569 } 2570 2571 static bool 2572 intel_dp_dsc_compute_pipe_bpp_limits(struct intel_connector *connector, 2573 struct link_config_limits *limits) 2574 { 2575 struct intel_display *display = to_intel_display(connector); 2576 const struct link_config_limits orig_limits = *limits; 2577 int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(); 2578 int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 2579 2580 limits->pipe.min_bpp = max(limits->pipe.min_bpp, dsc_min_bpc * 3); 2581 limits->pipe.min_bpp = align_min_sink_dsc_input_bpp(connector, limits->pipe.min_bpp); 2582 2583 limits->pipe.max_bpp = min(limits->pipe.max_bpp, dsc_max_bpc * 3); 2584 limits->pipe.max_bpp = align_max_sink_dsc_input_bpp(connector, limits->pipe.max_bpp); 2585 2586 if (limits->pipe.min_bpp <= 0 || 2587 limits->pipe.min_bpp > limits->pipe.max_bpp) { 2588 drm_dbg_kms(display->drm, 2589 "[CONNECTOR:%d:%s] Invalid DSC src/sink input BPP (src:%d-%d pipe:%d-%d sink-align:%d-%d)\n", 2590 connector->base.base.id, connector->base.name, 2591 dsc_min_bpc * 3, dsc_max_bpc * 3, 2592 orig_limits.pipe.min_bpp, orig_limits.pipe.max_bpp, 2593 limits->pipe.min_bpp, limits->pipe.max_bpp); 2594 2595 return false; 2596 } 2597 2598 return true; 2599 } 2600 2601 bool 2602 intel_dp_compute_config_limits(struct intel_dp *intel_dp, 2603 struct drm_connector_state *conn_state, 2604 struct intel_crtc_state *crtc_state, 2605 bool respect_downstream_limits, 2606 bool dsc, 2607 struct link_config_limits *limits) 2608 { 2609 struct intel_display *display = to_intel_display(intel_dp); 2610 struct intel_dp_link_caps *link_caps = intel_dp->link.caps; 2611 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2612 struct intel_connector *connector = 2613 to_intel_connector(conn_state->connector); 2614 2615 limits->link_config_filter = INTEL_DP_LINK_CAPS_FILTER_ALL; 2616 2617 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); 2618 if (is_mst) { 2619 /* 2620 * FIXME: If all the streams can't fit into the link with their 2621 * current pipe_bpp we should reduce pipe_bpp across the board 2622 * until things start to fit. Until then we limit to <= 8bpc 2623 * since that's what was hardcoded for all MST streams 2624 * previously. This hack should be removed once we have the 2625 * proper retry logic in place. 2626 */ 2627 limits->pipe.max_bpp = min(crtc_state->max_pipe_bpp, 24); 2628 } else { 2629 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, 2630 respect_downstream_limits); 2631 } 2632 2633 if (!dsc && intel_dp_in_hdr_mode(conn_state)) { 2634 if (intel_dp_supports_dsc(intel_dp, connector, crtc_state) && 2635 limits->pipe.max_bpp >= 30) 2636 limits->pipe.min_bpp = max(limits->pipe.min_bpp, 30); 2637 else 2638 drm_dbg_kms(display->drm, 2639 "[CONNECTOR:%d:%s] Can't force 30 bpp for HDR (pipe bpp: %d-%d DSC-support: %s)\n", 2640 connector->base.base.id, connector->base.name, 2641 limits->pipe.min_bpp, limits->pipe.max_bpp, 2642 str_yes_no(intel_dp_supports_dsc(intel_dp, connector, 2643 crtc_state))); 2644 } 2645 2646 if (limits->pipe.min_bpp <= 0 || 2647 limits->pipe.min_bpp > limits->pipe.max_bpp) { 2648 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Invalid pipe bpp range: %d-%d\n", 2649 connector->base.base.id, connector->base.name, 2650 limits->pipe.min_bpp, limits->pipe.max_bpp); 2651 2652 return false; 2653 } 2654 2655 if (dsc && !intel_dp_dsc_compute_pipe_bpp_limits(connector, limits)) 2656 return false; 2657 2658 /* 2659 * crtc_state->pipe_bpp is the non-DP specific baseline (platform / 2660 * EDID) maximum pipe BPP limited by the max-BPC connector property 2661 * request. Since by now pipe.max_bpp is <= the above baseline 2662 * maximum BPP, the only remaining reason for adjusting pipe.max_bpp 2663 * is the max-BPC connector property request. Adjust pipe.max_bpp to 2664 * this request within the current valid pipe.min_bpp .. pipe.max_bpp 2665 * range. 2666 */ 2667 limits->pipe.max_bpp = clamp(crtc_state->pipe_bpp, limits->pipe.min_bpp, 2668 limits->pipe.max_bpp); 2669 if (dsc) 2670 limits->pipe.max_bpp = align_max_sink_dsc_input_bpp(connector, 2671 limits->pipe.max_bpp); 2672 2673 if (limits->pipe.max_bpp != crtc_state->pipe_bpp) 2674 drm_dbg_kms(display->drm, 2675 "[CONNECTOR:%d:%s] Adjusting requested max pipe bpp %d -> %d\n", 2676 connector->base.base.id, connector->base.name, 2677 crtc_state->pipe_bpp, limits->pipe.max_bpp); 2678 2679 if (is_mst || intel_dp->use_max_params) { 2680 struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE; 2681 struct intel_dp_link_config max_config; 2682 2683 /* 2684 * For MST we always configure max link bw - the spec doesn't 2685 * seem to suggest we should do otherwise. 2686 * 2687 * Use the maximum clock and number of lanes the eDP panel 2688 * advertizes being capable of in case the initial fast 2689 * optimal params failed us. The panels are generally 2690 * designed to support only a single clock and lane 2691 * configuration, and typically on older panels these 2692 * values correspond to the native resolution of the panel. 2693 */ 2694 if (!intel_dp_get_connector_max_link_config(connector, limits, &max_config)) 2695 return false; 2696 2697 if (!intel_dp_link_caps_filter_add(link_caps, &new_filter, &max_config)) 2698 return false; 2699 2700 limits->link_config_filter = new_filter; 2701 } 2702 2703 if (!intel_dp_test_compute_config(connector, crtc_state, limits)) 2704 return false; 2705 2706 return intel_dp_compute_config_link_bpp_limits(connector, 2707 crtc_state, 2708 dsc, 2709 limits); 2710 } 2711 2712 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state) 2713 { 2714 const struct drm_display_mode *adjusted_mode = 2715 &crtc_state->hw.adjusted_mode; 2716 int link_bpp_x16 = crtc_state->dsc.compression_enable ? 2717 crtc_state->dsc.compressed_bpp_x16 : 2718 fxp_q4_from_int(crtc_state->pipe_bpp); 2719 2720 return intel_dp_link_required(crtc_state->port_clock, crtc_state->lane_count, 2721 adjusted_mode->crtc_clock, adjusted_mode->hdisplay, 2722 link_bpp_x16, 0); 2723 } 2724 2725 bool intel_dp_joiner_needs_dsc(struct intel_display *display, 2726 int num_joined_pipes) 2727 { 2728 /* 2729 * Pipe joiner needs compression up to display 12 due to bandwidth 2730 * limitation. DG2 onwards pipe joiner can be enabled without 2731 * compression. 2732 * Ultrajoiner always needs compression. 2733 */ 2734 return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) || 2735 num_joined_pipes == 4; 2736 } 2737 2738 static int 2739 intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder, 2740 struct intel_crtc_state *pipe_config, 2741 struct drm_connector_state *conn_state, 2742 bool respect_downstream_limits) 2743 { 2744 struct intel_display *display = to_intel_display(encoder); 2745 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2746 struct intel_connector *connector = 2747 to_intel_connector(conn_state->connector); 2748 const struct drm_display_mode *adjusted_mode = 2749 &pipe_config->hw.adjusted_mode; 2750 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2751 struct link_config_limits limits; 2752 bool dsc_needed, joiner_needs_dsc; 2753 int ret = 0; 2754 2755 intel_dp_dsc_reset_config(pipe_config); 2756 2757 joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes); 2758 2759 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || 2760 !intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config, 2761 respect_downstream_limits, 2762 false, 2763 &limits); 2764 2765 if (!dsc_needed) { 2766 /* 2767 * Optimize for slow and wide for everything, because there are some 2768 * eDP 1.3 and 1.4 panels don't work well with fast and narrow. 2769 */ 2770 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, 2771 conn_state, &limits); 2772 if (!ret && intel_dp_is_uhbr(pipe_config)) 2773 ret = intel_dp_mtp_tu_compute_config(intel_dp, 2774 pipe_config, 2775 conn_state, 2776 fxp_q4_from_int(pipe_config->pipe_bpp), 2777 fxp_q4_from_int(pipe_config->pipe_bpp), 2778 0, false); 2779 2780 if (ret || 2781 !intel_dp_dotclk_valid(display, 2782 adjusted_mode->crtc_clock, 2783 adjusted_mode->crtc_htotal, 2784 0, 2785 num_joined_pipes)) 2786 dsc_needed = true; 2787 } 2788 2789 if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) { 2790 drm_dbg_kms(display->drm, "DSC required but not available\n"); 2791 return -EINVAL; 2792 } 2793 2794 if (dsc_needed) { 2795 int dsc_slice_count; 2796 2797 drm_dbg_kms(display->drm, 2798 "Try DSC (fallback=%s, joiner=%s, force=%s)\n", 2799 str_yes_no(ret), str_yes_no(joiner_needs_dsc), 2800 str_yes_no(intel_dp->force_dsc_en)); 2801 2802 if (!intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config, 2803 respect_downstream_limits, 2804 true, 2805 &limits)) 2806 return -EINVAL; 2807 2808 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 2809 conn_state, &limits, 64); 2810 if (ret < 0) 2811 return ret; 2812 2813 dsc_slice_count = intel_dsc_line_slice_count(&pipe_config->dsc.slice_config); 2814 2815 if (!intel_dp_dotclk_valid(display, 2816 adjusted_mode->crtc_clock, 2817 adjusted_mode->crtc_htotal, 2818 dsc_slice_count, 2819 num_joined_pipes)) 2820 return -EINVAL; 2821 } 2822 2823 drm_dbg_kms(display->drm, 2824 "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " HDR %s link rate required %d available %d\n", 2825 pipe_config->lane_count, pipe_config->port_clock, 2826 pipe_config->pipe_bpp, 2827 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2828 str_yes_no(intel_dp_in_hdr_mode(conn_state)), 2829 intel_dp_config_required_rate(pipe_config), 2830 intel_dp_max_link_data_rate(intel_dp, 2831 pipe_config->port_clock, 2832 pipe_config->lane_count)); 2833 2834 return 0; 2835 } 2836 2837 static int 2838 intel_dp_compute_link_config(struct intel_encoder *encoder, 2839 struct intel_crtc_state *crtc_state, 2840 struct drm_connector_state *conn_state, 2841 bool respect_downstream_limits) 2842 { 2843 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2844 struct intel_connector *connector = 2845 to_intel_connector(conn_state->connector); 2846 const struct drm_display_mode *adjusted_mode = 2847 &crtc_state->hw.adjusted_mode; 2848 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2849 int num_joined_pipes; 2850 int ret = -EINVAL; 2851 2852 if (crtc_state->fec_enable && 2853 !intel_dp_supports_fec(intel_dp, connector, crtc_state)) 2854 return -EINVAL; 2855 2856 for_each_joiner_candidate(connector, adjusted_mode, num_joined_pipes) { 2857 /* 2858 * NOTE: 2859 * The crtc_state->joiner_pipes should have been set at the end 2860 * only if all the conditions are met. However that would mean 2861 * that num_joined_pipes is passed around to all helpers and 2862 * make them use it instead of using crtc_state->joiner_pipes 2863 * directly or indirectly (via intel_crtc_num_joined_pipes()). 2864 * 2865 * For now, setting crtc_state->joiner_pipes to the candidate 2866 * value to avoid the above churn and resetting it to 0, in case 2867 * no joiner candidate is found to be suitable for the given 2868 * configuration. 2869 */ 2870 if (num_joined_pipes > 1) 2871 crtc_state->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, 2872 crtc->pipe); 2873 2874 ret = intel_dp_compute_link_for_joined_pipes(encoder, crtc_state, conn_state, 2875 respect_downstream_limits); 2876 if (ret == 0 || ret == -EDEADLK) 2877 break; 2878 } 2879 2880 if (ret < 0) 2881 crtc_state->joiner_pipes = 0; 2882 2883 return ret; 2884 } 2885 2886 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 2887 const struct drm_connector_state *conn_state) 2888 { 2889 const struct intel_digital_connector_state *intel_conn_state = 2890 to_intel_digital_connector_state(conn_state); 2891 const struct drm_display_mode *adjusted_mode = 2892 &crtc_state->hw.adjusted_mode; 2893 2894 /* 2895 * Our YCbCr output is always limited range. 2896 * crtc_state->limited_color_range only applies to RGB, 2897 * and it must never be set for YCbCr or we risk setting 2898 * some conflicting bits in TRANSCONF which will mess up 2899 * the colors on the monitor. 2900 */ 2901 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2902 return false; 2903 2904 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2905 /* 2906 * See: 2907 * CEA-861-E - 5.1 Default Encoding Parameters 2908 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 2909 */ 2910 return crtc_state->pipe_bpp != 18 && 2911 drm_default_rgb_quant_range(adjusted_mode) == 2912 HDMI_QUANTIZATION_RANGE_LIMITED; 2913 } else { 2914 return intel_conn_state->broadcast_rgb == 2915 INTEL_BROADCAST_RGB_LIMITED; 2916 } 2917 } 2918 2919 static bool intel_dp_port_has_audio(struct intel_display *display, enum port port) 2920 { 2921 if (display->platform.g4x) 2922 return false; 2923 if (DISPLAY_VER(display) < 12 && port == PORT_A) 2924 return false; 2925 2926 return true; 2927 } 2928 2929 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, 2930 const struct drm_connector_state *conn_state, 2931 struct drm_dp_vsc_sdp *vsc) 2932 { 2933 struct intel_display *display = to_intel_display(crtc_state); 2934 2935 if (crtc_state->has_panel_replay) { 2936 /* 2937 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2938 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel 2939 * Encoding/Colorimetry Format indication. 2940 */ 2941 vsc->revision = 0x7; 2942 } else { 2943 /* 2944 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2945 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ 2946 * Colorimetry Format indication. 2947 */ 2948 vsc->revision = 0x5; 2949 } 2950 2951 vsc->length = 0x13; 2952 2953 /* DP 1.4a spec, Table 2-120 */ 2954 switch (crtc_state->output_format) { 2955 case INTEL_OUTPUT_FORMAT_YCBCR444: 2956 vsc->pixelformat = DP_PIXELFORMAT_YUV444; 2957 break; 2958 case INTEL_OUTPUT_FORMAT_YCBCR420: 2959 vsc->pixelformat = DP_PIXELFORMAT_YUV420; 2960 break; 2961 case INTEL_OUTPUT_FORMAT_RGB: 2962 default: 2963 vsc->pixelformat = DP_PIXELFORMAT_RGB; 2964 } 2965 2966 switch (conn_state->colorspace) { 2967 case DRM_MODE_COLORIMETRY_BT709_YCC: 2968 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2969 break; 2970 case DRM_MODE_COLORIMETRY_XVYCC_601: 2971 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; 2972 break; 2973 case DRM_MODE_COLORIMETRY_XVYCC_709: 2974 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; 2975 break; 2976 case DRM_MODE_COLORIMETRY_SYCC_601: 2977 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; 2978 break; 2979 case DRM_MODE_COLORIMETRY_OPYCC_601: 2980 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; 2981 break; 2982 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 2983 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; 2984 break; 2985 case DRM_MODE_COLORIMETRY_BT2020_RGB: 2986 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; 2987 break; 2988 case DRM_MODE_COLORIMETRY_BT2020_YCC: 2989 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; 2990 break; 2991 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 2992 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 2993 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; 2994 break; 2995 default: 2996 /* 2997 * RGB->YCBCR color conversion uses the BT.709 2998 * color space. 2999 */ 3000 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3001 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 3002 else 3003 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; 3004 break; 3005 } 3006 3007 vsc->bpc = crtc_state->pipe_bpp / 3; 3008 3009 /* only RGB pixelformat supports 6 bpc */ 3010 drm_WARN_ON(display->drm, 3011 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); 3012 3013 /* All YCbCr formats are always limited range. */ 3014 if (vsc->pixelformat == DP_PIXELFORMAT_RGB) 3015 vsc->dynamic_range = crtc_state->limited_color_range ? 3016 DP_DYNAMIC_RANGE_CTA : DP_DYNAMIC_RANGE_VESA; 3017 else 3018 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; 3019 3020 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; 3021 } 3022 3023 static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp, 3024 struct intel_crtc_state *crtc_state) 3025 { 3026 if (!intel_dp->as_sdp_v2_supported) 3027 return false; 3028 3029 /* 3030 * #TODO: Add AS SDP v1 support for PCONs (DP branch devices). 3031 */ 3032 if (drm_dp_is_branch(intel_dp->dpcd)) 3033 return false; 3034 3035 if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) && 3036 !intel_psr_pr_async_video_timing_supported(intel_dp)) 3037 return true; 3038 3039 return intel_vrr_possible(crtc_state); 3040 } 3041 3042 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, 3043 struct intel_crtc_state *crtc_state) 3044 { 3045 struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; 3046 const struct drm_display_mode *adjusted_mode = 3047 &crtc_state->hw.adjusted_mode; 3048 3049 /* 3050 * #FIXME: SDP/infoframe updates aren’t truly atomic, and with the new 3051 * cdclk->tc clock crossing we may transiently send a corrupted packet 3052 * if the update lands mid‑transmission. 3053 */ 3054 if (!intel_dp_needs_as_sdp(intel_dp, crtc_state)) 3055 return; 3056 3057 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); 3058 3059 as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; 3060 as_sdp->length = 0x9; 3061 as_sdp->duration_incr_ms = 0; 3062 as_sdp->revision = 0x2; 3063 as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state); 3064 3065 if (crtc_state->cmrr.enable) { 3066 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; 3067 as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode); 3068 as_sdp->target_rr_divider = true; 3069 } else if (crtc_state->vrr.enable) { 3070 as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL; 3071 } else { 3072 as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; 3073 } 3074 3075 /* 3076 * For Panel Replay with Async Video Timing support, the source can 3077 * disable sending the AS SDP during PR Active state. In that case, 3078 * the sink needs the coasting vtotal value to maintain the refresh 3079 * rate. The HW only samples this on PR_ALPM_CTL[AS SDP Transmission 3080 * in Active Disable], which we never program, so providing the value 3081 * unconditionally when the sink advertises the capability is safe. 3082 * 3083 * #TODO: 3084 * If we ever advertise support for coasting at other refresh targets, 3085 * this logic could be revisited. For now, use the minimum refresh rate 3086 * as the only safe coasting value. 3087 */ 3088 if (intel_psr_pr_async_video_timing_supported(intel_dp)) 3089 as_sdp->coasting_vtotal = crtc_state->vrr.vmax; 3090 } 3091 3092 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, 3093 struct intel_crtc_state *crtc_state, 3094 const struct drm_connector_state *conn_state) 3095 { 3096 struct drm_dp_vsc_sdp *vsc; 3097 3098 if ((!intel_dp->colorimetry_support || 3099 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) && 3100 !crtc_state->has_psr) 3101 return; 3102 3103 vsc = &crtc_state->infoframes.vsc; 3104 3105 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 3106 vsc->sdp_type = DP_SDP_VSC; 3107 3108 /* Needs colorimetry */ 3109 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { 3110 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 3111 vsc); 3112 } else if (crtc_state->has_panel_replay) { 3113 /* 3114 * [Panel Replay without colorimetry info] 3115 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 3116 * VSC SDP supporting 3D stereo + Panel Replay. 3117 */ 3118 vsc->revision = 0x6; 3119 vsc->length = 0x10; 3120 } else if (crtc_state->has_sel_update) { 3121 /* 3122 * [PSR2 without colorimetry] 3123 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 3124 * 3D stereo + PSR/PSR2 + Y-coordinate. 3125 */ 3126 vsc->revision = 0x4; 3127 vsc->length = 0xe; 3128 } else { 3129 /* 3130 * [PSR1] 3131 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 3132 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or 3133 * higher). 3134 */ 3135 vsc->revision = 0x2; 3136 vsc->length = 0x8; 3137 } 3138 } 3139 3140 bool 3141 intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state) 3142 { 3143 struct hdr_output_metadata *hdr_metadata; 3144 3145 if (!conn_state->hdr_output_metadata) 3146 return false; 3147 3148 hdr_metadata = conn_state->hdr_output_metadata->data; 3149 3150 return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084; 3151 } 3152 3153 static void 3154 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, 3155 struct intel_crtc_state *crtc_state, 3156 const struct drm_connector_state *conn_state) 3157 { 3158 struct intel_display *display = to_intel_display(intel_dp); 3159 int ret; 3160 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; 3161 3162 if (!conn_state->hdr_output_metadata) 3163 return; 3164 3165 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); 3166 3167 if (ret) { 3168 drm_dbg_kms(display->drm, 3169 "couldn't set HDR metadata in infoframe\n"); 3170 return; 3171 } 3172 3173 crtc_state->infoframes.enable |= 3174 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 3175 } 3176 3177 static bool can_enable_drrs(struct intel_connector *connector, 3178 const struct intel_crtc_state *pipe_config, 3179 const struct drm_display_mode *downclock_mode) 3180 { 3181 struct intel_display *display = to_intel_display(connector); 3182 3183 if (pipe_config->vrr.enable) 3184 return false; 3185 3186 /* 3187 * DRRS and PSR can't be enable together, so giving preference to PSR 3188 * as it allows more power-savings by complete shutting down display, 3189 * so to guarantee this, intel_drrs_compute_config() must be called 3190 * after intel_psr_compute_config(). 3191 */ 3192 if (pipe_config->has_psr) 3193 return false; 3194 3195 /* FIXME missing FDI M2/N2 etc. */ 3196 if (pipe_config->has_pch_encoder) 3197 return false; 3198 3199 if (!intel_cpu_transcoder_has_drrs(display, pipe_config->cpu_transcoder)) 3200 return false; 3201 3202 return downclock_mode && 3203 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 3204 } 3205 3206 static void 3207 intel_dp_drrs_compute_config(struct intel_connector *connector, 3208 struct intel_crtc_state *pipe_config, 3209 int link_bpp_x16) 3210 { 3211 struct intel_display *display = to_intel_display(connector); 3212 const struct drm_display_mode *downclock_mode = 3213 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 3214 int pixel_clock; 3215 3216 /* 3217 * FIXME all joined pipes share the same transcoder. 3218 * Need to account for that when updating M/N live. 3219 */ 3220 if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes) 3221 pipe_config->update_m_n = true; 3222 3223 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { 3224 if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder)) 3225 intel_zero_m_n(&pipe_config->dp_m2_n2); 3226 return; 3227 } 3228 3229 if (display->platform.ironlake || display->platform.sandybridge || 3230 display->platform.ivybridge) 3231 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; 3232 3233 pipe_config->has_drrs = true; 3234 3235 pixel_clock = downclock_mode->clock; 3236 if (pipe_config->splitter.enable) 3237 pixel_clock /= pipe_config->splitter.link_count; 3238 3239 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock, 3240 pipe_config->port_clock, 3241 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 3242 &pipe_config->dp_m2_n2); 3243 3244 /* FIXME: abstract this better */ 3245 if (pipe_config->splitter.enable) 3246 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 3247 } 3248 3249 static bool intel_dp_has_audio(struct intel_encoder *encoder, 3250 const struct drm_connector_state *conn_state) 3251 { 3252 struct intel_display *display = to_intel_display(encoder); 3253 const struct intel_digital_connector_state *intel_conn_state = 3254 to_intel_digital_connector_state(conn_state); 3255 struct intel_connector *connector = 3256 to_intel_connector(conn_state->connector); 3257 3258 if (!intel_dp_port_has_audio(display, encoder->port)) 3259 return false; 3260 3261 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 3262 return connector->base.display_info.has_audio; 3263 else 3264 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 3265 } 3266 3267 static int 3268 intel_dp_compute_output_format(struct intel_encoder *encoder, 3269 struct intel_crtc_state *crtc_state, 3270 struct drm_connector_state *conn_state, 3271 bool respect_downstream_limits, 3272 enum intel_output_format sink_format) 3273 { 3274 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3275 struct intel_connector *connector = intel_dp->attached_connector; 3276 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3277 3278 if (intel_dp_sink_format_valid(connector, adjusted_mode, 3279 sink_format) != MODE_OK) 3280 return -EINVAL; 3281 3282 crtc_state->sink_format = sink_format; 3283 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); 3284 3285 return intel_dp_compute_link_config(encoder, crtc_state, conn_state, 3286 respect_downstream_limits); 3287 } 3288 3289 static int 3290 intel_dp_compute_formats(struct intel_encoder *encoder, 3291 struct intel_crtc_state *crtc_state, 3292 struct drm_connector_state *conn_state, 3293 bool respect_downstream_limits) 3294 { 3295 struct intel_display *display = to_intel_display(encoder); 3296 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3297 struct intel_connector *connector = intel_dp->attached_connector; 3298 const struct drm_display_info *info = &connector->base.display_info; 3299 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3300 int ret; 3301 3302 if (drm_mode_is_420_only(info, adjusted_mode)) { 3303 ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state, 3304 respect_downstream_limits, 3305 INTEL_OUTPUT_FORMAT_YCBCR420); 3306 3307 if (ret && !respect_downstream_limits) { 3308 drm_dbg_kms(display->drm, 3309 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 3310 3311 ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state, 3312 respect_downstream_limits, 3313 INTEL_OUTPUT_FORMAT_RGB); 3314 } 3315 } else { 3316 ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state, 3317 respect_downstream_limits, 3318 INTEL_OUTPUT_FORMAT_RGB); 3319 3320 if (ret && drm_mode_is_420_also(info, adjusted_mode)) 3321 ret = intel_dp_compute_output_format(encoder, crtc_state, conn_state, 3322 respect_downstream_limits, 3323 INTEL_OUTPUT_FORMAT_YCBCR420); 3324 } 3325 3326 return ret; 3327 } 3328 3329 void 3330 intel_dp_audio_compute_config(struct intel_encoder *encoder, 3331 struct intel_crtc_state *pipe_config, 3332 struct drm_connector_state *conn_state) 3333 { 3334 pipe_config->has_audio = 3335 intel_dp_has_audio(encoder, conn_state) && 3336 intel_audio_compute_config(encoder, pipe_config, conn_state); 3337 3338 pipe_config->sdp_split_enable = pipe_config->has_audio && 3339 intel_dp_is_uhbr(pipe_config); 3340 } 3341 3342 void 3343 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, 3344 struct intel_encoder *encoder, 3345 const struct intel_crtc_state *crtc_state) 3346 { 3347 struct intel_connector *connector; 3348 struct intel_digital_connector_state *conn_state; 3349 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3350 int i; 3351 3352 if (intel_dp->needs_modeset_retry) 3353 return; 3354 3355 intel_dp->needs_modeset_retry = true; 3356 3357 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3358 intel_connector_queue_modeset_retry_work(intel_dp->attached_connector); 3359 3360 return; 3361 } 3362 3363 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { 3364 if (!conn_state->base.crtc) 3365 continue; 3366 3367 if (connector->mst.dp == intel_dp) 3368 intel_connector_queue_modeset_retry_work(connector); 3369 } 3370 } 3371 3372 int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, 3373 const struct drm_connector_state *conn_state) 3374 { 3375 struct intel_display *display = to_intel_display(crtc_state); 3376 const struct drm_display_mode *adjusted_mode = 3377 &crtc_state->hw.adjusted_mode; 3378 struct intel_connector *connector = to_intel_connector(conn_state->connector); 3379 int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8; 3380 /* 3381 * min symbol cycles is 3(BS,VBID, BE) for 128b/132b and 3382 * 5(BS, VBID, MVID, MAUD, BE) for 8b/10b 3383 */ 3384 int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5; 3385 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3386 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state); 3387 int min_hblank; 3388 int max_lane_count = 4; 3389 int hactive_sym_cycles, htotal_sym_cycles; 3390 int dsc_slices = 0; 3391 int link_bpp_x16; 3392 3393 if (DISPLAY_VER(display) < 30) 3394 return 0; 3395 3396 /* MIN_HBLANK should be set only for 8b/10b MST or for 128b/132b SST/MST */ 3397 if (!is_mst && !intel_dp_is_uhbr(crtc_state)) 3398 return 0; 3399 3400 if (crtc_state->dsc.compression_enable) { 3401 dsc_slices = intel_dp_dsc_get_slice_count(connector, 3402 adjusted_mode->crtc_clock, 3403 adjusted_mode->crtc_hdisplay, 3404 num_joined_pipes); 3405 if (!dsc_slices) { 3406 drm_dbg(display->drm, "failed to calculate dsc slice count\n"); 3407 return -EINVAL; 3408 } 3409 } 3410 3411 if (crtc_state->dsc.compression_enable) 3412 link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; 3413 else 3414 link_bpp_x16 = intel_dp_output_format_link_bpp_x16(crtc_state->output_format, 3415 crtc_state->pipe_bpp); 3416 3417 /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ 3418 hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count, 3419 adjusted_mode->hdisplay, 3420 dsc_slices, 3421 link_bpp_x16, 3422 symbol_size, is_mst); 3423 htotal_sym_cycles = adjusted_mode->htotal * hactive_sym_cycles / 3424 adjusted_mode->hdisplay; 3425 3426 min_hblank = htotal_sym_cycles - hactive_sym_cycles; 3427 /* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */ 3428 min_hblank = max(min_hblank, min_sym_cycles); 3429 3430 /* 3431 * adjust the BlankingStart/BlankingEnd framing control from 3432 * the calculated value 3433 */ 3434 min_hblank = min_hblank - 2; 3435 3436 /* 3437 * min_hblank formula is undergoing a change, to avoid underrun use the 3438 * recomended value in spec to compare with the calculated one and use the 3439 * minimum value 3440 */ 3441 if (intel_dp_is_uhbr(crtc_state)) { 3442 /* 3443 * Note: Bspec requires a min_hblank of 2 for YCBCR420 3444 * with compressed bpp 6, but the minimum compressed bpp 3445 * supported by the driver is 8. 3446 */ 3447 drm_WARN_ON(display->drm, 3448 (crtc_state->dsc.compression_enable && 3449 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 3450 crtc_state->dsc.compressed_bpp_x16 < fxp_q4_from_int(8))); 3451 min_hblank = min(3, min_hblank); 3452 } else { 3453 min_hblank = min(10, min_hblank); 3454 } 3455 3456 crtc_state->min_hblank = min_hblank; 3457 3458 return 0; 3459 } 3460 3461 int 3462 intel_dp_compute_config(struct intel_atomic_state *state, 3463 struct intel_encoder *encoder, 3464 struct intel_crtc_state *pipe_config, 3465 struct drm_connector_state *conn_state) 3466 { 3467 struct intel_display *display = to_intel_display(encoder); 3468 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 3469 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3470 struct intel_connector *connector = intel_dp->attached_connector; 3471 int ret = 0, link_bpp_x16; 3472 3473 if (intel_dp_is_edp(intel_dp)) { 3474 ret = intel_panel_compute_config(state, pipe_config, connector); 3475 if (ret) 3476 return ret; 3477 } 3478 3479 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 3480 return -EINVAL; 3481 3482 if (!connector->base.interlace_allowed && 3483 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 3484 return -EINVAL; 3485 3486 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 3487 return -EINVAL; 3488 3489 if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay)) 3490 return -EINVAL; 3491 3492 /* 3493 * Try to respect downstream TMDS clock limits first, if 3494 * that fails assume the user might know something we don't. 3495 */ 3496 ret = intel_dp_compute_formats(encoder, pipe_config, conn_state, true); 3497 if (ret) 3498 ret = intel_dp_compute_formats(encoder, pipe_config, conn_state, false); 3499 if (ret) 3500 return ret; 3501 3502 ret = intel_pfit_compute_config(pipe_config, conn_state); 3503 if (ret) 3504 return ret; 3505 3506 pipe_config->limited_color_range = 3507 intel_dp_limited_color_range(pipe_config, conn_state); 3508 3509 if (intel_dp_is_uhbr(pipe_config)) { 3510 /* 128b/132b SST also needs this */ 3511 pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder; 3512 } else { 3513 pipe_config->enhanced_framing = 3514 drm_dp_enhanced_frame_cap(intel_dp->dpcd); 3515 } 3516 3517 if (pipe_config->dsc.compression_enable) 3518 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; 3519 else 3520 link_bpp_x16 = intel_dp_output_format_link_bpp_x16(pipe_config->output_format, 3521 pipe_config->pipe_bpp); 3522 3523 if (intel_dp->mso_link_count) { 3524 int n = intel_dp->mso_link_count; 3525 int overlap = intel_dp->mso_pixel_overlap; 3526 3527 pipe_config->splitter.enable = true; 3528 pipe_config->splitter.link_count = n; 3529 pipe_config->splitter.pixel_overlap = overlap; 3530 3531 drm_dbg_kms(display->drm, 3532 "MSO link count %d, pixel overlap %d\n", 3533 n, overlap); 3534 3535 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; 3536 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; 3537 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; 3538 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; 3539 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; 3540 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; 3541 adjusted_mode->crtc_clock /= n; 3542 } 3543 3544 intel_dp_audio_compute_config(encoder, pipe_config, conn_state); 3545 3546 if (!intel_dp_is_uhbr(pipe_config)) { 3547 intel_link_compute_m_n(link_bpp_x16, 3548 pipe_config->lane_count, 3549 adjusted_mode->crtc_clock, 3550 pipe_config->port_clock, 3551 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 3552 &pipe_config->dp_m_n); 3553 } 3554 3555 ret = intel_dp_compute_min_hblank(pipe_config, conn_state); 3556 if (ret) 3557 return ret; 3558 3559 /* FIXME: abstract this better */ 3560 if (pipe_config->splitter.enable) 3561 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; 3562 3563 intel_vrr_compute_config(pipe_config, conn_state); 3564 intel_psr_compute_config(intel_dp, pipe_config, conn_state); 3565 intel_dp_compute_as_sdp(intel_dp, pipe_config); 3566 intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state); 3567 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); 3568 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); 3569 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); 3570 3571 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector, 3572 pipe_config); 3573 } 3574 3575 void intel_dp_set_link_params(struct intel_dp *intel_dp, 3576 int link_rate, int lane_count) 3577 { 3578 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 3579 intel_dp->link.active = false; 3580 intel_dp->needs_modeset_retry = false; 3581 intel_dp->link_rate = link_rate; 3582 intel_dp->lane_count = lane_count; 3583 } 3584 3585 void intel_dp_reset_link_params(struct intel_dp *intel_dp) 3586 { 3587 /* 3588 * TODO: Remove the following reset of link capabilities, as 3589 * this isn't needed after intel_dp_link_caps_update(reset=true) 3590 * was called. 3591 */ 3592 intel_dp_link_caps_reset(intel_dp->link.caps); 3593 intel_dp->link.mst_probed_lane_count = 0; 3594 intel_dp->link.mst_probed_rate = 0; 3595 intel_dp_link_training_reset(intel_dp->link.training); 3596 } 3597 3598 /* Enable backlight PWM and backlight PP control. */ 3599 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 3600 const struct drm_connector_state *conn_state) 3601 { 3602 struct intel_display *display = to_intel_display(crtc_state); 3603 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); 3604 3605 if (!intel_dp_is_edp(intel_dp)) 3606 return; 3607 3608 drm_dbg_kms(display->drm, "\n"); 3609 3610 intel_backlight_enable(crtc_state, conn_state); 3611 intel_pps_backlight_on(intel_dp); 3612 } 3613 3614 /* Disable backlight PP control and backlight PWM. */ 3615 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) 3616 { 3617 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); 3618 struct intel_display *display = to_intel_display(intel_dp); 3619 3620 if (!intel_dp_is_edp(intel_dp)) 3621 return; 3622 3623 drm_dbg_kms(display->drm, "\n"); 3624 3625 intel_pps_backlight_off(intel_dp); 3626 intel_backlight_disable(old_conn_state); 3627 } 3628 3629 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) 3630 { 3631 /* 3632 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus 3633 * be capable of signalling downstream hpd with a long pulse. 3634 * Whether or not that means D3 is safe to use is not clear, 3635 * but let's assume so until proven otherwise. 3636 * 3637 * FIXME should really check all downstream ports... 3638 */ 3639 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 3640 drm_dp_is_branch(intel_dp->dpcd) && 3641 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; 3642 } 3643 3644 static int 3645 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set) 3646 { 3647 int err; 3648 u8 val; 3649 3650 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val); 3651 if (err < 0) 3652 return err; 3653 3654 if (set) 3655 val |= flag; 3656 else 3657 val &= ~flag; 3658 3659 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val); 3660 } 3661 3662 static void 3663 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, 3664 bool enable) 3665 { 3666 struct intel_display *display = to_intel_display(connector); 3667 3668 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux, 3669 DP_DECOMPRESSION_EN, enable) < 0) 3670 drm_dbg_kms(display->drm, 3671 "Failed to %s sink decompression state\n", 3672 str_enable_disable(enable)); 3673 } 3674 3675 static void 3676 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, 3677 bool enable) 3678 { 3679 struct intel_display *display = to_intel_display(connector); 3680 struct drm_dp_aux *aux = connector->mst.port ? 3681 connector->mst.port->passthrough_aux : NULL; 3682 3683 if (!aux) 3684 return; 3685 3686 if (write_dsc_decompression_flag(aux, 3687 DP_DSC_PASSTHROUGH_EN, enable) < 0) 3688 drm_dbg_kms(display->drm, 3689 "Failed to %s sink compression passthrough state\n", 3690 str_enable_disable(enable)); 3691 } 3692 3693 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, 3694 const struct intel_connector *connector, 3695 bool for_get_ref) 3696 { 3697 struct intel_display *display = to_intel_display(state); 3698 struct drm_connector *_connector_iter; 3699 struct drm_connector_state *old_conn_state; 3700 struct drm_connector_state *new_conn_state; 3701 int ref_count = 0; 3702 int i; 3703 3704 /* 3705 * On SST the decompression AUX device won't be shared, each connector 3706 * uses for this its own AUX targeting the sink device. 3707 */ 3708 if (!connector->mst.dp) 3709 return connector->dp.dsc_decompression_enabled ? 1 : 0; 3710 3711 for_each_oldnew_connector_in_state(&state->base, _connector_iter, 3712 old_conn_state, new_conn_state, i) { 3713 const struct intel_connector * 3714 connector_iter = to_intel_connector(_connector_iter); 3715 3716 if (connector_iter->mst.dp != connector->mst.dp) 3717 continue; 3718 3719 if (!connector_iter->dp.dsc_decompression_enabled) 3720 continue; 3721 3722 drm_WARN_ON(display->drm, 3723 (for_get_ref && !new_conn_state->crtc) || 3724 (!for_get_ref && !old_conn_state->crtc)); 3725 3726 if (connector_iter->dp.dsc_decompression_aux == 3727 connector->dp.dsc_decompression_aux) 3728 ref_count++; 3729 } 3730 3731 return ref_count; 3732 } 3733 3734 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state, 3735 struct intel_connector *connector) 3736 { 3737 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0; 3738 3739 connector->dp.dsc_decompression_enabled = true; 3740 3741 return ret; 3742 } 3743 3744 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state, 3745 struct intel_connector *connector) 3746 { 3747 connector->dp.dsc_decompression_enabled = false; 3748 3749 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0; 3750 } 3751 3752 /** 3753 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device 3754 * @state: atomic state 3755 * @connector: connector to enable the decompression for 3756 * @new_crtc_state: new state for the CRTC driving @connector 3757 * 3758 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3759 * register of the appropriate sink/branch device. On SST this is always the 3760 * sink device, whereas on MST based on each device's DSC capabilities it's 3761 * either the last branch device (enabling decompression in it) or both the 3762 * last branch device (enabling passthrough in it) and the sink device 3763 * (enabling decompression in it). 3764 */ 3765 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, 3766 struct intel_connector *connector, 3767 const struct intel_crtc_state *new_crtc_state) 3768 { 3769 struct intel_display *display = to_intel_display(state); 3770 3771 if (!new_crtc_state->dsc.compression_enable) 3772 return; 3773 3774 if (drm_WARN_ON(display->drm, 3775 !connector->dp.dsc_decompression_aux || 3776 connector->dp.dsc_decompression_enabled)) 3777 return; 3778 3779 if (!intel_dp_dsc_aux_get_ref(state, connector)) 3780 return; 3781 3782 intel_dp_sink_set_dsc_passthrough(connector, true); 3783 intel_dp_sink_set_dsc_decompression(connector, true); 3784 } 3785 3786 /** 3787 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device 3788 * @state: atomic state 3789 * @connector: connector to disable the decompression for 3790 * @old_crtc_state: old state for the CRTC driving @connector 3791 * 3792 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3793 * register of the appropriate sink/branch device, corresponding to the 3794 * sequence in intel_dp_sink_enable_decompression(). 3795 */ 3796 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, 3797 struct intel_connector *connector, 3798 const struct intel_crtc_state *old_crtc_state) 3799 { 3800 struct intel_display *display = to_intel_display(state); 3801 3802 if (!old_crtc_state->dsc.compression_enable) 3803 return; 3804 3805 if (drm_WARN_ON(display->drm, 3806 !connector->dp.dsc_decompression_aux || 3807 !connector->dp.dsc_decompression_enabled)) 3808 return; 3809 3810 if (!intel_dp_dsc_aux_put_ref(state, connector)) 3811 return; 3812 3813 intel_dp_sink_set_dsc_decompression(connector, false); 3814 intel_dp_sink_set_dsc_passthrough(connector, false); 3815 } 3816 3817 static void 3818 intel_dp_init_source_oui(struct intel_dp *intel_dp) 3819 { 3820 struct intel_display *display = to_intel_display(intel_dp); 3821 u8 oui[] = { 0x00, 0xaa, 0x01 }; 3822 u8 buf[3] = {}; 3823 3824 if (READ_ONCE(intel_dp->oui_valid)) 3825 return; 3826 3827 WRITE_ONCE(intel_dp->oui_valid, true); 3828 3829 /* 3830 * During driver init, we want to be careful and avoid changing the source OUI if it's 3831 * already set to what we want, so as to avoid clearing any state by accident 3832 */ 3833 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) 3834 drm_dbg_kms(display->drm, "Failed to read source OUI\n"); 3835 3836 if (memcmp(oui, buf, sizeof(oui)) == 0) { 3837 /* Assume the OUI was written now. */ 3838 intel_dp->last_oui_write = jiffies; 3839 return; 3840 } 3841 3842 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) { 3843 drm_dbg_kms(display->drm, "Failed to write source OUI\n"); 3844 WRITE_ONCE(intel_dp->oui_valid, false); 3845 } 3846 3847 intel_dp->last_oui_write = jiffies; 3848 } 3849 3850 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp) 3851 { 3852 WRITE_ONCE(intel_dp->oui_valid, false); 3853 } 3854 3855 void intel_dp_wait_source_oui(struct intel_dp *intel_dp) 3856 { 3857 struct intel_display *display = to_intel_display(intel_dp); 3858 struct intel_connector *connector = intel_dp->attached_connector; 3859 3860 drm_dbg_kms(display->drm, 3861 "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n", 3862 connector->base.base.id, connector->base.name, 3863 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3864 3865 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 3866 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3867 } 3868 3869 /* If the device supports it, try to set the power state appropriately */ 3870 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) 3871 { 3872 struct intel_display *display = to_intel_display(intel_dp); 3873 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3874 int ret, i; 3875 3876 /* Should have a valid DPCD by this point */ 3877 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 3878 return; 3879 3880 if (mode != DP_SET_POWER_D0) { 3881 if (downstream_hpd_needs_d0(intel_dp)) 3882 return; 3883 3884 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3885 } else { 3886 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3887 3888 intel_lspcon_resume(dig_port); 3889 3890 /* Write the source OUI as early as possible */ 3891 intel_dp_init_source_oui(intel_dp); 3892 3893 /* 3894 * When turning on, we need to retry for 1ms to give the sink 3895 * time to wake up. 3896 */ 3897 for (i = 0; i < 3; i++) { 3898 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3899 if (ret == 1) 3900 break; 3901 msleep(1); 3902 } 3903 3904 if (ret == 1 && intel_lspcon_active(dig_port)) 3905 intel_lspcon_wait_pcon_mode(dig_port); 3906 } 3907 3908 if (ret != 1) 3909 drm_dbg_kms(display->drm, 3910 "[ENCODER:%d:%s] Set power to %s failed\n", 3911 encoder->base.base.id, encoder->base.name, 3912 mode == DP_SET_POWER_D0 ? "D0" : "D3"); 3913 } 3914 3915 static bool 3916 intel_dp_get_dpcd(struct intel_dp *intel_dp); 3917 3918 /** 3919 * intel_dp_sync_state - sync the encoder state during init/resume 3920 * @encoder: intel encoder to sync 3921 * @crtc_state: state for the CRTC connected to the encoder 3922 * 3923 * Sync any state stored in the encoder wrt. HW state during driver init 3924 * and system resume. 3925 */ 3926 void intel_dp_sync_state(struct intel_encoder *encoder, 3927 const struct intel_crtc_state *crtc_state) 3928 { 3929 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3930 bool dpcd_updated = false; 3931 3932 /* 3933 * Don't clobber DPCD if it's been already read out during output 3934 * setup (eDP) or detect. 3935 */ 3936 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) { 3937 intel_dp_get_dpcd(intel_dp); 3938 dpcd_updated = true; 3939 } 3940 3941 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); 3942 3943 if (crtc_state) { 3944 intel_dp_reset_link_params(intel_dp); 3945 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 3946 intel_dp->link.active = true; 3947 } 3948 } 3949 3950 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 3951 struct intel_crtc_state *crtc_state) 3952 { 3953 struct intel_display *display = to_intel_display(encoder); 3954 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3955 bool fastset = true; 3956 3957 /* 3958 * If BIOS has set an unsupported or non-standard link rate for some 3959 * reason force an encoder recompute and full modeset. 3960 */ 3961 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, 3962 crtc_state->port_clock) < 0) { 3963 drm_dbg_kms(display->drm, 3964 "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n", 3965 encoder->base.base.id, encoder->base.name); 3966 crtc_state->uapi.connectors_changed = true; 3967 fastset = false; 3968 } 3969 3970 /* 3971 * FIXME hack to force full modeset when DSC is being used. 3972 * 3973 * As long as we do not have full state readout and config comparison 3974 * of crtc_state->dsc, we have no way to ensure reliable fastset. 3975 * Remove once we have readout for DSC. 3976 */ 3977 if (crtc_state->dsc.compression_enable) { 3978 drm_dbg_kms(display->drm, 3979 "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n", 3980 encoder->base.base.id, encoder->base.name); 3981 crtc_state->uapi.mode_changed = true; 3982 fastset = false; 3983 } 3984 3985 if (CAN_PANEL_REPLAY(intel_dp)) { 3986 drm_dbg_kms(display->drm, 3987 "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n", 3988 encoder->base.base.id, encoder->base.name); 3989 crtc_state->uapi.mode_changed = true; 3990 fastset = false; 3991 } 3992 3993 return fastset; 3994 } 3995 3996 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) 3997 { 3998 struct intel_display *display = to_intel_display(intel_dp); 3999 4000 /* Clear the cached register set to avoid using stale values */ 4001 4002 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); 4003 4004 if (!drm_dp_is_branch(intel_dp->dpcd)) 4005 return; 4006 4007 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, 4008 intel_dp->pcon_dsc_dpcd, 4009 sizeof(intel_dp->pcon_dsc_dpcd)) < 0) 4010 drm_err(display->drm, "Failed to read DPCD register 0x%x\n", 4011 DP_PCON_DSC_ENCODER); 4012 4013 drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n", 4014 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); 4015 } 4016 4017 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) 4018 { 4019 static const int bw_gbps[] = {9, 18, 24, 32, 40, 48}; 4020 int i; 4021 4022 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { 4023 if (frl_bw_mask & (1 << i)) 4024 return bw_gbps[i]; 4025 } 4026 return 0; 4027 } 4028 4029 static int intel_dp_pcon_set_frl_mask(int max_frl) 4030 { 4031 switch (max_frl) { 4032 case 48: 4033 return DP_PCON_FRL_BW_MASK_48GBPS; 4034 case 40: 4035 return DP_PCON_FRL_BW_MASK_40GBPS; 4036 case 32: 4037 return DP_PCON_FRL_BW_MASK_32GBPS; 4038 case 24: 4039 return DP_PCON_FRL_BW_MASK_24GBPS; 4040 case 18: 4041 return DP_PCON_FRL_BW_MASK_18GBPS; 4042 case 9: 4043 return DP_PCON_FRL_BW_MASK_9GBPS; 4044 } 4045 4046 return 0; 4047 } 4048 4049 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) 4050 { 4051 struct intel_connector *connector = intel_dp->attached_connector; 4052 const struct drm_display_info *info = &connector->base.display_info; 4053 int max_frl_rate; 4054 int max_lanes, rate_per_lane; 4055 int max_dsc_lanes, dsc_rate_per_lane; 4056 4057 max_lanes = info->hdmi.max_lanes; 4058 rate_per_lane = info->hdmi.max_frl_rate_per_lane; 4059 max_frl_rate = max_lanes * rate_per_lane; 4060 4061 if (info->hdmi.dsc_cap.v_1p2) { 4062 max_dsc_lanes = info->hdmi.dsc_cap.max_lanes; 4063 dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane; 4064 if (max_dsc_lanes && dsc_rate_per_lane) 4065 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane); 4066 } 4067 4068 return max_frl_rate; 4069 } 4070 4071 static bool 4072 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp, 4073 u8 max_frl_bw_mask, u8 *frl_trained_mask) 4074 { 4075 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) && 4076 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL && 4077 *frl_trained_mask >= max_frl_bw_mask) 4078 return true; 4079 4080 return false; 4081 } 4082 4083 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) 4084 { 4085 struct intel_display *display = to_intel_display(intel_dp); 4086 #define TIMEOUT_FRL_READY_MS 500 4087 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 4088 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret; 4089 u8 max_frl_bw_mask = 0, frl_trained_mask; 4090 bool is_active; 4091 4092 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 4093 drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); 4094 4095 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp); 4096 drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n", 4097 max_edid_frl_bw); 4098 4099 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw); 4100 4101 if (max_frl_bw <= 0) 4102 return -EINVAL; 4103 4104 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); 4105 drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask); 4106 4107 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask)) 4108 goto frl_trained; 4109 4110 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); 4111 if (ret < 0) 4112 return ret; 4113 /* Wait for PCON to be FRL Ready */ 4114 ret = poll_timeout_us(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux), 4115 is_active, 4116 1000, TIMEOUT_FRL_READY_MS * 1000, false); 4117 if (ret) 4118 return ret; 4119 4120 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, 4121 DP_PCON_ENABLE_SEQUENTIAL_LINK); 4122 if (ret < 0) 4123 return ret; 4124 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, 4125 DP_PCON_FRL_LINK_TRAIN_NORMAL); 4126 if (ret < 0) 4127 return ret; 4128 ret = drm_dp_pcon_frl_enable(&intel_dp->aux); 4129 if (ret < 0) 4130 return ret; 4131 /* 4132 * Wait for FRL to be completed 4133 * Check if the HDMI Link is up and active. 4134 */ 4135 ret = poll_timeout_us(is_active = intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask), 4136 is_active, 4137 1000, TIMEOUT_HDMI_LINK_ACTIVE_MS * 1000, false); 4138 if (ret) 4139 return ret; 4140 4141 frl_trained: 4142 drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask); 4143 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); 4144 intel_dp->frl.is_trained = true; 4145 drm_dbg(display->drm, "FRL trained with : %d Gbps\n", 4146 intel_dp->frl.trained_rate_gbps); 4147 4148 return 0; 4149 } 4150 4151 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) 4152 { 4153 if (drm_dp_is_branch(intel_dp->dpcd) && 4154 intel_dp_has_hdmi_sink(intel_dp) && 4155 intel_dp_hdmi_sink_max_frl(intel_dp) > 0) 4156 return true; 4157 4158 return false; 4159 } 4160 4161 static 4162 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp) 4163 { 4164 int ret; 4165 u8 buf = 0; 4166 4167 /* Set PCON source control mode */ 4168 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE; 4169 4170 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 4171 if (ret < 0) 4172 return ret; 4173 4174 /* Set HDMI LINK ENABLE */ 4175 buf |= DP_PCON_ENABLE_HDMI_LINK; 4176 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 4177 if (ret < 0) 4178 return ret; 4179 4180 return 0; 4181 } 4182 4183 void intel_dp_check_frl_training(struct intel_dp *intel_dp) 4184 { 4185 struct intel_display *display = to_intel_display(intel_dp); 4186 4187 /* 4188 * Always go for FRL training if: 4189 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) 4190 * -sink is HDMI2.1 4191 */ 4192 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || 4193 !intel_dp_is_hdmi_2_1_sink(intel_dp) || 4194 intel_dp->frl.is_trained) 4195 return; 4196 4197 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) { 4198 int ret, mode; 4199 4200 drm_dbg(display->drm, 4201 "Couldn't set FRL mode, continuing with TMDS mode\n"); 4202 ret = intel_dp_pcon_set_tmds_mode(intel_dp); 4203 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); 4204 4205 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS) 4206 drm_dbg(display->drm, 4207 "Issue with PCON, cannot set TMDS mode\n"); 4208 } else { 4209 drm_dbg(display->drm, "FRL training Completed\n"); 4210 } 4211 } 4212 4213 static int 4214 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state) 4215 { 4216 int vactive = crtc_state->hw.adjusted_mode.vdisplay; 4217 4218 return intel_hdmi_dsc_get_slice_height(vactive); 4219 } 4220 4221 static int 4222 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, 4223 const struct intel_crtc_state *crtc_state) 4224 { 4225 struct intel_connector *connector = intel_dp->attached_connector; 4226 const struct drm_display_info *info = &connector->base.display_info; 4227 int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice; 4228 int hdmi_max_slices = info->hdmi.dsc_cap.max_slices; 4229 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); 4230 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); 4231 4232 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, 4233 pcon_max_slice_width, 4234 hdmi_max_slices, hdmi_throughput); 4235 } 4236 4237 static int 4238 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, 4239 const struct intel_crtc_state *crtc_state, 4240 int num_slices, int slice_width) 4241 { 4242 struct intel_connector *connector = intel_dp->attached_connector; 4243 const struct drm_display_info *info = &connector->base.display_info; 4244 int output_format = crtc_state->output_format; 4245 bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp; 4246 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); 4247 int hdmi_max_chunk_bytes = 4248 info->hdmi.dsc_cap.total_chunk_kbytes * 1024; 4249 4250 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, 4251 num_slices, output_format, hdmi_all_bpp, 4252 hdmi_max_chunk_bytes); 4253 } 4254 4255 void 4256 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 4257 const struct intel_crtc_state *crtc_state) 4258 { 4259 struct intel_display *display = to_intel_display(intel_dp); 4260 struct intel_connector *connector = intel_dp->attached_connector; 4261 const struct drm_display_info *info; 4262 u8 pps_param[6]; 4263 int slice_height; 4264 int slice_width; 4265 int num_slices; 4266 int bits_per_pixel; 4267 int ret; 4268 bool hdmi_is_dsc_1_2; 4269 4270 if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) 4271 return; 4272 4273 if (!connector) 4274 return; 4275 4276 info = &connector->base.display_info; 4277 4278 hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2; 4279 4280 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || 4281 !hdmi_is_dsc_1_2) 4282 return; 4283 4284 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); 4285 if (!slice_height) 4286 return; 4287 4288 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); 4289 if (!num_slices) 4290 return; 4291 4292 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, 4293 num_slices); 4294 4295 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, 4296 num_slices, slice_width); 4297 if (!bits_per_pixel) 4298 return; 4299 4300 pps_param[0] = slice_height & 0xFF; 4301 pps_param[1] = slice_height >> 8; 4302 pps_param[2] = slice_width & 0xFF; 4303 pps_param[3] = slice_width >> 8; 4304 pps_param[4] = bits_per_pixel & 0xFF; 4305 pps_param[5] = (bits_per_pixel >> 8) & 0x3; 4306 4307 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); 4308 if (ret < 0) 4309 drm_dbg_kms(display->drm, "Failed to set pcon DSC\n"); 4310 } 4311 4312 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 4313 const struct intel_crtc_state *crtc_state) 4314 { 4315 struct intel_display *display = to_intel_display(intel_dp); 4316 bool ycbcr444_to_420 = false; 4317 bool rgb_to_ycbcr = false; 4318 u8 tmp; 4319 4320 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) 4321 return; 4322 4323 if (!drm_dp_is_branch(intel_dp->dpcd)) 4324 return; 4325 4326 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0; 4327 4328 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4329 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) 4330 drm_dbg_kms(display->drm, 4331 "Failed to %s protocol converter HDMI mode\n", 4332 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp))); 4333 4334 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 4335 switch (crtc_state->output_format) { 4336 case INTEL_OUTPUT_FORMAT_YCBCR420: 4337 break; 4338 case INTEL_OUTPUT_FORMAT_YCBCR444: 4339 ycbcr444_to_420 = true; 4340 break; 4341 case INTEL_OUTPUT_FORMAT_RGB: 4342 rgb_to_ycbcr = true; 4343 ycbcr444_to_420 = true; 4344 break; 4345 default: 4346 MISSING_CASE(crtc_state->output_format); 4347 break; 4348 } 4349 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 4350 switch (crtc_state->output_format) { 4351 case INTEL_OUTPUT_FORMAT_YCBCR444: 4352 break; 4353 case INTEL_OUTPUT_FORMAT_RGB: 4354 rgb_to_ycbcr = true; 4355 break; 4356 default: 4357 MISSING_CASE(crtc_state->output_format); 4358 break; 4359 } 4360 } 4361 4362 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; 4363 4364 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4365 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) 4366 drm_dbg_kms(display->drm, 4367 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", 4368 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); 4369 4370 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; 4371 4372 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) 4373 drm_dbg_kms(display->drm, 4374 "Failed to %s protocol converter RGB->YCbCr conversion mode\n", 4375 str_enable_disable(tmp)); 4376 } 4377 4378 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) 4379 { 4380 u8 dprx = 0; 4381 4382 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 4383 &dprx) != 1) 4384 return false; 4385 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; 4386 } 4387 4388 static int intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, 4389 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 4390 { 4391 int ret; 4392 4393 ret = drm_dp_dpcd_read_data(aux, DP_DSC_SUPPORT, dsc_dpcd, 4394 DP_DSC_RECEIVER_CAP_SIZE); 4395 if (ret) { 4396 drm_dbg_kms(aux->drm_dev, 4397 "Could not read DSC DPCD register 0x%x Error: %pe\n", 4398 DP_DSC_SUPPORT, ERR_PTR(ret)); 4399 return ret; 4400 } 4401 4402 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", 4403 DP_DSC_RECEIVER_CAP_SIZE, 4404 dsc_dpcd); 4405 return 0; 4406 } 4407 4408 static void init_dsc_overall_throughput_limits(struct intel_connector *connector, bool is_branch) 4409 { 4410 u8 branch_caps[DP_DSC_BRANCH_CAP_SIZE]; 4411 int line_width; 4412 4413 connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 = INT_MAX; 4414 connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 = INT_MAX; 4415 connector->dp.dsc_branch_caps.max_line_width = INT_MAX; 4416 4417 if (!is_branch) 4418 return; 4419 4420 if (drm_dp_dpcd_read_data(connector->dp.dsc_decompression_aux, 4421 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, branch_caps, 4422 sizeof(branch_caps)) != 0) 4423 return; 4424 4425 connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 = 4426 drm_dp_dsc_branch_max_overall_throughput(branch_caps, true) ? : INT_MAX; 4427 4428 connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 = 4429 drm_dp_dsc_branch_max_overall_throughput(branch_caps, false) ? : INT_MAX; 4430 4431 line_width = drm_dp_dsc_branch_max_line_width(branch_caps); 4432 connector->dp.dsc_branch_caps.max_line_width = line_width > 0 ? line_width : INT_MAX; 4433 } 4434 4435 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, 4436 const struct drm_dp_desc *desc, bool is_branch, 4437 struct intel_connector *connector) 4438 { 4439 struct intel_display *display = to_intel_display(connector); 4440 4441 /* 4442 * Clear the cached register set to avoid using stale values 4443 * for the sinks that do not support DSC. 4444 */ 4445 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 4446 4447 /* Clear fec_capable to avoid using stale values */ 4448 connector->dp.fec_capability = 0; 4449 4450 memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps)); 4451 connector->dp.dsc_throughput_quirk = false; 4452 4453 if (dpcd_rev < DP_DPCD_REV_14) 4454 return; 4455 4456 if (intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, 4457 connector->dp.dsc_dpcd) < 0) 4458 return; 4459 4460 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, 4461 &connector->dp.fec_capability) < 0) { 4462 drm_dbg_kms(display->drm, "Could not read FEC DPCD register\n"); 4463 return; 4464 } 4465 4466 drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n", 4467 connector->dp.fec_capability); 4468 4469 if (!(connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)) 4470 return; 4471 4472 init_dsc_overall_throughput_limits(connector, is_branch); 4473 4474 /* 4475 * TODO: Move the HW rev check as well to the DRM core quirk table if 4476 * that's required after clarifying the list of affected devices. 4477 */ 4478 if (drm_dp_has_quirk(desc, DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) && 4479 desc->ident.hw_rev == 0x10) 4480 connector->dp.dsc_throughput_quirk = true; 4481 } 4482 4483 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) 4484 { 4485 if (edp_dpcd_rev < DP_EDP_14) 4486 return; 4487 4488 if (intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, 4489 connector->dp.dsc_dpcd) < 0) 4490 return; 4491 4492 if (connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED) 4493 init_dsc_overall_throughput_limits(connector, false); 4494 } 4495 4496 static void 4497 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) 4498 { 4499 struct intel_display *display = to_intel_display(intel_dp); 4500 4501 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ 4502 if (!HAS_DSC(display)) 4503 return; 4504 4505 if (intel_dp_is_edp(intel_dp)) 4506 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], 4507 connector); 4508 else 4509 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], 4510 &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd), 4511 connector); 4512 } 4513 4514 static void intel_edp_mso_mode_fixup(struct intel_connector *connector, 4515 struct drm_display_mode *mode) 4516 { 4517 struct intel_display *display = to_intel_display(connector); 4518 struct intel_dp *intel_dp = intel_attached_dp(connector); 4519 int n = intel_dp->mso_link_count; 4520 int overlap = intel_dp->mso_pixel_overlap; 4521 4522 if (!mode || !n) 4523 return; 4524 4525 mode->hdisplay = (mode->hdisplay - overlap) * n; 4526 mode->hsync_start = (mode->hsync_start - overlap) * n; 4527 mode->hsync_end = (mode->hsync_end - overlap) * n; 4528 mode->htotal = (mode->htotal - overlap) * n; 4529 mode->clock *= n; 4530 4531 drm_mode_set_name(mode); 4532 4533 drm_dbg_kms(display->drm, 4534 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n", 4535 connector->base.base.id, connector->base.name, 4536 DRM_MODE_ARG(mode)); 4537 } 4538 4539 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) 4540 { 4541 struct intel_display *display = to_intel_display(encoder); 4542 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4543 struct intel_connector *connector = intel_dp->attached_connector; 4544 4545 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { 4546 /* 4547 * This is a big fat ugly hack. 4548 * 4549 * Some machines in UEFI boot mode provide us a VBT that has 18 4550 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4551 * unknown we fail to light up. Yet the same BIOS boots up with 4552 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4553 * max, not what it tells us to use. 4554 * 4555 * Note: This will still be broken if the eDP panel is not lit 4556 * up by the BIOS, and thus we can't get the mode at module 4557 * load. 4558 */ 4559 drm_dbg_kms(display->drm, 4560 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4561 pipe_bpp, connector->panel.vbt.edp.bpp); 4562 connector->panel.vbt.edp.bpp = pipe_bpp; 4563 } 4564 } 4565 4566 static void intel_edp_mso_init(struct intel_dp *intel_dp) 4567 { 4568 struct intel_display *display = to_intel_display(intel_dp); 4569 struct intel_connector *connector = intel_dp->attached_connector; 4570 struct drm_display_info *info = &connector->base.display_info; 4571 u8 mso; 4572 4573 if (intel_dp->edp_dpcd[0] < DP_EDP_14) 4574 return; 4575 4576 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { 4577 drm_err(display->drm, "Failed to read MSO cap\n"); 4578 return; 4579 } 4580 4581 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ 4582 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; 4583 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { 4584 drm_err(display->drm, "Invalid MSO link count cap %u\n", mso); 4585 mso = 0; 4586 } 4587 4588 if (mso) { 4589 drm_dbg_kms(display->drm, 4590 "Sink MSO %ux%u configuration, pixel overlap %u\n", 4591 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, 4592 info->mso_pixel_overlap); 4593 if (!HAS_MSO(display)) { 4594 drm_err(display->drm, 4595 "No source MSO support, disabling\n"); 4596 mso = 0; 4597 } 4598 } 4599 4600 intel_dp->mso_link_count = mso; 4601 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; 4602 } 4603 4604 static void 4605 intel_edp_set_data_override_rates(struct intel_dp *intel_dp) 4606 { 4607 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4608 int *sink_rates = intel_dp->sink_rates; 4609 int i, count = 0; 4610 4611 for (i = 0; i < intel_dp->num_sink_rates; i++) { 4612 if (intel_bios_encoder_reject_edp_rate(encoder->devdata, 4613 intel_dp->sink_rates[i])) 4614 continue; 4615 4616 sink_rates[count++] = intel_dp->sink_rates[i]; 4617 } 4618 intel_dp->num_sink_rates = count; 4619 } 4620 4621 static void 4622 intel_edp_set_sink_rates(struct intel_dp *intel_dp) 4623 { 4624 struct intel_display *display = to_intel_display(intel_dp); 4625 4626 intel_dp->num_sink_rates = 0; 4627 4628 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { 4629 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 4630 int ret; 4631 int i; 4632 4633 ret = drm_dp_dpcd_read_data(&intel_dp->aux, 4634 DP_SUPPORTED_LINK_RATES, 4635 sink_rates, sizeof(sink_rates)); 4636 if (ret < 0) { 4637 drm_dbg_kms(display->drm, 4638 "Unable to read eDP supported link rates, using default rates\n"); 4639 memset(sink_rates, 0, sizeof(sink_rates)); 4640 } 4641 4642 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 4643 int rate; 4644 4645 /* Value read multiplied by 200kHz gives the per-lane 4646 * link rate in kHz. The source rates are, however, 4647 * stored in terms of LS_Clk kHz. The full conversion 4648 * back to symbols is 4649 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) 4650 */ 4651 rate = le16_to_cpu(sink_rates[i]) * 200 / 10; 4652 4653 if (rate == 0) 4654 break; 4655 4656 /* 4657 * Some platforms cannot reliably drive HBR3 rates due to PHY limitations, 4658 * even if the sink advertises support. Reject any sink rates above HBR2 on 4659 * the known machines for stable output. 4660 */ 4661 if (rate > 540000 && 4662 intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2)) 4663 break; 4664 4665 intel_dp->sink_rates[i] = rate; 4666 } 4667 intel_dp->num_sink_rates = i; 4668 } 4669 4670 /* 4671 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, 4672 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. 4673 */ 4674 if (intel_dp->num_sink_rates) 4675 intel_dp->use_rate_select = true; 4676 else 4677 intel_dp_set_sink_rates(intel_dp); 4678 4679 intel_edp_set_data_override_rates(intel_dp); 4680 } 4681 4682 static bool 4683 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 4684 { 4685 struct intel_display *display = to_intel_display(intel_dp); 4686 int ret; 4687 4688 /* this function is meant to be called only once */ 4689 drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); 4690 4691 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) 4692 return false; 4693 4694 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4695 drm_dp_is_branch(intel_dp->dpcd)); 4696 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4697 4698 intel_dp->colorimetry_support = 4699 intel_dp_get_colorimetry_status(intel_dp); 4700 4701 /* 4702 * Read the eDP display control registers. 4703 * 4704 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in 4705 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it 4706 * set, but require eDP 1.4+ detection (e.g. for supported link rates 4707 * method). The display control registers should read zero if they're 4708 * not supported anyway. 4709 */ 4710 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 4711 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 4712 sizeof(intel_dp->edp_dpcd)) { 4713 drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n", 4714 (int)sizeof(intel_dp->edp_dpcd), 4715 intel_dp->edp_dpcd); 4716 4717 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; 4718 } 4719 4720 /* 4721 * If needed, program our source OUI so we can make various Intel-specific AUX services 4722 * available (such as HDR backlight controls) 4723 */ 4724 intel_dp_init_source_oui(intel_dp); 4725 4726 /* Read the ALPM DPCD caps */ 4727 ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 4728 &intel_dp->alpm_dpcd); 4729 if (ret < 0) 4730 return false; 4731 4732 /* 4733 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 4734 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 4735 */ 4736 intel_psr_init_dpcd(intel_dp, connector); 4737 4738 intel_edp_set_sink_rates(intel_dp); 4739 intel_dp_set_max_sink_lane_count(intel_dp); 4740 4741 /* Read the eDP DSC DPCD registers */ 4742 intel_dp_detect_dsc_caps(intel_dp, connector); 4743 4744 return true; 4745 } 4746 4747 static bool 4748 intel_dp_has_sink_count(struct intel_dp *intel_dp) 4749 { 4750 if (!intel_dp->attached_connector) 4751 return false; 4752 4753 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, 4754 intel_dp->dpcd, 4755 &intel_dp->desc); 4756 } 4757 4758 void intel_dp_update_sink_caps(struct intel_dp *intel_dp) 4759 { 4760 struct intel_display *display = to_intel_display(intel_dp); 4761 4762 intel_dp_set_sink_rates(intel_dp); 4763 intel_dp_set_max_sink_lane_count(intel_dp); 4764 /* 4765 * Handle unexpected sink cap changes, or a race between setting 4766 * the deferred link params flag in the HPD IRQ handler and 4767 * clearing the flag during connector detect. 4768 */ 4769 if (intel_dp_set_common_link_params(intel_dp) && 4770 !intel_dp->reset_link_params) { 4771 drm_dbg_kms(display->drm, 4772 "DPRX capabilities changed before long HPD or RX_CAP_CHANGED signal\n"); 4773 intel_dp->reset_link_params = true; 4774 } 4775 } 4776 4777 static bool 4778 intel_dp_get_dpcd(struct intel_dp *intel_dp) 4779 { 4780 int ret; 4781 4782 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) 4783 return false; 4784 4785 /* 4786 * Don't clobber cached eDP rates. Also skip re-reading 4787 * the OUI/ID since we know it won't change. 4788 */ 4789 if (!intel_dp_is_edp(intel_dp)) { 4790 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4791 drm_dp_is_branch(intel_dp->dpcd)); 4792 4793 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4794 4795 intel_dp->colorimetry_support = 4796 intel_dp_get_colorimetry_status(intel_dp); 4797 4798 intel_dp_update_sink_caps(intel_dp); 4799 } 4800 4801 if (intel_dp_has_sink_count(intel_dp)) { 4802 ret = drm_dp_read_sink_count(&intel_dp->aux); 4803 if (ret < 0) 4804 return false; 4805 4806 /* 4807 * Sink count can change between short pulse hpd hence 4808 * a member variable in intel_dp will track any changes 4809 * between short pulse interrupts. 4810 */ 4811 intel_dp->sink_count = ret; 4812 4813 /* 4814 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 4815 * a dongle is present but no display. Unless we require to know 4816 * if a dongle is present or not, we don't need to update 4817 * downstream port information. So, an early return here saves 4818 * time from performing other operations which are not required. 4819 */ 4820 if (!intel_dp->sink_count) 4821 return false; 4822 } 4823 4824 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, 4825 intel_dp->downstream_ports) == 0; 4826 } 4827 4828 static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode) 4829 { 4830 if (mst_mode == DRM_DP_MST) 4831 return "MST"; 4832 else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG) 4833 return "SST w/ sideband messaging"; 4834 else 4835 return "SST"; 4836 } 4837 4838 static enum drm_dp_mst_mode 4839 intel_dp_mst_mode_choose(struct intel_dp *intel_dp, 4840 enum drm_dp_mst_mode sink_mst_mode) 4841 { 4842 struct intel_display *display = to_intel_display(intel_dp); 4843 4844 if (!display->params.enable_dp_mst) 4845 return DRM_DP_SST; 4846 4847 if (!intel_dp_mst_source_support(intel_dp)) 4848 return DRM_DP_SST; 4849 4850 if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG && 4851 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)) 4852 return DRM_DP_SST; 4853 4854 return sink_mst_mode; 4855 } 4856 4857 static enum drm_dp_mst_mode 4858 intel_dp_mst_detect(struct intel_dp *intel_dp) 4859 { 4860 struct intel_display *display = to_intel_display(intel_dp); 4861 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4862 enum drm_dp_mst_mode sink_mst_mode; 4863 enum drm_dp_mst_mode mst_detect; 4864 4865 sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 4866 4867 mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode); 4868 4869 drm_dbg_kms(display->drm, 4870 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n", 4871 encoder->base.base.id, encoder->base.name, 4872 str_yes_no(intel_dp_mst_source_support(intel_dp)), 4873 intel_dp_mst_mode_str(sink_mst_mode), 4874 str_yes_no(display->params.enable_dp_mst), 4875 intel_dp_mst_mode_str(mst_detect)); 4876 4877 return mst_detect; 4878 } 4879 4880 static void 4881 intel_dp_mst_configure(struct intel_dp *intel_dp) 4882 { 4883 if (!intel_dp_mst_source_support(intel_dp)) 4884 return; 4885 4886 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST; 4887 4888 if (intel_dp->is_mst) 4889 intel_dp_mst_prepare_probe(intel_dp); 4890 4891 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst); 4892 4893 /* Avoid stale info on the next detect cycle. */ 4894 intel_dp->mst_detect = DRM_DP_SST; 4895 } 4896 4897 static void 4898 intel_dp_mst_disconnect(struct intel_dp *intel_dp) 4899 { 4900 struct intel_display *display = to_intel_display(intel_dp); 4901 4902 if (!intel_dp->is_mst) 4903 return; 4904 4905 drm_dbg_kms(display->drm, 4906 "MST device may have disappeared %d vs %d\n", 4907 intel_dp->is_mst, intel_dp->mst.mgr.mst_state); 4908 intel_dp->is_mst = false; 4909 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst); 4910 } 4911 4912 #define INTEL_DP_DEVICE_SERVICE_IRQ_MASK_SST (DP_AUTOMATED_TEST_REQUEST | \ 4913 DP_CP_IRQ | \ 4914 DP_SINK_SPECIFIC_IRQ) 4915 4916 #define INTEL_DP_DEVICE_SERVICE_IRQ_MASK_MST (DP_CP_IRQ | \ 4917 DP_DOWN_REP_MSG_RDY | \ 4918 DP_UP_REQ_MSG_RDY) 4919 4920 #define INTEL_DP_LINK_SERVICE_IRQ_MASK_SST (RX_CAP_CHANGED | \ 4921 LINK_STATUS_CHANGED | \ 4922 HDMI_LINK_STATUS_CHANGED | \ 4923 CONNECTED_OFF_ENTRY_REQUESTED | \ 4924 DP_TUNNELING_IRQ) 4925 4926 #define INTEL_DP_LINK_SERVICE_IRQ_MASK_MST (RX_CAP_CHANGED | \ 4927 LINK_STATUS_CHANGED | \ 4928 DP_TUNNELING_IRQ) 4929 4930 static bool 4931 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi) 4932 { 4933 struct intel_display *display = to_intel_display(intel_dp); 4934 4935 /* 4936 * Display WA for HSD #13013007775: mtl/arl/lnl 4937 * Read the sink count and link service IRQ registers in separate 4938 * transactions to prevent disconnecting the sink on a TBT link 4939 * inadvertently. 4940 */ 4941 if (IS_DISPLAY_VER(display, 14, 20) && !display->platform.battlemage) { 4942 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 3) != 3) 4943 return false; 4944 4945 /* DP_SINK_COUNT_ESI + 3 == DP_LINK_SERVICE_IRQ_VECTOR_ESI0 */ 4946 return drm_dp_dpcd_readb(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, 4947 &esi[3]) == 1; 4948 } 4949 4950 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; 4951 } 4952 4953 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4]) 4954 { 4955 int retry; 4956 4957 for (retry = 0; retry < 3; retry++) { 4958 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1, 4959 &esi[1], 3) == 3) 4960 return true; 4961 } 4962 4963 return false; 4964 } 4965 4966 /* Return %true if reading the ESI vector succeeded, %false otherwise. */ 4967 static bool intel_dp_get_sink_irq_esi_sst(struct intel_dp *intel_dp, u8 esi[4]) 4968 { 4969 memset(esi, 0, 4); 4970 4971 /* 4972 * TODO: For DP_DPCD_REV >= 0x12 read 4973 * DP_SINK_COUNT_ESI and DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0. 4974 */ 4975 if (drm_dp_dpcd_read_data(&intel_dp->aux, DP_SINK_COUNT, esi, 2) != 0) 4976 return false; 4977 4978 if (intel_dp->dpcd[DP_DPCD_REV] < DP_DPCD_REV_12) 4979 return true; 4980 4981 /* TODO: Read DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 as well */ 4982 if (drm_dp_dpcd_read_byte(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &esi[3]) != 0) 4983 return false; 4984 4985 return true; 4986 } 4987 4988 /* Return %true if acking the ESI vector IRQ events succeeded, %false otherwise. */ 4989 static bool intel_dp_ack_sink_irq_esi_sst(struct intel_dp *intel_dp, u8 esi[4]) 4990 { 4991 /* 4992 * TODO: For DP_DPCD_REV >= 0x12 write 4993 * DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 4994 */ 4995 if (drm_dp_dpcd_write_byte(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, esi[1]) != 0) 4996 return false; 4997 4998 if (intel_dp->dpcd[DP_DPCD_REV] < DP_DPCD_REV_12) 4999 return true; 5000 5001 /* TODO: Read DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 as well */ 5002 if (drm_dp_dpcd_write_byte(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, esi[3]) != 0) 5003 return false; 5004 5005 return true; 5006 } 5007 5008 /* 5009 * Return %true if reading the ESI vector and acking the ESI IRQ events succeeded, 5010 * %false otherwise. 5011 */ 5012 static bool intel_dp_get_and_ack_sink_irq_esi_sst(struct intel_dp *intel_dp, u8 esi[4]) 5013 { 5014 struct intel_display *display = to_intel_display(intel_dp); 5015 struct intel_connector *connector = intel_dp->attached_connector; 5016 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5017 5018 if (!intel_dp_get_sink_irq_esi_sst(intel_dp, esi)) 5019 return false; 5020 5021 drm_dbg_kms(display->drm, 5022 "[CONNECTOR:%d:%s][ENCODER:%d:%s] DPRX ESI: %4ph\n", 5023 connector->base.base.id, connector->base.name, 5024 encoder->base.base.id, encoder->base.name, 5025 esi); 5026 5027 esi[1] &= INTEL_DP_DEVICE_SERVICE_IRQ_MASK_SST; 5028 esi[3] &= INTEL_DP_LINK_SERVICE_IRQ_MASK_SST; 5029 5030 if (mem_is_zero(&esi[1], 3)) 5031 return true; 5032 5033 if (!intel_dp_ack_sink_irq_esi_sst(intel_dp, esi)) 5034 return false; 5035 5036 return true; 5037 } 5038 5039 bool 5040 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 5041 const struct drm_connector_state *conn_state) 5042 { 5043 /* 5044 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 5045 * of Color Encoding Format and Content Color Gamut], in order to 5046 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. 5047 */ 5048 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 5049 return true; 5050 5051 switch (conn_state->colorspace) { 5052 case DRM_MODE_COLORIMETRY_SYCC_601: 5053 case DRM_MODE_COLORIMETRY_OPYCC_601: 5054 case DRM_MODE_COLORIMETRY_BT2020_YCC: 5055 case DRM_MODE_COLORIMETRY_BT2020_RGB: 5056 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 5057 return true; 5058 default: 5059 break; 5060 } 5061 5062 return false; 5063 } 5064 5065 static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, 5066 struct dp_sdp *sdp, size_t size) 5067 { 5068 size_t length = sizeof(struct dp_sdp); 5069 5070 if (size < length) 5071 return -ENOSPC; 5072 5073 memset(sdp, 0, size); 5074 5075 /* Prepare AS (Adaptive Sync) SDP Header */ 5076 sdp->sdp_header.HB0 = 0; 5077 sdp->sdp_header.HB1 = as_sdp->sdp_type; 5078 sdp->sdp_header.HB2 = as_sdp->revision; 5079 sdp->sdp_header.HB3 = as_sdp->length; 5080 5081 /* Fill AS (Adaptive Sync) SDP Payload */ 5082 sdp->db[0] = as_sdp->mode; 5083 sdp->db[1] = as_sdp->vtotal & 0xFF; 5084 sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF; 5085 sdp->db[3] = as_sdp->target_rr & 0xFF; 5086 sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; 5087 5088 if (as_sdp->target_rr_divider) 5089 sdp->db[4] |= 0x20; 5090 5091 sdp->db[7] = as_sdp->coasting_vtotal & 0xFF; 5092 sdp->db[8] = (as_sdp->coasting_vtotal >> 8) & 0xFF; 5093 5094 return length; 5095 } 5096 5097 static ssize_t 5098 intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display, 5099 const struct hdmi_drm_infoframe *drm_infoframe, 5100 struct dp_sdp *sdp, 5101 size_t size) 5102 { 5103 size_t length = sizeof(struct dp_sdp); 5104 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; 5105 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; 5106 ssize_t len; 5107 5108 if (size < length) 5109 return -ENOSPC; 5110 5111 memset(sdp, 0, size); 5112 5113 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); 5114 if (len < 0) { 5115 drm_dbg_kms(display->drm, 5116 "buffer size is smaller than hdr metadata infoframe\n"); 5117 return -ENOSPC; 5118 } 5119 5120 if (len != infoframe_size) { 5121 drm_dbg_kms(display->drm, "wrong static hdr metadata size\n"); 5122 return -ENOSPC; 5123 } 5124 5125 /* 5126 * Set up the infoframe sdp packet for HDR static metadata. 5127 * Prepare VSC Header for SU as per DP 1.4a spec, 5128 * Table 2-100 and Table 2-101 5129 */ 5130 5131 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ 5132 sdp->sdp_header.HB0 = 0; 5133 /* 5134 * Packet Type 80h + Non-audio INFOFRAME Type value 5135 * HDMI_INFOFRAME_TYPE_DRM: 0x87 5136 * - 80h + Non-audio INFOFRAME Type value 5137 * - InfoFrame Type: 0x07 5138 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] 5139 */ 5140 sdp->sdp_header.HB1 = drm_infoframe->type; 5141 /* 5142 * Least Significant Eight Bits of (Data Byte Count – 1) 5143 * infoframe_size - 1 5144 */ 5145 sdp->sdp_header.HB2 = 0x1D; 5146 /* INFOFRAME SDP Version Number */ 5147 sdp->sdp_header.HB3 = (0x13 << 2); 5148 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 5149 sdp->db[0] = drm_infoframe->version; 5150 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 5151 sdp->db[1] = drm_infoframe->length; 5152 /* 5153 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after 5154 * HDMI_INFOFRAME_HEADER_SIZE 5155 */ 5156 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); 5157 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], 5158 HDMI_DRM_INFOFRAME_SIZE); 5159 5160 /* 5161 * Size of DP infoframe sdp packet for HDR static metadata consists of 5162 * - DP SDP Header(struct dp_sdp_header): 4 bytes 5163 * - Two Data Blocks: 2 bytes 5164 * CTA Header Byte2 (INFOFRAME Version Number) 5165 * CTA Header Byte3 (Length of INFOFRAME) 5166 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes 5167 * 5168 * Prior to GEN11's GMP register size is identical to DP HDR static metadata 5169 * infoframe size. But GEN11+ has larger than that size, write_infoframe 5170 * will pad rest of the size. 5171 */ 5172 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; 5173 } 5174 5175 static void intel_write_dp_sdp(struct intel_encoder *encoder, 5176 const struct intel_crtc_state *crtc_state, 5177 unsigned int type) 5178 { 5179 struct intel_display *display = to_intel_display(encoder); 5180 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5181 struct dp_sdp sdp = {}; 5182 ssize_t len; 5183 5184 if ((crtc_state->infoframes.enable & 5185 intel_hdmi_infoframe_enable(type)) == 0) 5186 return; 5187 5188 switch (type) { 5189 case DP_SDP_VSC: 5190 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp); 5191 break; 5192 case HDMI_PACKET_TYPE_GAMUT_METADATA: 5193 len = intel_dp_hdr_metadata_infoframe_sdp_pack(display, 5194 &crtc_state->infoframes.drm.drm, 5195 &sdp, sizeof(sdp)); 5196 break; 5197 case DP_SDP_ADAPTIVE_SYNC: 5198 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp, 5199 sizeof(sdp)); 5200 break; 5201 default: 5202 MISSING_CASE(type); 5203 return; 5204 } 5205 5206 if (drm_WARN_ON(display->drm, len < 0)) 5207 return; 5208 5209 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); 5210 } 5211 5212 void intel_dp_set_infoframes(struct intel_encoder *encoder, 5213 bool enable, 5214 const struct intel_crtc_state *crtc_state, 5215 const struct drm_connector_state *conn_state) 5216 { 5217 struct intel_display *display = to_intel_display(encoder); 5218 intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); 5219 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 5220 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | 5221 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; 5222 5223 if (HAS_AS_SDP(display)) 5224 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL; 5225 5226 u32 val = intel_de_read(display, reg) & ~dip_enable; 5227 5228 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ 5229 if (!enable && HAS_DSC(display)) 5230 val &= ~VDIP_ENABLE_PPS; 5231 5232 /* 5233 * This routine disables VSC DIP if the function is called 5234 * to disable SDP or if it does not have PSR 5235 */ 5236 if (!enable || !crtc_state->has_psr) 5237 val &= ~VIDEO_DIP_ENABLE_VSC_HSW; 5238 5239 intel_de_write(display, reg, val); 5240 intel_de_posting_read(display, reg); 5241 5242 if (!enable) 5243 return; 5244 5245 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); 5246 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); 5247 5248 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); 5249 } 5250 5251 static 5252 int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, 5253 const void *buffer, size_t size) 5254 { 5255 const struct dp_sdp *sdp = buffer; 5256 5257 if (size < sizeof(struct dp_sdp)) 5258 return -EINVAL; 5259 5260 memset(as_sdp, 0, sizeof(*as_sdp)); 5261 5262 if (sdp->sdp_header.HB0 != 0) 5263 return -EINVAL; 5264 5265 if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC) 5266 return -EINVAL; 5267 5268 if ((sdp->sdp_header.HB3 & 0x3F) != 9) 5269 return -EINVAL; 5270 5271 as_sdp->sdp_type = sdp->sdp_header.HB1; 5272 as_sdp->length = sdp->sdp_header.HB3 & DP_AS_SDP_LENGTH_MASK; 5273 as_sdp->revision = sdp->sdp_header.HB2; 5274 as_sdp->mode = sdp->db[0] & DP_AS_SDP_OPERATION_MODE_MASK; 5275 as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; 5276 as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3]; 5277 as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; 5278 as_sdp->coasting_vtotal = (sdp->db[8] << 8) | sdp->db[7]; 5279 5280 return 0; 5281 } 5282 5283 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, 5284 const void *buffer, size_t size) 5285 { 5286 const struct dp_sdp *sdp = buffer; 5287 5288 if (size < sizeof(struct dp_sdp)) 5289 return -EINVAL; 5290 5291 memset(vsc, 0, sizeof(*vsc)); 5292 5293 if (sdp->sdp_header.HB0 != 0) 5294 return -EINVAL; 5295 5296 if (sdp->sdp_header.HB1 != DP_SDP_VSC) 5297 return -EINVAL; 5298 5299 vsc->sdp_type = sdp->sdp_header.HB1; 5300 vsc->revision = sdp->sdp_header.HB2; 5301 vsc->length = sdp->sdp_header.HB3; 5302 5303 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || 5304 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) || 5305 (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) { 5306 /* 5307 * - HB2 = 0x2, HB3 = 0x8 5308 * VSC SDP supporting 3D stereo + PSR 5309 * - HB2 = 0x4, HB3 = 0xe 5310 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of 5311 * first scan line of the SU region (applies to eDP v1.4b 5312 * and higher). 5313 * - HB2 = 0x6, HB3 = 0x10 5314 * VSC SDP supporting 3D stereo + Panel Replay. 5315 */ 5316 return 0; 5317 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { 5318 /* 5319 * - HB2 = 0x5, HB3 = 0x13 5320 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry 5321 * Format. 5322 */ 5323 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; 5324 vsc->colorimetry = sdp->db[16] & 0xf; 5325 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; 5326 5327 switch (sdp->db[17] & 0x7) { 5328 case 0x0: 5329 vsc->bpc = 6; 5330 break; 5331 case 0x1: 5332 vsc->bpc = 8; 5333 break; 5334 case 0x2: 5335 vsc->bpc = 10; 5336 break; 5337 case 0x3: 5338 vsc->bpc = 12; 5339 break; 5340 case 0x4: 5341 vsc->bpc = 16; 5342 break; 5343 default: 5344 MISSING_CASE(sdp->db[17] & 0x7); 5345 return -EINVAL; 5346 } 5347 5348 vsc->content_type = sdp->db[18] & 0x7; 5349 } else { 5350 return -EINVAL; 5351 } 5352 5353 return 0; 5354 } 5355 5356 static void 5357 intel_read_dp_as_sdp(struct intel_encoder *encoder, 5358 struct intel_crtc_state *crtc_state, 5359 struct drm_dp_as_sdp *as_sdp) 5360 { 5361 struct intel_display *display = to_intel_display(encoder); 5362 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5363 unsigned int type = DP_SDP_ADAPTIVE_SYNC; 5364 struct dp_sdp sdp = {}; 5365 int ret; 5366 5367 if ((crtc_state->infoframes.enable & 5368 intel_hdmi_infoframe_enable(type)) == 0) 5369 return; 5370 5371 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 5372 sizeof(sdp)); 5373 5374 ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp)); 5375 if (ret) 5376 drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n"); 5377 } 5378 5379 static int 5380 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, 5381 const void *buffer, size_t size) 5382 { 5383 int ret; 5384 5385 const struct dp_sdp *sdp = buffer; 5386 5387 if (size < sizeof(struct dp_sdp)) 5388 return -EINVAL; 5389 5390 if (sdp->sdp_header.HB0 != 0) 5391 return -EINVAL; 5392 5393 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) 5394 return -EINVAL; 5395 5396 /* 5397 * Least Significant Eight Bits of (Data Byte Count – 1) 5398 * 1Dh (i.e., Data Byte Count = 30 bytes). 5399 */ 5400 if (sdp->sdp_header.HB2 != 0x1D) 5401 return -EINVAL; 5402 5403 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ 5404 if ((sdp->sdp_header.HB3 & 0x3) != 0) 5405 return -EINVAL; 5406 5407 /* INFOFRAME SDP Version Number */ 5408 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) 5409 return -EINVAL; 5410 5411 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 5412 if (sdp->db[0] != 1) 5413 return -EINVAL; 5414 5415 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 5416 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) 5417 return -EINVAL; 5418 5419 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], 5420 HDMI_DRM_INFOFRAME_SIZE); 5421 5422 return ret; 5423 } 5424 5425 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, 5426 struct intel_crtc_state *crtc_state, 5427 struct drm_dp_vsc_sdp *vsc) 5428 { 5429 struct intel_display *display = to_intel_display(encoder); 5430 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5431 unsigned int type = DP_SDP_VSC; 5432 struct dp_sdp sdp = {}; 5433 int ret; 5434 5435 if ((crtc_state->infoframes.enable & 5436 intel_hdmi_infoframe_enable(type)) == 0) 5437 return; 5438 5439 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); 5440 5441 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); 5442 5443 if (ret) 5444 drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n"); 5445 } 5446 5447 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, 5448 struct intel_crtc_state *crtc_state, 5449 struct hdmi_drm_infoframe *drm_infoframe) 5450 { 5451 struct intel_display *display = to_intel_display(encoder); 5452 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5453 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; 5454 struct dp_sdp sdp = {}; 5455 int ret; 5456 5457 if ((crtc_state->infoframes.enable & 5458 intel_hdmi_infoframe_enable(type)) == 0) 5459 return; 5460 5461 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 5462 sizeof(sdp)); 5463 5464 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, 5465 sizeof(sdp)); 5466 5467 if (ret) 5468 drm_dbg_kms(display->drm, 5469 "Failed to unpack DP HDR Metadata Infoframe SDP\n"); 5470 } 5471 5472 void intel_read_dp_sdp(struct intel_encoder *encoder, 5473 struct intel_crtc_state *crtc_state, 5474 unsigned int type) 5475 { 5476 switch (type) { 5477 case DP_SDP_VSC: 5478 intel_read_dp_vsc_sdp(encoder, crtc_state, 5479 &crtc_state->infoframes.vsc); 5480 break; 5481 case HDMI_PACKET_TYPE_GAMUT_METADATA: 5482 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, 5483 &crtc_state->infoframes.drm.drm); 5484 break; 5485 case DP_SDP_ADAPTIVE_SYNC: 5486 intel_read_dp_as_sdp(encoder, crtc_state, 5487 &crtc_state->infoframes.as_sdp); 5488 break; 5489 default: 5490 MISSING_CASE(type); 5491 break; 5492 } 5493 } 5494 5495 static void 5496 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) 5497 { 5498 bool handled = false; 5499 5500 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst.mgr, esi, ack, &handled); 5501 5502 if (esi[1] & DP_CP_IRQ) { 5503 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5504 ack[1] |= DP_CP_IRQ; 5505 } 5506 } 5507 5508 static bool intel_dp_handle_link_service_irq(struct intel_dp *intel_dp, u8 irq_mask); 5509 5510 /** 5511 * intel_dp_check_mst_status - service any pending MST interrupts, check link status 5512 * @intel_dp: Intel DP struct 5513 * 5514 * Read any pending MST interrupts, call MST core to handle these and ack the 5515 * interrupts. Check if the main and AUX link state is ok. 5516 * 5517 * Returns: 5518 * - %true if pending interrupts were serviced (or no interrupts were 5519 * pending) w/o detecting an error condition. 5520 * - %false if an error condition - like AUX failure or a loss of link - is 5521 * detected, or another condition - like a DP tunnel BW state change - needs 5522 * servicing from the hotplug work. 5523 */ 5524 static bool 5525 intel_dp_check_mst_status(struct intel_dp *intel_dp) 5526 { 5527 struct intel_display *display = to_intel_display(intel_dp); 5528 bool force_retrain = intel_dp_link_training_get_force_retrain(intel_dp->link.training); 5529 bool reprobe_needed = false; 5530 int tries = 33; 5531 5532 while (--tries) { 5533 u8 esi[4] = {}; 5534 u8 ack[4] = {}; 5535 bool new_irqs; 5536 5537 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { 5538 drm_dbg_kms(display->drm, 5539 "failed to get ESI - device may have failed\n"); 5540 reprobe_needed = true; 5541 5542 break; 5543 } 5544 5545 drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi); 5546 5547 ack[3] |= esi[3] & INTEL_DP_LINK_SERVICE_IRQ_MASK_MST; 5548 5549 intel_dp_mst_hpd_irq(intel_dp, esi, ack); 5550 5551 new_irqs = !mem_is_zero(ack, sizeof(ack)); 5552 5553 drm_WARN_ON(display->drm, ack[1] & ~INTEL_DP_DEVICE_SERVICE_IRQ_MASK_MST); 5554 drm_WARN_ON(display->drm, ack[3] & ~INTEL_DP_LINK_SERVICE_IRQ_MASK_MST); 5555 5556 if (new_irqs && !intel_dp_ack_sink_irq_esi(intel_dp, ack)) 5557 drm_dbg_kms(display->drm, "Failed to ack ESI\n"); 5558 5559 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY)) 5560 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst.mgr); 5561 5562 if (force_retrain) { 5563 /* Defer forced retraining to the regular link status check. */ 5564 ack[3] |= LINK_STATUS_CHANGED; 5565 force_retrain = false; 5566 } 5567 5568 if (intel_dp_handle_link_service_irq(intel_dp, ack[3])) 5569 reprobe_needed = true; 5570 5571 if (!new_irqs) 5572 break; 5573 } 5574 5575 if (!tries) { 5576 drm_dbg_kms(display->drm, "DPRX ESI not clearing, device may be stuck\n"); 5577 reprobe_needed = true; 5578 } 5579 5580 return !reprobe_needed; 5581 } 5582 5583 static void 5584 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) 5585 { 5586 bool is_active; 5587 u8 buf = 0; 5588 5589 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); 5590 if (intel_dp->frl.is_trained && !is_active) { 5591 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) 5592 return; 5593 5594 buf &= ~DP_PCON_ENABLE_HDMI_LINK; 5595 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) 5596 return; 5597 5598 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); 5599 5600 intel_dp->frl.is_trained = false; 5601 5602 /* Restart FRL training or fall back to TMDS mode */ 5603 intel_dp_check_frl_training(intel_dp); 5604 } 5605 } 5606 5607 bool intel_dp_has_connector(struct intel_dp *intel_dp, 5608 const struct drm_connector_state *conn_state) 5609 { 5610 struct intel_display *display = to_intel_display(intel_dp); 5611 struct intel_encoder *encoder; 5612 enum pipe pipe; 5613 5614 if (!conn_state->best_encoder) 5615 return false; 5616 5617 /* SST */ 5618 encoder = &dp_to_dig_port(intel_dp)->base; 5619 if (conn_state->best_encoder == &encoder->base) 5620 return true; 5621 5622 /* MST */ 5623 for_each_pipe(display, pipe) { 5624 encoder = &intel_dp->mst.stream_encoders[pipe]->base; 5625 if (conn_state->best_encoder == &encoder->base) 5626 return true; 5627 } 5628 5629 return false; 5630 } 5631 5632 static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state) 5633 { 5634 struct intel_connector *connector = to_intel_connector(conn_state->connector); 5635 struct intel_display *display = to_intel_display(connector); 5636 5637 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); 5638 5639 if (!conn_state->commit) 5640 return; 5641 5642 drm_WARN_ON(display->drm, 5643 !wait_for_completion_timeout(&conn_state->commit->hw_done, 5644 msecs_to_jiffies(5000))); 5645 } 5646 5647 int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 5648 struct drm_modeset_acquire_ctx *ctx, 5649 u8 *pipe_mask) 5650 { 5651 struct intel_display *display = to_intel_display(intel_dp); 5652 struct drm_connector_list_iter conn_iter; 5653 struct intel_connector *connector; 5654 int ret = 0; 5655 5656 *pipe_mask = 0; 5657 5658 drm_connector_list_iter_begin(display->drm, &conn_iter); 5659 for_each_intel_connector_iter(connector, &conn_iter) { 5660 struct drm_connector_state *conn_state = 5661 connector->base.state; 5662 struct intel_crtc_state *crtc_state; 5663 struct intel_crtc *crtc; 5664 5665 if (!intel_dp_has_connector(intel_dp, conn_state)) 5666 continue; 5667 5668 crtc = to_intel_crtc(conn_state->crtc); 5669 if (!crtc) 5670 continue; 5671 5672 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 5673 if (ret) 5674 break; 5675 5676 crtc_state = to_intel_crtc_state(crtc->base.state); 5677 5678 drm_WARN_ON(display->drm, 5679 !intel_crtc_has_dp_encoder(crtc_state)); 5680 5681 if (!crtc_state->hw.active) 5682 continue; 5683 5684 wait_for_connector_hw_done(conn_state); 5685 5686 *pipe_mask |= BIT(crtc->pipe); 5687 } 5688 drm_connector_list_iter_end(&conn_iter); 5689 5690 return ret; 5691 } 5692 5693 void intel_dp_flush_connector_commits(struct intel_connector *connector) 5694 { 5695 wait_for_connector_hw_done(connector->base.state); 5696 } 5697 5698 static void intel_dp_handle_device_service_irq(struct intel_dp *intel_dp, u8 irq_mask) 5699 { 5700 struct intel_display *display = to_intel_display(intel_dp); 5701 5702 drm_WARN_ON(display->drm, irq_mask & ~INTEL_DP_DEVICE_SERVICE_IRQ_MASK_SST); 5703 5704 if (irq_mask & DP_AUTOMATED_TEST_REQUEST) 5705 intel_dp_test_request(intel_dp); 5706 5707 if (irq_mask & DP_CP_IRQ) 5708 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5709 5710 if (irq_mask & DP_SINK_SPECIFIC_IRQ) 5711 drm_dbg_kms(display->drm, "Sink specific irq unhandled\n"); 5712 } 5713 5714 5715 /* 5716 * Return %true if a full connector reprobe is required after handling a link 5717 * service IRQ event. 5718 */ 5719 static bool intel_dp_handle_link_service_irq(struct intel_dp *intel_dp, u8 irq_mask) 5720 { 5721 struct intel_display *display = to_intel_display(intel_dp); 5722 struct intel_connector *connector = intel_dp->attached_connector; 5723 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5724 bool reprobe_needed = false; 5725 5726 drm_WARN_ON(display->drm, irq_mask & ~(INTEL_DP_LINK_SERVICE_IRQ_MASK_SST | 5727 INTEL_DP_LINK_SERVICE_IRQ_MASK_MST)); 5728 5729 if (irq_mask & RX_CAP_CHANGED) { 5730 intel_dp->reset_link_params = true; 5731 reprobe_needed = true; 5732 } 5733 5734 if (irq_mask & LINK_STATUS_CHANGED) 5735 intel_dp_check_link_state(intel_dp); 5736 5737 if (irq_mask & HDMI_LINK_STATUS_CHANGED) 5738 intel_dp_handle_hdmi_link_status_change(intel_dp); 5739 5740 if (irq_mask & CONNECTED_OFF_ENTRY_REQUESTED) 5741 drm_dbg_kms(display->drm, 5742 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Allowing connected off request\n", 5743 connector->base.base.id, connector->base.name, 5744 encoder->base.base.id, encoder->base.name); 5745 5746 if ((irq_mask & DP_TUNNELING_IRQ) && 5747 drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr, 5748 &intel_dp->aux)) 5749 reprobe_needed = true; 5750 5751 return reprobe_needed; 5752 } 5753 5754 /* 5755 * According to DP spec 5756 * 5.1.2: 5757 * 1. Read DPCD 5758 * 2. Configure link according to Receiver Capabilities 5759 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 5760 * 4. Check link status on receipt of hot-plug interrupt 5761 * 5762 * intel_dp_short_pulse - handles short pulse interrupts 5763 * when full detection is not required. 5764 * Returns %true if short pulse is handled and full detection 5765 * is NOT required and %false otherwise. 5766 */ 5767 static bool 5768 intel_dp_short_pulse(struct intel_dp *intel_dp) 5769 { 5770 bool reprobe_needed = false; 5771 u8 esi[4] = {}; 5772 5773 intel_dp_test_reset(intel_dp); 5774 5775 if (!intel_dp_get_and_ack_sink_irq_esi_sst(intel_dp, esi)) 5776 return false; 5777 5778 /* 5779 * If the current value of sink count doesn't match with 5780 * the value that was stored earlier we need to do full 5781 * detection. 5782 */ 5783 if (intel_dp_has_sink_count(intel_dp) && 5784 DP_GET_SINK_COUNT(esi[0]) != intel_dp->sink_count) 5785 /* No need to proceed if we are going to do full detect */ 5786 return false; 5787 5788 intel_dp_handle_device_service_irq(intel_dp, esi[1]); 5789 5790 /* 5791 * Force checking the link status for DPCD_REV < 1.2 5792 * TODO: let the link status check depend on LINK_STATUS_CHANGED 5793 * or intel_dp->link.training.force_retrain for DPCD_REV >= 1.2 5794 */ 5795 esi[3] |= LINK_STATUS_CHANGED; 5796 if (intel_dp_handle_link_service_irq(intel_dp, esi[3])) 5797 reprobe_needed = true; 5798 5799 /* Handle CEC interrupts, if any */ 5800 drm_dp_cec_irq(&intel_dp->aux); 5801 5802 if (READ_ONCE(intel_dp->downstream_port_changed)) { 5803 WRITE_ONCE(intel_dp->downstream_port_changed, false); 5804 reprobe_needed = true; 5805 } 5806 5807 intel_psr_short_pulse(intel_dp); 5808 5809 if (intel_alpm_get_error(intel_dp)) { 5810 intel_alpm_disable(intel_dp); 5811 intel_dp->alpm.sink_alpm_error = true; 5812 } 5813 5814 if (intel_dp_test_short_pulse(intel_dp)) 5815 reprobe_needed = true; 5816 5817 return !reprobe_needed; 5818 } 5819 5820 /* XXX this is probably wrong for multiple downstream ports */ 5821 static enum drm_connector_status 5822 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 5823 { 5824 struct intel_display *display = to_intel_display(intel_dp); 5825 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5826 u8 *dpcd = intel_dp->dpcd; 5827 u8 type; 5828 5829 if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp))) 5830 return connector_status_connected; 5831 5832 WRITE_ONCE(intel_dp->downstream_port_changed, false); 5833 5834 intel_lspcon_resume(dig_port); 5835 5836 if (!intel_dp_get_dpcd(intel_dp)) 5837 return connector_status_disconnected; 5838 5839 intel_dp->mst_detect = intel_dp_mst_detect(intel_dp); 5840 5841 /* if there's no downstream port, we're done */ 5842 if (!drm_dp_is_branch(dpcd)) 5843 return connector_status_connected; 5844 5845 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 5846 if (intel_dp_has_sink_count(intel_dp) && 5847 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 5848 return intel_dp->sink_count ? 5849 connector_status_connected : connector_status_disconnected; 5850 } 5851 5852 if (intel_dp->mst_detect == DRM_DP_MST) 5853 return connector_status_connected; 5854 5855 /* If no HPD, poke DDC gently */ 5856 if (drm_probe_ddc(&intel_dp->aux.ddc)) 5857 return connector_status_connected; 5858 5859 /* Well we tried, say unknown for unreliable port types */ 5860 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 5861 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 5862 if (type == DP_DS_PORT_TYPE_VGA || 5863 type == DP_DS_PORT_TYPE_NON_EDID) 5864 return connector_status_unknown; 5865 } else { 5866 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 5867 DP_DWN_STRM_PORT_TYPE_MASK; 5868 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 5869 type == DP_DWN_STRM_PORT_TYPE_OTHER) 5870 return connector_status_unknown; 5871 } 5872 5873 /* Anything else is out of spec, warn and ignore */ 5874 drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n"); 5875 return connector_status_disconnected; 5876 } 5877 5878 static enum drm_connector_status 5879 edp_detect(struct intel_dp *intel_dp) 5880 { 5881 return connector_status_connected; 5882 } 5883 5884 void intel_digital_port_lock(struct intel_encoder *encoder) 5885 { 5886 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5887 5888 if (dig_port->lock) 5889 dig_port->lock(dig_port); 5890 } 5891 5892 void intel_digital_port_unlock(struct intel_encoder *encoder) 5893 { 5894 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5895 5896 if (dig_port->unlock) 5897 dig_port->unlock(dig_port); 5898 } 5899 5900 /* 5901 * intel_digital_port_connected_locked - is the specified port connected? 5902 * @encoder: intel_encoder 5903 * 5904 * In cases where there's a connector physically connected but it can't be used 5905 * by our hardware we also return false, since the rest of the driver should 5906 * pretty much treat the port as disconnected. This is relevant for type-C 5907 * (starting on ICL) where there's ownership involved. 5908 * 5909 * The caller must hold the lock acquired by calling intel_digital_port_lock() 5910 * when calling this function. 5911 * 5912 * Return %true if port is connected, %false otherwise. 5913 */ 5914 bool intel_digital_port_connected_locked(struct intel_encoder *encoder) 5915 { 5916 struct intel_display *display = to_intel_display(encoder); 5917 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5918 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); 5919 bool is_connected = false; 5920 5921 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) { 5922 poll_timeout_us(is_connected = dig_port->connected(encoder), 5923 is_connected || is_glitch_free, 5924 30, 4000, false); 5925 } 5926 5927 return is_connected; 5928 } 5929 5930 bool intel_digital_port_connected(struct intel_encoder *encoder) 5931 { 5932 bool ret; 5933 5934 intel_digital_port_lock(encoder); 5935 ret = intel_digital_port_connected_locked(encoder); 5936 intel_digital_port_unlock(encoder); 5937 5938 return ret; 5939 } 5940 5941 static const struct drm_edid * 5942 intel_dp_get_edid(struct intel_dp *intel_dp) 5943 { 5944 struct intel_connector *connector = intel_dp->attached_connector; 5945 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 5946 5947 /* Use panel fixed edid if we have one */ 5948 if (fixed_edid) { 5949 /* invalid edid */ 5950 if (IS_ERR(fixed_edid)) 5951 return NULL; 5952 5953 return drm_edid_dup(fixed_edid); 5954 } 5955 5956 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc); 5957 } 5958 5959 static void 5960 intel_dp_update_dfp(struct intel_dp *intel_dp, 5961 const struct drm_edid *drm_edid) 5962 { 5963 struct intel_display *display = to_intel_display(intel_dp); 5964 struct intel_connector *connector = intel_dp->attached_connector; 5965 5966 intel_dp->dfp.max_bpc = 5967 drm_dp_downstream_max_bpc(intel_dp->dpcd, 5968 intel_dp->downstream_ports, drm_edid); 5969 5970 intel_dp->dfp.max_dotclock = 5971 drm_dp_downstream_max_dotclock(intel_dp->dpcd, 5972 intel_dp->downstream_ports); 5973 5974 intel_dp->dfp.min_tmds_clock = 5975 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, 5976 intel_dp->downstream_ports, 5977 drm_edid); 5978 intel_dp->dfp.max_tmds_clock = 5979 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, 5980 intel_dp->downstream_ports, 5981 drm_edid); 5982 5983 intel_dp->dfp.pcon_max_frl_bw = 5984 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, 5985 intel_dp->downstream_ports); 5986 5987 drm_dbg_kms(display->drm, 5988 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", 5989 connector->base.base.id, connector->base.name, 5990 intel_dp->dfp.max_bpc, 5991 intel_dp->dfp.max_dotclock, 5992 intel_dp->dfp.min_tmds_clock, 5993 intel_dp->dfp.max_tmds_clock, 5994 intel_dp->dfp.pcon_max_frl_bw); 5995 5996 intel_dp_get_pcon_dsc_cap(intel_dp); 5997 } 5998 5999 static bool 6000 intel_dp_can_ycbcr420(struct intel_dp *intel_dp) 6001 { 6002 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) && 6003 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough)) 6004 return true; 6005 6006 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) && 6007 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 6008 return true; 6009 6010 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) && 6011 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 6012 return true; 6013 6014 return false; 6015 } 6016 6017 static void 6018 intel_dp_update_420(struct intel_dp *intel_dp) 6019 { 6020 struct intel_display *display = to_intel_display(intel_dp); 6021 struct intel_connector *connector = intel_dp->attached_connector; 6022 6023 intel_dp->dfp.ycbcr420_passthrough = 6024 drm_dp_downstream_420_passthrough(intel_dp->dpcd, 6025 intel_dp->downstream_ports); 6026 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ 6027 intel_dp->dfp.ycbcr_444_to_420 = 6028 intel_lspcon_active(dp_to_dig_port(intel_dp)) || 6029 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, 6030 intel_dp->downstream_ports); 6031 intel_dp->dfp.rgb_to_ycbcr = 6032 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, 6033 intel_dp->downstream_ports, 6034 DP_DS_HDMI_BT709_RGB_YCBCR_CONV); 6035 6036 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp); 6037 6038 drm_dbg_kms(display->drm, 6039 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", 6040 connector->base.base.id, connector->base.name, 6041 str_yes_no(intel_dp->dfp.rgb_to_ycbcr), 6042 str_yes_no(connector->base.ycbcr_420_allowed), 6043 str_yes_no(intel_dp->dfp.ycbcr_444_to_420)); 6044 } 6045 6046 static void 6047 intel_dp_set_edid(struct intel_dp *intel_dp) 6048 { 6049 struct intel_display *display = to_intel_display(intel_dp); 6050 struct intel_connector *connector = intel_dp->attached_connector; 6051 const struct drm_edid *drm_edid; 6052 bool vrr_capable; 6053 6054 intel_dp_unset_edid(intel_dp); 6055 drm_edid = intel_dp_get_edid(intel_dp); 6056 connector->detect_edid = drm_edid; 6057 6058 /* Below we depend on display info having been updated */ 6059 drm_edid_connector_update(&connector->base, drm_edid); 6060 6061 vrr_capable = intel_vrr_is_capable(connector); 6062 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n", 6063 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable)); 6064 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable); 6065 6066 intel_dp_update_dfp(intel_dp, drm_edid); 6067 intel_dp_update_420(intel_dp); 6068 6069 drm_dp_cec_attach(&intel_dp->aux, 6070 connector->base.display_info.source_physical_address); 6071 } 6072 6073 static void 6074 intel_dp_unset_edid(struct intel_dp *intel_dp) 6075 { 6076 struct intel_connector *connector = intel_dp->attached_connector; 6077 6078 drm_dp_cec_unset_edid(&intel_dp->aux); 6079 drm_edid_free(connector->detect_edid); 6080 connector->detect_edid = NULL; 6081 6082 intel_dp->dfp.max_bpc = 0; 6083 intel_dp->dfp.max_dotclock = 0; 6084 intel_dp->dfp.min_tmds_clock = 0; 6085 intel_dp->dfp.max_tmds_clock = 0; 6086 6087 intel_dp->dfp.pcon_max_frl_bw = 0; 6088 6089 intel_dp->dfp.ycbcr_444_to_420 = false; 6090 connector->base.ycbcr_420_allowed = false; 6091 6092 drm_connector_set_vrr_capable_property(&connector->base, 6093 false); 6094 } 6095 6096 static bool 6097 intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp) 6098 { 6099 u8 rx_features; 6100 6101 /* 6102 * The DP spec does not explicitly provide the AS SDP v2 capability. 6103 * So based on the DP v2.1 SCR, we infer it from the following bits: 6104 * 6105 * DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED indicates support for 6106 * FAVT, which is explicitly defined to use AS SDP v2. 6107 * 6108 * DP_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR indicates that the sink 6109 * does not support asynchronous video timing while in PR Active, 6110 * requiring the source to keep transmitting Adaptive-Sync SDPs. The 6111 * spec mandates that such sinks shall support AS SDP v2. 6112 * 6113 * #TODO: Check the Adaptive-Sync DisplayID 2.1 block once DisplayID 6114 * parsing is available. This may help detect AS SDP v2 support for 6115 * native DP 2.1 sinks that do not expose FAVT or PR-based capability 6116 * bits. 6117 * 6118 * In the presence of PCONs, check PCON support from DPCD and sink 6119 * support from Display ID. 6120 */ 6121 6122 if (drm_dp_dpcd_read_byte(&intel_dp->aux, 6123 DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1, 6124 &rx_features) == 1) { 6125 if (rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED) 6126 return true; 6127 } 6128 6129 if (intel_dp->psr.sink_panel_replay_support && 6130 !intel_psr_pr_async_video_timing_supported(intel_dp)) 6131 return true; 6132 6133 return false; 6134 } 6135 6136 static void 6137 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) 6138 { 6139 struct intel_display *display = to_intel_display(intel_dp); 6140 6141 intel_dp->as_sdp_supported = HAS_AS_SDP(display) && 6142 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); 6143 6144 if (!intel_dp->as_sdp_supported) 6145 return; 6146 6147 /* eDP Adaptive-Sync SDP always uses AS SDP v2 */ 6148 if (intel_dp_is_edp(intel_dp)) 6149 intel_dp->as_sdp_v2_supported = true; 6150 else 6151 intel_dp->as_sdp_v2_supported = intel_dp_sink_supports_as_sdp_v2(intel_dp); 6152 } 6153 6154 static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external) 6155 { 6156 struct intel_connector *connector = intel_dp->attached_connector; 6157 6158 if (intel_dp_is_edp(intel_dp)) 6159 return false; 6160 6161 if (force_on_external) 6162 return true; 6163 6164 if (intel_dp->is_mst) 6165 return false; 6166 6167 return drm_edid_has_quirk(&connector->base, DRM_EDID_QUIRK_DP_DPCD_PROBE); 6168 } 6169 6170 void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external) 6171 { 6172 drm_dp_dpcd_set_probe(&intel_dp->aux, 6173 intel_dp_needs_dpcd_probe(intel_dp, force_on_external)); 6174 } 6175 6176 static int 6177 intel_dp_detect(struct drm_connector *_connector, 6178 struct drm_modeset_acquire_ctx *ctx, 6179 bool force) 6180 { 6181 struct intel_display *display = to_intel_display(_connector->dev); 6182 struct intel_connector *connector = to_intel_connector(_connector); 6183 struct intel_dp *intel_dp = intel_attached_dp(connector); 6184 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 6185 struct intel_encoder *encoder = &dig_port->base; 6186 enum drm_connector_status status; 6187 int ret; 6188 6189 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 6190 connector->base.base.id, connector->base.name); 6191 drm_WARN_ON(display->drm, 6192 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 6193 6194 if (!intel_display_device_enabled(display)) 6195 return connector_status_disconnected; 6196 6197 if (!intel_display_driver_check_access(display)) 6198 return connector->base.status; 6199 6200 intel_dp_flush_connector_commits(connector); 6201 6202 intel_pps_vdd_on(intel_dp); 6203 6204 /* Can't disconnect eDP */ 6205 if (intel_dp_is_edp(intel_dp)) 6206 status = edp_detect(intel_dp); 6207 else if (intel_digital_port_connected(encoder)) 6208 status = intel_dp_detect_dpcd(intel_dp); 6209 else 6210 status = connector_status_disconnected; 6211 6212 if (status != connector_status_disconnected && 6213 !intel_dp_mst_verify_dpcd_state(intel_dp)) 6214 /* 6215 * This requires retrying detection for instance to re-enable 6216 * the MST mode that got reset via a long HPD pulse. The retry 6217 * will happen either via the hotplug handler's retry logic, 6218 * ensured by setting the connector here to SST/disconnected, 6219 * or via a userspace connector probing in response to the 6220 * hotplug uevent sent when removing the MST connectors. 6221 */ 6222 status = connector_status_disconnected; 6223 6224 if (status == connector_status_disconnected) { 6225 intel_dp_test_reset(intel_dp); 6226 /* 6227 * FIXME: Resetting these caps here cause 6228 * state computation fail if the connector need to be 6229 * modeset after sink disconnect. Move resetting them 6230 * to where new sink is connected. 6231 */ 6232 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 6233 memset(connector->dp.panel_replay_caps.dpcd, 0, 6234 sizeof(connector->dp.panel_replay_caps.dpcd)); 6235 intel_dp->psr.sink_panel_replay_support = false; 6236 connector->dp.panel_replay_caps.support = false; 6237 connector->dp.panel_replay_caps.su_support = false; 6238 connector->dp.panel_replay_caps.dsc_support = 6239 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; 6240 6241 intel_dp_mst_disconnect(intel_dp); 6242 6243 intel_dp_tunnel_disconnect(intel_dp); 6244 6245 goto out_unset_edid; 6246 } 6247 6248 intel_dp_init_source_oui(intel_dp); 6249 6250 ret = intel_dp_tunnel_detect(intel_dp, ctx); 6251 if (ret == -EDEADLK) { 6252 status = ret; 6253 6254 goto out_vdd_off; 6255 } 6256 6257 if (ret == 1) 6258 connector->base.epoch_counter++; 6259 6260 if (!intel_dp_is_edp(intel_dp)) 6261 intel_psr_init_dpcd(intel_dp, connector); 6262 6263 intel_dp_detect_dsc_caps(intel_dp, connector); 6264 6265 intel_dp_detect_sdp_caps(intel_dp); 6266 6267 if (intel_dp->reset_link_params) { 6268 intel_dp_reset_link_params(intel_dp); 6269 intel_dp->reset_link_params = false; 6270 } 6271 6272 intel_dp_mst_configure(intel_dp); 6273 6274 intel_dp_print_rates(intel_dp); 6275 6276 if (intel_dp->is_mst) { 6277 /* 6278 * If we are in MST mode then this connector 6279 * won't appear connected or have anything 6280 * with EDID on it 6281 */ 6282 status = connector_status_disconnected; 6283 goto out_unset_edid; 6284 } 6285 6286 /* 6287 * Some external monitors do not signal loss of link synchronization 6288 * with an IRQ_HPD, so force a link status check. 6289 * 6290 * TODO: this probably became redundant, so remove it: the link state 6291 * is rechecked/recovered now after modesets, where the loss of 6292 * synchronization tends to occur. 6293 */ 6294 if (!intel_dp_is_edp(intel_dp)) 6295 intel_dp_check_link_state(intel_dp); 6296 6297 /* 6298 * Clearing NACK and defer counts to get their exact values 6299 * while reading EDID which are required by Compliance tests 6300 * 4.2.2.4 and 4.2.2.5 6301 */ 6302 intel_dp->aux.i2c_nack_count = 0; 6303 intel_dp->aux.i2c_defer_count = 0; 6304 6305 intel_dp_set_edid(intel_dp); 6306 if (intel_dp_is_edp(intel_dp) || connector->detect_edid) 6307 status = connector_status_connected; 6308 6309 out_unset_edid: 6310 if (status != connector_status_connected && !intel_dp->is_mst) 6311 intel_dp_unset_edid(intel_dp); 6312 6313 intel_dp_dpcd_set_probe(intel_dp, false); 6314 6315 if (!intel_dp_is_edp(intel_dp)) 6316 drm_dp_set_subconnector_property(&connector->base, 6317 status, 6318 intel_dp->dpcd, 6319 intel_dp->downstream_ports); 6320 out_vdd_off: 6321 intel_pps_vdd_off(intel_dp); 6322 6323 return status; 6324 } 6325 6326 static void 6327 intel_dp_force(struct drm_connector *_connector) 6328 { 6329 struct intel_connector *connector = to_intel_connector(_connector); 6330 struct intel_display *display = to_intel_display(connector); 6331 struct intel_dp *intel_dp = intel_attached_dp(connector); 6332 6333 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 6334 connector->base.base.id, connector->base.name); 6335 6336 if (!intel_display_driver_check_access(display)) 6337 return; 6338 6339 intel_dp_unset_edid(intel_dp); 6340 6341 if (connector->base.status != connector_status_connected) 6342 return; 6343 6344 intel_dp_set_edid(intel_dp); 6345 6346 intel_dp_dpcd_set_probe(intel_dp, false); 6347 } 6348 6349 static int intel_dp_get_modes(struct drm_connector *_connector) 6350 { 6351 struct intel_display *display = to_intel_display(_connector->dev); 6352 struct intel_connector *connector = to_intel_connector(_connector); 6353 struct intel_dp *intel_dp = intel_attached_dp(connector); 6354 int num_modes; 6355 6356 /* drm_edid_connector_update() done in ->detect() or ->force() */ 6357 num_modes = drm_edid_connector_add_modes(&connector->base); 6358 6359 /* Also add fixed mode, which may or may not be present in EDID */ 6360 if (intel_dp_is_edp(intel_dp)) 6361 num_modes += intel_panel_get_modes(connector); 6362 6363 if (num_modes) 6364 return num_modes; 6365 6366 if (!connector->detect_edid) { 6367 struct drm_display_mode *mode; 6368 6369 mode = drm_dp_downstream_mode(display->drm, 6370 intel_dp->dpcd, 6371 intel_dp->downstream_ports); 6372 if (mode) { 6373 drm_mode_probed_add(&connector->base, mode); 6374 num_modes++; 6375 } 6376 } 6377 6378 return num_modes; 6379 } 6380 6381 static int 6382 intel_dp_connector_register(struct drm_connector *_connector) 6383 { 6384 struct intel_connector *connector = to_intel_connector(_connector); 6385 struct intel_display *display = to_intel_display(connector); 6386 struct intel_dp *intel_dp = intel_attached_dp(connector); 6387 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 6388 int ret; 6389 6390 ret = intel_connector_register(&connector->base); 6391 if (ret) 6392 return ret; 6393 6394 drm_dbg_kms(display->drm, "registering %s bus for %s\n", 6395 intel_dp->aux.name, connector->base.kdev->kobj.name); 6396 6397 intel_dp->aux.dev = connector->base.kdev; 6398 ret = drm_dp_aux_register(&intel_dp->aux); 6399 if (!ret) 6400 drm_dp_cec_register_connector(&intel_dp->aux, &connector->base); 6401 6402 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) 6403 return ret; 6404 6405 /* 6406 * ToDo: Clean this up to handle lspcon init and resume more 6407 * efficiently and streamlined. 6408 */ 6409 if (intel_lspcon_init(dig_port)) { 6410 if (intel_lspcon_detect_hdr_capability(dig_port)) 6411 drm_connector_attach_hdr_output_metadata_property(&connector->base); 6412 } 6413 6414 return ret; 6415 } 6416 6417 static void 6418 intel_dp_connector_unregister(struct drm_connector *_connector) 6419 { 6420 struct intel_connector *connector = to_intel_connector(_connector); 6421 struct intel_dp *intel_dp = intel_attached_dp(connector); 6422 6423 drm_dp_cec_unregister_connector(&intel_dp->aux); 6424 drm_dp_aux_unregister(&intel_dp->aux); 6425 intel_connector_unregister(&connector->base); 6426 } 6427 6428 void intel_dp_connector_sync_state(struct intel_connector *connector, 6429 const struct intel_crtc_state *crtc_state) 6430 { 6431 struct intel_display *display = to_intel_display(connector); 6432 6433 if (crtc_state && crtc_state->dsc.compression_enable) { 6434 drm_WARN_ON(display->drm, 6435 !connector->dp.dsc_decompression_aux); 6436 connector->dp.dsc_decompression_enabled = true; 6437 } else { 6438 connector->dp.dsc_decompression_enabled = false; 6439 } 6440 } 6441 6442 void intel_dp_encoder_flush_work(struct drm_encoder *_encoder) 6443 { 6444 struct intel_encoder *encoder = to_intel_encoder(_encoder); 6445 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 6446 struct intel_dp *intel_dp = &dig_port->dp; 6447 6448 intel_encoder_link_check_flush_work(encoder); 6449 6450 intel_dp_mst_encoder_cleanup(dig_port); 6451 6452 intel_dp_tunnel_destroy(intel_dp); 6453 6454 intel_pps_vdd_off_sync(intel_dp); 6455 6456 /* 6457 * Ensure power off delay is respected on module remove, so that we can 6458 * reduce delays at driver probe. See pps_init_timestamps(). 6459 */ 6460 intel_pps_wait_power_cycle(intel_dp); 6461 6462 intel_dp_aux_fini(intel_dp); 6463 } 6464 6465 void intel_dp_encoder_suspend(struct intel_encoder *encoder) 6466 { 6467 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 6468 6469 intel_pps_vdd_off_sync(intel_dp); 6470 6471 intel_dp_tunnel_suspend(intel_dp); 6472 } 6473 6474 void intel_dp_encoder_shutdown(struct intel_encoder *encoder) 6475 { 6476 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 6477 6478 intel_pps_wait_power_cycle(intel_dp); 6479 } 6480 6481 static int intel_modeset_tile_group(struct intel_atomic_state *state, 6482 int tile_group_id) 6483 { 6484 struct intel_display *display = to_intel_display(state); 6485 struct drm_connector_list_iter conn_iter; 6486 struct intel_connector *connector; 6487 int ret = 0; 6488 6489 drm_connector_list_iter_begin(display->drm, &conn_iter); 6490 for_each_intel_connector_iter(connector, &conn_iter) { 6491 struct drm_connector_state *conn_state; 6492 struct intel_crtc_state *crtc_state; 6493 struct intel_crtc *crtc; 6494 6495 if (!connector->base.has_tile || 6496 connector->base.tile_group->id != tile_group_id) 6497 continue; 6498 6499 conn_state = drm_atomic_get_connector_state(&state->base, 6500 &connector->base); 6501 if (IS_ERR(conn_state)) { 6502 ret = PTR_ERR(conn_state); 6503 break; 6504 } 6505 6506 crtc = to_intel_crtc(conn_state->crtc); 6507 6508 if (!crtc) 6509 continue; 6510 6511 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6512 crtc_state->uapi.mode_changed = true; 6513 6514 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6515 if (ret) 6516 break; 6517 } 6518 drm_connector_list_iter_end(&conn_iter); 6519 6520 return ret; 6521 } 6522 6523 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u16 transcoders) 6524 { 6525 struct intel_display *display = to_intel_display(state); 6526 struct intel_crtc *crtc; 6527 6528 if (transcoders == 0) 6529 return 0; 6530 6531 for_each_intel_crtc(display, crtc) { 6532 struct intel_crtc_state *crtc_state; 6533 int ret; 6534 6535 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6536 if (IS_ERR(crtc_state)) 6537 return PTR_ERR(crtc_state); 6538 6539 if (!crtc_state->hw.enable) 6540 continue; 6541 6542 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) 6543 continue; 6544 6545 crtc_state->uapi.mode_changed = true; 6546 6547 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6548 if (ret) 6549 return ret; 6550 6551 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6552 if (ret) 6553 return ret; 6554 6555 transcoders &= ~BIT(crtc_state->cpu_transcoder); 6556 } 6557 6558 drm_WARN_ON(display->drm, transcoders != 0); 6559 6560 return 0; 6561 } 6562 6563 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, 6564 struct drm_connector *_connector) 6565 { 6566 struct intel_connector *connector = to_intel_connector(_connector); 6567 const struct drm_connector_state *old_conn_state = 6568 drm_atomic_get_old_connector_state(&state->base, &connector->base); 6569 const struct intel_crtc_state *old_crtc_state; 6570 struct intel_crtc *crtc; 6571 u16 transcoders; 6572 6573 crtc = to_intel_crtc(old_conn_state->crtc); 6574 if (!crtc) 6575 return 0; 6576 6577 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6578 6579 if (!old_crtc_state->hw.active) 6580 return 0; 6581 6582 transcoders = old_crtc_state->sync_mode_slaves_mask; 6583 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) 6584 transcoders |= BIT(old_crtc_state->master_transcoder); 6585 6586 return intel_modeset_affected_transcoders(state, 6587 transcoders); 6588 } 6589 6590 static int intel_dp_connector_atomic_check(struct drm_connector *_connector, 6591 struct drm_atomic_commit *_state) 6592 { 6593 struct intel_connector *connector = to_intel_connector(_connector); 6594 struct intel_display *display = to_intel_display(connector); 6595 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6596 struct drm_connector_state *conn_state = 6597 drm_atomic_get_new_connector_state(_state, &connector->base); 6598 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 6599 int ret; 6600 6601 ret = intel_digital_connector_atomic_check(&connector->base, &state->base); 6602 if (ret) 6603 return ret; 6604 6605 if (intel_dp_mst_source_support(intel_dp)) { 6606 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst.mgr); 6607 if (ret) 6608 return ret; 6609 } 6610 6611 if (!intel_connector_needs_modeset(state, &connector->base)) 6612 return 0; 6613 6614 ret = intel_dp_tunnel_atomic_check_state(state, 6615 intel_dp, 6616 connector); 6617 if (ret) 6618 return ret; 6619 6620 /* 6621 * We don't enable port sync on BDW due to missing w/as and 6622 * due to not having adjusted the modeset sequence appropriately. 6623 */ 6624 if (DISPLAY_VER(display) < 9) 6625 return 0; 6626 6627 if (connector->base.has_tile) { 6628 ret = intel_modeset_tile_group(state, connector->base.tile_group->id); 6629 if (ret) 6630 return ret; 6631 } 6632 6633 return intel_modeset_synced_crtcs(state, &connector->base); 6634 } 6635 6636 static void intel_dp_oob_hotplug_event(struct drm_connector *_connector, 6637 enum drm_connector_status hpd_state) 6638 { 6639 struct intel_connector *connector = to_intel_connector(_connector); 6640 struct intel_display *display = to_intel_display(connector); 6641 struct intel_encoder *encoder = intel_attached_encoder(connector); 6642 bool hpd_high = hpd_state == connector_status_connected; 6643 unsigned int hpd_pin = encoder->hpd_pin; 6644 bool need_work = false; 6645 6646 spin_lock_irq(&display->irq.lock); 6647 if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) { 6648 display->hotplug.event_bits |= BIT(hpd_pin); 6649 6650 __assign_bit(hpd_pin, 6651 &display->hotplug.oob_hotplug_last_state, 6652 hpd_high); 6653 need_work = true; 6654 } 6655 spin_unlock_irq(&display->irq.lock); 6656 6657 if (need_work) 6658 intel_hpd_schedule_detection(display); 6659 } 6660 6661 static const struct drm_connector_funcs intel_dp_connector_funcs = { 6662 .force = intel_dp_force, 6663 .fill_modes = drm_helper_probe_single_connector_modes, 6664 .atomic_get_property = intel_digital_connector_atomic_get_property, 6665 .atomic_set_property = intel_digital_connector_atomic_set_property, 6666 .late_register = intel_dp_connector_register, 6667 .early_unregister = intel_dp_connector_unregister, 6668 .destroy = intel_connector_destroy, 6669 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6670 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 6671 .oob_hotplug_event = intel_dp_oob_hotplug_event, 6672 }; 6673 6674 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 6675 .detect_ctx = intel_dp_detect, 6676 .get_modes = intel_dp_get_modes, 6677 .mode_valid = intel_dp_mode_valid, 6678 .atomic_check = intel_dp_connector_atomic_check, 6679 }; 6680 6681 enum irqreturn 6682 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) 6683 { 6684 struct intel_display *display = to_intel_display(dig_port); 6685 struct intel_dp *intel_dp = &dig_port->dp; 6686 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 6687 6688 if (dig_port->base.type == INTEL_OUTPUT_EDP && 6689 (long_hpd || 6690 intel_display_rpm_suspended(display) || 6691 !intel_pps_have_panel_power_or_vdd(intel_dp))) { 6692 /* 6693 * vdd off can generate a long/short pulse on eDP which 6694 * would require vdd on to handle it, and thus we 6695 * would end up in an endless cycle of 6696 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." 6697 */ 6698 drm_dbg_kms(display->drm, 6699 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", 6700 long_hpd ? "long" : "short", 6701 dig_port->base.base.base.id, 6702 dig_port->base.base.name); 6703 return IRQ_HANDLED; 6704 } 6705 6706 drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", 6707 dig_port->base.base.base.id, 6708 dig_port->base.base.name, 6709 long_hpd ? "long" : "short"); 6710 6711 /* 6712 * TBT DP tunnels require the GFX driver to read out the DPRX caps in 6713 * response to long HPD pulses. The DP hotplug handler does that, 6714 * however the hotplug handler may be blocked by another 6715 * connector's/encoder's hotplug handler. Since the TBT CM may not 6716 * complete the DP tunnel BW request for the latter connector/encoder 6717 * waiting for this encoder's DPRX read, perform a dummy read here. 6718 */ 6719 if (long_hpd) { 6720 intel_dp_dpcd_set_probe(intel_dp, true); 6721 6722 intel_dp_read_dprx_caps(intel_dp, dpcd); 6723 6724 intel_dp->reset_link_params = true; 6725 intel_dp_invalidate_source_oui(intel_dp); 6726 6727 return IRQ_NONE; 6728 } 6729 6730 if (intel_dp->is_mst) { 6731 if (!intel_dp_check_mst_status(intel_dp)) 6732 return IRQ_NONE; 6733 } else if (!intel_dp_short_pulse(intel_dp)) { 6734 return IRQ_NONE; 6735 } 6736 6737 return IRQ_HANDLED; 6738 } 6739 6740 static bool _intel_dp_is_port_edp(struct intel_display *display, 6741 const struct intel_bios_encoder_data *devdata, 6742 enum port port) 6743 { 6744 /* 6745 * eDP not supported on g4x. so bail out early just 6746 * for a bit extra safety in case the VBT is bonkers. 6747 */ 6748 if (DISPLAY_VER(display) < 5) 6749 return false; 6750 6751 if (DISPLAY_VER(display) < 9 && port == PORT_A) 6752 return true; 6753 6754 return devdata && intel_bios_encoder_supports_edp(devdata); 6755 } 6756 6757 bool intel_dp_is_port_edp(struct intel_display *display, enum port port) 6758 { 6759 const struct intel_bios_encoder_data *devdata = 6760 intel_bios_encoder_data_lookup(display, port); 6761 6762 return _intel_dp_is_port_edp(display, devdata, port); 6763 } 6764 6765 bool 6766 intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder) 6767 { 6768 struct intel_display *display = to_intel_display(encoder); 6769 enum port port = encoder->port; 6770 6771 if (intel_bios_encoder_is_lspcon(encoder->devdata)) 6772 return false; 6773 6774 if (DISPLAY_VER(display) >= 11) 6775 return true; 6776 6777 if (port == PORT_A) 6778 return false; 6779 6780 if (display->platform.haswell || display->platform.broadwell || 6781 DISPLAY_VER(display) >= 9) 6782 return true; 6783 6784 return false; 6785 } 6786 6787 static void 6788 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *_connector) 6789 { 6790 struct intel_connector *connector = to_intel_connector(_connector); 6791 struct intel_display *display = to_intel_display(intel_dp); 6792 enum port port = dp_to_dig_port(intel_dp)->base.port; 6793 6794 if (!intel_dp_is_edp(intel_dp)) 6795 drm_connector_attach_dp_subconnector_property(&connector->base); 6796 6797 if (!display->platform.g4x && port != PORT_A) 6798 intel_attach_force_audio_property(&connector->base); 6799 6800 intel_attach_broadcast_rgb_property(&connector->base); 6801 if (HAS_GMCH(display)) 6802 drm_connector_attach_max_bpc_property(&connector->base, 6, 10); 6803 else if (DISPLAY_VER(display) >= 5) 6804 drm_connector_attach_max_bpc_property(&connector->base, 6, 12); 6805 6806 /* Register HDMI colorspace for case of lspcon */ 6807 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) { 6808 drm_connector_attach_content_type_property(&connector->base); 6809 intel_attach_hdmi_colorspace_property(&connector->base); 6810 } else { 6811 intel_attach_dp_colorspace_property(&connector->base); 6812 } 6813 6814 if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) 6815 drm_connector_attach_hdr_output_metadata_property(&connector->base); 6816 6817 if (HAS_VRR(display)) 6818 drm_connector_attach_vrr_capable_property(&connector->base); 6819 } 6820 6821 static void 6822 intel_edp_add_properties(struct intel_dp *intel_dp) 6823 { 6824 struct intel_display *display = to_intel_display(intel_dp); 6825 struct intel_connector *connector = intel_dp->attached_connector; 6826 const struct drm_display_mode *fixed_mode = 6827 intel_panel_preferred_fixed_mode(connector); 6828 6829 intel_attach_scaling_mode_property(&connector->base); 6830 6831 drm_connector_set_panel_orientation_with_quirk(&connector->base, 6832 display->vbt.orientation, 6833 fixed_mode->hdisplay, 6834 fixed_mode->vdisplay); 6835 } 6836 6837 static void intel_edp_backlight_setup(struct intel_dp *intel_dp, 6838 struct intel_connector *connector) 6839 { 6840 struct intel_display *display = to_intel_display(intel_dp); 6841 enum pipe pipe = INVALID_PIPE; 6842 6843 if (display->platform.valleyview || display->platform.cherryview) 6844 pipe = vlv_pps_backlight_initial_pipe(intel_dp); 6845 6846 intel_backlight_setup(connector, pipe); 6847 } 6848 6849 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 6850 struct intel_connector *connector) 6851 { 6852 struct intel_display *display = to_intel_display(intel_dp); 6853 struct drm_display_mode *fixed_mode; 6854 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 6855 bool has_dpcd; 6856 const struct drm_edid *drm_edid; 6857 6858 if (!intel_dp_is_edp(intel_dp)) 6859 return true; 6860 6861 /* 6862 * On IBX/CPT we may get here with LVDS already registered. Since the 6863 * driver uses the only internal power sequencer available for both 6864 * eDP and LVDS bail out early in this case to prevent interfering 6865 * with an already powered-on LVDS power sequencer. 6866 */ 6867 if (intel_get_lvds_encoder(display)) { 6868 drm_WARN_ON(display->drm, 6869 !(HAS_PCH_IBX(display) || HAS_PCH_CPT(display))); 6870 drm_info(display->drm, 6871 "LVDS was detected, not registering eDP\n"); 6872 6873 return false; 6874 } 6875 6876 intel_bios_init_panel_early(display, &connector->panel, 6877 encoder->devdata); 6878 6879 if (!intel_pps_init(intel_dp)) { 6880 drm_info(display->drm, 6881 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n", 6882 encoder->base.base.id, encoder->base.name); 6883 /* 6884 * The BIOS may have still enabled VDD on the PPS even 6885 * though it's unusable. Make sure we turn it back off 6886 * and to release the power domain references/etc. 6887 */ 6888 goto out_vdd_off; 6889 } 6890 6891 /* 6892 * Enable HPD sense for live status check. 6893 * intel_hpd_irq_setup() will turn it off again 6894 * if it's no longer needed later. 6895 * 6896 * The DPCD probe below will make sure VDD is on. 6897 */ 6898 intel_hpd_enable_detection(encoder); 6899 6900 intel_alpm_init(intel_dp); 6901 6902 /* Cache DPCD and EDID for edp. */ 6903 has_dpcd = intel_edp_init_dpcd(intel_dp, connector); 6904 6905 if (!has_dpcd) { 6906 /* if this fails, presume the device is a ghost */ 6907 drm_info(display->drm, 6908 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n", 6909 encoder->base.base.id, encoder->base.name); 6910 goto out_vdd_off; 6911 } 6912 6913 /* 6914 * VBT and straps are liars. Also check HPD as that seems 6915 * to be the most reliable piece of information available. 6916 * 6917 * ... expect on devices that forgot to hook HPD up for eDP 6918 * (eg. Acer Chromebook C710), so we'll check it only if multiple 6919 * ports are attempting to use the same AUX CH, according to VBT. 6920 */ 6921 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) { 6922 /* 6923 * If this fails, presume the DPCD answer came 6924 * from some other port using the same AUX CH. 6925 * 6926 * FIXME maybe cleaner to check this before the 6927 * DPCD read? Would need sort out the VDD handling... 6928 */ 6929 if (!intel_digital_port_connected(encoder)) { 6930 drm_info(display->drm, 6931 "[ENCODER:%d:%s] HPD is down, disabling eDP\n", 6932 encoder->base.base.id, encoder->base.name); 6933 goto out_vdd_off; 6934 } 6935 6936 /* 6937 * Unfortunately even the HPD based detection fails on 6938 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall 6939 * back to checking for a VGA branch device. Only do this 6940 * on known affected platforms to minimize false positives. 6941 */ 6942 if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) && 6943 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) == 6944 DP_DWN_STRM_PORT_TYPE_ANALOG) { 6945 drm_info(display->drm, 6946 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n", 6947 encoder->base.base.id, encoder->base.name); 6948 goto out_vdd_off; 6949 } 6950 } 6951 6952 mutex_lock(&display->drm->mode_config.mutex); 6953 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc); 6954 if (!drm_edid) { 6955 /* Fallback to EDID from ACPI OpRegion, if any */ 6956 drm_edid = intel_opregion_get_edid(connector); 6957 if (drm_edid) 6958 drm_dbg_kms(display->drm, 6959 "[CONNECTOR:%d:%s] Using OpRegion EDID\n", 6960 connector->base.base.id, connector->base.name); 6961 } 6962 if (drm_edid) { 6963 if (drm_edid_connector_update(&connector->base, drm_edid) || 6964 !drm_edid_connector_add_modes(&connector->base)) { 6965 drm_edid_connector_update(&connector->base, NULL); 6966 drm_edid_free(drm_edid); 6967 drm_edid = ERR_PTR(-EINVAL); 6968 } 6969 } else { 6970 drm_edid = ERR_PTR(-ENOENT); 6971 } 6972 6973 intel_bios_init_panel_late(display, &connector->panel, encoder->devdata, 6974 IS_ERR(drm_edid) ? NULL : drm_edid); 6975 6976 intel_panel_add_edid_fixed_modes(connector, true); 6977 6978 /* MSO requires information from the EDID */ 6979 intel_edp_mso_init(intel_dp); 6980 6981 /* multiply the mode clock and horizontal timings for MSO */ 6982 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) 6983 intel_edp_mso_mode_fixup(connector, fixed_mode); 6984 6985 /* fallback to VBT if available for eDP */ 6986 if (!intel_panel_preferred_fixed_mode(connector)) 6987 intel_panel_add_vbt_lfp_fixed_mode(connector); 6988 6989 mutex_unlock(&display->drm->mode_config.mutex); 6990 6991 if (!intel_panel_preferred_fixed_mode(connector)) { 6992 drm_info(display->drm, 6993 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n", 6994 encoder->base.base.id, encoder->base.name); 6995 goto out_vdd_off; 6996 } 6997 6998 intel_panel_init(connector, drm_edid); 6999 7000 intel_edp_backlight_setup(intel_dp, connector); 7001 7002 intel_edp_add_properties(intel_dp); 7003 7004 intel_pps_init_late(intel_dp); 7005 7006 return true; 7007 7008 out_vdd_off: 7009 intel_pps_vdd_off_sync(intel_dp); 7010 intel_bios_fini_panel(&connector->panel); 7011 7012 return false; 7013 } 7014 7015 bool 7016 intel_dp_init_connector(struct intel_digital_port *dig_port, 7017 struct intel_connector *connector) 7018 { 7019 struct intel_display *display = to_intel_display(dig_port); 7020 struct intel_dp *intel_dp = &dig_port->dp; 7021 struct intel_encoder *encoder = &dig_port->base; 7022 struct drm_device *dev = encoder->base.dev; 7023 enum port port = encoder->port; 7024 int type; 7025 7026 if (drm_WARN(dev, dig_port->max_lanes < 1, 7027 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", 7028 dig_port->max_lanes, encoder->base.base.id, 7029 encoder->base.name)) 7030 return false; 7031 7032 intel_dp->reset_link_params = true; 7033 7034 /* Preserve the current hw state. */ 7035 intel_dp->DP = intel_de_read(display, intel_dp->output_reg); 7036 intel_dp->attached_connector = connector; 7037 7038 if (_intel_dp_is_port_edp(display, encoder->devdata, port)) { 7039 /* 7040 * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30, 7041 * although in theory it could work on TypeC legacy ports. 7042 */ 7043 drm_WARN_ON(dev, intel_encoder_is_tc(encoder) && 7044 DISPLAY_VER(display) < 30); 7045 type = DRM_MODE_CONNECTOR_eDP; 7046 encoder->type = INTEL_OUTPUT_EDP; 7047 7048 /* eDP only on port B and/or C on vlv/chv */ 7049 if (drm_WARN_ON(dev, (display->platform.valleyview || 7050 display->platform.cherryview) && 7051 port != PORT_B && port != PORT_C)) 7052 return false; 7053 } else { 7054 type = DRM_MODE_CONNECTOR_DisplayPort; 7055 } 7056 7057 intel_dp_set_default_sink_rates(intel_dp); 7058 intel_dp_set_default_max_sink_lane_count(intel_dp); 7059 7060 if (display->platform.valleyview || display->platform.cherryview) 7061 vlv_pps_pipe_init(intel_dp); 7062 7063 intel_dp_aux_init(intel_dp); 7064 connector->dp.dsc_decompression_aux = &intel_dp->aux; 7065 7066 drm_dbg_kms(display->drm, 7067 "Adding %s connector on [ENCODER:%d:%s]\n", 7068 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 7069 encoder->base.base.id, encoder->base.name); 7070 7071 drm_connector_init_with_ddc(dev, &connector->base, &intel_dp_connector_funcs, 7072 type, &intel_dp->aux.ddc); 7073 drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs); 7074 7075 if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12) 7076 connector->base.interlace_allowed = true; 7077 7078 if (type != DRM_MODE_CONNECTOR_eDP) 7079 connector->polled = DRM_CONNECTOR_POLL_HPD; 7080 connector->base.polled = connector->polled; 7081 7082 intel_connector_attach_encoder(connector, encoder); 7083 7084 if (HAS_DDI(display)) 7085 connector->get_hw_state = intel_ddi_connector_get_hw_state; 7086 else 7087 connector->get_hw_state = intel_connector_get_hw_state; 7088 connector->sync_state = intel_dp_connector_sync_state; 7089 7090 if (!intel_edp_init_connector(intel_dp, connector)) { 7091 intel_dp_aux_fini(intel_dp); 7092 goto fail; 7093 } 7094 7095 intel_dp_set_source_rates(intel_dp); 7096 intel_dp_set_common_link_params(intel_dp); 7097 intel_dp_reset_link_params(intel_dp); 7098 7099 /* init MST on ports that can support it */ 7100 intel_dp_mst_encoder_init(dig_port, connector->base.base.id); 7101 7102 intel_dp_add_properties(intel_dp, &connector->base); 7103 7104 if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) { 7105 int ret = intel_dp_hdcp_init(dig_port, connector); 7106 if (ret) 7107 drm_dbg_kms(display->drm, 7108 "HDCP init failed, skipping.\n"); 7109 } 7110 7111 intel_dp->frl.is_trained = false; 7112 intel_dp->frl.trained_rate_gbps = 0; 7113 7114 intel_psr_init(intel_dp); 7115 7116 return true; 7117 7118 fail: 7119 intel_display_power_flush_work(display); 7120 drm_connector_cleanup(&connector->base); 7121 7122 return false; 7123 } 7124 7125 void intel_dp_cleanup_connector(struct intel_digital_port *dig_port, 7126 struct intel_connector *connector) 7127 { 7128 struct intel_display *display = to_intel_display(connector); 7129 struct intel_dp *intel_dp = &dig_port->dp; 7130 7131 intel_display_power_flush_work(display); 7132 7133 intel_dp_mst_encoder_cleanup(dig_port); 7134 intel_dp_aux_fini(intel_dp); 7135 drm_connector_cleanup(&connector->base); 7136 } 7137 7138 void intel_dp_mst_suspend(struct intel_display *display) 7139 { 7140 struct intel_encoder *encoder; 7141 7142 if (!HAS_DISPLAY(display)) 7143 return; 7144 7145 for_each_intel_encoder(display->drm, encoder) { 7146 struct intel_dp *intel_dp; 7147 7148 if (encoder->type != INTEL_OUTPUT_DDI) 7149 continue; 7150 7151 intel_dp = enc_to_intel_dp(encoder); 7152 7153 if (!intel_dp_mst_source_support(intel_dp)) 7154 continue; 7155 7156 if (intel_dp->is_mst) 7157 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst.mgr); 7158 } 7159 } 7160 7161 void intel_dp_mst_resume(struct intel_display *display) 7162 { 7163 struct intel_encoder *encoder; 7164 7165 if (!HAS_DISPLAY(display)) 7166 return; 7167 7168 for_each_intel_encoder(display->drm, encoder) { 7169 struct intel_dp *intel_dp; 7170 int ret; 7171 7172 if (encoder->type != INTEL_OUTPUT_DDI) 7173 continue; 7174 7175 intel_dp = enc_to_intel_dp(encoder); 7176 7177 if (!intel_dp_mst_source_support(intel_dp)) 7178 continue; 7179 7180 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst.mgr, true); 7181 if (ret) { 7182 intel_dp->is_mst = false; 7183 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, false); 7184 } 7185 } 7186 } 7187 7188 static 7189 int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state) 7190 { 7191 struct intel_display *display = to_intel_display(crtc_state); 7192 int guardband = intel_crtc_vblank_length(crtc_state); 7193 int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false); 7194 7195 if (guardband < min_sdp_guardband) { 7196 drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n", 7197 guardband, min_sdp_guardband); 7198 return -EINVAL; 7199 } 7200 7201 return 0; 7202 } 7203 7204 int intel_dp_compute_config_late(struct intel_encoder *encoder, 7205 struct intel_crtc_state *crtc_state, 7206 struct drm_connector_state *conn_state) 7207 { 7208 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 7209 int ret; 7210 7211 intel_psr_compute_config_late(intel_dp, crtc_state); 7212 7213 ret = intel_dp_sdp_compute_config_late(crtc_state); 7214 if (ret) 7215 return ret; 7216 7217 intel_alpm_lobf_compute_config_late(intel_dp, crtc_state); 7218 7219 return 0; 7220 } 7221 7222 static 7223 int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 type) 7224 { 7225 switch (type) { 7226 case DP_SDP_VSC_EXT_VESA: 7227 case DP_SDP_VSC_EXT_CEA: 7228 return 10; 7229 case HDMI_PACKET_TYPE_GAMUT_METADATA: 7230 return 8; 7231 case DP_SDP_PPS: 7232 return 7; 7233 case DP_SDP_ADAPTIVE_SYNC: 7234 return crtc_state->vrr.vsync_start + 1; 7235 default: 7236 break; 7237 } 7238 7239 return 0; 7240 } 7241 7242 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state, 7243 bool assume_all_enabled) 7244 { 7245 int sdp_guardband = 0; 7246 7247 if (assume_all_enabled || 7248 crtc_state->infoframes.enable & 7249 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 7250 sdp_guardband = max(sdp_guardband, 7251 intel_dp_get_lines_for_sdp(crtc_state, 7252 HDMI_PACKET_TYPE_GAMUT_METADATA)); 7253 7254 if (assume_all_enabled || 7255 crtc_state->dsc.compression_enable) 7256 sdp_guardband = max(sdp_guardband, 7257 intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS)); 7258 7259 if (crtc_state->infoframes.enable & 7260 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) 7261 sdp_guardband = max(sdp_guardband, 7262 intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC)); 7263 7264 return sdp_guardband; 7265 } 7266 7267 bool intel_dp_joiner_candidate_valid(struct intel_connector *connector, 7268 int hdisplay, 7269 int num_joined_pipes) 7270 { 7271 struct intel_display *display = to_intel_display(connector); 7272 struct intel_dp *intel_dp = intel_attached_dp(connector); 7273 7274 if (!intel_dp_can_join(intel_dp, num_joined_pipes)) 7275 return false; 7276 7277 if (hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display)) 7278 return false; 7279 7280 if (connector->force_joined_pipes && connector->force_joined_pipes != num_joined_pipes) 7281 return false; 7282 7283 return true; 7284 } 7285 7286 u8 intel_dp_as_sdp_transmission_time(void) 7287 { 7288 /* 7289 * DP allows AS SDP position to move during PR active in some cases, but 7290 * software-controlled refresh rate changes with DC6v / ALPM require the 7291 * AS SDP to remain at T1. Use T1 unconditionally for now. 7292 */ 7293 7294 return DP_PR_AS_SDP_SETUP_TIME_T1; 7295 } 7296 7297 int intel_dp_link_init(struct intel_dp *intel_dp) 7298 { 7299 intel_dp->link.training = intel_dp_link_training_init(intel_dp); 7300 if (!intel_dp->link.training) 7301 return -ENOMEM; 7302 7303 intel_dp->link.caps = intel_dp_link_caps_init(intel_dp); 7304 if (!intel_dp->link.caps) { 7305 intel_dp_link_training_cleanup(intel_dp->link.training); 7306 7307 return -ENOMEM; 7308 } 7309 7310 return 0; 7311 } 7312 7313 void intel_dp_link_cleanup(struct intel_dp *intel_dp) 7314 { 7315 intel_dp_link_caps_cleanup(intel_dp->link.caps); 7316 intel_dp_link_training_cleanup(intel_dp->link.training); 7317 } 7318