1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/export.h> 29 #include <linux/i2c.h> 30 #include <linux/notifier.h> 31 #include <linux/slab.h> 32 #include <linux/types.h> 33 34 #include <asm/byteorder.h> 35 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_dp_helper.h> 39 #include <drm/drm_edid.h> 40 #include <drm/drm_probe_helper.h> 41 42 #include "i915_debugfs.h" 43 #include "i915_drv.h" 44 #include "i915_trace.h" 45 #include "intel_atomic.h" 46 #include "intel_audio.h" 47 #include "intel_connector.h" 48 #include "intel_ddi.h" 49 #include "intel_display_types.h" 50 #include "intel_dp.h" 51 #include "intel_dp_link_training.h" 52 #include "intel_dp_mst.h" 53 #include "intel_dpio_phy.h" 54 #include "intel_fifo_underrun.h" 55 #include "intel_hdcp.h" 56 #include "intel_hdmi.h" 57 #include "intel_hotplug.h" 58 #include "intel_lspcon.h" 59 #include "intel_lvds.h" 60 #include "intel_panel.h" 61 #include "intel_psr.h" 62 #include "intel_sideband.h" 63 #include "intel_tc.h" 64 #include "intel_vdsc.h" 65 66 #define DP_DPRX_ESI_LEN 14 67 68 /* DP DSC throughput values used for slice count calculations KPixels/s */ 69 #define DP_DSC_PEAK_PIXEL_RATE 2720000 70 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 71 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 72 73 /* DP DSC FEC Overhead factor = 1/(0.972261) */ 74 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261 75 76 /* Compliance test status bits */ 77 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 78 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) 79 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) 80 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) 81 82 struct dp_link_dpll { 83 int clock; 84 struct dpll dpll; 85 }; 86 87 static const struct dp_link_dpll g4x_dpll[] = { 88 { 162000, 89 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 90 { 270000, 91 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 92 }; 93 94 static const struct dp_link_dpll pch_dpll[] = { 95 { 162000, 96 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 97 { 270000, 98 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 99 }; 100 101 static const struct dp_link_dpll vlv_dpll[] = { 102 { 162000, 103 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 104 { 270000, 105 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 106 }; 107 108 /* 109 * CHV supports eDP 1.4 that have more link rates. 110 * Below only provides the fixed rate but exclude variable rate. 111 */ 112 static const struct dp_link_dpll chv_dpll[] = { 113 /* 114 * CHV requires to program fractional division for m2. 115 * m2 is stored in fixed point format using formula below 116 * (m2_int << 22) | m2_fraction 117 */ 118 { 162000, /* m2_int = 32, m2_fraction = 1677722 */ 119 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 120 { 270000, /* m2_int = 27, m2_fraction = 0 */ 121 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 122 }; 123 124 /* Constants for DP DSC configurations */ 125 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 126 127 /* With Single pipe configuration, HW is capable of supporting maximum 128 * of 4 slices per line. 129 */ 130 static const u8 valid_dsc_slicecount[] = {1, 2, 4}; 131 132 /** 133 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 134 * @intel_dp: DP struct 135 * 136 * If a CPU or PCH DP output is attached to an eDP panel, this function 137 * will return true, and false otherwise. 138 */ 139 bool intel_dp_is_edp(struct intel_dp *intel_dp) 140 { 141 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 142 143 return dig_port->base.type == INTEL_OUTPUT_EDP; 144 } 145 146 static void intel_dp_link_down(struct intel_encoder *encoder, 147 const struct intel_crtc_state *old_crtc_state); 148 static bool edp_panel_vdd_on(struct intel_dp *intel_dp); 149 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 150 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, 151 const struct intel_crtc_state *crtc_state); 152 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, 153 enum pipe pipe); 154 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 155 156 /* update sink rates from dpcd */ 157 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 158 { 159 static const int dp_rates[] = { 160 162000, 270000, 540000, 810000 161 }; 162 int i, max_rate; 163 int max_lttpr_rate; 164 165 if (drm_dp_has_quirk(&intel_dp->desc, 0, 166 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { 167 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ 168 static const int quirk_rates[] = { 162000, 270000, 324000 }; 169 170 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); 171 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); 172 173 return; 174 } 175 176 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 177 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); 178 if (max_lttpr_rate) 179 max_rate = min(max_rate, max_lttpr_rate); 180 181 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { 182 if (dp_rates[i] > max_rate) 183 break; 184 intel_dp->sink_rates[i] = dp_rates[i]; 185 } 186 187 intel_dp->num_sink_rates = i; 188 } 189 190 /* Get length of rates array potentially limited by max_rate. */ 191 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) 192 { 193 int i; 194 195 /* Limit results by potentially reduced max rate */ 196 for (i = 0; i < len; i++) { 197 if (rates[len - i - 1] <= max_rate) 198 return len - i; 199 } 200 201 return 0; 202 } 203 204 /* Get length of common rates array potentially limited by max_rate. */ 205 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, 206 int max_rate) 207 { 208 return intel_dp_rate_limit_len(intel_dp->common_rates, 209 intel_dp->num_common_rates, max_rate); 210 } 211 212 /* Theoretical max between source and sink */ 213 static int intel_dp_max_common_rate(struct intel_dp *intel_dp) 214 { 215 return intel_dp->common_rates[intel_dp->num_common_rates - 1]; 216 } 217 218 /* Theoretical max between source and sink */ 219 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) 220 { 221 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 222 int source_max = dig_port->max_lanes; 223 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); 224 int fia_max = intel_tc_port_fia_max_lane_count(dig_port); 225 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); 226 227 if (lttpr_max) 228 sink_max = min(sink_max, lttpr_max); 229 230 return min3(source_max, sink_max, fia_max); 231 } 232 233 int intel_dp_max_lane_count(struct intel_dp *intel_dp) 234 { 235 return intel_dp->max_link_lane_count; 236 } 237 238 int 239 intel_dp_link_required(int pixel_clock, int bpp) 240 { 241 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 242 return DIV_ROUND_UP(pixel_clock * bpp, 8); 243 } 244 245 int 246 intel_dp_max_data_rate(int max_link_clock, int max_lanes) 247 { 248 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the 249 * link rate that is generally expressed in Gbps. Since, 8 bits of data 250 * is transmitted every LS_Clk per lane, there is no need to account for 251 * the channel encoding that is done in the PHY layer here. 252 */ 253 254 return max_link_clock * max_lanes; 255 } 256 257 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp) 258 { 259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 260 struct intel_encoder *encoder = &intel_dig_port->base; 261 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 262 263 return INTEL_GEN(dev_priv) >= 12 || 264 (INTEL_GEN(dev_priv) == 11 && 265 encoder->port != PORT_A); 266 } 267 268 static int cnl_max_source_rate(struct intel_dp *intel_dp) 269 { 270 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 271 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 272 enum port port = dig_port->base.port; 273 274 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 275 276 /* Low voltage SKUs are limited to max of 5.4G */ 277 if (voltage == VOLTAGE_INFO_0_85V) 278 return 540000; 279 280 /* For this SKU 8.1G is supported in all ports */ 281 if (IS_CNL_WITH_PORT_F(dev_priv)) 282 return 810000; 283 284 /* For other SKUs, max rate on ports A and D is 5.4G */ 285 if (port == PORT_A || port == PORT_D) 286 return 540000; 287 288 return 810000; 289 } 290 291 static int icl_max_source_rate(struct intel_dp *intel_dp) 292 { 293 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 294 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 295 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 296 297 if (intel_phy_is_combo(dev_priv, phy) && 298 !intel_dp_is_edp(intel_dp)) 299 return 540000; 300 301 return 810000; 302 } 303 304 static int ehl_max_source_rate(struct intel_dp *intel_dp) 305 { 306 if (intel_dp_is_edp(intel_dp)) 307 return 540000; 308 309 return 810000; 310 } 311 312 static void 313 intel_dp_set_source_rates(struct intel_dp *intel_dp) 314 { 315 /* The values must be in increasing order */ 316 static const int cnl_rates[] = { 317 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000 318 }; 319 static const int bxt_rates[] = { 320 162000, 216000, 243000, 270000, 324000, 432000, 540000 321 }; 322 static const int skl_rates[] = { 323 162000, 216000, 270000, 324000, 432000, 540000 324 }; 325 static const int hsw_rates[] = { 326 162000, 270000, 540000 327 }; 328 static const int g4x_rates[] = { 329 162000, 270000 330 }; 331 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 332 struct intel_encoder *encoder = &dig_port->base; 333 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 334 const int *source_rates; 335 int size, max_rate = 0, vbt_max_rate; 336 337 /* This should only be done once */ 338 drm_WARN_ON(&dev_priv->drm, 339 intel_dp->source_rates || intel_dp->num_source_rates); 340 341 if (INTEL_GEN(dev_priv) >= 10) { 342 source_rates = cnl_rates; 343 size = ARRAY_SIZE(cnl_rates); 344 if (IS_GEN(dev_priv, 10)) 345 max_rate = cnl_max_source_rate(intel_dp); 346 else if (IS_JSL_EHL(dev_priv)) 347 max_rate = ehl_max_source_rate(intel_dp); 348 else 349 max_rate = icl_max_source_rate(intel_dp); 350 } else if (IS_GEN9_LP(dev_priv)) { 351 source_rates = bxt_rates; 352 size = ARRAY_SIZE(bxt_rates); 353 } else if (IS_GEN9_BC(dev_priv)) { 354 source_rates = skl_rates; 355 size = ARRAY_SIZE(skl_rates); 356 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || 357 IS_BROADWELL(dev_priv)) { 358 source_rates = hsw_rates; 359 size = ARRAY_SIZE(hsw_rates); 360 } else { 361 source_rates = g4x_rates; 362 size = ARRAY_SIZE(g4x_rates); 363 } 364 365 vbt_max_rate = intel_bios_dp_max_link_rate(encoder); 366 if (max_rate && vbt_max_rate) 367 max_rate = min(max_rate, vbt_max_rate); 368 else if (vbt_max_rate) 369 max_rate = vbt_max_rate; 370 371 if (max_rate) 372 size = intel_dp_rate_limit_len(source_rates, size, max_rate); 373 374 intel_dp->source_rates = source_rates; 375 intel_dp->num_source_rates = size; 376 } 377 378 static int intersect_rates(const int *source_rates, int source_len, 379 const int *sink_rates, int sink_len, 380 int *common_rates) 381 { 382 int i = 0, j = 0, k = 0; 383 384 while (i < source_len && j < sink_len) { 385 if (source_rates[i] == sink_rates[j]) { 386 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 387 return k; 388 common_rates[k] = source_rates[i]; 389 ++k; 390 ++i; 391 ++j; 392 } else if (source_rates[i] < sink_rates[j]) { 393 ++i; 394 } else { 395 ++j; 396 } 397 } 398 return k; 399 } 400 401 /* return index of rate in rates array, or -1 if not found */ 402 static int intel_dp_rate_index(const int *rates, int len, int rate) 403 { 404 int i; 405 406 for (i = 0; i < len; i++) 407 if (rate == rates[i]) 408 return i; 409 410 return -1; 411 } 412 413 static void intel_dp_set_common_rates(struct intel_dp *intel_dp) 414 { 415 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 416 417 drm_WARN_ON(&i915->drm, 418 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); 419 420 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, 421 intel_dp->num_source_rates, 422 intel_dp->sink_rates, 423 intel_dp->num_sink_rates, 424 intel_dp->common_rates); 425 426 /* Paranoia, there should always be something in common. */ 427 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) { 428 intel_dp->common_rates[0] = 162000; 429 intel_dp->num_common_rates = 1; 430 } 431 } 432 433 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 434 u8 lane_count) 435 { 436 /* 437 * FIXME: we need to synchronize the current link parameters with 438 * hardware readout. Currently fast link training doesn't work on 439 * boot-up. 440 */ 441 if (link_rate == 0 || 442 link_rate > intel_dp->max_link_rate) 443 return false; 444 445 if (lane_count == 0 || 446 lane_count > intel_dp_max_lane_count(intel_dp)) 447 return false; 448 449 return true; 450 } 451 452 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, 453 int link_rate, 454 u8 lane_count) 455 { 456 const struct drm_display_mode *fixed_mode = 457 intel_dp->attached_connector->panel.fixed_mode; 458 int mode_rate, max_rate; 459 460 mode_rate = intel_dp_link_required(fixed_mode->clock, 18); 461 max_rate = intel_dp_max_data_rate(link_rate, lane_count); 462 if (mode_rate > max_rate) 463 return false; 464 465 return true; 466 } 467 468 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 469 int link_rate, u8 lane_count) 470 { 471 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 472 int index; 473 474 /* 475 * TODO: Enable fallback on MST links once MST link compute can handle 476 * the fallback params. 477 */ 478 if (intel_dp->is_mst) { 479 drm_err(&i915->drm, "Link Training Unsuccessful\n"); 480 return -1; 481 } 482 483 index = intel_dp_rate_index(intel_dp->common_rates, 484 intel_dp->num_common_rates, 485 link_rate); 486 if (index > 0) { 487 if (intel_dp_is_edp(intel_dp) && 488 !intel_dp_can_link_train_fallback_for_edp(intel_dp, 489 intel_dp->common_rates[index - 1], 490 lane_count)) { 491 drm_dbg_kms(&i915->drm, 492 "Retrying Link training for eDP with same parameters\n"); 493 return 0; 494 } 495 intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; 496 intel_dp->max_link_lane_count = lane_count; 497 } else if (lane_count > 1) { 498 if (intel_dp_is_edp(intel_dp) && 499 !intel_dp_can_link_train_fallback_for_edp(intel_dp, 500 intel_dp_max_common_rate(intel_dp), 501 lane_count >> 1)) { 502 drm_dbg_kms(&i915->drm, 503 "Retrying Link training for eDP with same parameters\n"); 504 return 0; 505 } 506 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); 507 intel_dp->max_link_lane_count = lane_count >> 1; 508 } else { 509 drm_err(&i915->drm, "Link Training Unsuccessful\n"); 510 return -1; 511 } 512 513 return 0; 514 } 515 516 u32 intel_dp_mode_to_fec_clock(u32 mode_clock) 517 { 518 return div_u64(mul_u32_u32(mode_clock, 1000000U), 519 DP_DSC_FEC_OVERHEAD_FACTOR); 520 } 521 522 static int 523 small_joiner_ram_size_bits(struct drm_i915_private *i915) 524 { 525 if (INTEL_GEN(i915) >= 11) 526 return 7680 * 8; 527 else 528 return 6144 * 8; 529 } 530 531 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, 532 u32 link_clock, u32 lane_count, 533 u32 mode_clock, u32 mode_hdisplay, 534 bool bigjoiner) 535 { 536 u32 bits_per_pixel, max_bpp_small_joiner_ram; 537 int i; 538 539 /* 540 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* 541 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP) 542 * for SST -> TimeSlotsPerMTP is 1, 543 * for MST -> TimeSlotsPerMTP has to be calculated 544 */ 545 bits_per_pixel = (link_clock * lane_count * 8) / 546 intel_dp_mode_to_fec_clock(mode_clock); 547 drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); 548 549 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ 550 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / 551 mode_hdisplay; 552 553 if (bigjoiner) 554 max_bpp_small_joiner_ram *= 2; 555 556 drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n", 557 max_bpp_small_joiner_ram); 558 559 /* 560 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW 561 * check, output bpp from small joiner RAM check) 562 */ 563 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); 564 565 if (bigjoiner) { 566 u32 max_bpp_bigjoiner = 567 i915->max_cdclk_freq * 48 / 568 intel_dp_mode_to_fec_clock(mode_clock); 569 570 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner); 571 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner); 572 } 573 574 /* Error out if the max bpp is less than smallest allowed valid bpp */ 575 if (bits_per_pixel < valid_dsc_bpp[0]) { 576 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n", 577 bits_per_pixel, valid_dsc_bpp[0]); 578 return 0; 579 } 580 581 /* Find the nearest match in the array of known BPPs from VESA */ 582 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { 583 if (bits_per_pixel < valid_dsc_bpp[i + 1]) 584 break; 585 } 586 bits_per_pixel = valid_dsc_bpp[i]; 587 588 /* 589 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, 590 * fractional part is 0 591 */ 592 return bits_per_pixel << 4; 593 } 594 595 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, 596 int mode_clock, int mode_hdisplay, 597 bool bigjoiner) 598 { 599 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 600 u8 min_slice_count, i; 601 int max_slice_width; 602 603 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) 604 min_slice_count = DIV_ROUND_UP(mode_clock, 605 DP_DSC_MAX_ENC_THROUGHPUT_0); 606 else 607 min_slice_count = DIV_ROUND_UP(mode_clock, 608 DP_DSC_MAX_ENC_THROUGHPUT_1); 609 610 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); 611 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { 612 drm_dbg_kms(&i915->drm, 613 "Unsupported slice width %d by DP DSC Sink device\n", 614 max_slice_width); 615 return 0; 616 } 617 /* Also take into account max slice width */ 618 min_slice_count = max_t(u8, min_slice_count, 619 DIV_ROUND_UP(mode_hdisplay, 620 max_slice_width)); 621 622 /* Find the closest match to the valid slice count values */ 623 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { 624 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner; 625 626 if (test_slice_count > 627 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false)) 628 break; 629 630 /* big joiner needs small joiner to be enabled */ 631 if (bigjoiner && test_slice_count < 4) 632 continue; 633 634 if (min_slice_count <= test_slice_count) 635 return test_slice_count; 636 } 637 638 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n", 639 min_slice_count); 640 return 0; 641 } 642 643 static enum intel_output_format 644 intel_dp_output_format(struct drm_connector *connector, 645 const struct drm_display_mode *mode) 646 { 647 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 648 const struct drm_display_info *info = &connector->display_info; 649 650 if (!connector->ycbcr_420_allowed || 651 !drm_mode_is_420_only(info, mode)) 652 return INTEL_OUTPUT_FORMAT_RGB; 653 654 if (intel_dp->dfp.ycbcr_444_to_420) 655 return INTEL_OUTPUT_FORMAT_YCBCR444; 656 else 657 return INTEL_OUTPUT_FORMAT_YCBCR420; 658 } 659 660 int intel_dp_min_bpp(enum intel_output_format output_format) 661 { 662 if (output_format == INTEL_OUTPUT_FORMAT_RGB) 663 return 6 * 3; 664 else 665 return 8 * 3; 666 } 667 668 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) 669 { 670 /* 671 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output 672 * format of the number of bytes per pixel will be half the number 673 * of bytes of RGB pixel. 674 */ 675 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 676 bpp /= 2; 677 678 return bpp; 679 } 680 681 static int 682 intel_dp_mode_min_output_bpp(struct drm_connector *connector, 683 const struct drm_display_mode *mode) 684 { 685 enum intel_output_format output_format = 686 intel_dp_output_format(connector, mode); 687 688 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); 689 } 690 691 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv, 692 int hdisplay) 693 { 694 /* 695 * Older platforms don't like hdisplay==4096 with DP. 696 * 697 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline 698 * and frame counter increment), but we don't get vblank interrupts, 699 * and the pipe underruns immediately. The link also doesn't seem 700 * to get trained properly. 701 * 702 * On CHV the vblank interrupts don't seem to disappear but 703 * otherwise the symptoms are similar. 704 * 705 * TODO: confirm the behaviour on HSW+ 706 */ 707 return hdisplay == 4096 && !HAS_DDI(dev_priv); 708 } 709 710 static enum drm_mode_status 711 intel_dp_mode_valid_downstream(struct intel_connector *connector, 712 const struct drm_display_mode *mode, 713 int target_clock) 714 { 715 struct intel_dp *intel_dp = intel_attached_dp(connector); 716 const struct drm_display_info *info = &connector->base.display_info; 717 int tmds_clock; 718 719 if (intel_dp->dfp.max_dotclock && 720 target_clock > intel_dp->dfp.max_dotclock) 721 return MODE_CLOCK_HIGH; 722 723 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ 724 tmds_clock = target_clock; 725 if (drm_mode_is_420_only(info, mode)) 726 tmds_clock /= 2; 727 728 if (intel_dp->dfp.min_tmds_clock && 729 tmds_clock < intel_dp->dfp.min_tmds_clock) 730 return MODE_CLOCK_LOW; 731 if (intel_dp->dfp.max_tmds_clock && 732 tmds_clock > intel_dp->dfp.max_tmds_clock) 733 return MODE_CLOCK_HIGH; 734 735 return MODE_OK; 736 } 737 738 static enum drm_mode_status 739 intel_dp_mode_valid(struct drm_connector *connector, 740 struct drm_display_mode *mode) 741 { 742 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 743 struct intel_connector *intel_connector = to_intel_connector(connector); 744 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 745 struct drm_i915_private *dev_priv = to_i915(connector->dev); 746 int target_clock = mode->clock; 747 int max_rate, mode_rate, max_lanes, max_link_clock; 748 int max_dotclk = dev_priv->max_dotclk_freq; 749 u16 dsc_max_output_bpp = 0; 750 u8 dsc_slice_count = 0; 751 enum drm_mode_status status; 752 bool dsc = false, bigjoiner = false; 753 754 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 755 return MODE_NO_DBLESCAN; 756 757 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 758 return MODE_H_ILLEGAL; 759 760 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 761 if (mode->hdisplay > fixed_mode->hdisplay) 762 return MODE_PANEL; 763 764 if (mode->vdisplay > fixed_mode->vdisplay) 765 return MODE_PANEL; 766 767 target_clock = fixed_mode->clock; 768 } 769 770 if (mode->clock < 10000) 771 return MODE_CLOCK_LOW; 772 773 if ((target_clock > max_dotclk || mode->hdisplay > 5120) && 774 intel_dp_can_bigjoiner(intel_dp)) { 775 bigjoiner = true; 776 max_dotclk *= 2; 777 } 778 if (target_clock > max_dotclk) 779 return MODE_CLOCK_HIGH; 780 781 max_link_clock = intel_dp_max_link_rate(intel_dp); 782 max_lanes = intel_dp_max_lane_count(intel_dp); 783 784 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 785 mode_rate = intel_dp_link_required(target_clock, 786 intel_dp_mode_min_output_bpp(connector, mode)); 787 788 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) 789 return MODE_H_ILLEGAL; 790 791 /* 792 * Output bpp is stored in 6.4 format so right shift by 4 to get the 793 * integer value since we support only integer values of bpp. 794 */ 795 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) && 796 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { 797 if (intel_dp_is_edp(intel_dp)) { 798 dsc_max_output_bpp = 799 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; 800 dsc_slice_count = 801 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, 802 true); 803 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { 804 dsc_max_output_bpp = 805 intel_dp_dsc_get_output_bpp(dev_priv, 806 max_link_clock, 807 max_lanes, 808 target_clock, 809 mode->hdisplay, 810 bigjoiner) >> 4; 811 dsc_slice_count = 812 intel_dp_dsc_get_slice_count(intel_dp, 813 target_clock, 814 mode->hdisplay, 815 bigjoiner); 816 } 817 818 dsc = dsc_max_output_bpp && dsc_slice_count; 819 } 820 821 /* big joiner configuration needs DSC */ 822 if (bigjoiner && !dsc) 823 return MODE_CLOCK_HIGH; 824 825 if (mode_rate > max_rate && !dsc) 826 return MODE_CLOCK_HIGH; 827 828 status = intel_dp_mode_valid_downstream(intel_connector, 829 mode, target_clock); 830 if (status != MODE_OK) 831 return status; 832 833 return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner); 834 } 835 836 u32 intel_dp_pack_aux(const u8 *src, int src_bytes) 837 { 838 int i; 839 u32 v = 0; 840 841 if (src_bytes > 4) 842 src_bytes = 4; 843 for (i = 0; i < src_bytes; i++) 844 v |= ((u32)src[i]) << ((3 - i) * 8); 845 return v; 846 } 847 848 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes) 849 { 850 int i; 851 if (dst_bytes > 4) 852 dst_bytes = 4; 853 for (i = 0; i < dst_bytes; i++) 854 dst[i] = src >> ((3-i) * 8); 855 } 856 857 static void 858 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp); 859 static void 860 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, 861 bool force_disable_vdd); 862 static void 863 intel_dp_pps_init(struct intel_dp *intel_dp); 864 865 static intel_wakeref_t 866 pps_lock(struct intel_dp *intel_dp) 867 { 868 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 869 intel_wakeref_t wakeref; 870 871 /* 872 * See intel_power_sequencer_reset() why we need 873 * a power domain reference here. 874 */ 875 wakeref = intel_display_power_get(dev_priv, 876 intel_aux_power_domain(dp_to_dig_port(intel_dp))); 877 878 mutex_lock(&dev_priv->pps_mutex); 879 880 return wakeref; 881 } 882 883 static intel_wakeref_t 884 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref) 885 { 886 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 887 888 mutex_unlock(&dev_priv->pps_mutex); 889 intel_display_power_put(dev_priv, 890 intel_aux_power_domain(dp_to_dig_port(intel_dp)), 891 wakeref); 892 return 0; 893 } 894 895 #define with_pps_lock(dp, wf) \ 896 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf))) 897 898 static void 899 vlv_power_sequencer_kick(struct intel_dp *intel_dp) 900 { 901 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 902 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 903 enum pipe pipe = intel_dp->pps_pipe; 904 bool pll_enabled, release_cl_override = false; 905 enum dpio_phy phy = DPIO_PHY(pipe); 906 enum dpio_channel ch = vlv_pipe_to_channel(pipe); 907 u32 DP; 908 909 if (drm_WARN(&dev_priv->drm, 910 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, 911 "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", 912 pipe_name(pipe), dig_port->base.base.base.id, 913 dig_port->base.base.name)) 914 return; 915 916 drm_dbg_kms(&dev_priv->drm, 917 "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", 918 pipe_name(pipe), dig_port->base.base.base.id, 919 dig_port->base.base.name); 920 921 /* Preserve the BIOS-computed detected bit. This is 922 * supposed to be read-only. 923 */ 924 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; 925 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 926 DP |= DP_PORT_WIDTH(1); 927 DP |= DP_LINK_TRAIN_PAT_1; 928 929 if (IS_CHERRYVIEW(dev_priv)) 930 DP |= DP_PIPE_SEL_CHV(pipe); 931 else 932 DP |= DP_PIPE_SEL(pipe); 933 934 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; 935 936 /* 937 * The DPLL for the pipe must be enabled for this to work. 938 * So enable temporarily it if it's not already enabled. 939 */ 940 if (!pll_enabled) { 941 release_cl_override = IS_CHERRYVIEW(dev_priv) && 942 !chv_phy_powergate_ch(dev_priv, phy, ch, true); 943 944 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? 945 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { 946 drm_err(&dev_priv->drm, 947 "Failed to force on pll for pipe %c!\n", 948 pipe_name(pipe)); 949 return; 950 } 951 } 952 953 /* 954 * Similar magic as in intel_dp_enable_port(). 955 * We _must_ do this port enable + disable trick 956 * to make this power sequencer lock onto the port. 957 * Otherwise even VDD force bit won't work. 958 */ 959 intel_de_write(dev_priv, intel_dp->output_reg, DP); 960 intel_de_posting_read(dev_priv, intel_dp->output_reg); 961 962 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN); 963 intel_de_posting_read(dev_priv, intel_dp->output_reg); 964 965 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN); 966 intel_de_posting_read(dev_priv, intel_dp->output_reg); 967 968 if (!pll_enabled) { 969 vlv_force_pll_off(dev_priv, pipe); 970 971 if (release_cl_override) 972 chv_phy_powergate_ch(dev_priv, phy, ch, false); 973 } 974 } 975 976 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) 977 { 978 struct intel_encoder *encoder; 979 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); 980 981 /* 982 * We don't have power sequencer currently. 983 * Pick one that's not used by other ports. 984 */ 985 for_each_intel_dp(&dev_priv->drm, encoder) { 986 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 987 988 if (encoder->type == INTEL_OUTPUT_EDP) { 989 drm_WARN_ON(&dev_priv->drm, 990 intel_dp->active_pipe != INVALID_PIPE && 991 intel_dp->active_pipe != 992 intel_dp->pps_pipe); 993 994 if (intel_dp->pps_pipe != INVALID_PIPE) 995 pipes &= ~(1 << intel_dp->pps_pipe); 996 } else { 997 drm_WARN_ON(&dev_priv->drm, 998 intel_dp->pps_pipe != INVALID_PIPE); 999 1000 if (intel_dp->active_pipe != INVALID_PIPE) 1001 pipes &= ~(1 << intel_dp->active_pipe); 1002 } 1003 } 1004 1005 if (pipes == 0) 1006 return INVALID_PIPE; 1007 1008 return ffs(pipes) - 1; 1009 } 1010 1011 static enum pipe 1012 vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 1013 { 1014 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1015 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1016 enum pipe pipe; 1017 1018 lockdep_assert_held(&dev_priv->pps_mutex); 1019 1020 /* We should never land here with regular DP ports */ 1021 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); 1022 1023 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE && 1024 intel_dp->active_pipe != intel_dp->pps_pipe); 1025 1026 if (intel_dp->pps_pipe != INVALID_PIPE) 1027 return intel_dp->pps_pipe; 1028 1029 pipe = vlv_find_free_pps(dev_priv); 1030 1031 /* 1032 * Didn't find one. This should not happen since there 1033 * are two power sequencers and up to two eDP ports. 1034 */ 1035 if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE)) 1036 pipe = PIPE_A; 1037 1038 vlv_steal_power_sequencer(dev_priv, pipe); 1039 intel_dp->pps_pipe = pipe; 1040 1041 drm_dbg_kms(&dev_priv->drm, 1042 "picked pipe %c power sequencer for [ENCODER:%d:%s]\n", 1043 pipe_name(intel_dp->pps_pipe), 1044 dig_port->base.base.base.id, 1045 dig_port->base.base.name); 1046 1047 /* init power sequencer on this pipe and port */ 1048 intel_dp_init_panel_power_sequencer(intel_dp); 1049 intel_dp_init_panel_power_sequencer_registers(intel_dp, true); 1050 1051 /* 1052 * Even vdd force doesn't work until we've made 1053 * the power sequencer lock in on the port. 1054 */ 1055 vlv_power_sequencer_kick(intel_dp); 1056 1057 return intel_dp->pps_pipe; 1058 } 1059 1060 static int 1061 bxt_power_sequencer_idx(struct intel_dp *intel_dp) 1062 { 1063 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1064 int backlight_controller = dev_priv->vbt.backlight.controller; 1065 1066 lockdep_assert_held(&dev_priv->pps_mutex); 1067 1068 /* We should never land here with regular DP ports */ 1069 drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); 1070 1071 if (!intel_dp->pps_reset) 1072 return backlight_controller; 1073 1074 intel_dp->pps_reset = false; 1075 1076 /* 1077 * Only the HW needs to be reprogrammed, the SW state is fixed and 1078 * has been setup during connector init. 1079 */ 1080 intel_dp_init_panel_power_sequencer_registers(intel_dp, false); 1081 1082 return backlight_controller; 1083 } 1084 1085 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, 1086 enum pipe pipe); 1087 1088 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, 1089 enum pipe pipe) 1090 { 1091 return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; 1092 } 1093 1094 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, 1095 enum pipe pipe) 1096 { 1097 return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD; 1098 } 1099 1100 static bool vlv_pipe_any(struct drm_i915_private *dev_priv, 1101 enum pipe pipe) 1102 { 1103 return true; 1104 } 1105 1106 static enum pipe 1107 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, 1108 enum port port, 1109 vlv_pipe_check pipe_check) 1110 { 1111 enum pipe pipe; 1112 1113 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 1114 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & 1115 PANEL_PORT_SELECT_MASK; 1116 1117 if (port_sel != PANEL_PORT_SELECT_VLV(port)) 1118 continue; 1119 1120 if (!pipe_check(dev_priv, pipe)) 1121 continue; 1122 1123 return pipe; 1124 } 1125 1126 return INVALID_PIPE; 1127 } 1128 1129 static void 1130 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) 1131 { 1132 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1133 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1134 enum port port = dig_port->base.port; 1135 1136 lockdep_assert_held(&dev_priv->pps_mutex); 1137 1138 /* try to find a pipe with this port selected */ 1139 /* first pick one where the panel is on */ 1140 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 1141 vlv_pipe_has_pp_on); 1142 /* didn't find one? pick one where vdd is on */ 1143 if (intel_dp->pps_pipe == INVALID_PIPE) 1144 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 1145 vlv_pipe_has_vdd_on); 1146 /* didn't find one? pick one with just the correct port */ 1147 if (intel_dp->pps_pipe == INVALID_PIPE) 1148 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 1149 vlv_pipe_any); 1150 1151 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ 1152 if (intel_dp->pps_pipe == INVALID_PIPE) { 1153 drm_dbg_kms(&dev_priv->drm, 1154 "no initial power sequencer for [ENCODER:%d:%s]\n", 1155 dig_port->base.base.base.id, 1156 dig_port->base.base.name); 1157 return; 1158 } 1159 1160 drm_dbg_kms(&dev_priv->drm, 1161 "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", 1162 dig_port->base.base.base.id, 1163 dig_port->base.base.name, 1164 pipe_name(intel_dp->pps_pipe)); 1165 1166 intel_dp_init_panel_power_sequencer(intel_dp); 1167 intel_dp_init_panel_power_sequencer_registers(intel_dp, false); 1168 } 1169 1170 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) 1171 { 1172 struct intel_encoder *encoder; 1173 1174 if (drm_WARN_ON(&dev_priv->drm, 1175 !(IS_VALLEYVIEW(dev_priv) || 1176 IS_CHERRYVIEW(dev_priv) || 1177 IS_GEN9_LP(dev_priv)))) 1178 return; 1179 1180 /* 1181 * We can't grab pps_mutex here due to deadlock with power_domain 1182 * mutex when power_domain functions are called while holding pps_mutex. 1183 * That also means that in order to use pps_pipe the code needs to 1184 * hold both a power domain reference and pps_mutex, and the power domain 1185 * reference get/put must be done while _not_ holding pps_mutex. 1186 * pps_{lock,unlock}() do these steps in the correct order, so one 1187 * should use them always. 1188 */ 1189 1190 for_each_intel_dp(&dev_priv->drm, encoder) { 1191 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1192 1193 drm_WARN_ON(&dev_priv->drm, 1194 intel_dp->active_pipe != INVALID_PIPE); 1195 1196 if (encoder->type != INTEL_OUTPUT_EDP) 1197 continue; 1198 1199 if (IS_GEN9_LP(dev_priv)) 1200 intel_dp->pps_reset = true; 1201 else 1202 intel_dp->pps_pipe = INVALID_PIPE; 1203 } 1204 } 1205 1206 struct pps_registers { 1207 i915_reg_t pp_ctrl; 1208 i915_reg_t pp_stat; 1209 i915_reg_t pp_on; 1210 i915_reg_t pp_off; 1211 i915_reg_t pp_div; 1212 }; 1213 1214 static void intel_pps_get_registers(struct intel_dp *intel_dp, 1215 struct pps_registers *regs) 1216 { 1217 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1218 int pps_idx = 0; 1219 1220 memset(regs, 0, sizeof(*regs)); 1221 1222 if (IS_GEN9_LP(dev_priv)) 1223 pps_idx = bxt_power_sequencer_idx(intel_dp); 1224 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1225 pps_idx = vlv_power_sequencer_pipe(intel_dp); 1226 1227 regs->pp_ctrl = PP_CONTROL(pps_idx); 1228 regs->pp_stat = PP_STATUS(pps_idx); 1229 regs->pp_on = PP_ON_DELAYS(pps_idx); 1230 regs->pp_off = PP_OFF_DELAYS(pps_idx); 1231 1232 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ 1233 if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 1234 regs->pp_div = INVALID_MMIO_REG; 1235 else 1236 regs->pp_div = PP_DIVISOR(pps_idx); 1237 } 1238 1239 static i915_reg_t 1240 _pp_ctrl_reg(struct intel_dp *intel_dp) 1241 { 1242 struct pps_registers regs; 1243 1244 intel_pps_get_registers(intel_dp, ®s); 1245 1246 return regs.pp_ctrl; 1247 } 1248 1249 static i915_reg_t 1250 _pp_stat_reg(struct intel_dp *intel_dp) 1251 { 1252 struct pps_registers regs; 1253 1254 intel_pps_get_registers(intel_dp, ®s); 1255 1256 return regs.pp_stat; 1257 } 1258 1259 static bool edp_have_panel_power(struct intel_dp *intel_dp) 1260 { 1261 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1262 1263 lockdep_assert_held(&dev_priv->pps_mutex); 1264 1265 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1266 intel_dp->pps_pipe == INVALID_PIPE) 1267 return false; 1268 1269 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; 1270 } 1271 1272 static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 1273 { 1274 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1275 1276 lockdep_assert_held(&dev_priv->pps_mutex); 1277 1278 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1279 intel_dp->pps_pipe == INVALID_PIPE) 1280 return false; 1281 1282 return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; 1283 } 1284 1285 static void 1286 intel_dp_check_edp(struct intel_dp *intel_dp) 1287 { 1288 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1289 1290 if (!intel_dp_is_edp(intel_dp)) 1291 return; 1292 1293 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 1294 drm_WARN(&dev_priv->drm, 1, 1295 "eDP powered off while attempting aux channel communication.\n"); 1296 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n", 1297 intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), 1298 intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp))); 1299 } 1300 } 1301 1302 static u32 1303 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 1304 { 1305 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1306 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 1307 const unsigned int timeout_ms = 10; 1308 u32 status; 1309 bool done; 1310 1311 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 1312 done = wait_event_timeout(i915->gmbus_wait_queue, C, 1313 msecs_to_jiffies_timeout(timeout_ms)); 1314 1315 /* just trace the final value */ 1316 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 1317 1318 if (!done) 1319 drm_err(&i915->drm, 1320 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 1321 intel_dp->aux.name, timeout_ms, status); 1322 #undef C 1323 1324 return status; 1325 } 1326 1327 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 1328 { 1329 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1330 1331 if (index) 1332 return 0; 1333 1334 /* 1335 * The clock divider is based off the hrawclk, and would like to run at 1336 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 1337 */ 1338 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000); 1339 } 1340 1341 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 1342 { 1343 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1344 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1345 u32 freq; 1346 1347 if (index) 1348 return 0; 1349 1350 /* 1351 * The clock divider is based off the cdclk or PCH rawclk, and would 1352 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 1353 * divide by 2000 and use that 1354 */ 1355 if (dig_port->aux_ch == AUX_CH_A) 1356 freq = dev_priv->cdclk.hw.cdclk; 1357 else 1358 freq = RUNTIME_INFO(dev_priv)->rawclk_freq; 1359 return DIV_ROUND_CLOSEST(freq, 2000); 1360 } 1361 1362 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 1363 { 1364 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1365 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1366 1367 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { 1368 /* Workaround for non-ULT HSW */ 1369 switch (index) { 1370 case 0: return 63; 1371 case 1: return 72; 1372 default: return 0; 1373 } 1374 } 1375 1376 return ilk_get_aux_clock_divider(intel_dp, index); 1377 } 1378 1379 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 1380 { 1381 /* 1382 * SKL doesn't need us to program the AUX clock divider (Hardware will 1383 * derive the clock from CDCLK automatically). We still implement the 1384 * get_aux_clock_divider vfunc to plug-in into the existing code. 1385 */ 1386 return index ? 0 : 1; 1387 } 1388 1389 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 1390 int send_bytes, 1391 u32 aux_clock_divider) 1392 { 1393 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1394 struct drm_i915_private *dev_priv = 1395 to_i915(dig_port->base.base.dev); 1396 u32 precharge, timeout; 1397 1398 if (IS_GEN(dev_priv, 6)) 1399 precharge = 3; 1400 else 1401 precharge = 5; 1402 1403 if (IS_BROADWELL(dev_priv)) 1404 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 1405 else 1406 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 1407 1408 return DP_AUX_CH_CTL_SEND_BUSY | 1409 DP_AUX_CH_CTL_DONE | 1410 DP_AUX_CH_CTL_INTERRUPT | 1411 DP_AUX_CH_CTL_TIME_OUT_ERROR | 1412 timeout | 1413 DP_AUX_CH_CTL_RECEIVE_ERROR | 1414 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1415 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1416 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 1417 } 1418 1419 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 1420 int send_bytes, 1421 u32 unused) 1422 { 1423 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1424 struct drm_i915_private *i915 = 1425 to_i915(dig_port->base.base.dev); 1426 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 1427 u32 ret; 1428 1429 ret = DP_AUX_CH_CTL_SEND_BUSY | 1430 DP_AUX_CH_CTL_DONE | 1431 DP_AUX_CH_CTL_INTERRUPT | 1432 DP_AUX_CH_CTL_TIME_OUT_ERROR | 1433 DP_AUX_CH_CTL_TIME_OUT_MAX | 1434 DP_AUX_CH_CTL_RECEIVE_ERROR | 1435 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1436 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 1437 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 1438 1439 if (intel_phy_is_tc(i915, phy) && 1440 dig_port->tc_mode == TC_PORT_TBT_ALT) 1441 ret |= DP_AUX_CH_CTL_TBT_IO; 1442 1443 return ret; 1444 } 1445 1446 static int 1447 intel_dp_aux_xfer(struct intel_dp *intel_dp, 1448 const u8 *send, int send_bytes, 1449 u8 *recv, int recv_size, 1450 u32 aux_send_ctl_flags) 1451 { 1452 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1453 struct drm_i915_private *i915 = 1454 to_i915(dig_port->base.base.dev); 1455 struct intel_uncore *uncore = &i915->uncore; 1456 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 1457 bool is_tc_port = intel_phy_is_tc(i915, phy); 1458 i915_reg_t ch_ctl, ch_data[5]; 1459 u32 aux_clock_divider; 1460 enum intel_display_power_domain aux_domain; 1461 intel_wakeref_t aux_wakeref; 1462 intel_wakeref_t pps_wakeref; 1463 int i, ret, recv_bytes; 1464 int try, clock = 0; 1465 u32 status; 1466 bool vdd; 1467 1468 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 1469 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 1470 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 1471 1472 if (is_tc_port) 1473 intel_tc_port_lock(dig_port); 1474 1475 aux_domain = intel_aux_power_domain(dig_port); 1476 1477 aux_wakeref = intel_display_power_get(i915, aux_domain); 1478 pps_wakeref = pps_lock(intel_dp); 1479 1480 /* 1481 * We will be called with VDD already enabled for dpcd/edid/oui reads. 1482 * In such cases we want to leave VDD enabled and it's up to upper layers 1483 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 1484 * ourselves. 1485 */ 1486 vdd = edp_panel_vdd_on(intel_dp); 1487 1488 /* dp aux is extremely sensitive to irq latency, hence request the 1489 * lowest possible wakeup latency and so prevent the cpu from going into 1490 * deep sleep states. 1491 */ 1492 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 1493 1494 intel_dp_check_edp(intel_dp); 1495 1496 /* Try to wait for any previous AUX channel activity */ 1497 for (try = 0; try < 3; try++) { 1498 status = intel_uncore_read_notrace(uncore, ch_ctl); 1499 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 1500 break; 1501 msleep(1); 1502 } 1503 /* just trace the final value */ 1504 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 1505 1506 if (try == 3) { 1507 const u32 status = intel_uncore_read(uncore, ch_ctl); 1508 1509 if (status != intel_dp->aux_busy_last_status) { 1510 drm_WARN(&i915->drm, 1, 1511 "%s: not started (status 0x%08x)\n", 1512 intel_dp->aux.name, status); 1513 intel_dp->aux_busy_last_status = status; 1514 } 1515 1516 ret = -EBUSY; 1517 goto out; 1518 } 1519 1520 /* Only 5 data registers! */ 1521 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { 1522 ret = -E2BIG; 1523 goto out; 1524 } 1525 1526 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 1527 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 1528 send_bytes, 1529 aux_clock_divider); 1530 1531 send_ctl |= aux_send_ctl_flags; 1532 1533 /* Must try at least 3 times according to DP spec */ 1534 for (try = 0; try < 5; try++) { 1535 /* Load the send data into the aux channel data registers */ 1536 for (i = 0; i < send_bytes; i += 4) 1537 intel_uncore_write(uncore, 1538 ch_data[i >> 2], 1539 intel_dp_pack_aux(send + i, 1540 send_bytes - i)); 1541 1542 /* Send the command and wait for it to complete */ 1543 intel_uncore_write(uncore, ch_ctl, send_ctl); 1544 1545 status = intel_dp_aux_wait_done(intel_dp); 1546 1547 /* Clear done status and any errors */ 1548 intel_uncore_write(uncore, 1549 ch_ctl, 1550 status | 1551 DP_AUX_CH_CTL_DONE | 1552 DP_AUX_CH_CTL_TIME_OUT_ERROR | 1553 DP_AUX_CH_CTL_RECEIVE_ERROR); 1554 1555 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 1556 * 400us delay required for errors and timeouts 1557 * Timeout errors from the HW already meet this 1558 * requirement so skip to next iteration 1559 */ 1560 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 1561 continue; 1562 1563 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 1564 usleep_range(400, 500); 1565 continue; 1566 } 1567 if (status & DP_AUX_CH_CTL_DONE) 1568 goto done; 1569 } 1570 } 1571 1572 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 1573 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", 1574 intel_dp->aux.name, status); 1575 ret = -EBUSY; 1576 goto out; 1577 } 1578 1579 done: 1580 /* Check for timeout or receive error. 1581 * Timeouts occur when the sink is not connected 1582 */ 1583 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 1584 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", 1585 intel_dp->aux.name, status); 1586 ret = -EIO; 1587 goto out; 1588 } 1589 1590 /* Timeouts occur when the device isn't connected, so they're 1591 * "normal" -- don't fill the kernel log with these */ 1592 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 1593 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", 1594 intel_dp->aux.name, status); 1595 ret = -ETIMEDOUT; 1596 goto out; 1597 } 1598 1599 /* Unload any bytes sent back from the other side */ 1600 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 1601 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 1602 1603 /* 1604 * By BSpec: "Message sizes of 0 or >20 are not allowed." 1605 * We have no idea of what happened so we return -EBUSY so 1606 * drm layer takes care for the necessary retries. 1607 */ 1608 if (recv_bytes == 0 || recv_bytes > 20) { 1609 drm_dbg_kms(&i915->drm, 1610 "%s: Forbidden recv_bytes = %d on aux transaction\n", 1611 intel_dp->aux.name, recv_bytes); 1612 ret = -EBUSY; 1613 goto out; 1614 } 1615 1616 if (recv_bytes > recv_size) 1617 recv_bytes = recv_size; 1618 1619 for (i = 0; i < recv_bytes; i += 4) 1620 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]), 1621 recv + i, recv_bytes - i); 1622 1623 ret = recv_bytes; 1624 out: 1625 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 1626 1627 if (vdd) 1628 edp_panel_vdd_off(intel_dp, false); 1629 1630 pps_unlock(intel_dp, pps_wakeref); 1631 intel_display_power_put_async(i915, aux_domain, aux_wakeref); 1632 1633 if (is_tc_port) 1634 intel_tc_port_unlock(dig_port); 1635 1636 return ret; 1637 } 1638 1639 #define BARE_ADDRESS_SIZE 3 1640 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 1641 1642 static void 1643 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 1644 const struct drm_dp_aux_msg *msg) 1645 { 1646 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 1647 txbuf[1] = (msg->address >> 8) & 0xff; 1648 txbuf[2] = msg->address & 0xff; 1649 txbuf[3] = msg->size - 1; 1650 } 1651 1652 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 1653 { 1654 /* 1655 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 1656 * select bit to inform the hardware to send the Aksv after our header 1657 * since we can't access that data from software. 1658 */ 1659 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 1660 msg->address == DP_AUX_HDCP_AKSV) 1661 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 1662 1663 return 0; 1664 } 1665 1666 static ssize_t 1667 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1668 { 1669 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 1670 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1671 u8 txbuf[20], rxbuf[20]; 1672 size_t txsize, rxsize; 1673 u32 flags = intel_dp_aux_xfer_flags(msg); 1674 int ret; 1675 1676 intel_dp_aux_header(txbuf, msg); 1677 1678 switch (msg->request & ~DP_AUX_I2C_MOT) { 1679 case DP_AUX_NATIVE_WRITE: 1680 case DP_AUX_I2C_WRITE: 1681 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 1682 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 1683 rxsize = 2; /* 0 or 1 data bytes */ 1684 1685 if (drm_WARN_ON(&i915->drm, txsize > 20)) 1686 return -E2BIG; 1687 1688 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size); 1689 1690 if (msg->buffer) 1691 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 1692 1693 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 1694 rxbuf, rxsize, flags); 1695 if (ret > 0) { 1696 msg->reply = rxbuf[0] >> 4; 1697 1698 if (ret > 1) { 1699 /* Number of bytes written in a short write. */ 1700 ret = clamp_t(int, rxbuf[1], 0, msg->size); 1701 } else { 1702 /* Return payload size. */ 1703 ret = msg->size; 1704 } 1705 } 1706 break; 1707 1708 case DP_AUX_NATIVE_READ: 1709 case DP_AUX_I2C_READ: 1710 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 1711 rxsize = msg->size + 1; 1712 1713 if (drm_WARN_ON(&i915->drm, rxsize > 20)) 1714 return -E2BIG; 1715 1716 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 1717 rxbuf, rxsize, flags); 1718 if (ret > 0) { 1719 msg->reply = rxbuf[0] >> 4; 1720 /* 1721 * Assume happy day, and copy the data. The caller is 1722 * expected to check msg->reply before touching it. 1723 * 1724 * Return payload size. 1725 */ 1726 ret--; 1727 memcpy(msg->buffer, rxbuf + 1, ret); 1728 } 1729 break; 1730 1731 default: 1732 ret = -EINVAL; 1733 break; 1734 } 1735 1736 return ret; 1737 } 1738 1739 1740 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 1741 { 1742 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1743 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1744 enum aux_ch aux_ch = dig_port->aux_ch; 1745 1746 switch (aux_ch) { 1747 case AUX_CH_B: 1748 case AUX_CH_C: 1749 case AUX_CH_D: 1750 return DP_AUX_CH_CTL(aux_ch); 1751 default: 1752 MISSING_CASE(aux_ch); 1753 return DP_AUX_CH_CTL(AUX_CH_B); 1754 } 1755 } 1756 1757 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 1758 { 1759 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1760 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1761 enum aux_ch aux_ch = dig_port->aux_ch; 1762 1763 switch (aux_ch) { 1764 case AUX_CH_B: 1765 case AUX_CH_C: 1766 case AUX_CH_D: 1767 return DP_AUX_CH_DATA(aux_ch, index); 1768 default: 1769 MISSING_CASE(aux_ch); 1770 return DP_AUX_CH_DATA(AUX_CH_B, index); 1771 } 1772 } 1773 1774 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 1775 { 1776 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1777 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1778 enum aux_ch aux_ch = dig_port->aux_ch; 1779 1780 switch (aux_ch) { 1781 case AUX_CH_A: 1782 return DP_AUX_CH_CTL(aux_ch); 1783 case AUX_CH_B: 1784 case AUX_CH_C: 1785 case AUX_CH_D: 1786 return PCH_DP_AUX_CH_CTL(aux_ch); 1787 default: 1788 MISSING_CASE(aux_ch); 1789 return DP_AUX_CH_CTL(AUX_CH_A); 1790 } 1791 } 1792 1793 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 1794 { 1795 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1796 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1797 enum aux_ch aux_ch = dig_port->aux_ch; 1798 1799 switch (aux_ch) { 1800 case AUX_CH_A: 1801 return DP_AUX_CH_DATA(aux_ch, index); 1802 case AUX_CH_B: 1803 case AUX_CH_C: 1804 case AUX_CH_D: 1805 return PCH_DP_AUX_CH_DATA(aux_ch, index); 1806 default: 1807 MISSING_CASE(aux_ch); 1808 return DP_AUX_CH_DATA(AUX_CH_A, index); 1809 } 1810 } 1811 1812 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 1813 { 1814 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1815 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1816 enum aux_ch aux_ch = dig_port->aux_ch; 1817 1818 switch (aux_ch) { 1819 case AUX_CH_A: 1820 case AUX_CH_B: 1821 case AUX_CH_C: 1822 case AUX_CH_D: 1823 case AUX_CH_E: 1824 case AUX_CH_F: 1825 return DP_AUX_CH_CTL(aux_ch); 1826 default: 1827 MISSING_CASE(aux_ch); 1828 return DP_AUX_CH_CTL(AUX_CH_A); 1829 } 1830 } 1831 1832 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 1833 { 1834 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1835 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1836 enum aux_ch aux_ch = dig_port->aux_ch; 1837 1838 switch (aux_ch) { 1839 case AUX_CH_A: 1840 case AUX_CH_B: 1841 case AUX_CH_C: 1842 case AUX_CH_D: 1843 case AUX_CH_E: 1844 case AUX_CH_F: 1845 return DP_AUX_CH_DATA(aux_ch, index); 1846 default: 1847 MISSING_CASE(aux_ch); 1848 return DP_AUX_CH_DATA(AUX_CH_A, index); 1849 } 1850 } 1851 1852 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 1853 { 1854 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1855 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1856 enum aux_ch aux_ch = dig_port->aux_ch; 1857 1858 switch (aux_ch) { 1859 case AUX_CH_A: 1860 case AUX_CH_B: 1861 case AUX_CH_C: 1862 case AUX_CH_USBC1: 1863 case AUX_CH_USBC2: 1864 case AUX_CH_USBC3: 1865 case AUX_CH_USBC4: 1866 case AUX_CH_USBC5: 1867 case AUX_CH_USBC6: 1868 return DP_AUX_CH_CTL(aux_ch); 1869 default: 1870 MISSING_CASE(aux_ch); 1871 return DP_AUX_CH_CTL(AUX_CH_A); 1872 } 1873 } 1874 1875 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 1876 { 1877 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1878 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1879 enum aux_ch aux_ch = dig_port->aux_ch; 1880 1881 switch (aux_ch) { 1882 case AUX_CH_A: 1883 case AUX_CH_B: 1884 case AUX_CH_C: 1885 case AUX_CH_USBC1: 1886 case AUX_CH_USBC2: 1887 case AUX_CH_USBC3: 1888 case AUX_CH_USBC4: 1889 case AUX_CH_USBC5: 1890 case AUX_CH_USBC6: 1891 return DP_AUX_CH_DATA(aux_ch, index); 1892 default: 1893 MISSING_CASE(aux_ch); 1894 return DP_AUX_CH_DATA(AUX_CH_A, index); 1895 } 1896 } 1897 1898 static void 1899 intel_dp_aux_fini(struct intel_dp *intel_dp) 1900 { 1901 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 1902 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 1903 1904 kfree(intel_dp->aux.name); 1905 } 1906 1907 static void 1908 intel_dp_aux_init(struct intel_dp *intel_dp) 1909 { 1910 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1911 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1912 struct intel_encoder *encoder = &dig_port->base; 1913 enum aux_ch aux_ch = dig_port->aux_ch; 1914 1915 if (INTEL_GEN(dev_priv) >= 12) { 1916 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 1917 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 1918 } else if (INTEL_GEN(dev_priv) >= 9) { 1919 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 1920 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 1921 } else if (HAS_PCH_SPLIT(dev_priv)) { 1922 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 1923 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 1924 } else { 1925 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 1926 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 1927 } 1928 1929 if (INTEL_GEN(dev_priv) >= 9) 1930 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 1931 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 1932 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 1933 else if (HAS_PCH_SPLIT(dev_priv)) 1934 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 1935 else 1936 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 1937 1938 if (INTEL_GEN(dev_priv) >= 9) 1939 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 1940 else 1941 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 1942 1943 drm_dp_aux_init(&intel_dp->aux); 1944 1945 /* Failure to allocate our preferred name is not critical */ 1946 if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) 1947 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s", 1948 aux_ch - AUX_CH_USBC1 + '1', 1949 encoder->base.name); 1950 else 1951 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 1952 aux_ch_name(aux_ch), 1953 encoder->base.name); 1954 1955 intel_dp->aux.transfer = intel_dp_aux_transfer; 1956 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 1957 } 1958 1959 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) 1960 { 1961 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; 1962 1963 return max_rate >= 540000; 1964 } 1965 1966 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp) 1967 { 1968 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; 1969 1970 return max_rate >= 810000; 1971 } 1972 1973 static void 1974 intel_dp_set_clock(struct intel_encoder *encoder, 1975 struct intel_crtc_state *pipe_config) 1976 { 1977 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1978 const struct dp_link_dpll *divisor = NULL; 1979 int i, count = 0; 1980 1981 if (IS_G4X(dev_priv)) { 1982 divisor = g4x_dpll; 1983 count = ARRAY_SIZE(g4x_dpll); 1984 } else if (HAS_PCH_SPLIT(dev_priv)) { 1985 divisor = pch_dpll; 1986 count = ARRAY_SIZE(pch_dpll); 1987 } else if (IS_CHERRYVIEW(dev_priv)) { 1988 divisor = chv_dpll; 1989 count = ARRAY_SIZE(chv_dpll); 1990 } else if (IS_VALLEYVIEW(dev_priv)) { 1991 divisor = vlv_dpll; 1992 count = ARRAY_SIZE(vlv_dpll); 1993 } 1994 1995 if (divisor && count) { 1996 for (i = 0; i < count; i++) { 1997 if (pipe_config->port_clock == divisor[i].clock) { 1998 pipe_config->dpll = divisor[i].dpll; 1999 pipe_config->clock_set = true; 2000 break; 2001 } 2002 } 2003 } 2004 } 2005 2006 static void snprintf_int_array(char *str, size_t len, 2007 const int *array, int nelem) 2008 { 2009 int i; 2010 2011 str[0] = '\0'; 2012 2013 for (i = 0; i < nelem; i++) { 2014 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); 2015 if (r >= len) 2016 return; 2017 str += r; 2018 len -= r; 2019 } 2020 } 2021 2022 static void intel_dp_print_rates(struct intel_dp *intel_dp) 2023 { 2024 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2025 char str[128]; /* FIXME: too big for stack? */ 2026 2027 if (!drm_debug_enabled(DRM_UT_KMS)) 2028 return; 2029 2030 snprintf_int_array(str, sizeof(str), 2031 intel_dp->source_rates, intel_dp->num_source_rates); 2032 drm_dbg_kms(&i915->drm, "source rates: %s\n", str); 2033 2034 snprintf_int_array(str, sizeof(str), 2035 intel_dp->sink_rates, intel_dp->num_sink_rates); 2036 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str); 2037 2038 snprintf_int_array(str, sizeof(str), 2039 intel_dp->common_rates, intel_dp->num_common_rates); 2040 drm_dbg_kms(&i915->drm, "common rates: %s\n", str); 2041 } 2042 2043 int 2044 intel_dp_max_link_rate(struct intel_dp *intel_dp) 2045 { 2046 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2047 int len; 2048 2049 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); 2050 if (drm_WARN_ON(&i915->drm, len <= 0)) 2051 return 162000; 2052 2053 return intel_dp->common_rates[len - 1]; 2054 } 2055 2056 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 2057 { 2058 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2059 int i = intel_dp_rate_index(intel_dp->sink_rates, 2060 intel_dp->num_sink_rates, rate); 2061 2062 if (drm_WARN_ON(&i915->drm, i < 0)) 2063 i = 0; 2064 2065 return i; 2066 } 2067 2068 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 2069 u8 *link_bw, u8 *rate_select) 2070 { 2071 /* eDP 1.4 rate select method. */ 2072 if (intel_dp->use_rate_select) { 2073 *link_bw = 0; 2074 *rate_select = 2075 intel_dp_rate_select(intel_dp, port_clock); 2076 } else { 2077 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 2078 *rate_select = 0; 2079 } 2080 } 2081 2082 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 2083 const struct intel_crtc_state *pipe_config) 2084 { 2085 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2086 2087 /* On TGL, FEC is supported on all Pipes */ 2088 if (INTEL_GEN(dev_priv) >= 12) 2089 return true; 2090 2091 if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A) 2092 return true; 2093 2094 return false; 2095 } 2096 2097 static bool intel_dp_supports_fec(struct intel_dp *intel_dp, 2098 const struct intel_crtc_state *pipe_config) 2099 { 2100 return intel_dp_source_supports_fec(intel_dp, pipe_config) && 2101 drm_dp_sink_supports_fec(intel_dp->fec_capable); 2102 } 2103 2104 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 2105 const struct intel_crtc_state *crtc_state) 2106 { 2107 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable) 2108 return false; 2109 2110 return intel_dsc_source_support(crtc_state) && 2111 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); 2112 } 2113 2114 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp, 2115 const struct intel_crtc_state *crtc_state) 2116 { 2117 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2118 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && 2119 intel_dp->dfp.ycbcr_444_to_420); 2120 } 2121 2122 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp, 2123 const struct intel_crtc_state *crtc_state, int bpc) 2124 { 2125 int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8; 2126 2127 if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) 2128 clock /= 2; 2129 2130 return clock; 2131 } 2132 2133 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp, 2134 const struct intel_crtc_state *crtc_state, int bpc) 2135 { 2136 int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc); 2137 2138 if (intel_dp->dfp.min_tmds_clock && 2139 tmds_clock < intel_dp->dfp.min_tmds_clock) 2140 return false; 2141 2142 if (intel_dp->dfp.max_tmds_clock && 2143 tmds_clock > intel_dp->dfp.max_tmds_clock) 2144 return false; 2145 2146 return true; 2147 } 2148 2149 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp, 2150 const struct intel_crtc_state *crtc_state, 2151 int bpc) 2152 { 2153 2154 return intel_hdmi_deep_color_possible(crtc_state, bpc, 2155 intel_dp->has_hdmi_sink, 2156 intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) && 2157 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc); 2158 } 2159 2160 static int intel_dp_max_bpp(struct intel_dp *intel_dp, 2161 const struct intel_crtc_state *crtc_state) 2162 { 2163 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2164 struct intel_connector *intel_connector = intel_dp->attached_connector; 2165 int bpp, bpc; 2166 2167 bpc = crtc_state->pipe_bpp / 3; 2168 2169 if (intel_dp->dfp.max_bpc) 2170 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); 2171 2172 if (intel_dp->dfp.min_tmds_clock) { 2173 for (; bpc >= 10; bpc -= 2) { 2174 if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc)) 2175 break; 2176 } 2177 } 2178 2179 bpp = bpc * 3; 2180 if (intel_dp_is_edp(intel_dp)) { 2181 /* Get bpp from vbt only for panels that dont have bpp in edid */ 2182 if (intel_connector->base.display_info.bpc == 0 && 2183 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { 2184 drm_dbg_kms(&dev_priv->drm, 2185 "clamping bpp for eDP panel to BIOS-provided %i\n", 2186 dev_priv->vbt.edp.bpp); 2187 bpp = dev_priv->vbt.edp.bpp; 2188 } 2189 } 2190 2191 return bpp; 2192 } 2193 2194 /* Adjust link config limits based on compliance test requests. */ 2195 void 2196 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, 2197 struct intel_crtc_state *pipe_config, 2198 struct link_config_limits *limits) 2199 { 2200 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2201 2202 /* For DP Compliance we override the computed bpp for the pipe */ 2203 if (intel_dp->compliance.test_data.bpc != 0) { 2204 int bpp = 3 * intel_dp->compliance.test_data.bpc; 2205 2206 limits->min_bpp = limits->max_bpp = bpp; 2207 pipe_config->dither_force_disable = bpp == 6 * 3; 2208 2209 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp); 2210 } 2211 2212 /* Use values requested by Compliance Test Request */ 2213 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { 2214 int index; 2215 2216 /* Validate the compliance test data since max values 2217 * might have changed due to link train fallback. 2218 */ 2219 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, 2220 intel_dp->compliance.test_lane_count)) { 2221 index = intel_dp_rate_index(intel_dp->common_rates, 2222 intel_dp->num_common_rates, 2223 intel_dp->compliance.test_link_rate); 2224 if (index >= 0) 2225 limits->min_clock = limits->max_clock = index; 2226 limits->min_lane_count = limits->max_lane_count = 2227 intel_dp->compliance.test_lane_count; 2228 } 2229 } 2230 } 2231 2232 /* Optimize link config in order: max bpp, min clock, min lanes */ 2233 static int 2234 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 2235 struct intel_crtc_state *pipe_config, 2236 const struct link_config_limits *limits) 2237 { 2238 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2239 int bpp, clock, lane_count; 2240 int mode_rate, link_clock, link_avail; 2241 2242 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { 2243 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 2244 2245 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 2246 output_bpp); 2247 2248 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { 2249 for (lane_count = limits->min_lane_count; 2250 lane_count <= limits->max_lane_count; 2251 lane_count <<= 1) { 2252 link_clock = intel_dp->common_rates[clock]; 2253 link_avail = intel_dp_max_data_rate(link_clock, 2254 lane_count); 2255 2256 if (mode_rate <= link_avail) { 2257 pipe_config->lane_count = lane_count; 2258 pipe_config->pipe_bpp = bpp; 2259 pipe_config->port_clock = link_clock; 2260 2261 return 0; 2262 } 2263 } 2264 } 2265 } 2266 2267 return -EINVAL; 2268 } 2269 2270 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) 2271 { 2272 int i, num_bpc; 2273 u8 dsc_bpc[3] = {0}; 2274 2275 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, 2276 dsc_bpc); 2277 for (i = 0; i < num_bpc; i++) { 2278 if (dsc_max_bpc >= dsc_bpc[i]) 2279 return dsc_bpc[i] * 3; 2280 } 2281 2282 return 0; 2283 } 2284 2285 #define DSC_SUPPORTED_VERSION_MIN 1 2286 2287 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, 2288 struct intel_crtc_state *crtc_state) 2289 { 2290 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2291 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2292 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 2293 u8 line_buf_depth; 2294 int ret; 2295 2296 ret = intel_dsc_compute_params(encoder, crtc_state); 2297 if (ret) 2298 return ret; 2299 2300 /* 2301 * Slice Height of 8 works for all currently available panels. So start 2302 * with that if pic_height is an integral multiple of 8. Eventually add 2303 * logic to try multiple slice heights. 2304 */ 2305 if (vdsc_cfg->pic_height % 8 == 0) 2306 vdsc_cfg->slice_height = 8; 2307 else if (vdsc_cfg->pic_height % 4 == 0) 2308 vdsc_cfg->slice_height = 4; 2309 else 2310 vdsc_cfg->slice_height = 2; 2311 2312 vdsc_cfg->dsc_version_major = 2313 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 2314 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; 2315 vdsc_cfg->dsc_version_minor = 2316 min(DSC_SUPPORTED_VERSION_MIN, 2317 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 2318 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT); 2319 2320 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & 2321 DP_DSC_RGB; 2322 2323 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); 2324 if (!line_buf_depth) { 2325 drm_dbg_kms(&i915->drm, 2326 "DSC Sink Line Buffer Depth invalid\n"); 2327 return -EINVAL; 2328 } 2329 2330 if (vdsc_cfg->dsc_version_minor == 2) 2331 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? 2332 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; 2333 else 2334 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? 2335 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; 2336 2337 vdsc_cfg->block_pred_enable = 2338 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & 2339 DP_DSC_BLK_PREDICTION_IS_SUPPORTED; 2340 2341 return drm_dsc_compute_rc_parameters(vdsc_cfg); 2342 } 2343 2344 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 2345 struct intel_crtc_state *pipe_config, 2346 struct drm_connector_state *conn_state, 2347 struct link_config_limits *limits) 2348 { 2349 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2350 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2351 const struct drm_display_mode *adjusted_mode = 2352 &pipe_config->hw.adjusted_mode; 2353 u8 dsc_max_bpc; 2354 int pipe_bpp; 2355 int ret; 2356 2357 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && 2358 intel_dp_supports_fec(intel_dp, pipe_config); 2359 2360 if (!intel_dp_supports_dsc(intel_dp, pipe_config)) 2361 return -EINVAL; 2362 2363 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 2364 if (INTEL_GEN(dev_priv) >= 12) 2365 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); 2366 else 2367 dsc_max_bpc = min_t(u8, 10, 2368 conn_state->max_requested_bpc); 2369 2370 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc); 2371 2372 /* Min Input BPC for ICL+ is 8 */ 2373 if (pipe_bpp < 8 * 3) { 2374 drm_dbg_kms(&dev_priv->drm, 2375 "No DSC support for less than 8bpc\n"); 2376 return -EINVAL; 2377 } 2378 2379 /* 2380 * For now enable DSC for max bpp, max link rate, max lane count. 2381 * Optimize this later for the minimum possible link rate/lane count 2382 * with DSC enabled for the requested mode. 2383 */ 2384 pipe_config->pipe_bpp = pipe_bpp; 2385 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; 2386 pipe_config->lane_count = limits->max_lane_count; 2387 2388 if (intel_dp_is_edp(intel_dp)) { 2389 pipe_config->dsc.compressed_bpp = 2390 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, 2391 pipe_config->pipe_bpp); 2392 pipe_config->dsc.slice_count = 2393 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, 2394 true); 2395 } else { 2396 u16 dsc_max_output_bpp; 2397 u8 dsc_dp_slice_count; 2398 2399 dsc_max_output_bpp = 2400 intel_dp_dsc_get_output_bpp(dev_priv, 2401 pipe_config->port_clock, 2402 pipe_config->lane_count, 2403 adjusted_mode->crtc_clock, 2404 adjusted_mode->crtc_hdisplay, 2405 pipe_config->bigjoiner); 2406 dsc_dp_slice_count = 2407 intel_dp_dsc_get_slice_count(intel_dp, 2408 adjusted_mode->crtc_clock, 2409 adjusted_mode->crtc_hdisplay, 2410 pipe_config->bigjoiner); 2411 if (!dsc_max_output_bpp || !dsc_dp_slice_count) { 2412 drm_dbg_kms(&dev_priv->drm, 2413 "Compressed BPP/Slice Count not supported\n"); 2414 return -EINVAL; 2415 } 2416 pipe_config->dsc.compressed_bpp = min_t(u16, 2417 dsc_max_output_bpp >> 4, 2418 pipe_config->pipe_bpp); 2419 pipe_config->dsc.slice_count = dsc_dp_slice_count; 2420 } 2421 /* 2422 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate 2423 * is greater than the maximum Cdclock and if slice count is even 2424 * then we need to use 2 VDSC instances. 2425 */ 2426 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq || 2427 pipe_config->bigjoiner) { 2428 if (pipe_config->dsc.slice_count < 2) { 2429 drm_dbg_kms(&dev_priv->drm, 2430 "Cannot split stream to use 2 VDSC instances\n"); 2431 return -EINVAL; 2432 } 2433 2434 pipe_config->dsc.dsc_split = true; 2435 } 2436 2437 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); 2438 if (ret < 0) { 2439 drm_dbg_kms(&dev_priv->drm, 2440 "Cannot compute valid DSC parameters for Input Bpp = %d " 2441 "Compressed BPP = %d\n", 2442 pipe_config->pipe_bpp, 2443 pipe_config->dsc.compressed_bpp); 2444 return ret; 2445 } 2446 2447 pipe_config->dsc.compression_enable = true; 2448 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " 2449 "Compressed Bpp = %d Slice Count = %d\n", 2450 pipe_config->pipe_bpp, 2451 pipe_config->dsc.compressed_bpp, 2452 pipe_config->dsc.slice_count); 2453 2454 return 0; 2455 } 2456 2457 static int 2458 intel_dp_compute_link_config(struct intel_encoder *encoder, 2459 struct intel_crtc_state *pipe_config, 2460 struct drm_connector_state *conn_state) 2461 { 2462 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2463 const struct drm_display_mode *adjusted_mode = 2464 &pipe_config->hw.adjusted_mode; 2465 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2466 struct link_config_limits limits; 2467 int common_len; 2468 int ret; 2469 2470 common_len = intel_dp_common_len_rate_limit(intel_dp, 2471 intel_dp->max_link_rate); 2472 2473 /* No common link rates between source and sink */ 2474 drm_WARN_ON(encoder->base.dev, common_len <= 0); 2475 2476 limits.min_clock = 0; 2477 limits.max_clock = common_len - 1; 2478 2479 limits.min_lane_count = 1; 2480 limits.max_lane_count = intel_dp_max_lane_count(intel_dp); 2481 2482 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); 2483 limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config); 2484 2485 if (intel_dp_is_edp(intel_dp)) { 2486 /* 2487 * Use the maximum clock and number of lanes the eDP panel 2488 * advertizes being capable of. The panels are generally 2489 * designed to support only a single clock and lane 2490 * configuration, and typically these values correspond to the 2491 * native resolution of the panel. 2492 */ 2493 limits.min_lane_count = limits.max_lane_count; 2494 limits.min_clock = limits.max_clock; 2495 } 2496 2497 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); 2498 2499 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i " 2500 "max rate %d max bpp %d pixel clock %iKHz\n", 2501 limits.max_lane_count, 2502 intel_dp->common_rates[limits.max_clock], 2503 limits.max_bpp, adjusted_mode->crtc_clock); 2504 2505 if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq || 2506 adjusted_mode->crtc_hdisplay > 5120) && 2507 intel_dp_can_bigjoiner(intel_dp)) 2508 pipe_config->bigjoiner = true; 2509 2510 /* 2511 * Optimize for slow and wide. This is the place to add alternative 2512 * optimization policy. 2513 */ 2514 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); 2515 2516 /* enable compression if the mode doesn't fit available BW */ 2517 drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); 2518 if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) { 2519 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 2520 conn_state, &limits); 2521 if (ret < 0) 2522 return ret; 2523 } 2524 2525 if (pipe_config->dsc.compression_enable) { 2526 drm_dbg_kms(&i915->drm, 2527 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", 2528 pipe_config->lane_count, pipe_config->port_clock, 2529 pipe_config->pipe_bpp, 2530 pipe_config->dsc.compressed_bpp); 2531 2532 drm_dbg_kms(&i915->drm, 2533 "DP link rate required %i available %i\n", 2534 intel_dp_link_required(adjusted_mode->crtc_clock, 2535 pipe_config->dsc.compressed_bpp), 2536 intel_dp_max_data_rate(pipe_config->port_clock, 2537 pipe_config->lane_count)); 2538 } else { 2539 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n", 2540 pipe_config->lane_count, pipe_config->port_clock, 2541 pipe_config->pipe_bpp); 2542 2543 drm_dbg_kms(&i915->drm, 2544 "DP link rate required %i available %i\n", 2545 intel_dp_link_required(adjusted_mode->crtc_clock, 2546 pipe_config->pipe_bpp), 2547 intel_dp_max_data_rate(pipe_config->port_clock, 2548 pipe_config->lane_count)); 2549 } 2550 return 0; 2551 } 2552 2553 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 2554 const struct drm_connector_state *conn_state) 2555 { 2556 const struct intel_digital_connector_state *intel_conn_state = 2557 to_intel_digital_connector_state(conn_state); 2558 const struct drm_display_mode *adjusted_mode = 2559 &crtc_state->hw.adjusted_mode; 2560 2561 /* 2562 * Our YCbCr output is always limited range. 2563 * crtc_state->limited_color_range only applies to RGB, 2564 * and it must never be set for YCbCr or we risk setting 2565 * some conflicting bits in PIPECONF which will mess up 2566 * the colors on the monitor. 2567 */ 2568 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2569 return false; 2570 2571 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2572 /* 2573 * See: 2574 * CEA-861-E - 5.1 Default Encoding Parameters 2575 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 2576 */ 2577 return crtc_state->pipe_bpp != 18 && 2578 drm_default_rgb_quant_range(adjusted_mode) == 2579 HDMI_QUANTIZATION_RANGE_LIMITED; 2580 } else { 2581 return intel_conn_state->broadcast_rgb == 2582 INTEL_BROADCAST_RGB_LIMITED; 2583 } 2584 } 2585 2586 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv, 2587 enum port port) 2588 { 2589 if (IS_G4X(dev_priv)) 2590 return false; 2591 if (INTEL_GEN(dev_priv) < 12 && port == PORT_A) 2592 return false; 2593 2594 return true; 2595 } 2596 2597 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, 2598 const struct drm_connector_state *conn_state, 2599 struct drm_dp_vsc_sdp *vsc) 2600 { 2601 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2603 2604 /* 2605 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2606 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ 2607 * Colorimetry Format indication. 2608 */ 2609 vsc->revision = 0x5; 2610 vsc->length = 0x13; 2611 2612 /* DP 1.4a spec, Table 2-120 */ 2613 switch (crtc_state->output_format) { 2614 case INTEL_OUTPUT_FORMAT_YCBCR444: 2615 vsc->pixelformat = DP_PIXELFORMAT_YUV444; 2616 break; 2617 case INTEL_OUTPUT_FORMAT_YCBCR420: 2618 vsc->pixelformat = DP_PIXELFORMAT_YUV420; 2619 break; 2620 case INTEL_OUTPUT_FORMAT_RGB: 2621 default: 2622 vsc->pixelformat = DP_PIXELFORMAT_RGB; 2623 } 2624 2625 switch (conn_state->colorspace) { 2626 case DRM_MODE_COLORIMETRY_BT709_YCC: 2627 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2628 break; 2629 case DRM_MODE_COLORIMETRY_XVYCC_601: 2630 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; 2631 break; 2632 case DRM_MODE_COLORIMETRY_XVYCC_709: 2633 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; 2634 break; 2635 case DRM_MODE_COLORIMETRY_SYCC_601: 2636 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; 2637 break; 2638 case DRM_MODE_COLORIMETRY_OPYCC_601: 2639 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; 2640 break; 2641 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 2642 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; 2643 break; 2644 case DRM_MODE_COLORIMETRY_BT2020_RGB: 2645 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; 2646 break; 2647 case DRM_MODE_COLORIMETRY_BT2020_YCC: 2648 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; 2649 break; 2650 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 2651 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 2652 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; 2653 break; 2654 default: 2655 /* 2656 * RGB->YCBCR color conversion uses the BT.709 2657 * color space. 2658 */ 2659 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2660 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2661 else 2662 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; 2663 break; 2664 } 2665 2666 vsc->bpc = crtc_state->pipe_bpp / 3; 2667 2668 /* only RGB pixelformat supports 6 bpc */ 2669 drm_WARN_ON(&dev_priv->drm, 2670 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); 2671 2672 /* all YCbCr are always limited range */ 2673 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; 2674 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; 2675 } 2676 2677 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, 2678 struct intel_crtc_state *crtc_state, 2679 const struct drm_connector_state *conn_state) 2680 { 2681 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc; 2682 2683 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */ 2684 if (crtc_state->has_psr) 2685 return; 2686 2687 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 2688 return; 2689 2690 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 2691 vsc->sdp_type = DP_SDP_VSC; 2692 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 2693 &crtc_state->infoframes.vsc); 2694 } 2695 2696 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, 2697 const struct intel_crtc_state *crtc_state, 2698 const struct drm_connector_state *conn_state, 2699 struct drm_dp_vsc_sdp *vsc) 2700 { 2701 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2702 2703 vsc->sdp_type = DP_SDP_VSC; 2704 2705 if (dev_priv->psr.psr2_enabled) { 2706 if (dev_priv->psr.colorimetry_support && 2707 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { 2708 /* [PSR2, +Colorimetry] */ 2709 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 2710 vsc); 2711 } else { 2712 /* 2713 * [PSR2, -Colorimetry] 2714 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 2715 * 3D stereo + PSR/PSR2 + Y-coordinate. 2716 */ 2717 vsc->revision = 0x4; 2718 vsc->length = 0xe; 2719 } 2720 } else { 2721 /* 2722 * [PSR1] 2723 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2724 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or 2725 * higher). 2726 */ 2727 vsc->revision = 0x2; 2728 vsc->length = 0x8; 2729 } 2730 } 2731 2732 static void 2733 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, 2734 struct intel_crtc_state *crtc_state, 2735 const struct drm_connector_state *conn_state) 2736 { 2737 int ret; 2738 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2739 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; 2740 2741 if (!conn_state->hdr_output_metadata) 2742 return; 2743 2744 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); 2745 2746 if (ret) { 2747 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n"); 2748 return; 2749 } 2750 2751 crtc_state->infoframes.enable |= 2752 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 2753 } 2754 2755 static void 2756 intel_dp_drrs_compute_config(struct intel_dp *intel_dp, 2757 struct intel_crtc_state *pipe_config, 2758 int output_bpp, bool constant_n) 2759 { 2760 struct intel_connector *intel_connector = intel_dp->attached_connector; 2761 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2762 2763 /* 2764 * DRRS and PSR can't be enable together, so giving preference to PSR 2765 * as it allows more power-savings by complete shutting down display, 2766 * so to guarantee this, intel_dp_drrs_compute_config() must be called 2767 * after intel_psr_compute_config(). 2768 */ 2769 if (pipe_config->has_psr) 2770 return; 2771 2772 if (!intel_connector->panel.downclock_mode || 2773 dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT) 2774 return; 2775 2776 pipe_config->has_drrs = true; 2777 intel_link_compute_m_n(output_bpp, pipe_config->lane_count, 2778 intel_connector->panel.downclock_mode->clock, 2779 pipe_config->port_clock, &pipe_config->dp_m2_n2, 2780 constant_n, pipe_config->fec_enable); 2781 } 2782 2783 int 2784 intel_dp_compute_config(struct intel_encoder *encoder, 2785 struct intel_crtc_state *pipe_config, 2786 struct drm_connector_state *conn_state) 2787 { 2788 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2789 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2790 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2791 enum port port = encoder->port; 2792 struct intel_connector *intel_connector = intel_dp->attached_connector; 2793 struct intel_digital_connector_state *intel_conn_state = 2794 to_intel_digital_connector_state(conn_state); 2795 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0, 2796 DP_DPCD_QUIRK_CONSTANT_N); 2797 int ret = 0, output_bpp; 2798 2799 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) 2800 pipe_config->has_pch_encoder = true; 2801 2802 pipe_config->output_format = intel_dp_output_format(&intel_connector->base, 2803 adjusted_mode); 2804 2805 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 2806 ret = intel_pch_panel_fitting(pipe_config, conn_state); 2807 if (ret) 2808 return ret; 2809 } 2810 2811 if (!intel_dp_port_has_audio(dev_priv, port)) 2812 pipe_config->has_audio = false; 2813 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2814 pipe_config->has_audio = intel_dp->has_audio; 2815 else 2816 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; 2817 2818 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 2819 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 2820 adjusted_mode); 2821 2822 if (HAS_GMCH(dev_priv)) 2823 ret = intel_gmch_panel_fitting(pipe_config, conn_state); 2824 else 2825 ret = intel_pch_panel_fitting(pipe_config, conn_state); 2826 if (ret) 2827 return ret; 2828 } 2829 2830 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2831 return -EINVAL; 2832 2833 if (HAS_GMCH(dev_priv) && 2834 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2835 return -EINVAL; 2836 2837 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2838 return -EINVAL; 2839 2840 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay)) 2841 return -EINVAL; 2842 2843 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); 2844 if (ret < 0) 2845 return ret; 2846 2847 pipe_config->limited_color_range = 2848 intel_dp_limited_color_range(pipe_config, conn_state); 2849 2850 if (pipe_config->dsc.compression_enable) 2851 output_bpp = pipe_config->dsc.compressed_bpp; 2852 else 2853 output_bpp = intel_dp_output_bpp(pipe_config->output_format, 2854 pipe_config->pipe_bpp); 2855 2856 intel_link_compute_m_n(output_bpp, 2857 pipe_config->lane_count, 2858 adjusted_mode->crtc_clock, 2859 pipe_config->port_clock, 2860 &pipe_config->dp_m_n, 2861 constant_n, pipe_config->fec_enable); 2862 2863 if (!HAS_DDI(dev_priv)) 2864 intel_dp_set_clock(encoder, pipe_config); 2865 2866 intel_psr_compute_config(intel_dp, pipe_config); 2867 intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp, 2868 constant_n); 2869 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); 2870 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); 2871 2872 return 0; 2873 } 2874 2875 void intel_dp_set_link_params(struct intel_dp *intel_dp, 2876 int link_rate, int lane_count) 2877 { 2878 intel_dp->link_trained = false; 2879 intel_dp->link_rate = link_rate; 2880 intel_dp->lane_count = lane_count; 2881 } 2882 2883 static void intel_dp_prepare(struct intel_encoder *encoder, 2884 const struct intel_crtc_state *pipe_config) 2885 { 2886 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2887 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2888 enum port port = encoder->port; 2889 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2890 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2891 2892 intel_dp_set_link_params(intel_dp, 2893 pipe_config->port_clock, 2894 pipe_config->lane_count); 2895 2896 /* 2897 * There are four kinds of DP registers: 2898 * 2899 * IBX PCH 2900 * SNB CPU 2901 * IVB CPU 2902 * CPT PCH 2903 * 2904 * IBX PCH and CPU are the same for almost everything, 2905 * except that the CPU DP PLL is configured in this 2906 * register 2907 * 2908 * CPT PCH is quite different, having many bits moved 2909 * to the TRANS_DP_CTL register instead. That 2910 * configuration happens (oddly) in ilk_pch_enable 2911 */ 2912 2913 /* Preserve the BIOS-computed detected bit. This is 2914 * supposed to be read-only. 2915 */ 2916 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; 2917 2918 /* Handle DP bits in common between all three register formats */ 2919 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 2920 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); 2921 2922 /* Split out the IBX/CPU vs CPT settings */ 2923 2924 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { 2925 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 2926 intel_dp->DP |= DP_SYNC_HS_HIGH; 2927 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 2928 intel_dp->DP |= DP_SYNC_VS_HIGH; 2929 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 2930 2931 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2932 intel_dp->DP |= DP_ENHANCED_FRAMING; 2933 2934 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); 2935 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 2936 u32 trans_dp; 2937 2938 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 2939 2940 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)); 2941 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2942 trans_dp |= TRANS_DP_ENH_FRAMING; 2943 else 2944 trans_dp &= ~TRANS_DP_ENH_FRAMING; 2945 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp); 2946 } else { 2947 if (IS_G4X(dev_priv) && pipe_config->limited_color_range) 2948 intel_dp->DP |= DP_COLOR_RANGE_16_235; 2949 2950 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 2951 intel_dp->DP |= DP_SYNC_HS_HIGH; 2952 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 2953 intel_dp->DP |= DP_SYNC_VS_HIGH; 2954 intel_dp->DP |= DP_LINK_TRAIN_OFF; 2955 2956 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2957 intel_dp->DP |= DP_ENHANCED_FRAMING; 2958 2959 if (IS_CHERRYVIEW(dev_priv)) 2960 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); 2961 else 2962 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); 2963 } 2964 } 2965 2966 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 2967 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 2968 2969 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 2970 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 2971 2972 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 2973 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 2974 2975 static void intel_pps_verify_state(struct intel_dp *intel_dp); 2976 2977 static void wait_panel_status(struct intel_dp *intel_dp, 2978 u32 mask, 2979 u32 value) 2980 { 2981 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2982 i915_reg_t pp_stat_reg, pp_ctrl_reg; 2983 2984 lockdep_assert_held(&dev_priv->pps_mutex); 2985 2986 intel_pps_verify_state(intel_dp); 2987 2988 pp_stat_reg = _pp_stat_reg(intel_dp); 2989 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2990 2991 drm_dbg_kms(&dev_priv->drm, 2992 "mask %08x value %08x status %08x control %08x\n", 2993 mask, value, 2994 intel_de_read(dev_priv, pp_stat_reg), 2995 intel_de_read(dev_priv, pp_ctrl_reg)); 2996 2997 if (intel_de_wait_for_register(dev_priv, pp_stat_reg, 2998 mask, value, 5000)) 2999 drm_err(&dev_priv->drm, 3000 "Panel status timeout: status %08x control %08x\n", 3001 intel_de_read(dev_priv, pp_stat_reg), 3002 intel_de_read(dev_priv, pp_ctrl_reg)); 3003 3004 drm_dbg_kms(&dev_priv->drm, "Wait complete\n"); 3005 } 3006 3007 static void wait_panel_on(struct intel_dp *intel_dp) 3008 { 3009 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3010 3011 drm_dbg_kms(&i915->drm, "Wait for panel power on\n"); 3012 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 3013 } 3014 3015 static void wait_panel_off(struct intel_dp *intel_dp) 3016 { 3017 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3018 3019 drm_dbg_kms(&i915->drm, "Wait for panel power off time\n"); 3020 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 3021 } 3022 3023 static void wait_panel_power_cycle(struct intel_dp *intel_dp) 3024 { 3025 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3026 ktime_t panel_power_on_time; 3027 s64 panel_power_off_duration; 3028 3029 drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n"); 3030 3031 /* take the difference of currrent time and panel power off time 3032 * and then make panel wait for t11_t12 if needed. */ 3033 panel_power_on_time = ktime_get_boottime(); 3034 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); 3035 3036 /* When we disable the VDD override bit last we have to do the manual 3037 * wait. */ 3038 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) 3039 wait_remaining_ms_from_jiffies(jiffies, 3040 intel_dp->panel_power_cycle_delay - panel_power_off_duration); 3041 3042 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 3043 } 3044 3045 static void wait_backlight_on(struct intel_dp *intel_dp) 3046 { 3047 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 3048 intel_dp->backlight_on_delay); 3049 } 3050 3051 static void edp_wait_backlight_off(struct intel_dp *intel_dp) 3052 { 3053 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 3054 intel_dp->backlight_off_delay); 3055 } 3056 3057 /* Read the current pp_control value, unlocking the register if it 3058 * is locked 3059 */ 3060 3061 static u32 ilk_get_pp_control(struct intel_dp *intel_dp) 3062 { 3063 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3064 u32 control; 3065 3066 lockdep_assert_held(&dev_priv->pps_mutex); 3067 3068 control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)); 3069 if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) && 3070 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { 3071 control &= ~PANEL_UNLOCK_MASK; 3072 control |= PANEL_UNLOCK_REGS; 3073 } 3074 return control; 3075 } 3076 3077 /* 3078 * Must be paired with edp_panel_vdd_off(). 3079 * Must hold pps_mutex around the whole on/off sequence. 3080 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 3081 */ 3082 static bool edp_panel_vdd_on(struct intel_dp *intel_dp) 3083 { 3084 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3085 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3086 u32 pp; 3087 i915_reg_t pp_stat_reg, pp_ctrl_reg; 3088 bool need_to_disable = !intel_dp->want_panel_vdd; 3089 3090 lockdep_assert_held(&dev_priv->pps_mutex); 3091 3092 if (!intel_dp_is_edp(intel_dp)) 3093 return false; 3094 3095 cancel_delayed_work(&intel_dp->panel_vdd_work); 3096 intel_dp->want_panel_vdd = true; 3097 3098 if (edp_have_panel_vdd(intel_dp)) 3099 return need_to_disable; 3100 3101 intel_display_power_get(dev_priv, 3102 intel_aux_power_domain(dig_port)); 3103 3104 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n", 3105 dig_port->base.base.base.id, 3106 dig_port->base.base.name); 3107 3108 if (!edp_have_panel_power(intel_dp)) 3109 wait_panel_power_cycle(intel_dp); 3110 3111 pp = ilk_get_pp_control(intel_dp); 3112 pp |= EDP_FORCE_VDD; 3113 3114 pp_stat_reg = _pp_stat_reg(intel_dp); 3115 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 3116 3117 intel_de_write(dev_priv, pp_ctrl_reg, pp); 3118 intel_de_posting_read(dev_priv, pp_ctrl_reg); 3119 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 3120 intel_de_read(dev_priv, pp_stat_reg), 3121 intel_de_read(dev_priv, pp_ctrl_reg)); 3122 /* 3123 * If the panel wasn't on, delay before accessing aux channel 3124 */ 3125 if (!edp_have_panel_power(intel_dp)) { 3126 drm_dbg_kms(&dev_priv->drm, 3127 "[ENCODER:%d:%s] panel power wasn't enabled\n", 3128 dig_port->base.base.base.id, 3129 dig_port->base.base.name); 3130 msleep(intel_dp->panel_power_up_delay); 3131 } 3132 3133 return need_to_disable; 3134 } 3135 3136 /* 3137 * Must be paired with intel_edp_panel_vdd_off() or 3138 * intel_edp_panel_off(). 3139 * Nested calls to these functions are not allowed since 3140 * we drop the lock. Caller must use some higher level 3141 * locking to prevent nested calls from other threads. 3142 */ 3143 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 3144 { 3145 intel_wakeref_t wakeref; 3146 bool vdd; 3147 3148 if (!intel_dp_is_edp(intel_dp)) 3149 return; 3150 3151 vdd = false; 3152 with_pps_lock(intel_dp, wakeref) 3153 vdd = edp_panel_vdd_on(intel_dp); 3154 I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n", 3155 dp_to_dig_port(intel_dp)->base.base.base.id, 3156 dp_to_dig_port(intel_dp)->base.base.name); 3157 } 3158 3159 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 3160 { 3161 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3162 struct intel_digital_port *dig_port = 3163 dp_to_dig_port(intel_dp); 3164 u32 pp; 3165 i915_reg_t pp_stat_reg, pp_ctrl_reg; 3166 3167 lockdep_assert_held(&dev_priv->pps_mutex); 3168 3169 drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd); 3170 3171 if (!edp_have_panel_vdd(intel_dp)) 3172 return; 3173 3174 drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n", 3175 dig_port->base.base.base.id, 3176 dig_port->base.base.name); 3177 3178 pp = ilk_get_pp_control(intel_dp); 3179 pp &= ~EDP_FORCE_VDD; 3180 3181 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 3182 pp_stat_reg = _pp_stat_reg(intel_dp); 3183 3184 intel_de_write(dev_priv, pp_ctrl_reg, pp); 3185 intel_de_posting_read(dev_priv, pp_ctrl_reg); 3186 3187 /* Make sure sequencer is idle before allowing subsequent activity */ 3188 drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 3189 intel_de_read(dev_priv, pp_stat_reg), 3190 intel_de_read(dev_priv, pp_ctrl_reg)); 3191 3192 if ((pp & PANEL_POWER_ON) == 0) 3193 intel_dp->panel_power_off_time = ktime_get_boottime(); 3194 3195 intel_display_power_put_unchecked(dev_priv, 3196 intel_aux_power_domain(dig_port)); 3197 } 3198 3199 static void edp_panel_vdd_work(struct work_struct *__work) 3200 { 3201 struct intel_dp *intel_dp = 3202 container_of(to_delayed_work(__work), 3203 struct intel_dp, panel_vdd_work); 3204 intel_wakeref_t wakeref; 3205 3206 with_pps_lock(intel_dp, wakeref) { 3207 if (!intel_dp->want_panel_vdd) 3208 edp_panel_vdd_off_sync(intel_dp); 3209 } 3210 } 3211 3212 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) 3213 { 3214 unsigned long delay; 3215 3216 /* 3217 * Queue the timer to fire a long time from now (relative to the power 3218 * down delay) to keep the panel power up across a sequence of 3219 * operations. 3220 */ 3221 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); 3222 schedule_delayed_work(&intel_dp->panel_vdd_work, delay); 3223 } 3224 3225 /* 3226 * Must be paired with edp_panel_vdd_on(). 3227 * Must hold pps_mutex around the whole on/off sequence. 3228 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 3229 */ 3230 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 3231 { 3232 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3233 3234 lockdep_assert_held(&dev_priv->pps_mutex); 3235 3236 if (!intel_dp_is_edp(intel_dp)) 3237 return; 3238 3239 I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on", 3240 dp_to_dig_port(intel_dp)->base.base.base.id, 3241 dp_to_dig_port(intel_dp)->base.base.name); 3242 3243 intel_dp->want_panel_vdd = false; 3244 3245 if (sync) 3246 edp_panel_vdd_off_sync(intel_dp); 3247 else 3248 edp_panel_vdd_schedule_off(intel_dp); 3249 } 3250 3251 static void edp_panel_on(struct intel_dp *intel_dp) 3252 { 3253 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3254 u32 pp; 3255 i915_reg_t pp_ctrl_reg; 3256 3257 lockdep_assert_held(&dev_priv->pps_mutex); 3258 3259 if (!intel_dp_is_edp(intel_dp)) 3260 return; 3261 3262 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n", 3263 dp_to_dig_port(intel_dp)->base.base.base.id, 3264 dp_to_dig_port(intel_dp)->base.base.name); 3265 3266 if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp), 3267 "[ENCODER:%d:%s] panel power already on\n", 3268 dp_to_dig_port(intel_dp)->base.base.base.id, 3269 dp_to_dig_port(intel_dp)->base.base.name)) 3270 return; 3271 3272 wait_panel_power_cycle(intel_dp); 3273 3274 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 3275 pp = ilk_get_pp_control(intel_dp); 3276 if (IS_GEN(dev_priv, 5)) { 3277 /* ILK workaround: disable reset around power sequence */ 3278 pp &= ~PANEL_POWER_RESET; 3279 intel_de_write(dev_priv, pp_ctrl_reg, pp); 3280 intel_de_posting_read(dev_priv, pp_ctrl_reg); 3281 } 3282 3283 pp |= PANEL_POWER_ON; 3284 if (!IS_GEN(dev_priv, 5)) 3285 pp |= PANEL_POWER_RESET; 3286 3287 intel_de_write(dev_priv, pp_ctrl_reg, pp); 3288 intel_de_posting_read(dev_priv, pp_ctrl_reg); 3289 3290 wait_panel_on(intel_dp); 3291 intel_dp->last_power_on = jiffies; 3292 3293 if (IS_GEN(dev_priv, 5)) { 3294 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 3295 intel_de_write(dev_priv, pp_ctrl_reg, pp); 3296 intel_de_posting_read(dev_priv, pp_ctrl_reg); 3297 } 3298 } 3299 3300 void intel_edp_panel_on(struct intel_dp *intel_dp) 3301 { 3302 intel_wakeref_t wakeref; 3303 3304 if (!intel_dp_is_edp(intel_dp)) 3305 return; 3306 3307 with_pps_lock(intel_dp, wakeref) 3308 edp_panel_on(intel_dp); 3309 } 3310 3311 3312 static void edp_panel_off(struct intel_dp *intel_dp) 3313 { 3314 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3315 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3316 u32 pp; 3317 i915_reg_t pp_ctrl_reg; 3318 3319 lockdep_assert_held(&dev_priv->pps_mutex); 3320 3321 if (!intel_dp_is_edp(intel_dp)) 3322 return; 3323 3324 drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n", 3325 dig_port->base.base.base.id, dig_port->base.base.name); 3326 3327 drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd, 3328 "Need [ENCODER:%d:%s] VDD to turn off panel\n", 3329 dig_port->base.base.base.id, dig_port->base.base.name); 3330 3331 pp = ilk_get_pp_control(intel_dp); 3332 /* We need to switch off panel power _and_ force vdd, for otherwise some 3333 * panels get very unhappy and cease to work. */ 3334 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 3335 EDP_BLC_ENABLE); 3336 3337 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 3338 3339 intel_dp->want_panel_vdd = false; 3340 3341 intel_de_write(dev_priv, pp_ctrl_reg, pp); 3342 intel_de_posting_read(dev_priv, pp_ctrl_reg); 3343 3344 wait_panel_off(intel_dp); 3345 intel_dp->panel_power_off_time = ktime_get_boottime(); 3346 3347 /* We got a reference when we enabled the VDD. */ 3348 intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port)); 3349 } 3350 3351 void intel_edp_panel_off(struct intel_dp *intel_dp) 3352 { 3353 intel_wakeref_t wakeref; 3354 3355 if (!intel_dp_is_edp(intel_dp)) 3356 return; 3357 3358 with_pps_lock(intel_dp, wakeref) 3359 edp_panel_off(intel_dp); 3360 } 3361 3362 /* Enable backlight in the panel power control. */ 3363 static void _intel_edp_backlight_on(struct intel_dp *intel_dp) 3364 { 3365 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3366 intel_wakeref_t wakeref; 3367 3368 /* 3369 * If we enable the backlight right away following a panel power 3370 * on, we may see slight flicker as the panel syncs with the eDP 3371 * link. So delay a bit to make sure the image is solid before 3372 * allowing it to appear. 3373 */ 3374 wait_backlight_on(intel_dp); 3375 3376 with_pps_lock(intel_dp, wakeref) { 3377 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 3378 u32 pp; 3379 3380 pp = ilk_get_pp_control(intel_dp); 3381 pp |= EDP_BLC_ENABLE; 3382 3383 intel_de_write(dev_priv, pp_ctrl_reg, pp); 3384 intel_de_posting_read(dev_priv, pp_ctrl_reg); 3385 } 3386 } 3387 3388 /* Enable backlight PWM and backlight PP control. */ 3389 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 3390 const struct drm_connector_state *conn_state) 3391 { 3392 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); 3393 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3394 3395 if (!intel_dp_is_edp(intel_dp)) 3396 return; 3397 3398 drm_dbg_kms(&i915->drm, "\n"); 3399 3400 intel_panel_enable_backlight(crtc_state, conn_state); 3401 _intel_edp_backlight_on(intel_dp); 3402 } 3403 3404 /* Disable backlight in the panel power control. */ 3405 static void _intel_edp_backlight_off(struct intel_dp *intel_dp) 3406 { 3407 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3408 intel_wakeref_t wakeref; 3409 3410 if (!intel_dp_is_edp(intel_dp)) 3411 return; 3412 3413 with_pps_lock(intel_dp, wakeref) { 3414 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 3415 u32 pp; 3416 3417 pp = ilk_get_pp_control(intel_dp); 3418 pp &= ~EDP_BLC_ENABLE; 3419 3420 intel_de_write(dev_priv, pp_ctrl_reg, pp); 3421 intel_de_posting_read(dev_priv, pp_ctrl_reg); 3422 } 3423 3424 intel_dp->last_backlight_off = jiffies; 3425 edp_wait_backlight_off(intel_dp); 3426 } 3427 3428 /* Disable backlight PP control and backlight PWM. */ 3429 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) 3430 { 3431 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); 3432 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3433 3434 if (!intel_dp_is_edp(intel_dp)) 3435 return; 3436 3437 drm_dbg_kms(&i915->drm, "\n"); 3438 3439 _intel_edp_backlight_off(intel_dp); 3440 intel_panel_disable_backlight(old_conn_state); 3441 } 3442 3443 /* 3444 * Hook for controlling the panel power control backlight through the bl_power 3445 * sysfs attribute. Take care to handle multiple calls. 3446 */ 3447 static void intel_edp_backlight_power(struct intel_connector *connector, 3448 bool enable) 3449 { 3450 struct drm_i915_private *i915 = to_i915(connector->base.dev); 3451 struct intel_dp *intel_dp = intel_attached_dp(connector); 3452 intel_wakeref_t wakeref; 3453 bool is_enabled; 3454 3455 is_enabled = false; 3456 with_pps_lock(intel_dp, wakeref) 3457 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE; 3458 if (is_enabled == enable) 3459 return; 3460 3461 drm_dbg_kms(&i915->drm, "panel power control backlight %s\n", 3462 enable ? "enable" : "disable"); 3463 3464 if (enable) 3465 _intel_edp_backlight_on(intel_dp); 3466 else 3467 _intel_edp_backlight_off(intel_dp); 3468 } 3469 3470 static void assert_dp_port(struct intel_dp *intel_dp, bool state) 3471 { 3472 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3473 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 3474 bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN; 3475 3476 I915_STATE_WARN(cur_state != state, 3477 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", 3478 dig_port->base.base.base.id, dig_port->base.base.name, 3479 onoff(state), onoff(cur_state)); 3480 } 3481 #define assert_dp_port_disabled(d) assert_dp_port((d), false) 3482 3483 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 3484 { 3485 bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE; 3486 3487 I915_STATE_WARN(cur_state != state, 3488 "eDP PLL state assertion failure (expected %s, current %s)\n", 3489 onoff(state), onoff(cur_state)); 3490 } 3491 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 3492 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 3493 3494 static void ilk_edp_pll_on(struct intel_dp *intel_dp, 3495 const struct intel_crtc_state *pipe_config) 3496 { 3497 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3498 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3499 3500 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); 3501 assert_dp_port_disabled(intel_dp); 3502 assert_edp_pll_disabled(dev_priv); 3503 3504 drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n", 3505 pipe_config->port_clock); 3506 3507 intel_dp->DP &= ~DP_PLL_FREQ_MASK; 3508 3509 if (pipe_config->port_clock == 162000) 3510 intel_dp->DP |= DP_PLL_FREQ_162MHZ; 3511 else 3512 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 3513 3514 intel_de_write(dev_priv, DP_A, intel_dp->DP); 3515 intel_de_posting_read(dev_priv, DP_A); 3516 udelay(500); 3517 3518 /* 3519 * [DevILK] Work around required when enabling DP PLL 3520 * while a pipe is enabled going to FDI: 3521 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 3522 * 2. Program DP PLL enable 3523 */ 3524 if (IS_GEN(dev_priv, 5)) 3525 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); 3526 3527 intel_dp->DP |= DP_PLL_ENABLE; 3528 3529 intel_de_write(dev_priv, DP_A, intel_dp->DP); 3530 intel_de_posting_read(dev_priv, DP_A); 3531 udelay(200); 3532 } 3533 3534 static void ilk_edp_pll_off(struct intel_dp *intel_dp, 3535 const struct intel_crtc_state *old_crtc_state) 3536 { 3537 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 3538 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3539 3540 assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder); 3541 assert_dp_port_disabled(intel_dp); 3542 assert_edp_pll_enabled(dev_priv); 3543 3544 drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n"); 3545 3546 intel_dp->DP &= ~DP_PLL_ENABLE; 3547 3548 intel_de_write(dev_priv, DP_A, intel_dp->DP); 3549 intel_de_posting_read(dev_priv, DP_A); 3550 udelay(200); 3551 } 3552 3553 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) 3554 { 3555 /* 3556 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus 3557 * be capable of signalling downstream hpd with a long pulse. 3558 * Whether or not that means D3 is safe to use is not clear, 3559 * but let's assume so until proven otherwise. 3560 * 3561 * FIXME should really check all downstream ports... 3562 */ 3563 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 3564 drm_dp_is_branch(intel_dp->dpcd) && 3565 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; 3566 } 3567 3568 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, 3569 const struct intel_crtc_state *crtc_state, 3570 bool enable) 3571 { 3572 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3573 int ret; 3574 3575 if (!crtc_state->dsc.compression_enable) 3576 return; 3577 3578 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, 3579 enable ? DP_DECOMPRESSION_EN : 0); 3580 if (ret < 0) 3581 drm_dbg_kms(&i915->drm, 3582 "Failed to %s sink decompression state\n", 3583 enable ? "enable" : "disable"); 3584 } 3585 3586 /* If the device supports it, try to set the power state appropriately */ 3587 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) 3588 { 3589 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3590 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3591 int ret, i; 3592 3593 /* Should have a valid DPCD by this point */ 3594 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 3595 return; 3596 3597 if (mode != DP_SET_POWER_D0) { 3598 if (downstream_hpd_needs_d0(intel_dp)) 3599 return; 3600 3601 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3602 } else { 3603 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); 3604 3605 lspcon_resume(dp_to_dig_port(intel_dp)); 3606 3607 /* 3608 * When turning on, we need to retry for 1ms to give the sink 3609 * time to wake up. 3610 */ 3611 for (i = 0; i < 3; i++) { 3612 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3613 if (ret == 1) 3614 break; 3615 msleep(1); 3616 } 3617 3618 if (ret == 1 && lspcon->active) 3619 lspcon_wait_pcon_mode(lspcon); 3620 } 3621 3622 if (ret != 1) 3623 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n", 3624 encoder->base.base.id, encoder->base.name, 3625 mode == DP_SET_POWER_D0 ? "D0" : "D3"); 3626 } 3627 3628 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, 3629 enum port port, enum pipe *pipe) 3630 { 3631 enum pipe p; 3632 3633 for_each_pipe(dev_priv, p) { 3634 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); 3635 3636 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { 3637 *pipe = p; 3638 return true; 3639 } 3640 } 3641 3642 drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n", 3643 port_name(port)); 3644 3645 /* must initialize pipe to something for the asserts */ 3646 *pipe = PIPE_A; 3647 3648 return false; 3649 } 3650 3651 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, 3652 i915_reg_t dp_reg, enum port port, 3653 enum pipe *pipe) 3654 { 3655 bool ret; 3656 u32 val; 3657 3658 val = intel_de_read(dev_priv, dp_reg); 3659 3660 ret = val & DP_PORT_EN; 3661 3662 /* asserts want to know the pipe even if the port is disabled */ 3663 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) 3664 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB; 3665 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) 3666 ret &= cpt_dp_port_selected(dev_priv, port, pipe); 3667 else if (IS_CHERRYVIEW(dev_priv)) 3668 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV; 3669 else 3670 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT; 3671 3672 return ret; 3673 } 3674 3675 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 3676 enum pipe *pipe) 3677 { 3678 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3679 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3680 intel_wakeref_t wakeref; 3681 bool ret; 3682 3683 wakeref = intel_display_power_get_if_enabled(dev_priv, 3684 encoder->power_domain); 3685 if (!wakeref) 3686 return false; 3687 3688 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg, 3689 encoder->port, pipe); 3690 3691 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 3692 3693 return ret; 3694 } 3695 3696 static void intel_dp_get_config(struct intel_encoder *encoder, 3697 struct intel_crtc_state *pipe_config) 3698 { 3699 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3700 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3701 u32 tmp, flags = 0; 3702 enum port port = encoder->port; 3703 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3704 3705 if (encoder->type == INTEL_OUTPUT_EDP) 3706 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3707 else 3708 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3709 3710 tmp = intel_de_read(dev_priv, intel_dp->output_reg); 3711 3712 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 3713 3714 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 3715 u32 trans_dp = intel_de_read(dev_priv, 3716 TRANS_DP_CTL(crtc->pipe)); 3717 3718 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 3719 flags |= DRM_MODE_FLAG_PHSYNC; 3720 else 3721 flags |= DRM_MODE_FLAG_NHSYNC; 3722 3723 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 3724 flags |= DRM_MODE_FLAG_PVSYNC; 3725 else 3726 flags |= DRM_MODE_FLAG_NVSYNC; 3727 } else { 3728 if (tmp & DP_SYNC_HS_HIGH) 3729 flags |= DRM_MODE_FLAG_PHSYNC; 3730 else 3731 flags |= DRM_MODE_FLAG_NHSYNC; 3732 3733 if (tmp & DP_SYNC_VS_HIGH) 3734 flags |= DRM_MODE_FLAG_PVSYNC; 3735 else 3736 flags |= DRM_MODE_FLAG_NVSYNC; 3737 } 3738 3739 pipe_config->hw.adjusted_mode.flags |= flags; 3740 3741 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) 3742 pipe_config->limited_color_range = true; 3743 3744 pipe_config->lane_count = 3745 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; 3746 3747 intel_dp_get_m_n(crtc, pipe_config); 3748 3749 if (port == PORT_A) { 3750 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) 3751 pipe_config->port_clock = 162000; 3752 else 3753 pipe_config->port_clock = 270000; 3754 } 3755 3756 pipe_config->hw.adjusted_mode.crtc_clock = 3757 intel_dotclock_calculate(pipe_config->port_clock, 3758 &pipe_config->dp_m_n); 3759 3760 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && 3761 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3762 /* 3763 * This is a big fat ugly hack. 3764 * 3765 * Some machines in UEFI boot mode provide us a VBT that has 18 3766 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3767 * unknown we fail to light up. Yet the same BIOS boots up with 3768 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3769 * max, not what it tells us to use. 3770 * 3771 * Note: This will still be broken if the eDP panel is not lit 3772 * up by the BIOS, and thus we can't get the mode at module 3773 * load. 3774 */ 3775 drm_dbg_kms(&dev_priv->drm, 3776 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3777 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3778 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3779 } 3780 } 3781 3782 static bool 3783 intel_dp_get_dpcd(struct intel_dp *intel_dp); 3784 3785 /** 3786 * intel_dp_sync_state - sync the encoder state during init/resume 3787 * @encoder: intel encoder to sync 3788 * @crtc_state: state for the CRTC connected to the encoder 3789 * 3790 * Sync any state stored in the encoder wrt. HW state during driver init 3791 * and system resume. 3792 */ 3793 void intel_dp_sync_state(struct intel_encoder *encoder, 3794 const struct intel_crtc_state *crtc_state) 3795 { 3796 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3797 3798 /* 3799 * Don't clobber DPCD if it's been already read out during output 3800 * setup (eDP) or detect. 3801 */ 3802 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 3803 intel_dp_get_dpcd(intel_dp); 3804 3805 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); 3806 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); 3807 } 3808 3809 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 3810 struct intel_crtc_state *crtc_state) 3811 { 3812 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3813 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3814 3815 /* 3816 * If BIOS has set an unsupported or non-standard link rate for some 3817 * reason force an encoder recompute and full modeset. 3818 */ 3819 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, 3820 crtc_state->port_clock) < 0) { 3821 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n"); 3822 crtc_state->uapi.connectors_changed = true; 3823 return false; 3824 } 3825 3826 /* 3827 * FIXME hack to force full modeset when DSC is being used. 3828 * 3829 * As long as we do not have full state readout and config comparison 3830 * of crtc_state->dsc, we have no way to ensure reliable fastset. 3831 * Remove once we have readout for DSC. 3832 */ 3833 if (crtc_state->dsc.compression_enable) { 3834 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n"); 3835 crtc_state->uapi.mode_changed = true; 3836 return false; 3837 } 3838 3839 if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) { 3840 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n"); 3841 crtc_state->uapi.mode_changed = true; 3842 return false; 3843 } 3844 3845 return true; 3846 } 3847 3848 static void intel_disable_dp(struct intel_atomic_state *state, 3849 struct intel_encoder *encoder, 3850 const struct intel_crtc_state *old_crtc_state, 3851 const struct drm_connector_state *old_conn_state) 3852 { 3853 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3854 3855 intel_dp->link_trained = false; 3856 3857 if (old_crtc_state->has_audio) 3858 intel_audio_codec_disable(encoder, 3859 old_crtc_state, old_conn_state); 3860 3861 /* Make sure the panel is off before trying to change the mode. But also 3862 * ensure that we have vdd while we switch off the panel. */ 3863 intel_edp_panel_vdd_on(intel_dp); 3864 intel_edp_backlight_off(old_conn_state); 3865 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3866 intel_edp_panel_off(intel_dp); 3867 } 3868 3869 static void g4x_disable_dp(struct intel_atomic_state *state, 3870 struct intel_encoder *encoder, 3871 const struct intel_crtc_state *old_crtc_state, 3872 const struct drm_connector_state *old_conn_state) 3873 { 3874 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 3875 } 3876 3877 static void vlv_disable_dp(struct intel_atomic_state *state, 3878 struct intel_encoder *encoder, 3879 const struct intel_crtc_state *old_crtc_state, 3880 const struct drm_connector_state *old_conn_state) 3881 { 3882 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 3883 } 3884 3885 static void g4x_post_disable_dp(struct intel_atomic_state *state, 3886 struct intel_encoder *encoder, 3887 const struct intel_crtc_state *old_crtc_state, 3888 const struct drm_connector_state *old_conn_state) 3889 { 3890 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3891 enum port port = encoder->port; 3892 3893 /* 3894 * Bspec does not list a specific disable sequence for g4x DP. 3895 * Follow the ilk+ sequence (disable pipe before the port) for 3896 * g4x DP as it does not suffer from underruns like the normal 3897 * g4x modeset sequence (disable pipe after the port). 3898 */ 3899 intel_dp_link_down(encoder, old_crtc_state); 3900 3901 /* Only ilk+ has port A */ 3902 if (port == PORT_A) 3903 ilk_edp_pll_off(intel_dp, old_crtc_state); 3904 } 3905 3906 static void vlv_post_disable_dp(struct intel_atomic_state *state, 3907 struct intel_encoder *encoder, 3908 const struct intel_crtc_state *old_crtc_state, 3909 const struct drm_connector_state *old_conn_state) 3910 { 3911 intel_dp_link_down(encoder, old_crtc_state); 3912 } 3913 3914 static void chv_post_disable_dp(struct intel_atomic_state *state, 3915 struct intel_encoder *encoder, 3916 const struct intel_crtc_state *old_crtc_state, 3917 const struct drm_connector_state *old_conn_state) 3918 { 3919 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3920 3921 intel_dp_link_down(encoder, old_crtc_state); 3922 3923 vlv_dpio_get(dev_priv); 3924 3925 /* Assert data lane reset */ 3926 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 3927 3928 vlv_dpio_put(dev_priv); 3929 } 3930 3931 static void 3932 cpt_set_link_train(struct intel_dp *intel_dp, 3933 const struct intel_crtc_state *crtc_state, 3934 u8 dp_train_pat) 3935 { 3936 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3937 u32 *DP = &intel_dp->DP; 3938 3939 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 3940 3941 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3942 case DP_TRAINING_PATTERN_DISABLE: 3943 *DP |= DP_LINK_TRAIN_OFF_CPT; 3944 break; 3945 case DP_TRAINING_PATTERN_1: 3946 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 3947 break; 3948 case DP_TRAINING_PATTERN_2: 3949 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 3950 break; 3951 case DP_TRAINING_PATTERN_3: 3952 drm_dbg_kms(&dev_priv->drm, 3953 "TPS3 not supported, using TPS2 instead\n"); 3954 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 3955 break; 3956 } 3957 3958 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 3959 intel_de_posting_read(dev_priv, intel_dp->output_reg); 3960 } 3961 3962 static void 3963 g4x_set_link_train(struct intel_dp *intel_dp, 3964 const struct intel_crtc_state *crtc_state, 3965 u8 dp_train_pat) 3966 { 3967 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3968 u32 *DP = &intel_dp->DP; 3969 3970 *DP &= ~DP_LINK_TRAIN_MASK; 3971 3972 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3973 case DP_TRAINING_PATTERN_DISABLE: 3974 *DP |= DP_LINK_TRAIN_OFF; 3975 break; 3976 case DP_TRAINING_PATTERN_1: 3977 *DP |= DP_LINK_TRAIN_PAT_1; 3978 break; 3979 case DP_TRAINING_PATTERN_2: 3980 *DP |= DP_LINK_TRAIN_PAT_2; 3981 break; 3982 case DP_TRAINING_PATTERN_3: 3983 drm_dbg_kms(&dev_priv->drm, 3984 "TPS3 not supported, using TPS2 instead\n"); 3985 *DP |= DP_LINK_TRAIN_PAT_2; 3986 break; 3987 } 3988 3989 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 3990 intel_de_posting_read(dev_priv, intel_dp->output_reg); 3991 } 3992 3993 static void intel_dp_enable_port(struct intel_dp *intel_dp, 3994 const struct intel_crtc_state *crtc_state) 3995 { 3996 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3997 3998 /* enable with pattern 1 (as per spec) */ 3999 4000 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 4001 DP_TRAINING_PATTERN_1); 4002 4003 /* 4004 * Magic for VLV/CHV. We _must_ first set up the register 4005 * without actually enabling the port, and then do another 4006 * write to enable the port. Otherwise link training will 4007 * fail when the power sequencer is freshly used for this port. 4008 */ 4009 intel_dp->DP |= DP_PORT_EN; 4010 if (crtc_state->has_audio) 4011 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 4012 4013 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 4014 intel_de_posting_read(dev_priv, intel_dp->output_reg); 4015 } 4016 4017 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 4018 const struct intel_crtc_state *crtc_state) 4019 { 4020 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4021 u8 tmp; 4022 4023 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) 4024 return; 4025 4026 if (!drm_dp_is_branch(intel_dp->dpcd)) 4027 return; 4028 4029 tmp = intel_dp->has_hdmi_sink ? 4030 DP_HDMI_DVI_OUTPUT_CONFIG : 0; 4031 4032 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4033 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) 4034 drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n", 4035 enableddisabled(intel_dp->has_hdmi_sink)); 4036 4037 tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && 4038 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; 4039 4040 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4041 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) 4042 drm_dbg_kms(&i915->drm, 4043 "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n", 4044 enableddisabled(intel_dp->dfp.ycbcr_444_to_420)); 4045 4046 tmp = 0; 4047 4048 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4049 DP_PROTOCOL_CONVERTER_CONTROL_2, tmp) <= 0) 4050 drm_dbg_kms(&i915->drm, 4051 "Failed to set protocol converter YCbCr 4:2:2 conversion mode to %s\n", 4052 enableddisabled(false)); 4053 } 4054 4055 static void intel_enable_dp(struct intel_atomic_state *state, 4056 struct intel_encoder *encoder, 4057 const struct intel_crtc_state *pipe_config, 4058 const struct drm_connector_state *conn_state) 4059 { 4060 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4061 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4062 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4063 u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg); 4064 enum pipe pipe = crtc->pipe; 4065 intel_wakeref_t wakeref; 4066 4067 if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN)) 4068 return; 4069 4070 with_pps_lock(intel_dp, wakeref) { 4071 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4072 vlv_init_panel_power_sequencer(encoder, pipe_config); 4073 4074 intel_dp_enable_port(intel_dp, pipe_config); 4075 4076 edp_panel_vdd_on(intel_dp); 4077 edp_panel_on(intel_dp); 4078 edp_panel_vdd_off(intel_dp, true); 4079 } 4080 4081 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 4082 unsigned int lane_mask = 0x0; 4083 4084 if (IS_CHERRYVIEW(dev_priv)) 4085 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); 4086 4087 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), 4088 lane_mask); 4089 } 4090 4091 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 4092 intel_dp_configure_protocol_converter(intel_dp, pipe_config); 4093 intel_dp_start_link_train(intel_dp, pipe_config); 4094 intel_dp_stop_link_train(intel_dp, pipe_config); 4095 4096 if (pipe_config->has_audio) { 4097 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n", 4098 pipe_name(pipe)); 4099 intel_audio_codec_enable(encoder, pipe_config, conn_state); 4100 } 4101 } 4102 4103 static void g4x_enable_dp(struct intel_atomic_state *state, 4104 struct intel_encoder *encoder, 4105 const struct intel_crtc_state *pipe_config, 4106 const struct drm_connector_state *conn_state) 4107 { 4108 intel_enable_dp(state, encoder, pipe_config, conn_state); 4109 intel_edp_backlight_on(pipe_config, conn_state); 4110 } 4111 4112 static void vlv_enable_dp(struct intel_atomic_state *state, 4113 struct intel_encoder *encoder, 4114 const struct intel_crtc_state *pipe_config, 4115 const struct drm_connector_state *conn_state) 4116 { 4117 intel_edp_backlight_on(pipe_config, conn_state); 4118 } 4119 4120 static void g4x_pre_enable_dp(struct intel_atomic_state *state, 4121 struct intel_encoder *encoder, 4122 const struct intel_crtc_state *pipe_config, 4123 const struct drm_connector_state *conn_state) 4124 { 4125 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4126 enum port port = encoder->port; 4127 4128 intel_dp_prepare(encoder, pipe_config); 4129 4130 /* Only ilk+ has port A */ 4131 if (port == PORT_A) 4132 ilk_edp_pll_on(intel_dp, pipe_config); 4133 } 4134 4135 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) 4136 { 4137 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4138 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4139 enum pipe pipe = intel_dp->pps_pipe; 4140 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); 4141 4142 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE); 4143 4144 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) 4145 return; 4146 4147 edp_panel_vdd_off_sync(intel_dp); 4148 4149 /* 4150 * VLV seems to get confused when multiple power sequencers 4151 * have the same port selected (even if only one has power/vdd 4152 * enabled). The failure manifests as vlv_wait_port_ready() failing 4153 * CHV on the other hand doesn't seem to mind having the same port 4154 * selected in multiple power sequencers, but let's clear the 4155 * port select always when logically disconnecting a power sequencer 4156 * from a port. 4157 */ 4158 drm_dbg_kms(&dev_priv->drm, 4159 "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", 4160 pipe_name(pipe), dig_port->base.base.base.id, 4161 dig_port->base.base.name); 4162 intel_de_write(dev_priv, pp_on_reg, 0); 4163 intel_de_posting_read(dev_priv, pp_on_reg); 4164 4165 intel_dp->pps_pipe = INVALID_PIPE; 4166 } 4167 4168 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, 4169 enum pipe pipe) 4170 { 4171 struct intel_encoder *encoder; 4172 4173 lockdep_assert_held(&dev_priv->pps_mutex); 4174 4175 for_each_intel_dp(&dev_priv->drm, encoder) { 4176 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4177 4178 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe, 4179 "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n", 4180 pipe_name(pipe), encoder->base.base.id, 4181 encoder->base.name); 4182 4183 if (intel_dp->pps_pipe != pipe) 4184 continue; 4185 4186 drm_dbg_kms(&dev_priv->drm, 4187 "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n", 4188 pipe_name(pipe), encoder->base.base.id, 4189 encoder->base.name); 4190 4191 /* make sure vdd is off before we steal it */ 4192 vlv_detach_power_sequencer(intel_dp); 4193 } 4194 } 4195 4196 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, 4197 const struct intel_crtc_state *crtc_state) 4198 { 4199 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4200 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4201 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4202 4203 lockdep_assert_held(&dev_priv->pps_mutex); 4204 4205 drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE); 4206 4207 if (intel_dp->pps_pipe != INVALID_PIPE && 4208 intel_dp->pps_pipe != crtc->pipe) { 4209 /* 4210 * If another power sequencer was being used on this 4211 * port previously make sure to turn off vdd there while 4212 * we still have control of it. 4213 */ 4214 vlv_detach_power_sequencer(intel_dp); 4215 } 4216 4217 /* 4218 * We may be stealing the power 4219 * sequencer from another port. 4220 */ 4221 vlv_steal_power_sequencer(dev_priv, crtc->pipe); 4222 4223 intel_dp->active_pipe = crtc->pipe; 4224 4225 if (!intel_dp_is_edp(intel_dp)) 4226 return; 4227 4228 /* now it's all ours */ 4229 intel_dp->pps_pipe = crtc->pipe; 4230 4231 drm_dbg_kms(&dev_priv->drm, 4232 "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n", 4233 pipe_name(intel_dp->pps_pipe), encoder->base.base.id, 4234 encoder->base.name); 4235 4236 /* init power sequencer on this pipe and port */ 4237 intel_dp_init_panel_power_sequencer(intel_dp); 4238 intel_dp_init_panel_power_sequencer_registers(intel_dp, true); 4239 } 4240 4241 static void vlv_pre_enable_dp(struct intel_atomic_state *state, 4242 struct intel_encoder *encoder, 4243 const struct intel_crtc_state *pipe_config, 4244 const struct drm_connector_state *conn_state) 4245 { 4246 vlv_phy_pre_encoder_enable(encoder, pipe_config); 4247 4248 intel_enable_dp(state, encoder, pipe_config, conn_state); 4249 } 4250 4251 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state, 4252 struct intel_encoder *encoder, 4253 const struct intel_crtc_state *pipe_config, 4254 const struct drm_connector_state *conn_state) 4255 { 4256 intel_dp_prepare(encoder, pipe_config); 4257 4258 vlv_phy_pre_pll_enable(encoder, pipe_config); 4259 } 4260 4261 static void chv_pre_enable_dp(struct intel_atomic_state *state, 4262 struct intel_encoder *encoder, 4263 const struct intel_crtc_state *pipe_config, 4264 const struct drm_connector_state *conn_state) 4265 { 4266 chv_phy_pre_encoder_enable(encoder, pipe_config); 4267 4268 intel_enable_dp(state, encoder, pipe_config, conn_state); 4269 4270 /* Second common lane will stay alive on its own now */ 4271 chv_phy_release_cl2_override(encoder); 4272 } 4273 4274 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state, 4275 struct intel_encoder *encoder, 4276 const struct intel_crtc_state *pipe_config, 4277 const struct drm_connector_state *conn_state) 4278 { 4279 intel_dp_prepare(encoder, pipe_config); 4280 4281 chv_phy_pre_pll_enable(encoder, pipe_config); 4282 } 4283 4284 static void chv_dp_post_pll_disable(struct intel_atomic_state *state, 4285 struct intel_encoder *encoder, 4286 const struct intel_crtc_state *old_crtc_state, 4287 const struct drm_connector_state *old_conn_state) 4288 { 4289 chv_phy_post_pll_disable(encoder, old_crtc_state); 4290 } 4291 4292 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp, 4293 const struct intel_crtc_state *crtc_state) 4294 { 4295 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 4296 } 4297 4298 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp, 4299 const struct intel_crtc_state *crtc_state) 4300 { 4301 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 4302 } 4303 4304 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp) 4305 { 4306 return DP_TRAIN_PRE_EMPH_LEVEL_2; 4307 } 4308 4309 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp) 4310 { 4311 return DP_TRAIN_PRE_EMPH_LEVEL_3; 4312 } 4313 4314 static void vlv_set_signal_levels(struct intel_dp *intel_dp, 4315 const struct intel_crtc_state *crtc_state) 4316 { 4317 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4318 unsigned long demph_reg_value, preemph_reg_value, 4319 uniqtranscale_reg_value; 4320 u8 train_set = intel_dp->train_set[0]; 4321 4322 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 4323 case DP_TRAIN_PRE_EMPH_LEVEL_0: 4324 preemph_reg_value = 0x0004000; 4325 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 4326 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 4327 demph_reg_value = 0x2B405555; 4328 uniqtranscale_reg_value = 0x552AB83A; 4329 break; 4330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 4331 demph_reg_value = 0x2B404040; 4332 uniqtranscale_reg_value = 0x5548B83A; 4333 break; 4334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 4335 demph_reg_value = 0x2B245555; 4336 uniqtranscale_reg_value = 0x5560B83A; 4337 break; 4338 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 4339 demph_reg_value = 0x2B405555; 4340 uniqtranscale_reg_value = 0x5598DA3A; 4341 break; 4342 default: 4343 return; 4344 } 4345 break; 4346 case DP_TRAIN_PRE_EMPH_LEVEL_1: 4347 preemph_reg_value = 0x0002000; 4348 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 4349 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 4350 demph_reg_value = 0x2B404040; 4351 uniqtranscale_reg_value = 0x5552B83A; 4352 break; 4353 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 4354 demph_reg_value = 0x2B404848; 4355 uniqtranscale_reg_value = 0x5580B83A; 4356 break; 4357 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 4358 demph_reg_value = 0x2B404040; 4359 uniqtranscale_reg_value = 0x55ADDA3A; 4360 break; 4361 default: 4362 return; 4363 } 4364 break; 4365 case DP_TRAIN_PRE_EMPH_LEVEL_2: 4366 preemph_reg_value = 0x0000000; 4367 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 4368 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 4369 demph_reg_value = 0x2B305555; 4370 uniqtranscale_reg_value = 0x5570B83A; 4371 break; 4372 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 4373 demph_reg_value = 0x2B2B4040; 4374 uniqtranscale_reg_value = 0x55ADDA3A; 4375 break; 4376 default: 4377 return; 4378 } 4379 break; 4380 case DP_TRAIN_PRE_EMPH_LEVEL_3: 4381 preemph_reg_value = 0x0006000; 4382 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 4383 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 4384 demph_reg_value = 0x1B405555; 4385 uniqtranscale_reg_value = 0x55ADDA3A; 4386 break; 4387 default: 4388 return; 4389 } 4390 break; 4391 default: 4392 return; 4393 } 4394 4395 vlv_set_phy_signal_level(encoder, crtc_state, 4396 demph_reg_value, preemph_reg_value, 4397 uniqtranscale_reg_value, 0); 4398 } 4399 4400 static void chv_set_signal_levels(struct intel_dp *intel_dp, 4401 const struct intel_crtc_state *crtc_state) 4402 { 4403 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4404 u32 deemph_reg_value, margin_reg_value; 4405 bool uniq_trans_scale = false; 4406 u8 train_set = intel_dp->train_set[0]; 4407 4408 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 4409 case DP_TRAIN_PRE_EMPH_LEVEL_0: 4410 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 4411 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 4412 deemph_reg_value = 128; 4413 margin_reg_value = 52; 4414 break; 4415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 4416 deemph_reg_value = 128; 4417 margin_reg_value = 77; 4418 break; 4419 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 4420 deemph_reg_value = 128; 4421 margin_reg_value = 102; 4422 break; 4423 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 4424 deemph_reg_value = 128; 4425 margin_reg_value = 154; 4426 uniq_trans_scale = true; 4427 break; 4428 default: 4429 return; 4430 } 4431 break; 4432 case DP_TRAIN_PRE_EMPH_LEVEL_1: 4433 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 4434 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 4435 deemph_reg_value = 85; 4436 margin_reg_value = 78; 4437 break; 4438 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 4439 deemph_reg_value = 85; 4440 margin_reg_value = 116; 4441 break; 4442 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 4443 deemph_reg_value = 85; 4444 margin_reg_value = 154; 4445 break; 4446 default: 4447 return; 4448 } 4449 break; 4450 case DP_TRAIN_PRE_EMPH_LEVEL_2: 4451 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 4452 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 4453 deemph_reg_value = 64; 4454 margin_reg_value = 104; 4455 break; 4456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 4457 deemph_reg_value = 64; 4458 margin_reg_value = 154; 4459 break; 4460 default: 4461 return; 4462 } 4463 break; 4464 case DP_TRAIN_PRE_EMPH_LEVEL_3: 4465 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 4466 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 4467 deemph_reg_value = 43; 4468 margin_reg_value = 154; 4469 break; 4470 default: 4471 return; 4472 } 4473 break; 4474 default: 4475 return; 4476 } 4477 4478 chv_set_phy_signal_level(encoder, crtc_state, 4479 deemph_reg_value, margin_reg_value, 4480 uniq_trans_scale); 4481 } 4482 4483 static u32 g4x_signal_levels(u8 train_set) 4484 { 4485 u32 signal_levels = 0; 4486 4487 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 4488 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 4489 default: 4490 signal_levels |= DP_VOLTAGE_0_4; 4491 break; 4492 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 4493 signal_levels |= DP_VOLTAGE_0_6; 4494 break; 4495 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 4496 signal_levels |= DP_VOLTAGE_0_8; 4497 break; 4498 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 4499 signal_levels |= DP_VOLTAGE_1_2; 4500 break; 4501 } 4502 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 4503 case DP_TRAIN_PRE_EMPH_LEVEL_0: 4504 default: 4505 signal_levels |= DP_PRE_EMPHASIS_0; 4506 break; 4507 case DP_TRAIN_PRE_EMPH_LEVEL_1: 4508 signal_levels |= DP_PRE_EMPHASIS_3_5; 4509 break; 4510 case DP_TRAIN_PRE_EMPH_LEVEL_2: 4511 signal_levels |= DP_PRE_EMPHASIS_6; 4512 break; 4513 case DP_TRAIN_PRE_EMPH_LEVEL_3: 4514 signal_levels |= DP_PRE_EMPHASIS_9_5; 4515 break; 4516 } 4517 return signal_levels; 4518 } 4519 4520 static void 4521 g4x_set_signal_levels(struct intel_dp *intel_dp, 4522 const struct intel_crtc_state *crtc_state) 4523 { 4524 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4525 u8 train_set = intel_dp->train_set[0]; 4526 u32 signal_levels; 4527 4528 signal_levels = g4x_signal_levels(train_set); 4529 4530 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 4531 signal_levels); 4532 4533 intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK); 4534 intel_dp->DP |= signal_levels; 4535 4536 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 4537 intel_de_posting_read(dev_priv, intel_dp->output_reg); 4538 } 4539 4540 /* SNB CPU eDP voltage swing and pre-emphasis control */ 4541 static u32 snb_cpu_edp_signal_levels(u8 train_set) 4542 { 4543 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 4544 DP_TRAIN_PRE_EMPHASIS_MASK); 4545 4546 switch (signal_levels) { 4547 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 4548 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 4549 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 4550 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 4551 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 4552 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 4553 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 4554 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 4555 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 4556 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 4557 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 4558 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 4559 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 4560 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 4561 default: 4562 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 4563 "0x%x\n", signal_levels); 4564 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 4565 } 4566 } 4567 4568 static void 4569 snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, 4570 const struct intel_crtc_state *crtc_state) 4571 { 4572 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4573 u8 train_set = intel_dp->train_set[0]; 4574 u32 signal_levels; 4575 4576 signal_levels = snb_cpu_edp_signal_levels(train_set); 4577 4578 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 4579 signal_levels); 4580 4581 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 4582 intel_dp->DP |= signal_levels; 4583 4584 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 4585 intel_de_posting_read(dev_priv, intel_dp->output_reg); 4586 } 4587 4588 /* IVB CPU eDP voltage swing and pre-emphasis control */ 4589 static u32 ivb_cpu_edp_signal_levels(u8 train_set) 4590 { 4591 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 4592 DP_TRAIN_PRE_EMPHASIS_MASK); 4593 4594 switch (signal_levels) { 4595 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 4596 return EDP_LINK_TRAIN_400MV_0DB_IVB; 4597 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 4598 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 4599 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 4600 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 4601 return EDP_LINK_TRAIN_400MV_6DB_IVB; 4602 4603 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 4604 return EDP_LINK_TRAIN_600MV_0DB_IVB; 4605 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 4606 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 4607 4608 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 4609 return EDP_LINK_TRAIN_800MV_0DB_IVB; 4610 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 4611 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 4612 4613 default: 4614 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 4615 "0x%x\n", signal_levels); 4616 return EDP_LINK_TRAIN_500MV_0DB_IVB; 4617 } 4618 } 4619 4620 static void 4621 ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp, 4622 const struct intel_crtc_state *crtc_state) 4623 { 4624 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4625 u8 train_set = intel_dp->train_set[0]; 4626 u32 signal_levels; 4627 4628 signal_levels = ivb_cpu_edp_signal_levels(train_set); 4629 4630 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 4631 signal_levels); 4632 4633 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 4634 intel_dp->DP |= signal_levels; 4635 4636 intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); 4637 intel_de_posting_read(dev_priv, intel_dp->output_reg); 4638 } 4639 4640 void 4641 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 4642 const struct intel_crtc_state *crtc_state, 4643 u8 dp_train_pat) 4644 { 4645 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4646 4647 if ((intel_dp_training_pattern_symbol(dp_train_pat)) != 4648 DP_TRAINING_PATTERN_DISABLE) 4649 drm_dbg_kms(&dev_priv->drm, 4650 "Using DP training pattern TPS%d\n", 4651 intel_dp_training_pattern_symbol(dp_train_pat)); 4652 4653 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); 4654 } 4655 4656 static void 4657 intel_dp_link_down(struct intel_encoder *encoder, 4658 const struct intel_crtc_state *old_crtc_state) 4659 { 4660 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4661 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4662 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 4663 enum port port = encoder->port; 4664 u32 DP = intel_dp->DP; 4665 4666 if (drm_WARN_ON(&dev_priv->drm, 4667 (intel_de_read(dev_priv, intel_dp->output_reg) & 4668 DP_PORT_EN) == 0)) 4669 return; 4670 4671 drm_dbg_kms(&dev_priv->drm, "\n"); 4672 4673 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || 4674 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { 4675 DP &= ~DP_LINK_TRAIN_MASK_CPT; 4676 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 4677 } else { 4678 DP &= ~DP_LINK_TRAIN_MASK; 4679 DP |= DP_LINK_TRAIN_PAT_IDLE; 4680 } 4681 intel_de_write(dev_priv, intel_dp->output_reg, DP); 4682 intel_de_posting_read(dev_priv, intel_dp->output_reg); 4683 4684 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 4685 intel_de_write(dev_priv, intel_dp->output_reg, DP); 4686 intel_de_posting_read(dev_priv, intel_dp->output_reg); 4687 4688 /* 4689 * HW workaround for IBX, we need to move the port 4690 * to transcoder A after disabling it to allow the 4691 * matching HDMI port to be enabled on transcoder A. 4692 */ 4693 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { 4694 /* 4695 * We get CPU/PCH FIFO underruns on the other pipe when 4696 * doing the workaround. Sweep them under the rug. 4697 */ 4698 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 4699 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 4700 4701 /* always enable with pattern 1 (as per spec) */ 4702 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); 4703 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | 4704 DP_LINK_TRAIN_PAT_1; 4705 intel_de_write(dev_priv, intel_dp->output_reg, DP); 4706 intel_de_posting_read(dev_priv, intel_dp->output_reg); 4707 4708 DP &= ~DP_PORT_EN; 4709 intel_de_write(dev_priv, intel_dp->output_reg, DP); 4710 intel_de_posting_read(dev_priv, intel_dp->output_reg); 4711 4712 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 4713 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 4714 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 4715 } 4716 4717 msleep(intel_dp->panel_power_down_delay); 4718 4719 intel_dp->DP = DP; 4720 4721 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 4722 intel_wakeref_t wakeref; 4723 4724 with_pps_lock(intel_dp, wakeref) 4725 intel_dp->active_pipe = INVALID_PIPE; 4726 } 4727 } 4728 4729 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) 4730 { 4731 u8 dprx = 0; 4732 4733 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 4734 &dprx) != 1) 4735 return false; 4736 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; 4737 } 4738 4739 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) 4740 { 4741 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4742 4743 /* 4744 * Clear the cached register set to avoid using stale values 4745 * for the sinks that do not support DSC. 4746 */ 4747 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); 4748 4749 /* Clear fec_capable to avoid using stale values */ 4750 intel_dp->fec_capable = 0; 4751 4752 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ 4753 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || 4754 intel_dp->edp_dpcd[0] >= DP_EDP_14) { 4755 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, 4756 intel_dp->dsc_dpcd, 4757 sizeof(intel_dp->dsc_dpcd)) < 0) 4758 drm_err(&i915->drm, 4759 "Failed to read DPCD register 0x%x\n", 4760 DP_DSC_SUPPORT); 4761 4762 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n", 4763 (int)sizeof(intel_dp->dsc_dpcd), 4764 intel_dp->dsc_dpcd); 4765 4766 /* FEC is supported only on DP 1.4 */ 4767 if (!intel_dp_is_edp(intel_dp) && 4768 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, 4769 &intel_dp->fec_capable) < 0) 4770 drm_err(&i915->drm, 4771 "Failed to read FEC DPCD register\n"); 4772 4773 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", 4774 intel_dp->fec_capable); 4775 } 4776 } 4777 4778 static bool 4779 intel_edp_init_dpcd(struct intel_dp *intel_dp) 4780 { 4781 struct drm_i915_private *dev_priv = 4782 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 4783 4784 /* this function is meant to be called only once */ 4785 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); 4786 4787 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) 4788 return false; 4789 4790 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4791 drm_dp_is_branch(intel_dp->dpcd)); 4792 4793 /* 4794 * Read the eDP display control registers. 4795 * 4796 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in 4797 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it 4798 * set, but require eDP 1.4+ detection (e.g. for supported link rates 4799 * method). The display control registers should read zero if they're 4800 * not supported anyway. 4801 */ 4802 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 4803 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 4804 sizeof(intel_dp->edp_dpcd)) 4805 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", 4806 (int)sizeof(intel_dp->edp_dpcd), 4807 intel_dp->edp_dpcd); 4808 4809 /* 4810 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 4811 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 4812 */ 4813 intel_psr_init_dpcd(intel_dp); 4814 4815 /* Read the eDP 1.4+ supported link rates. */ 4816 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { 4817 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 4818 int i; 4819 4820 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 4821 sink_rates, sizeof(sink_rates)); 4822 4823 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 4824 int val = le16_to_cpu(sink_rates[i]); 4825 4826 if (val == 0) 4827 break; 4828 4829 /* Value read multiplied by 200kHz gives the per-lane 4830 * link rate in kHz. The source rates are, however, 4831 * stored in terms of LS_Clk kHz. The full conversion 4832 * back to symbols is 4833 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) 4834 */ 4835 intel_dp->sink_rates[i] = (val * 200) / 10; 4836 } 4837 intel_dp->num_sink_rates = i; 4838 } 4839 4840 /* 4841 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, 4842 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. 4843 */ 4844 if (intel_dp->num_sink_rates) 4845 intel_dp->use_rate_select = true; 4846 else 4847 intel_dp_set_sink_rates(intel_dp); 4848 4849 intel_dp_set_common_rates(intel_dp); 4850 4851 /* Read the eDP DSC DPCD registers */ 4852 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 4853 intel_dp_get_dsc_sink_cap(intel_dp); 4854 4855 return true; 4856 } 4857 4858 static bool 4859 intel_dp_has_sink_count(struct intel_dp *intel_dp) 4860 { 4861 if (!intel_dp->attached_connector) 4862 return false; 4863 4864 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, 4865 intel_dp->dpcd, 4866 &intel_dp->desc); 4867 } 4868 4869 static bool 4870 intel_dp_get_dpcd(struct intel_dp *intel_dp) 4871 { 4872 int ret; 4873 4874 intel_dp_lttpr_init(intel_dp); 4875 4876 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) 4877 return false; 4878 4879 /* 4880 * Don't clobber cached eDP rates. Also skip re-reading 4881 * the OUI/ID since we know it won't change. 4882 */ 4883 if (!intel_dp_is_edp(intel_dp)) { 4884 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4885 drm_dp_is_branch(intel_dp->dpcd)); 4886 4887 intel_dp_set_sink_rates(intel_dp); 4888 intel_dp_set_common_rates(intel_dp); 4889 } 4890 4891 if (intel_dp_has_sink_count(intel_dp)) { 4892 ret = drm_dp_read_sink_count(&intel_dp->aux); 4893 if (ret < 0) 4894 return false; 4895 4896 /* 4897 * Sink count can change between short pulse hpd hence 4898 * a member variable in intel_dp will track any changes 4899 * between short pulse interrupts. 4900 */ 4901 intel_dp->sink_count = ret; 4902 4903 /* 4904 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 4905 * a dongle is present but no display. Unless we require to know 4906 * if a dongle is present or not, we don't need to update 4907 * downstream port information. So, an early return here saves 4908 * time from performing other operations which are not required. 4909 */ 4910 if (!intel_dp->sink_count) 4911 return false; 4912 } 4913 4914 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, 4915 intel_dp->downstream_ports) == 0; 4916 } 4917 4918 static bool 4919 intel_dp_can_mst(struct intel_dp *intel_dp) 4920 { 4921 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4922 4923 return i915->params.enable_dp_mst && 4924 intel_dp->can_mst && 4925 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 4926 } 4927 4928 static void 4929 intel_dp_configure_mst(struct intel_dp *intel_dp) 4930 { 4931 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4932 struct intel_encoder *encoder = 4933 &dp_to_dig_port(intel_dp)->base; 4934 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 4935 4936 drm_dbg_kms(&i915->drm, 4937 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n", 4938 encoder->base.base.id, encoder->base.name, 4939 yesno(intel_dp->can_mst), yesno(sink_can_mst), 4940 yesno(i915->params.enable_dp_mst)); 4941 4942 if (!intel_dp->can_mst) 4943 return; 4944 4945 intel_dp->is_mst = sink_can_mst && 4946 i915->params.enable_dp_mst; 4947 4948 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4949 intel_dp->is_mst); 4950 } 4951 4952 static bool 4953 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) 4954 { 4955 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, 4956 sink_irq_vector, DP_DPRX_ESI_LEN) == 4957 DP_DPRX_ESI_LEN; 4958 } 4959 4960 bool 4961 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 4962 const struct drm_connector_state *conn_state) 4963 { 4964 /* 4965 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 4966 * of Color Encoding Format and Content Color Gamut], in order to 4967 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. 4968 */ 4969 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 4970 return true; 4971 4972 switch (conn_state->colorspace) { 4973 case DRM_MODE_COLORIMETRY_SYCC_601: 4974 case DRM_MODE_COLORIMETRY_OPYCC_601: 4975 case DRM_MODE_COLORIMETRY_BT2020_YCC: 4976 case DRM_MODE_COLORIMETRY_BT2020_RGB: 4977 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 4978 return true; 4979 default: 4980 break; 4981 } 4982 4983 return false; 4984 } 4985 4986 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 4987 struct dp_sdp *sdp, size_t size) 4988 { 4989 size_t length = sizeof(struct dp_sdp); 4990 4991 if (size < length) 4992 return -ENOSPC; 4993 4994 memset(sdp, 0, size); 4995 4996 /* 4997 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 4998 * VSC SDP Header Bytes 4999 */ 5000 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ 5001 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ 5002 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ 5003 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ 5004 5005 /* 5006 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as 5007 * per DP 1.4a spec. 5008 */ 5009 if (vsc->revision != 0x5) 5010 goto out; 5011 5012 /* VSC SDP Payload for DB16 through DB18 */ 5013 /* Pixel Encoding and Colorimetry Formats */ 5014 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ 5015 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ 5016 5017 switch (vsc->bpc) { 5018 case 6: 5019 /* 6bpc: 0x0 */ 5020 break; 5021 case 8: 5022 sdp->db[17] = 0x1; /* DB17[3:0] */ 5023 break; 5024 case 10: 5025 sdp->db[17] = 0x2; 5026 break; 5027 case 12: 5028 sdp->db[17] = 0x3; 5029 break; 5030 case 16: 5031 sdp->db[17] = 0x4; 5032 break; 5033 default: 5034 MISSING_CASE(vsc->bpc); 5035 break; 5036 } 5037 /* Dynamic Range and Component Bit Depth */ 5038 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 5039 sdp->db[17] |= 0x80; /* DB17[7] */ 5040 5041 /* Content Type */ 5042 sdp->db[18] = vsc->content_type & 0x7; 5043 5044 out: 5045 return length; 5046 } 5047 5048 static ssize_t 5049 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe, 5050 struct dp_sdp *sdp, 5051 size_t size) 5052 { 5053 size_t length = sizeof(struct dp_sdp); 5054 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; 5055 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; 5056 ssize_t len; 5057 5058 if (size < length) 5059 return -ENOSPC; 5060 5061 memset(sdp, 0, size); 5062 5063 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); 5064 if (len < 0) { 5065 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n"); 5066 return -ENOSPC; 5067 } 5068 5069 if (len != infoframe_size) { 5070 DRM_DEBUG_KMS("wrong static hdr metadata size\n"); 5071 return -ENOSPC; 5072 } 5073 5074 /* 5075 * Set up the infoframe sdp packet for HDR static metadata. 5076 * Prepare VSC Header for SU as per DP 1.4a spec, 5077 * Table 2-100 and Table 2-101 5078 */ 5079 5080 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ 5081 sdp->sdp_header.HB0 = 0; 5082 /* 5083 * Packet Type 80h + Non-audio INFOFRAME Type value 5084 * HDMI_INFOFRAME_TYPE_DRM: 0x87 5085 * - 80h + Non-audio INFOFRAME Type value 5086 * - InfoFrame Type: 0x07 5087 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] 5088 */ 5089 sdp->sdp_header.HB1 = drm_infoframe->type; 5090 /* 5091 * Least Significant Eight Bits of (Data Byte Count – 1) 5092 * infoframe_size - 1 5093 */ 5094 sdp->sdp_header.HB2 = 0x1D; 5095 /* INFOFRAME SDP Version Number */ 5096 sdp->sdp_header.HB3 = (0x13 << 2); 5097 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 5098 sdp->db[0] = drm_infoframe->version; 5099 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 5100 sdp->db[1] = drm_infoframe->length; 5101 /* 5102 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after 5103 * HDMI_INFOFRAME_HEADER_SIZE 5104 */ 5105 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); 5106 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], 5107 HDMI_DRM_INFOFRAME_SIZE); 5108 5109 /* 5110 * Size of DP infoframe sdp packet for HDR static metadata consists of 5111 * - DP SDP Header(struct dp_sdp_header): 4 bytes 5112 * - Two Data Blocks: 2 bytes 5113 * CTA Header Byte2 (INFOFRAME Version Number) 5114 * CTA Header Byte3 (Length of INFOFRAME) 5115 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes 5116 * 5117 * Prior to GEN11's GMP register size is identical to DP HDR static metadata 5118 * infoframe size. But GEN11+ has larger than that size, write_infoframe 5119 * will pad rest of the size. 5120 */ 5121 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; 5122 } 5123 5124 static void intel_write_dp_sdp(struct intel_encoder *encoder, 5125 const struct intel_crtc_state *crtc_state, 5126 unsigned int type) 5127 { 5128 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5129 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5130 struct dp_sdp sdp = {}; 5131 ssize_t len; 5132 5133 if ((crtc_state->infoframes.enable & 5134 intel_hdmi_infoframe_enable(type)) == 0) 5135 return; 5136 5137 switch (type) { 5138 case DP_SDP_VSC: 5139 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp, 5140 sizeof(sdp)); 5141 break; 5142 case HDMI_PACKET_TYPE_GAMUT_METADATA: 5143 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm, 5144 &sdp, sizeof(sdp)); 5145 break; 5146 default: 5147 MISSING_CASE(type); 5148 return; 5149 } 5150 5151 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 5152 return; 5153 5154 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); 5155 } 5156 5157 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, 5158 const struct intel_crtc_state *crtc_state, 5159 struct drm_dp_vsc_sdp *vsc) 5160 { 5161 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5162 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5163 struct dp_sdp sdp = {}; 5164 ssize_t len; 5165 5166 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp)); 5167 5168 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 5169 return; 5170 5171 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, 5172 &sdp, len); 5173 } 5174 5175 void intel_dp_set_infoframes(struct intel_encoder *encoder, 5176 bool enable, 5177 const struct intel_crtc_state *crtc_state, 5178 const struct drm_connector_state *conn_state) 5179 { 5180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5181 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5182 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 5183 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 5184 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | 5185 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; 5186 u32 val = intel_de_read(dev_priv, reg); 5187 5188 /* TODO: Add DSC case (DIP_ENABLE_PPS) */ 5189 /* When PSR is enabled, this routine doesn't disable VSC DIP */ 5190 if (intel_psr_enabled(intel_dp)) 5191 val &= ~dip_enable; 5192 else 5193 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW); 5194 5195 if (!enable) { 5196 intel_de_write(dev_priv, reg, val); 5197 intel_de_posting_read(dev_priv, reg); 5198 return; 5199 } 5200 5201 intel_de_write(dev_priv, reg, val); 5202 intel_de_posting_read(dev_priv, reg); 5203 5204 /* When PSR is enabled, VSC SDP is handled by PSR routine */ 5205 if (!intel_psr_enabled(intel_dp)) 5206 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); 5207 5208 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); 5209 } 5210 5211 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, 5212 const void *buffer, size_t size) 5213 { 5214 const struct dp_sdp *sdp = buffer; 5215 5216 if (size < sizeof(struct dp_sdp)) 5217 return -EINVAL; 5218 5219 memset(vsc, 0, size); 5220 5221 if (sdp->sdp_header.HB0 != 0) 5222 return -EINVAL; 5223 5224 if (sdp->sdp_header.HB1 != DP_SDP_VSC) 5225 return -EINVAL; 5226 5227 vsc->sdp_type = sdp->sdp_header.HB1; 5228 vsc->revision = sdp->sdp_header.HB2; 5229 vsc->length = sdp->sdp_header.HB3; 5230 5231 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || 5232 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) { 5233 /* 5234 * - HB2 = 0x2, HB3 = 0x8 5235 * VSC SDP supporting 3D stereo + PSR 5236 * - HB2 = 0x4, HB3 = 0xe 5237 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of 5238 * first scan line of the SU region (applies to eDP v1.4b 5239 * and higher). 5240 */ 5241 return 0; 5242 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { 5243 /* 5244 * - HB2 = 0x5, HB3 = 0x13 5245 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry 5246 * Format. 5247 */ 5248 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; 5249 vsc->colorimetry = sdp->db[16] & 0xf; 5250 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; 5251 5252 switch (sdp->db[17] & 0x7) { 5253 case 0x0: 5254 vsc->bpc = 6; 5255 break; 5256 case 0x1: 5257 vsc->bpc = 8; 5258 break; 5259 case 0x2: 5260 vsc->bpc = 10; 5261 break; 5262 case 0x3: 5263 vsc->bpc = 12; 5264 break; 5265 case 0x4: 5266 vsc->bpc = 16; 5267 break; 5268 default: 5269 MISSING_CASE(sdp->db[17] & 0x7); 5270 return -EINVAL; 5271 } 5272 5273 vsc->content_type = sdp->db[18] & 0x7; 5274 } else { 5275 return -EINVAL; 5276 } 5277 5278 return 0; 5279 } 5280 5281 static int 5282 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, 5283 const void *buffer, size_t size) 5284 { 5285 int ret; 5286 5287 const struct dp_sdp *sdp = buffer; 5288 5289 if (size < sizeof(struct dp_sdp)) 5290 return -EINVAL; 5291 5292 if (sdp->sdp_header.HB0 != 0) 5293 return -EINVAL; 5294 5295 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) 5296 return -EINVAL; 5297 5298 /* 5299 * Least Significant Eight Bits of (Data Byte Count – 1) 5300 * 1Dh (i.e., Data Byte Count = 30 bytes). 5301 */ 5302 if (sdp->sdp_header.HB2 != 0x1D) 5303 return -EINVAL; 5304 5305 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ 5306 if ((sdp->sdp_header.HB3 & 0x3) != 0) 5307 return -EINVAL; 5308 5309 /* INFOFRAME SDP Version Number */ 5310 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) 5311 return -EINVAL; 5312 5313 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 5314 if (sdp->db[0] != 1) 5315 return -EINVAL; 5316 5317 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 5318 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) 5319 return -EINVAL; 5320 5321 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], 5322 HDMI_DRM_INFOFRAME_SIZE); 5323 5324 return ret; 5325 } 5326 5327 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, 5328 struct intel_crtc_state *crtc_state, 5329 struct drm_dp_vsc_sdp *vsc) 5330 { 5331 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5332 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5333 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5334 unsigned int type = DP_SDP_VSC; 5335 struct dp_sdp sdp = {}; 5336 int ret; 5337 5338 /* When PSR is enabled, VSC SDP is handled by PSR routine */ 5339 if (intel_psr_enabled(intel_dp)) 5340 return; 5341 5342 if ((crtc_state->infoframes.enable & 5343 intel_hdmi_infoframe_enable(type)) == 0) 5344 return; 5345 5346 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); 5347 5348 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); 5349 5350 if (ret) 5351 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n"); 5352 } 5353 5354 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, 5355 struct intel_crtc_state *crtc_state, 5356 struct hdmi_drm_infoframe *drm_infoframe) 5357 { 5358 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5359 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5360 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; 5361 struct dp_sdp sdp = {}; 5362 int ret; 5363 5364 if ((crtc_state->infoframes.enable & 5365 intel_hdmi_infoframe_enable(type)) == 0) 5366 return; 5367 5368 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 5369 sizeof(sdp)); 5370 5371 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, 5372 sizeof(sdp)); 5373 5374 if (ret) 5375 drm_dbg_kms(&dev_priv->drm, 5376 "Failed to unpack DP HDR Metadata Infoframe SDP\n"); 5377 } 5378 5379 void intel_read_dp_sdp(struct intel_encoder *encoder, 5380 struct intel_crtc_state *crtc_state, 5381 unsigned int type) 5382 { 5383 if (encoder->type != INTEL_OUTPUT_DDI) 5384 return; 5385 5386 switch (type) { 5387 case DP_SDP_VSC: 5388 intel_read_dp_vsc_sdp(encoder, crtc_state, 5389 &crtc_state->infoframes.vsc); 5390 break; 5391 case HDMI_PACKET_TYPE_GAMUT_METADATA: 5392 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, 5393 &crtc_state->infoframes.drm.drm); 5394 break; 5395 default: 5396 MISSING_CASE(type); 5397 break; 5398 } 5399 } 5400 5401 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) 5402 { 5403 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5404 int status = 0; 5405 int test_link_rate; 5406 u8 test_lane_count, test_link_bw; 5407 /* (DP CTS 1.2) 5408 * 4.3.1.11 5409 */ 5410 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ 5411 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, 5412 &test_lane_count); 5413 5414 if (status <= 0) { 5415 drm_dbg_kms(&i915->drm, "Lane count read failed\n"); 5416 return DP_TEST_NAK; 5417 } 5418 test_lane_count &= DP_MAX_LANE_COUNT_MASK; 5419 5420 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, 5421 &test_link_bw); 5422 if (status <= 0) { 5423 drm_dbg_kms(&i915->drm, "Link Rate read failed\n"); 5424 return DP_TEST_NAK; 5425 } 5426 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); 5427 5428 /* Validate the requested link rate and lane count */ 5429 if (!intel_dp_link_params_valid(intel_dp, test_link_rate, 5430 test_lane_count)) 5431 return DP_TEST_NAK; 5432 5433 intel_dp->compliance.test_lane_count = test_lane_count; 5434 intel_dp->compliance.test_link_rate = test_link_rate; 5435 5436 return DP_TEST_ACK; 5437 } 5438 5439 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) 5440 { 5441 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5442 u8 test_pattern; 5443 u8 test_misc; 5444 __be16 h_width, v_height; 5445 int status = 0; 5446 5447 /* Read the TEST_PATTERN (DP CTS 3.1.5) */ 5448 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, 5449 &test_pattern); 5450 if (status <= 0) { 5451 drm_dbg_kms(&i915->drm, "Test pattern read failed\n"); 5452 return DP_TEST_NAK; 5453 } 5454 if (test_pattern != DP_COLOR_RAMP) 5455 return DP_TEST_NAK; 5456 5457 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, 5458 &h_width, 2); 5459 if (status <= 0) { 5460 drm_dbg_kms(&i915->drm, "H Width read failed\n"); 5461 return DP_TEST_NAK; 5462 } 5463 5464 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, 5465 &v_height, 2); 5466 if (status <= 0) { 5467 drm_dbg_kms(&i915->drm, "V Height read failed\n"); 5468 return DP_TEST_NAK; 5469 } 5470 5471 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, 5472 &test_misc); 5473 if (status <= 0) { 5474 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n"); 5475 return DP_TEST_NAK; 5476 } 5477 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) 5478 return DP_TEST_NAK; 5479 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) 5480 return DP_TEST_NAK; 5481 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { 5482 case DP_TEST_BIT_DEPTH_6: 5483 intel_dp->compliance.test_data.bpc = 6; 5484 break; 5485 case DP_TEST_BIT_DEPTH_8: 5486 intel_dp->compliance.test_data.bpc = 8; 5487 break; 5488 default: 5489 return DP_TEST_NAK; 5490 } 5491 5492 intel_dp->compliance.test_data.video_pattern = test_pattern; 5493 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); 5494 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); 5495 /* Set test active flag here so userspace doesn't interrupt things */ 5496 intel_dp->compliance.test_active = true; 5497 5498 return DP_TEST_ACK; 5499 } 5500 5501 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) 5502 { 5503 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5504 u8 test_result = DP_TEST_ACK; 5505 struct intel_connector *intel_connector = intel_dp->attached_connector; 5506 struct drm_connector *connector = &intel_connector->base; 5507 5508 if (intel_connector->detect_edid == NULL || 5509 connector->edid_corrupt || 5510 intel_dp->aux.i2c_defer_count > 6) { 5511 /* Check EDID read for NACKs, DEFERs and corruption 5512 * (DP CTS 1.2 Core r1.1) 5513 * 4.2.2.4 : Failed EDID read, I2C_NAK 5514 * 4.2.2.5 : Failed EDID read, I2C_DEFER 5515 * 4.2.2.6 : EDID corruption detected 5516 * Use failsafe mode for all cases 5517 */ 5518 if (intel_dp->aux.i2c_nack_count > 0 || 5519 intel_dp->aux.i2c_defer_count > 0) 5520 drm_dbg_kms(&i915->drm, 5521 "EDID read had %d NACKs, %d DEFERs\n", 5522 intel_dp->aux.i2c_nack_count, 5523 intel_dp->aux.i2c_defer_count); 5524 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; 5525 } else { 5526 struct edid *block = intel_connector->detect_edid; 5527 5528 /* We have to write the checksum 5529 * of the last block read 5530 */ 5531 block += intel_connector->detect_edid->extensions; 5532 5533 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, 5534 block->checksum) <= 0) 5535 drm_dbg_kms(&i915->drm, 5536 "Failed to write EDID checksum\n"); 5537 5538 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; 5539 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; 5540 } 5541 5542 /* Set test active flag here so userspace doesn't interrupt things */ 5543 intel_dp->compliance.test_active = true; 5544 5545 return test_result; 5546 } 5547 5548 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, 5549 const struct intel_crtc_state *crtc_state) 5550 { 5551 struct drm_i915_private *dev_priv = 5552 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 5553 struct drm_dp_phy_test_params *data = 5554 &intel_dp->compliance.test_data.phytest; 5555 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5556 enum pipe pipe = crtc->pipe; 5557 u32 pattern_val; 5558 5559 switch (data->phy_pattern) { 5560 case DP_PHY_TEST_PATTERN_NONE: 5561 DRM_DEBUG_KMS("Disable Phy Test Pattern\n"); 5562 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); 5563 break; 5564 case DP_PHY_TEST_PATTERN_D10_2: 5565 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n"); 5566 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 5567 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); 5568 break; 5569 case DP_PHY_TEST_PATTERN_ERROR_COUNT: 5570 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n"); 5571 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 5572 DDI_DP_COMP_CTL_ENABLE | 5573 DDI_DP_COMP_CTL_SCRAMBLED_0); 5574 break; 5575 case DP_PHY_TEST_PATTERN_PRBS7: 5576 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n"); 5577 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 5578 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); 5579 break; 5580 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 5581 /* 5582 * FIXME: Ideally pattern should come from DPCD 0x250. As 5583 * current firmware of DPR-100 could not set it, so hardcoding 5584 * now for complaince test. 5585 */ 5586 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); 5587 pattern_val = 0x3e0f83e0; 5588 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); 5589 pattern_val = 0x0f83e0f8; 5590 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); 5591 pattern_val = 0x0000f83e; 5592 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); 5593 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 5594 DDI_DP_COMP_CTL_ENABLE | 5595 DDI_DP_COMP_CTL_CUSTOM80); 5596 break; 5597 case DP_PHY_TEST_PATTERN_CP2520: 5598 /* 5599 * FIXME: Ideally pattern should come from DPCD 0x24A. As 5600 * current firmware of DPR-100 could not set it, so hardcoding 5601 * now for complaince test. 5602 */ 5603 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n"); 5604 pattern_val = 0xFB; 5605 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 5606 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | 5607 pattern_val); 5608 break; 5609 default: 5610 WARN(1, "Invalid Phy Test Pattern\n"); 5611 } 5612 } 5613 5614 static void 5615 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp, 5616 const struct intel_crtc_state *crtc_state) 5617 { 5618 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5619 struct drm_device *dev = dig_port->base.base.dev; 5620 struct drm_i915_private *dev_priv = to_i915(dev); 5621 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 5622 enum pipe pipe = crtc->pipe; 5623 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; 5624 5625 trans_ddi_func_ctl_value = intel_de_read(dev_priv, 5626 TRANS_DDI_FUNC_CTL(pipe)); 5627 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); 5628 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); 5629 5630 trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | 5631 TGL_TRANS_DDI_PORT_MASK); 5632 trans_conf_value &= ~PIPECONF_ENABLE; 5633 dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; 5634 5635 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); 5636 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), 5637 trans_ddi_func_ctl_value); 5638 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); 5639 } 5640 5641 static void 5642 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, 5643 const struct intel_crtc_state *crtc_state) 5644 { 5645 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5646 struct drm_device *dev = dig_port->base.base.dev; 5647 struct drm_i915_private *dev_priv = to_i915(dev); 5648 enum port port = dig_port->base.port; 5649 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 5650 enum pipe pipe = crtc->pipe; 5651 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; 5652 5653 trans_ddi_func_ctl_value = intel_de_read(dev_priv, 5654 TRANS_DDI_FUNC_CTL(pipe)); 5655 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); 5656 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); 5657 5658 trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | 5659 TGL_TRANS_DDI_SELECT_PORT(port); 5660 trans_conf_value |= PIPECONF_ENABLE; 5661 dp_tp_ctl_value |= DP_TP_CTL_ENABLE; 5662 5663 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); 5664 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); 5665 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), 5666 trans_ddi_func_ctl_value); 5667 } 5668 5669 static void intel_dp_process_phy_request(struct intel_dp *intel_dp, 5670 const struct intel_crtc_state *crtc_state) 5671 { 5672 struct drm_dp_phy_test_params *data = 5673 &intel_dp->compliance.test_data.phytest; 5674 u8 link_status[DP_LINK_STATUS_SIZE]; 5675 5676 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 5677 link_status) < 0) { 5678 DRM_DEBUG_KMS("failed to get link status\n"); 5679 return; 5680 } 5681 5682 /* retrieve vswing & pre-emphasis setting */ 5683 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, 5684 link_status); 5685 5686 intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state); 5687 5688 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX); 5689 5690 intel_dp_phy_pattern_update(intel_dp, crtc_state); 5691 5692 intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state); 5693 5694 drm_dp_set_phy_test_pattern(&intel_dp->aux, data, 5695 link_status[DP_DPCD_REV]); 5696 } 5697 5698 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) 5699 { 5700 struct drm_dp_phy_test_params *data = 5701 &intel_dp->compliance.test_data.phytest; 5702 5703 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) { 5704 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n"); 5705 return DP_TEST_NAK; 5706 } 5707 5708 /* Set test active flag here so userspace doesn't interrupt things */ 5709 intel_dp->compliance.test_active = true; 5710 5711 return DP_TEST_ACK; 5712 } 5713 5714 static void intel_dp_handle_test_request(struct intel_dp *intel_dp) 5715 { 5716 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5717 u8 response = DP_TEST_NAK; 5718 u8 request = 0; 5719 int status; 5720 5721 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); 5722 if (status <= 0) { 5723 drm_dbg_kms(&i915->drm, 5724 "Could not read test request from sink\n"); 5725 goto update_status; 5726 } 5727 5728 switch (request) { 5729 case DP_TEST_LINK_TRAINING: 5730 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n"); 5731 response = intel_dp_autotest_link_training(intel_dp); 5732 break; 5733 case DP_TEST_LINK_VIDEO_PATTERN: 5734 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n"); 5735 response = intel_dp_autotest_video_pattern(intel_dp); 5736 break; 5737 case DP_TEST_LINK_EDID_READ: 5738 drm_dbg_kms(&i915->drm, "EDID test requested\n"); 5739 response = intel_dp_autotest_edid(intel_dp); 5740 break; 5741 case DP_TEST_LINK_PHY_TEST_PATTERN: 5742 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); 5743 response = intel_dp_autotest_phy_pattern(intel_dp); 5744 break; 5745 default: 5746 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n", 5747 request); 5748 break; 5749 } 5750 5751 if (response & DP_TEST_ACK) 5752 intel_dp->compliance.test_type = request; 5753 5754 update_status: 5755 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); 5756 if (status <= 0) 5757 drm_dbg_kms(&i915->drm, 5758 "Could not write test response to sink\n"); 5759 } 5760 5761 /** 5762 * intel_dp_check_mst_status - service any pending MST interrupts, check link status 5763 * @intel_dp: Intel DP struct 5764 * 5765 * Read any pending MST interrupts, call MST core to handle these and ack the 5766 * interrupts. Check if the main and AUX link state is ok. 5767 * 5768 * Returns: 5769 * - %true if pending interrupts were serviced (or no interrupts were 5770 * pending) w/o detecting an error condition. 5771 * - %false if an error condition - like AUX failure or a loss of link - is 5772 * detected, which needs servicing from the hotplug work. 5773 */ 5774 static bool 5775 intel_dp_check_mst_status(struct intel_dp *intel_dp) 5776 { 5777 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5778 bool link_ok = true; 5779 5780 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); 5781 5782 for (;;) { 5783 u8 esi[DP_DPRX_ESI_LEN] = {}; 5784 bool handled; 5785 int retry; 5786 5787 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { 5788 drm_dbg_kms(&i915->drm, 5789 "failed to get ESI - device may have failed\n"); 5790 link_ok = false; 5791 5792 break; 5793 } 5794 5795 /* check link status - esi[10] = 0x200c */ 5796 if (intel_dp->active_mst_links > 0 && link_ok && 5797 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { 5798 drm_dbg_kms(&i915->drm, 5799 "channel EQ not ok, retraining\n"); 5800 link_ok = false; 5801 } 5802 5803 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi); 5804 5805 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); 5806 if (!handled) 5807 break; 5808 5809 for (retry = 0; retry < 3; retry++) { 5810 int wret; 5811 5812 wret = drm_dp_dpcd_write(&intel_dp->aux, 5813 DP_SINK_COUNT_ESI+1, 5814 &esi[1], 3); 5815 if (wret == 3) 5816 break; 5817 } 5818 } 5819 5820 return link_ok; 5821 } 5822 5823 static bool 5824 intel_dp_needs_link_retrain(struct intel_dp *intel_dp) 5825 { 5826 u8 link_status[DP_LINK_STATUS_SIZE]; 5827 5828 if (!intel_dp->link_trained) 5829 return false; 5830 5831 /* 5832 * While PSR source HW is enabled, it will control main-link sending 5833 * frames, enabling and disabling it so trying to do a retrain will fail 5834 * as the link would or not be on or it could mix training patterns 5835 * and frame data at the same time causing retrain to fail. 5836 * Also when exiting PSR, HW will retrain the link anyways fixing 5837 * any link status error. 5838 */ 5839 if (intel_psr_enabled(intel_dp)) 5840 return false; 5841 5842 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 5843 link_status) < 0) 5844 return false; 5845 5846 /* 5847 * Validate the cached values of intel_dp->link_rate and 5848 * intel_dp->lane_count before attempting to retrain. 5849 * 5850 * FIXME would be nice to user the crtc state here, but since 5851 * we need to call this from the short HPD handler that seems 5852 * a bit hard. 5853 */ 5854 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, 5855 intel_dp->lane_count)) 5856 return false; 5857 5858 /* Retrain if Channel EQ or CR not ok */ 5859 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); 5860 } 5861 5862 static bool intel_dp_has_connector(struct intel_dp *intel_dp, 5863 const struct drm_connector_state *conn_state) 5864 { 5865 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5866 struct intel_encoder *encoder; 5867 enum pipe pipe; 5868 5869 if (!conn_state->best_encoder) 5870 return false; 5871 5872 /* SST */ 5873 encoder = &dp_to_dig_port(intel_dp)->base; 5874 if (conn_state->best_encoder == &encoder->base) 5875 return true; 5876 5877 /* MST */ 5878 for_each_pipe(i915, pipe) { 5879 encoder = &intel_dp->mst_encoders[pipe]->base; 5880 if (conn_state->best_encoder == &encoder->base) 5881 return true; 5882 } 5883 5884 return false; 5885 } 5886 5887 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp, 5888 struct drm_modeset_acquire_ctx *ctx, 5889 u32 *crtc_mask) 5890 { 5891 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5892 struct drm_connector_list_iter conn_iter; 5893 struct intel_connector *connector; 5894 int ret = 0; 5895 5896 *crtc_mask = 0; 5897 5898 if (!intel_dp_needs_link_retrain(intel_dp)) 5899 return 0; 5900 5901 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 5902 for_each_intel_connector_iter(connector, &conn_iter) { 5903 struct drm_connector_state *conn_state = 5904 connector->base.state; 5905 struct intel_crtc_state *crtc_state; 5906 struct intel_crtc *crtc; 5907 5908 if (!intel_dp_has_connector(intel_dp, conn_state)) 5909 continue; 5910 5911 crtc = to_intel_crtc(conn_state->crtc); 5912 if (!crtc) 5913 continue; 5914 5915 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 5916 if (ret) 5917 break; 5918 5919 crtc_state = to_intel_crtc_state(crtc->base.state); 5920 5921 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); 5922 5923 if (!crtc_state->hw.active) 5924 continue; 5925 5926 if (conn_state->commit && 5927 !try_wait_for_completion(&conn_state->commit->hw_done)) 5928 continue; 5929 5930 *crtc_mask |= drm_crtc_mask(&crtc->base); 5931 } 5932 drm_connector_list_iter_end(&conn_iter); 5933 5934 if (!intel_dp_needs_link_retrain(intel_dp)) 5935 *crtc_mask = 0; 5936 5937 return ret; 5938 } 5939 5940 static bool intel_dp_is_connected(struct intel_dp *intel_dp) 5941 { 5942 struct intel_connector *connector = intel_dp->attached_connector; 5943 5944 return connector->base.status == connector_status_connected || 5945 intel_dp->is_mst; 5946 } 5947 5948 int intel_dp_retrain_link(struct intel_encoder *encoder, 5949 struct drm_modeset_acquire_ctx *ctx) 5950 { 5951 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5952 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5953 struct intel_crtc *crtc; 5954 u32 crtc_mask; 5955 int ret; 5956 5957 if (!intel_dp_is_connected(intel_dp)) 5958 return 0; 5959 5960 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 5961 ctx); 5962 if (ret) 5963 return ret; 5964 5965 ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask); 5966 if (ret) 5967 return ret; 5968 5969 if (crtc_mask == 0) 5970 return 0; 5971 5972 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n", 5973 encoder->base.base.id, encoder->base.name); 5974 5975 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { 5976 const struct intel_crtc_state *crtc_state = 5977 to_intel_crtc_state(crtc->base.state); 5978 5979 /* Suppress underruns caused by re-training */ 5980 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 5981 if (crtc_state->has_pch_encoder) 5982 intel_set_pch_fifo_underrun_reporting(dev_priv, 5983 intel_crtc_pch_transcoder(crtc), false); 5984 } 5985 5986 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { 5987 const struct intel_crtc_state *crtc_state = 5988 to_intel_crtc_state(crtc->base.state); 5989 5990 /* retrain on the MST master transcoder */ 5991 if (INTEL_GEN(dev_priv) >= 12 && 5992 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 5993 !intel_dp_mst_is_master_trans(crtc_state)) 5994 continue; 5995 5996 intel_dp_start_link_train(intel_dp, crtc_state); 5997 intel_dp_stop_link_train(intel_dp, crtc_state); 5998 break; 5999 } 6000 6001 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { 6002 const struct intel_crtc_state *crtc_state = 6003 to_intel_crtc_state(crtc->base.state); 6004 6005 /* Keep underrun reporting disabled until things are stable */ 6006 intel_wait_for_vblank(dev_priv, crtc->pipe); 6007 6008 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 6009 if (crtc_state->has_pch_encoder) 6010 intel_set_pch_fifo_underrun_reporting(dev_priv, 6011 intel_crtc_pch_transcoder(crtc), true); 6012 } 6013 6014 return 0; 6015 } 6016 6017 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, 6018 struct drm_modeset_acquire_ctx *ctx, 6019 u32 *crtc_mask) 6020 { 6021 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 6022 struct drm_connector_list_iter conn_iter; 6023 struct intel_connector *connector; 6024 int ret = 0; 6025 6026 *crtc_mask = 0; 6027 6028 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 6029 for_each_intel_connector_iter(connector, &conn_iter) { 6030 struct drm_connector_state *conn_state = 6031 connector->base.state; 6032 struct intel_crtc_state *crtc_state; 6033 struct intel_crtc *crtc; 6034 6035 if (!intel_dp_has_connector(intel_dp, conn_state)) 6036 continue; 6037 6038 crtc = to_intel_crtc(conn_state->crtc); 6039 if (!crtc) 6040 continue; 6041 6042 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 6043 if (ret) 6044 break; 6045 6046 crtc_state = to_intel_crtc_state(crtc->base.state); 6047 6048 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); 6049 6050 if (!crtc_state->hw.active) 6051 continue; 6052 6053 if (conn_state->commit && 6054 !try_wait_for_completion(&conn_state->commit->hw_done)) 6055 continue; 6056 6057 *crtc_mask |= drm_crtc_mask(&crtc->base); 6058 } 6059 drm_connector_list_iter_end(&conn_iter); 6060 6061 return ret; 6062 } 6063 6064 static int intel_dp_do_phy_test(struct intel_encoder *encoder, 6065 struct drm_modeset_acquire_ctx *ctx) 6066 { 6067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 6068 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 6069 struct intel_crtc *crtc; 6070 u32 crtc_mask; 6071 int ret; 6072 6073 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 6074 ctx); 6075 if (ret) 6076 return ret; 6077 6078 ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask); 6079 if (ret) 6080 return ret; 6081 6082 if (crtc_mask == 0) 6083 return 0; 6084 6085 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n", 6086 encoder->base.base.id, encoder->base.name); 6087 6088 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { 6089 const struct intel_crtc_state *crtc_state = 6090 to_intel_crtc_state(crtc->base.state); 6091 6092 /* test on the MST master transcoder */ 6093 if (INTEL_GEN(dev_priv) >= 12 && 6094 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 6095 !intel_dp_mst_is_master_trans(crtc_state)) 6096 continue; 6097 6098 intel_dp_process_phy_request(intel_dp, crtc_state); 6099 break; 6100 } 6101 6102 return 0; 6103 } 6104 6105 static void intel_dp_phy_test(struct intel_encoder *encoder) 6106 { 6107 struct drm_modeset_acquire_ctx ctx; 6108 int ret; 6109 6110 drm_modeset_acquire_init(&ctx, 0); 6111 6112 for (;;) { 6113 ret = intel_dp_do_phy_test(encoder, &ctx); 6114 6115 if (ret == -EDEADLK) { 6116 drm_modeset_backoff(&ctx); 6117 continue; 6118 } 6119 6120 break; 6121 } 6122 6123 drm_modeset_drop_locks(&ctx); 6124 drm_modeset_acquire_fini(&ctx); 6125 drm_WARN(encoder->base.dev, ret, 6126 "Acquiring modeset locks failed with %i\n", ret); 6127 } 6128 6129 /* 6130 * If display is now connected check links status, 6131 * there has been known issues of link loss triggering 6132 * long pulse. 6133 * 6134 * Some sinks (eg. ASUS PB287Q) seem to perform some 6135 * weird HPD ping pong during modesets. So we can apparently 6136 * end up with HPD going low during a modeset, and then 6137 * going back up soon after. And once that happens we must 6138 * retrain the link to get a picture. That's in case no 6139 * userspace component reacted to intermittent HPD dip. 6140 */ 6141 static enum intel_hotplug_state 6142 intel_dp_hotplug(struct intel_encoder *encoder, 6143 struct intel_connector *connector) 6144 { 6145 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 6146 struct drm_modeset_acquire_ctx ctx; 6147 enum intel_hotplug_state state; 6148 int ret; 6149 6150 if (intel_dp->compliance.test_active && 6151 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 6152 intel_dp_phy_test(encoder); 6153 /* just do the PHY test and nothing else */ 6154 return INTEL_HOTPLUG_UNCHANGED; 6155 } 6156 6157 state = intel_encoder_hotplug(encoder, connector); 6158 6159 drm_modeset_acquire_init(&ctx, 0); 6160 6161 for (;;) { 6162 ret = intel_dp_retrain_link(encoder, &ctx); 6163 6164 if (ret == -EDEADLK) { 6165 drm_modeset_backoff(&ctx); 6166 continue; 6167 } 6168 6169 break; 6170 } 6171 6172 drm_modeset_drop_locks(&ctx); 6173 drm_modeset_acquire_fini(&ctx); 6174 drm_WARN(encoder->base.dev, ret, 6175 "Acquiring modeset locks failed with %i\n", ret); 6176 6177 /* 6178 * Keeping it consistent with intel_ddi_hotplug() and 6179 * intel_hdmi_hotplug(). 6180 */ 6181 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 6182 state = INTEL_HOTPLUG_RETRY; 6183 6184 return state; 6185 } 6186 6187 static void intel_dp_check_service_irq(struct intel_dp *intel_dp) 6188 { 6189 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 6190 u8 val; 6191 6192 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 6193 return; 6194 6195 if (drm_dp_dpcd_readb(&intel_dp->aux, 6196 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) 6197 return; 6198 6199 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); 6200 6201 if (val & DP_AUTOMATED_TEST_REQUEST) 6202 intel_dp_handle_test_request(intel_dp); 6203 6204 if (val & DP_CP_IRQ) 6205 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 6206 6207 if (val & DP_SINK_SPECIFIC_IRQ) 6208 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n"); 6209 } 6210 6211 /* 6212 * According to DP spec 6213 * 5.1.2: 6214 * 1. Read DPCD 6215 * 2. Configure link according to Receiver Capabilities 6216 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 6217 * 4. Check link status on receipt of hot-plug interrupt 6218 * 6219 * intel_dp_short_pulse - handles short pulse interrupts 6220 * when full detection is not required. 6221 * Returns %true if short pulse is handled and full detection 6222 * is NOT required and %false otherwise. 6223 */ 6224 static bool 6225 intel_dp_short_pulse(struct intel_dp *intel_dp) 6226 { 6227 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6228 u8 old_sink_count = intel_dp->sink_count; 6229 bool ret; 6230 6231 /* 6232 * Clearing compliance test variables to allow capturing 6233 * of values for next automated test request. 6234 */ 6235 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 6236 6237 /* 6238 * Now read the DPCD to see if it's actually running 6239 * If the current value of sink count doesn't match with 6240 * the value that was stored earlier or dpcd read failed 6241 * we need to do full detection 6242 */ 6243 ret = intel_dp_get_dpcd(intel_dp); 6244 6245 if ((old_sink_count != intel_dp->sink_count) || !ret) { 6246 /* No need to proceed if we are going to do full detect */ 6247 return false; 6248 } 6249 6250 intel_dp_check_service_irq(intel_dp); 6251 6252 /* Handle CEC interrupts, if any */ 6253 drm_dp_cec_irq(&intel_dp->aux); 6254 6255 /* defer to the hotplug work for link retraining if needed */ 6256 if (intel_dp_needs_link_retrain(intel_dp)) 6257 return false; 6258 6259 intel_psr_short_pulse(intel_dp); 6260 6261 switch (intel_dp->compliance.test_type) { 6262 case DP_TEST_LINK_TRAINING: 6263 drm_dbg_kms(&dev_priv->drm, 6264 "Link Training Compliance Test requested\n"); 6265 /* Send a Hotplug Uevent to userspace to start modeset */ 6266 drm_kms_helper_hotplug_event(&dev_priv->drm); 6267 break; 6268 case DP_TEST_LINK_PHY_TEST_PATTERN: 6269 drm_dbg_kms(&dev_priv->drm, 6270 "PHY test pattern Compliance Test requested\n"); 6271 /* 6272 * Schedule long hpd to do the test 6273 * 6274 * FIXME get rid of the ad-hoc phy test modeset code 6275 * and properly incorporate it into the normal modeset. 6276 */ 6277 return false; 6278 } 6279 6280 return true; 6281 } 6282 6283 /* XXX this is probably wrong for multiple downstream ports */ 6284 static enum drm_connector_status 6285 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 6286 { 6287 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 6288 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 6289 u8 *dpcd = intel_dp->dpcd; 6290 u8 type; 6291 6292 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp))) 6293 return connector_status_connected; 6294 6295 lspcon_resume(dig_port); 6296 6297 if (!intel_dp_get_dpcd(intel_dp)) 6298 return connector_status_disconnected; 6299 6300 /* if there's no downstream port, we're done */ 6301 if (!drm_dp_is_branch(dpcd)) 6302 return connector_status_connected; 6303 6304 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 6305 if (intel_dp_has_sink_count(intel_dp) && 6306 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 6307 return intel_dp->sink_count ? 6308 connector_status_connected : connector_status_disconnected; 6309 } 6310 6311 if (intel_dp_can_mst(intel_dp)) 6312 return connector_status_connected; 6313 6314 /* If no HPD, poke DDC gently */ 6315 if (drm_probe_ddc(&intel_dp->aux.ddc)) 6316 return connector_status_connected; 6317 6318 /* Well we tried, say unknown for unreliable port types */ 6319 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 6320 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 6321 if (type == DP_DS_PORT_TYPE_VGA || 6322 type == DP_DS_PORT_TYPE_NON_EDID) 6323 return connector_status_unknown; 6324 } else { 6325 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 6326 DP_DWN_STRM_PORT_TYPE_MASK; 6327 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 6328 type == DP_DWN_STRM_PORT_TYPE_OTHER) 6329 return connector_status_unknown; 6330 } 6331 6332 /* Anything else is out of spec, warn and ignore */ 6333 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n"); 6334 return connector_status_disconnected; 6335 } 6336 6337 static enum drm_connector_status 6338 edp_detect(struct intel_dp *intel_dp) 6339 { 6340 return connector_status_connected; 6341 } 6342 6343 static bool ibx_digital_port_connected(struct intel_encoder *encoder) 6344 { 6345 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 6346 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 6347 6348 return intel_de_read(dev_priv, SDEISR) & bit; 6349 } 6350 6351 static bool g4x_digital_port_connected(struct intel_encoder *encoder) 6352 { 6353 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 6354 u32 bit; 6355 6356 switch (encoder->hpd_pin) { 6357 case HPD_PORT_B: 6358 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 6359 break; 6360 case HPD_PORT_C: 6361 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 6362 break; 6363 case HPD_PORT_D: 6364 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 6365 break; 6366 default: 6367 MISSING_CASE(encoder->hpd_pin); 6368 return false; 6369 } 6370 6371 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; 6372 } 6373 6374 static bool gm45_digital_port_connected(struct intel_encoder *encoder) 6375 { 6376 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 6377 u32 bit; 6378 6379 switch (encoder->hpd_pin) { 6380 case HPD_PORT_B: 6381 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; 6382 break; 6383 case HPD_PORT_C: 6384 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; 6385 break; 6386 case HPD_PORT_D: 6387 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; 6388 break; 6389 default: 6390 MISSING_CASE(encoder->hpd_pin); 6391 return false; 6392 } 6393 6394 return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; 6395 } 6396 6397 static bool ilk_digital_port_connected(struct intel_encoder *encoder) 6398 { 6399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 6400 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 6401 6402 return intel_de_read(dev_priv, DEISR) & bit; 6403 } 6404 6405 /* 6406 * intel_digital_port_connected - is the specified port connected? 6407 * @encoder: intel_encoder 6408 * 6409 * In cases where there's a connector physically connected but it can't be used 6410 * by our hardware we also return false, since the rest of the driver should 6411 * pretty much treat the port as disconnected. This is relevant for type-C 6412 * (starting on ICL) where there's ownership involved. 6413 * 6414 * Return %true if port is connected, %false otherwise. 6415 */ 6416 bool intel_digital_port_connected(struct intel_encoder *encoder) 6417 { 6418 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 6419 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 6420 bool is_connected = false; 6421 intel_wakeref_t wakeref; 6422 6423 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) 6424 is_connected = dig_port->connected(encoder); 6425 6426 return is_connected; 6427 } 6428 6429 static struct edid * 6430 intel_dp_get_edid(struct intel_dp *intel_dp) 6431 { 6432 struct intel_connector *intel_connector = intel_dp->attached_connector; 6433 6434 /* use cached edid if we have one */ 6435 if (intel_connector->edid) { 6436 /* invalid edid */ 6437 if (IS_ERR(intel_connector->edid)) 6438 return NULL; 6439 6440 return drm_edid_duplicate(intel_connector->edid); 6441 } else 6442 return drm_get_edid(&intel_connector->base, 6443 &intel_dp->aux.ddc); 6444 } 6445 6446 static void 6447 intel_dp_update_dfp(struct intel_dp *intel_dp, 6448 const struct edid *edid) 6449 { 6450 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 6451 struct intel_connector *connector = intel_dp->attached_connector; 6452 6453 intel_dp->dfp.max_bpc = 6454 drm_dp_downstream_max_bpc(intel_dp->dpcd, 6455 intel_dp->downstream_ports, edid); 6456 6457 intel_dp->dfp.max_dotclock = 6458 drm_dp_downstream_max_dotclock(intel_dp->dpcd, 6459 intel_dp->downstream_ports); 6460 6461 intel_dp->dfp.min_tmds_clock = 6462 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, 6463 intel_dp->downstream_ports, 6464 edid); 6465 intel_dp->dfp.max_tmds_clock = 6466 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, 6467 intel_dp->downstream_ports, 6468 edid); 6469 6470 drm_dbg_kms(&i915->drm, 6471 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d\n", 6472 connector->base.base.id, connector->base.name, 6473 intel_dp->dfp.max_bpc, 6474 intel_dp->dfp.max_dotclock, 6475 intel_dp->dfp.min_tmds_clock, 6476 intel_dp->dfp.max_tmds_clock); 6477 } 6478 6479 static void 6480 intel_dp_update_420(struct intel_dp *intel_dp) 6481 { 6482 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 6483 struct intel_connector *connector = intel_dp->attached_connector; 6484 bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420; 6485 6486 /* No YCbCr output support on gmch platforms */ 6487 if (HAS_GMCH(i915)) 6488 return; 6489 6490 /* 6491 * ILK doesn't seem capable of DP YCbCr output. The 6492 * displayed image is severly corrupted. SNB+ is fine. 6493 */ 6494 if (IS_GEN(i915, 5)) 6495 return; 6496 6497 is_branch = drm_dp_is_branch(intel_dp->dpcd); 6498 ycbcr_420_passthrough = 6499 drm_dp_downstream_420_passthrough(intel_dp->dpcd, 6500 intel_dp->downstream_ports); 6501 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ 6502 ycbcr_444_to_420 = 6503 dp_to_dig_port(intel_dp)->lspcon.active || 6504 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, 6505 intel_dp->downstream_ports); 6506 6507 if (INTEL_GEN(i915) >= 11) { 6508 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */ 6509 intel_dp->dfp.ycbcr_444_to_420 = 6510 ycbcr_444_to_420 && !ycbcr_420_passthrough; 6511 6512 connector->base.ycbcr_420_allowed = 6513 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough; 6514 } else { 6515 /* 4:4:4->4:2:0 conversion is the only way */ 6516 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420; 6517 6518 connector->base.ycbcr_420_allowed = ycbcr_444_to_420; 6519 } 6520 6521 drm_dbg_kms(&i915->drm, 6522 "[CONNECTOR:%d:%s] YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", 6523 connector->base.base.id, connector->base.name, 6524 yesno(connector->base.ycbcr_420_allowed), 6525 yesno(intel_dp->dfp.ycbcr_444_to_420)); 6526 } 6527 6528 static void 6529 intel_dp_set_edid(struct intel_dp *intel_dp) 6530 { 6531 struct intel_connector *connector = intel_dp->attached_connector; 6532 struct edid *edid; 6533 6534 intel_dp_unset_edid(intel_dp); 6535 edid = intel_dp_get_edid(intel_dp); 6536 connector->detect_edid = edid; 6537 6538 intel_dp_update_dfp(intel_dp, edid); 6539 intel_dp_update_420(intel_dp); 6540 6541 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 6542 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 6543 intel_dp->has_audio = drm_detect_monitor_audio(edid); 6544 } 6545 6546 drm_dp_cec_set_edid(&intel_dp->aux, edid); 6547 intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); 6548 } 6549 6550 static void 6551 intel_dp_unset_edid(struct intel_dp *intel_dp) 6552 { 6553 struct intel_connector *connector = intel_dp->attached_connector; 6554 6555 drm_dp_cec_unset_edid(&intel_dp->aux); 6556 kfree(connector->detect_edid); 6557 connector->detect_edid = NULL; 6558 6559 intel_dp->has_hdmi_sink = false; 6560 intel_dp->has_audio = false; 6561 intel_dp->edid_quirks = 0; 6562 6563 intel_dp->dfp.max_bpc = 0; 6564 intel_dp->dfp.max_dotclock = 0; 6565 intel_dp->dfp.min_tmds_clock = 0; 6566 intel_dp->dfp.max_tmds_clock = 0; 6567 6568 intel_dp->dfp.ycbcr_444_to_420 = false; 6569 connector->base.ycbcr_420_allowed = false; 6570 } 6571 6572 static int 6573 intel_dp_detect(struct drm_connector *connector, 6574 struct drm_modeset_acquire_ctx *ctx, 6575 bool force) 6576 { 6577 struct drm_i915_private *dev_priv = to_i915(connector->dev); 6578 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 6579 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 6580 struct intel_encoder *encoder = &dig_port->base; 6581 enum drm_connector_status status; 6582 6583 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 6584 connector->base.id, connector->name); 6585 drm_WARN_ON(&dev_priv->drm, 6586 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 6587 6588 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 6589 return connector_status_disconnected; 6590 6591 /* Can't disconnect eDP */ 6592 if (intel_dp_is_edp(intel_dp)) 6593 status = edp_detect(intel_dp); 6594 else if (intel_digital_port_connected(encoder)) 6595 status = intel_dp_detect_dpcd(intel_dp); 6596 else 6597 status = connector_status_disconnected; 6598 6599 if (status == connector_status_disconnected) { 6600 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 6601 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); 6602 6603 if (intel_dp->is_mst) { 6604 drm_dbg_kms(&dev_priv->drm, 6605 "MST device may have disappeared %d vs %d\n", 6606 intel_dp->is_mst, 6607 intel_dp->mst_mgr.mst_state); 6608 intel_dp->is_mst = false; 6609 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 6610 intel_dp->is_mst); 6611 } 6612 6613 goto out; 6614 } 6615 6616 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ 6617 if (INTEL_GEN(dev_priv) >= 11) 6618 intel_dp_get_dsc_sink_cap(intel_dp); 6619 6620 intel_dp_configure_mst(intel_dp); 6621 6622 /* 6623 * TODO: Reset link params when switching to MST mode, until MST 6624 * supports link training fallback params. 6625 */ 6626 if (intel_dp->reset_link_params || intel_dp->is_mst) { 6627 /* Initial max link lane count */ 6628 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); 6629 6630 /* Initial max link rate */ 6631 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); 6632 6633 intel_dp->reset_link_params = false; 6634 } 6635 6636 intel_dp_print_rates(intel_dp); 6637 6638 if (intel_dp->is_mst) { 6639 /* 6640 * If we are in MST mode then this connector 6641 * won't appear connected or have anything 6642 * with EDID on it 6643 */ 6644 status = connector_status_disconnected; 6645 goto out; 6646 } 6647 6648 /* 6649 * Some external monitors do not signal loss of link synchronization 6650 * with an IRQ_HPD, so force a link status check. 6651 */ 6652 if (!intel_dp_is_edp(intel_dp)) { 6653 int ret; 6654 6655 ret = intel_dp_retrain_link(encoder, ctx); 6656 if (ret) 6657 return ret; 6658 } 6659 6660 /* 6661 * Clearing NACK and defer counts to get their exact values 6662 * while reading EDID which are required by Compliance tests 6663 * 4.2.2.4 and 4.2.2.5 6664 */ 6665 intel_dp->aux.i2c_nack_count = 0; 6666 intel_dp->aux.i2c_defer_count = 0; 6667 6668 intel_dp_set_edid(intel_dp); 6669 if (intel_dp_is_edp(intel_dp) || 6670 to_intel_connector(connector)->detect_edid) 6671 status = connector_status_connected; 6672 6673 intel_dp_check_service_irq(intel_dp); 6674 6675 out: 6676 if (status != connector_status_connected && !intel_dp->is_mst) 6677 intel_dp_unset_edid(intel_dp); 6678 6679 /* 6680 * Make sure the refs for power wells enabled during detect are 6681 * dropped to avoid a new detect cycle triggered by HPD polling. 6682 */ 6683 intel_display_power_flush_work(dev_priv); 6684 6685 if (!intel_dp_is_edp(intel_dp)) 6686 drm_dp_set_subconnector_property(connector, 6687 status, 6688 intel_dp->dpcd, 6689 intel_dp->downstream_ports); 6690 return status; 6691 } 6692 6693 static void 6694 intel_dp_force(struct drm_connector *connector) 6695 { 6696 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 6697 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 6698 struct intel_encoder *intel_encoder = &dig_port->base; 6699 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 6700 enum intel_display_power_domain aux_domain = 6701 intel_aux_power_domain(dig_port); 6702 intel_wakeref_t wakeref; 6703 6704 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 6705 connector->base.id, connector->name); 6706 intel_dp_unset_edid(intel_dp); 6707 6708 if (connector->status != connector_status_connected) 6709 return; 6710 6711 wakeref = intel_display_power_get(dev_priv, aux_domain); 6712 6713 intel_dp_set_edid(intel_dp); 6714 6715 intel_display_power_put(dev_priv, aux_domain, wakeref); 6716 } 6717 6718 static int intel_dp_get_modes(struct drm_connector *connector) 6719 { 6720 struct intel_connector *intel_connector = to_intel_connector(connector); 6721 struct edid *edid; 6722 6723 edid = intel_connector->detect_edid; 6724 if (edid) { 6725 int ret = intel_connector_update_modes(connector, edid); 6726 if (ret) 6727 return ret; 6728 } 6729 6730 /* if eDP has no EDID, fall back to fixed mode */ 6731 if (intel_dp_is_edp(intel_attached_dp(intel_connector)) && 6732 intel_connector->panel.fixed_mode) { 6733 struct drm_display_mode *mode; 6734 6735 mode = drm_mode_duplicate(connector->dev, 6736 intel_connector->panel.fixed_mode); 6737 if (mode) { 6738 drm_mode_probed_add(connector, mode); 6739 return 1; 6740 } 6741 } 6742 6743 if (!edid) { 6744 struct intel_dp *intel_dp = intel_attached_dp(intel_connector); 6745 struct drm_display_mode *mode; 6746 6747 mode = drm_dp_downstream_mode(connector->dev, 6748 intel_dp->dpcd, 6749 intel_dp->downstream_ports); 6750 if (mode) { 6751 drm_mode_probed_add(connector, mode); 6752 return 1; 6753 } 6754 } 6755 6756 return 0; 6757 } 6758 6759 static int 6760 intel_dp_connector_register(struct drm_connector *connector) 6761 { 6762 struct drm_i915_private *i915 = to_i915(connector->dev); 6763 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 6764 int ret; 6765 6766 ret = intel_connector_register(connector); 6767 if (ret) 6768 return ret; 6769 6770 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n", 6771 intel_dp->aux.name, connector->kdev->kobj.name); 6772 6773 intel_dp->aux.dev = connector->kdev; 6774 ret = drm_dp_aux_register(&intel_dp->aux); 6775 if (!ret) 6776 drm_dp_cec_register_connector(&intel_dp->aux, connector); 6777 return ret; 6778 } 6779 6780 static void 6781 intel_dp_connector_unregister(struct drm_connector *connector) 6782 { 6783 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 6784 6785 drm_dp_cec_unregister_connector(&intel_dp->aux); 6786 drm_dp_aux_unregister(&intel_dp->aux); 6787 intel_connector_unregister(connector); 6788 } 6789 6790 void intel_dp_encoder_flush_work(struct drm_encoder *encoder) 6791 { 6792 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 6793 struct intel_dp *intel_dp = &dig_port->dp; 6794 6795 intel_dp_mst_encoder_cleanup(dig_port); 6796 if (intel_dp_is_edp(intel_dp)) { 6797 intel_wakeref_t wakeref; 6798 6799 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 6800 /* 6801 * vdd might still be enabled do to the delayed vdd off. 6802 * Make sure vdd is actually turned off here. 6803 */ 6804 with_pps_lock(intel_dp, wakeref) 6805 edp_panel_vdd_off_sync(intel_dp); 6806 } 6807 6808 intel_dp_aux_fini(intel_dp); 6809 } 6810 6811 static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 6812 { 6813 intel_dp_encoder_flush_work(encoder); 6814 6815 drm_encoder_cleanup(encoder); 6816 kfree(enc_to_dig_port(to_intel_encoder(encoder))); 6817 } 6818 6819 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) 6820 { 6821 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 6822 intel_wakeref_t wakeref; 6823 6824 if (!intel_dp_is_edp(intel_dp)) 6825 return; 6826 6827 /* 6828 * vdd might still be enabled do to the delayed vdd off. 6829 * Make sure vdd is actually turned off here. 6830 */ 6831 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 6832 with_pps_lock(intel_dp, wakeref) 6833 edp_panel_vdd_off_sync(intel_dp); 6834 } 6835 6836 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder) 6837 { 6838 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 6839 intel_wakeref_t wakeref; 6840 6841 if (!intel_dp_is_edp(intel_dp)) 6842 return; 6843 6844 with_pps_lock(intel_dp, wakeref) 6845 wait_panel_power_cycle(intel_dp); 6846 } 6847 6848 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) 6849 { 6850 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6851 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 6852 6853 lockdep_assert_held(&dev_priv->pps_mutex); 6854 6855 if (!edp_have_panel_vdd(intel_dp)) 6856 return; 6857 6858 /* 6859 * The VDD bit needs a power domain reference, so if the bit is 6860 * already enabled when we boot or resume, grab this reference and 6861 * schedule a vdd off, so we don't hold on to the reference 6862 * indefinitely. 6863 */ 6864 drm_dbg_kms(&dev_priv->drm, 6865 "VDD left on by BIOS, adjusting state tracking\n"); 6866 intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port)); 6867 6868 edp_panel_vdd_schedule_off(intel_dp); 6869 } 6870 6871 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) 6872 { 6873 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6874 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 6875 enum pipe pipe; 6876 6877 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg, 6878 encoder->port, &pipe)) 6879 return pipe; 6880 6881 return INVALID_PIPE; 6882 } 6883 6884 void intel_dp_encoder_reset(struct drm_encoder *encoder) 6885 { 6886 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 6887 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 6888 intel_wakeref_t wakeref; 6889 6890 if (!HAS_DDI(dev_priv)) 6891 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); 6892 6893 intel_dp->reset_link_params = true; 6894 6895 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && 6896 !intel_dp_is_edp(intel_dp)) 6897 return; 6898 6899 with_pps_lock(intel_dp, wakeref) { 6900 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6901 intel_dp->active_pipe = vlv_active_pipe(intel_dp); 6902 6903 if (intel_dp_is_edp(intel_dp)) { 6904 /* 6905 * Reinit the power sequencer, in case BIOS did 6906 * something nasty with it. 6907 */ 6908 intel_dp_pps_init(intel_dp); 6909 intel_edp_panel_vdd_sanitize(intel_dp); 6910 } 6911 } 6912 } 6913 6914 static int intel_modeset_tile_group(struct intel_atomic_state *state, 6915 int tile_group_id) 6916 { 6917 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6918 struct drm_connector_list_iter conn_iter; 6919 struct drm_connector *connector; 6920 int ret = 0; 6921 6922 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 6923 drm_for_each_connector_iter(connector, &conn_iter) { 6924 struct drm_connector_state *conn_state; 6925 struct intel_crtc_state *crtc_state; 6926 struct intel_crtc *crtc; 6927 6928 if (!connector->has_tile || 6929 connector->tile_group->id != tile_group_id) 6930 continue; 6931 6932 conn_state = drm_atomic_get_connector_state(&state->base, 6933 connector); 6934 if (IS_ERR(conn_state)) { 6935 ret = PTR_ERR(conn_state); 6936 break; 6937 } 6938 6939 crtc = to_intel_crtc(conn_state->crtc); 6940 6941 if (!crtc) 6942 continue; 6943 6944 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6945 crtc_state->uapi.mode_changed = true; 6946 6947 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6948 if (ret) 6949 break; 6950 } 6951 drm_connector_list_iter_end(&conn_iter); 6952 6953 return ret; 6954 } 6955 6956 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) 6957 { 6958 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6959 struct intel_crtc *crtc; 6960 6961 if (transcoders == 0) 6962 return 0; 6963 6964 for_each_intel_crtc(&dev_priv->drm, crtc) { 6965 struct intel_crtc_state *crtc_state; 6966 int ret; 6967 6968 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6969 if (IS_ERR(crtc_state)) 6970 return PTR_ERR(crtc_state); 6971 6972 if (!crtc_state->hw.enable) 6973 continue; 6974 6975 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) 6976 continue; 6977 6978 crtc_state->uapi.mode_changed = true; 6979 6980 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6981 if (ret) 6982 return ret; 6983 6984 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6985 if (ret) 6986 return ret; 6987 6988 transcoders &= ~BIT(crtc_state->cpu_transcoder); 6989 } 6990 6991 drm_WARN_ON(&dev_priv->drm, transcoders != 0); 6992 6993 return 0; 6994 } 6995 6996 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, 6997 struct drm_connector *connector) 6998 { 6999 const struct drm_connector_state *old_conn_state = 7000 drm_atomic_get_old_connector_state(&state->base, connector); 7001 const struct intel_crtc_state *old_crtc_state; 7002 struct intel_crtc *crtc; 7003 u8 transcoders; 7004 7005 crtc = to_intel_crtc(old_conn_state->crtc); 7006 if (!crtc) 7007 return 0; 7008 7009 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 7010 7011 if (!old_crtc_state->hw.active) 7012 return 0; 7013 7014 transcoders = old_crtc_state->sync_mode_slaves_mask; 7015 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) 7016 transcoders |= BIT(old_crtc_state->master_transcoder); 7017 7018 return intel_modeset_affected_transcoders(state, 7019 transcoders); 7020 } 7021 7022 static int intel_dp_connector_atomic_check(struct drm_connector *conn, 7023 struct drm_atomic_state *_state) 7024 { 7025 struct drm_i915_private *dev_priv = to_i915(conn->dev); 7026 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7027 int ret; 7028 7029 ret = intel_digital_connector_atomic_check(conn, &state->base); 7030 if (ret) 7031 return ret; 7032 7033 /* 7034 * We don't enable port sync on BDW due to missing w/as and 7035 * due to not having adjusted the modeset sequence appropriately. 7036 */ 7037 if (INTEL_GEN(dev_priv) < 9) 7038 return 0; 7039 7040 if (!intel_connector_needs_modeset(state, conn)) 7041 return 0; 7042 7043 if (conn->has_tile) { 7044 ret = intel_modeset_tile_group(state, conn->tile_group->id); 7045 if (ret) 7046 return ret; 7047 } 7048 7049 return intel_modeset_synced_crtcs(state, conn); 7050 } 7051 7052 static const struct drm_connector_funcs intel_dp_connector_funcs = { 7053 .force = intel_dp_force, 7054 .fill_modes = drm_helper_probe_single_connector_modes, 7055 .atomic_get_property = intel_digital_connector_atomic_get_property, 7056 .atomic_set_property = intel_digital_connector_atomic_set_property, 7057 .late_register = intel_dp_connector_register, 7058 .early_unregister = intel_dp_connector_unregister, 7059 .destroy = intel_connector_destroy, 7060 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 7061 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 7062 }; 7063 7064 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 7065 .detect_ctx = intel_dp_detect, 7066 .get_modes = intel_dp_get_modes, 7067 .mode_valid = intel_dp_mode_valid, 7068 .atomic_check = intel_dp_connector_atomic_check, 7069 }; 7070 7071 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 7072 .reset = intel_dp_encoder_reset, 7073 .destroy = intel_dp_encoder_destroy, 7074 }; 7075 7076 static bool intel_edp_have_power(struct intel_dp *intel_dp) 7077 { 7078 intel_wakeref_t wakeref; 7079 bool have_power = false; 7080 7081 with_pps_lock(intel_dp, wakeref) { 7082 have_power = edp_have_panel_power(intel_dp) && 7083 edp_have_panel_vdd(intel_dp); 7084 } 7085 7086 return have_power; 7087 } 7088 7089 enum irqreturn 7090 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) 7091 { 7092 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 7093 struct intel_dp *intel_dp = &dig_port->dp; 7094 7095 if (dig_port->base.type == INTEL_OUTPUT_EDP && 7096 (long_hpd || !intel_edp_have_power(intel_dp))) { 7097 /* 7098 * vdd off can generate a long/short pulse on eDP which 7099 * would require vdd on to handle it, and thus we 7100 * would end up in an endless cycle of 7101 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." 7102 */ 7103 drm_dbg_kms(&i915->drm, 7104 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", 7105 long_hpd ? "long" : "short", 7106 dig_port->base.base.base.id, 7107 dig_port->base.base.name); 7108 return IRQ_HANDLED; 7109 } 7110 7111 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", 7112 dig_port->base.base.base.id, 7113 dig_port->base.base.name, 7114 long_hpd ? "long" : "short"); 7115 7116 if (long_hpd) { 7117 intel_dp->reset_link_params = true; 7118 return IRQ_NONE; 7119 } 7120 7121 if (intel_dp->is_mst) { 7122 if (!intel_dp_check_mst_status(intel_dp)) 7123 return IRQ_NONE; 7124 } else if (!intel_dp_short_pulse(intel_dp)) { 7125 return IRQ_NONE; 7126 } 7127 7128 return IRQ_HANDLED; 7129 } 7130 7131 /* check the VBT to see whether the eDP is on another port */ 7132 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) 7133 { 7134 /* 7135 * eDP not supported on g4x. so bail out early just 7136 * for a bit extra safety in case the VBT is bonkers. 7137 */ 7138 if (INTEL_GEN(dev_priv) < 5) 7139 return false; 7140 7141 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) 7142 return true; 7143 7144 return intel_bios_is_port_edp(dev_priv, port); 7145 } 7146 7147 static void 7148 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 7149 { 7150 struct drm_i915_private *dev_priv = to_i915(connector->dev); 7151 enum port port = dp_to_dig_port(intel_dp)->base.port; 7152 7153 if (!intel_dp_is_edp(intel_dp)) 7154 drm_connector_attach_dp_subconnector_property(connector); 7155 7156 if (!IS_G4X(dev_priv) && port != PORT_A) 7157 intel_attach_force_audio_property(connector); 7158 7159 intel_attach_broadcast_rgb_property(connector); 7160 if (HAS_GMCH(dev_priv)) 7161 drm_connector_attach_max_bpc_property(connector, 6, 10); 7162 else if (INTEL_GEN(dev_priv) >= 5) 7163 drm_connector_attach_max_bpc_property(connector, 6, 12); 7164 7165 intel_attach_colorspace_property(connector); 7166 7167 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11) 7168 drm_object_attach_property(&connector->base, 7169 connector->dev->mode_config.hdr_output_metadata_property, 7170 0); 7171 7172 if (intel_dp_is_edp(intel_dp)) { 7173 u32 allowed_scalers; 7174 7175 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); 7176 if (!HAS_GMCH(dev_priv)) 7177 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 7178 7179 drm_connector_attach_scaling_mode_property(connector, allowed_scalers); 7180 7181 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; 7182 7183 } 7184 } 7185 7186 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 7187 { 7188 intel_dp->panel_power_off_time = ktime_get_boottime(); 7189 intel_dp->last_power_on = jiffies; 7190 intel_dp->last_backlight_off = jiffies; 7191 } 7192 7193 static void 7194 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) 7195 { 7196 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 7197 u32 pp_on, pp_off, pp_ctl; 7198 struct pps_registers regs; 7199 7200 intel_pps_get_registers(intel_dp, ®s); 7201 7202 pp_ctl = ilk_get_pp_control(intel_dp); 7203 7204 /* Ensure PPS is unlocked */ 7205 if (!HAS_DDI(dev_priv)) 7206 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl); 7207 7208 pp_on = intel_de_read(dev_priv, regs.pp_on); 7209 pp_off = intel_de_read(dev_priv, regs.pp_off); 7210 7211 /* Pull timing values out of registers */ 7212 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); 7213 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); 7214 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); 7215 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); 7216 7217 if (i915_mmio_reg_valid(regs.pp_div)) { 7218 u32 pp_div; 7219 7220 pp_div = intel_de_read(dev_priv, regs.pp_div); 7221 7222 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; 7223 } else { 7224 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; 7225 } 7226 } 7227 7228 static void 7229 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) 7230 { 7231 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 7232 state_name, 7233 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); 7234 } 7235 7236 static void 7237 intel_pps_verify_state(struct intel_dp *intel_dp) 7238 { 7239 struct edp_power_seq hw; 7240 struct edp_power_seq *sw = &intel_dp->pps_delays; 7241 7242 intel_pps_readout_hw_state(intel_dp, &hw); 7243 7244 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || 7245 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { 7246 DRM_ERROR("PPS state mismatch\n"); 7247 intel_pps_dump_state("sw", sw); 7248 intel_pps_dump_state("hw", &hw); 7249 } 7250 } 7251 7252 static void 7253 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) 7254 { 7255 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 7256 struct edp_power_seq cur, vbt, spec, 7257 *final = &intel_dp->pps_delays; 7258 7259 lockdep_assert_held(&dev_priv->pps_mutex); 7260 7261 /* already initialized? */ 7262 if (final->t11_t12 != 0) 7263 return; 7264 7265 intel_pps_readout_hw_state(intel_dp, &cur); 7266 7267 intel_pps_dump_state("cur", &cur); 7268 7269 vbt = dev_priv->vbt.edp.pps; 7270 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay 7271 * of 500ms appears to be too short. Ocassionally the panel 7272 * just fails to power back on. Increasing the delay to 800ms 7273 * seems sufficient to avoid this problem. 7274 */ 7275 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { 7276 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10); 7277 drm_dbg_kms(&dev_priv->drm, 7278 "Increasing T12 panel delay as per the quirk to %d\n", 7279 vbt.t11_t12); 7280 } 7281 /* T11_T12 delay is special and actually in units of 100ms, but zero 7282 * based in the hw (so we need to add 100 ms). But the sw vbt 7283 * table multiplies it with 1000 to make it in units of 100usec, 7284 * too. */ 7285 vbt.t11_t12 += 100 * 10; 7286 7287 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 7288 * our hw here, which are all in 100usec. */ 7289 spec.t1_t3 = 210 * 10; 7290 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 7291 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 7292 spec.t10 = 500 * 10; 7293 /* This one is special and actually in units of 100ms, but zero 7294 * based in the hw (so we need to add 100 ms). But the sw vbt 7295 * table multiplies it with 1000 to make it in units of 100usec, 7296 * too. */ 7297 spec.t11_t12 = (510 + 100) * 10; 7298 7299 intel_pps_dump_state("vbt", &vbt); 7300 7301 /* Use the max of the register settings and vbt. If both are 7302 * unset, fall back to the spec limits. */ 7303 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ 7304 spec.field : \ 7305 max(cur.field, vbt.field)) 7306 assign_final(t1_t3); 7307 assign_final(t8); 7308 assign_final(t9); 7309 assign_final(t10); 7310 assign_final(t11_t12); 7311 #undef assign_final 7312 7313 #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) 7314 intel_dp->panel_power_up_delay = get_delay(t1_t3); 7315 intel_dp->backlight_on_delay = get_delay(t8); 7316 intel_dp->backlight_off_delay = get_delay(t9); 7317 intel_dp->panel_power_down_delay = get_delay(t10); 7318 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 7319 #undef get_delay 7320 7321 drm_dbg_kms(&dev_priv->drm, 7322 "panel power up delay %d, power down delay %d, power cycle delay %d\n", 7323 intel_dp->panel_power_up_delay, 7324 intel_dp->panel_power_down_delay, 7325 intel_dp->panel_power_cycle_delay); 7326 7327 drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n", 7328 intel_dp->backlight_on_delay, 7329 intel_dp->backlight_off_delay); 7330 7331 /* 7332 * We override the HW backlight delays to 1 because we do manual waits 7333 * on them. For T8, even BSpec recommends doing it. For T9, if we 7334 * don't do this, we'll end up waiting for the backlight off delay 7335 * twice: once when we do the manual sleep, and once when we disable 7336 * the panel and wait for the PP_STATUS bit to become zero. 7337 */ 7338 final->t8 = 1; 7339 final->t9 = 1; 7340 7341 /* 7342 * HW has only a 100msec granularity for t11_t12 so round it up 7343 * accordingly. 7344 */ 7345 final->t11_t12 = roundup(final->t11_t12, 100 * 10); 7346 } 7347 7348 static void 7349 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, 7350 bool force_disable_vdd) 7351 { 7352 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 7353 u32 pp_on, pp_off, port_sel = 0; 7354 int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000; 7355 struct pps_registers regs; 7356 enum port port = dp_to_dig_port(intel_dp)->base.port; 7357 const struct edp_power_seq *seq = &intel_dp->pps_delays; 7358 7359 lockdep_assert_held(&dev_priv->pps_mutex); 7360 7361 intel_pps_get_registers(intel_dp, ®s); 7362 7363 /* 7364 * On some VLV machines the BIOS can leave the VDD 7365 * enabled even on power sequencers which aren't 7366 * hooked up to any port. This would mess up the 7367 * power domain tracking the first time we pick 7368 * one of these power sequencers for use since 7369 * edp_panel_vdd_on() would notice that the VDD was 7370 * already on and therefore wouldn't grab the power 7371 * domain reference. Disable VDD first to avoid this. 7372 * This also avoids spuriously turning the VDD on as 7373 * soon as the new power sequencer gets initialized. 7374 */ 7375 if (force_disable_vdd) { 7376 u32 pp = ilk_get_pp_control(intel_dp); 7377 7378 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON, 7379 "Panel power already on\n"); 7380 7381 if (pp & EDP_FORCE_VDD) 7382 drm_dbg_kms(&dev_priv->drm, 7383 "VDD already on, disabling first\n"); 7384 7385 pp &= ~EDP_FORCE_VDD; 7386 7387 intel_de_write(dev_priv, regs.pp_ctrl, pp); 7388 } 7389 7390 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | 7391 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); 7392 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | 7393 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); 7394 7395 /* Haswell doesn't have any port selection bits for the panel 7396 * power sequencer any more. */ 7397 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7398 port_sel = PANEL_PORT_SELECT_VLV(port); 7399 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 7400 switch (port) { 7401 case PORT_A: 7402 port_sel = PANEL_PORT_SELECT_DPA; 7403 break; 7404 case PORT_C: 7405 port_sel = PANEL_PORT_SELECT_DPC; 7406 break; 7407 case PORT_D: 7408 port_sel = PANEL_PORT_SELECT_DPD; 7409 break; 7410 default: 7411 MISSING_CASE(port); 7412 break; 7413 } 7414 } 7415 7416 pp_on |= port_sel; 7417 7418 intel_de_write(dev_priv, regs.pp_on, pp_on); 7419 intel_de_write(dev_priv, regs.pp_off, pp_off); 7420 7421 /* 7422 * Compute the divisor for the pp clock, simply match the Bspec formula. 7423 */ 7424 if (i915_mmio_reg_valid(regs.pp_div)) { 7425 intel_de_write(dev_priv, regs.pp_div, 7426 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); 7427 } else { 7428 u32 pp_ctl; 7429 7430 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl); 7431 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK; 7432 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); 7433 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl); 7434 } 7435 7436 drm_dbg_kms(&dev_priv->drm, 7437 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 7438 intel_de_read(dev_priv, regs.pp_on), 7439 intel_de_read(dev_priv, regs.pp_off), 7440 i915_mmio_reg_valid(regs.pp_div) ? 7441 intel_de_read(dev_priv, regs.pp_div) : 7442 (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); 7443 } 7444 7445 static void intel_dp_pps_init(struct intel_dp *intel_dp) 7446 { 7447 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 7448 7449 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7450 vlv_initial_power_sequencer_setup(intel_dp); 7451 } else { 7452 intel_dp_init_panel_power_sequencer(intel_dp); 7453 intel_dp_init_panel_power_sequencer_registers(intel_dp, false); 7454 } 7455 } 7456 7457 /** 7458 * intel_dp_set_drrs_state - program registers for RR switch to take effect 7459 * @dev_priv: i915 device 7460 * @crtc_state: a pointer to the active intel_crtc_state 7461 * @refresh_rate: RR to be programmed 7462 * 7463 * This function gets called when refresh rate (RR) has to be changed from 7464 * one frequency to another. Switches can be between high and low RR 7465 * supported by the panel or to any other RR based on media playback (in 7466 * this case, RR value needs to be passed from user space). 7467 * 7468 * The caller of this function needs to take a lock on dev_priv->drrs. 7469 */ 7470 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, 7471 const struct intel_crtc_state *crtc_state, 7472 int refresh_rate) 7473 { 7474 struct intel_dp *intel_dp = dev_priv->drrs.dp; 7475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 7476 enum drrs_refresh_rate_type index = DRRS_HIGH_RR; 7477 7478 if (refresh_rate <= 0) { 7479 drm_dbg_kms(&dev_priv->drm, 7480 "Refresh rate should be positive non-zero.\n"); 7481 return; 7482 } 7483 7484 if (intel_dp == NULL) { 7485 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); 7486 return; 7487 } 7488 7489 if (!intel_crtc) { 7490 drm_dbg_kms(&dev_priv->drm, 7491 "DRRS: intel_crtc not initialized\n"); 7492 return; 7493 } 7494 7495 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { 7496 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); 7497 return; 7498 } 7499 7500 if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) == 7501 refresh_rate) 7502 index = DRRS_LOW_RR; 7503 7504 if (index == dev_priv->drrs.refresh_rate_type) { 7505 drm_dbg_kms(&dev_priv->drm, 7506 "DRRS requested for previously set RR...ignoring\n"); 7507 return; 7508 } 7509 7510 if (!crtc_state->hw.active) { 7511 drm_dbg_kms(&dev_priv->drm, 7512 "eDP encoder disabled. CRTC not Active\n"); 7513 return; 7514 } 7515 7516 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { 7517 switch (index) { 7518 case DRRS_HIGH_RR: 7519 intel_dp_set_m_n(crtc_state, M1_N1); 7520 break; 7521 case DRRS_LOW_RR: 7522 intel_dp_set_m_n(crtc_state, M2_N2); 7523 break; 7524 case DRRS_MAX_RR: 7525 default: 7526 drm_err(&dev_priv->drm, 7527 "Unsupported refreshrate type\n"); 7528 } 7529 } else if (INTEL_GEN(dev_priv) > 6) { 7530 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); 7531 u32 val; 7532 7533 val = intel_de_read(dev_priv, reg); 7534 if (index > DRRS_HIGH_RR) { 7535 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 7536 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; 7537 else 7538 val |= PIPECONF_EDP_RR_MODE_SWITCH; 7539 } else { 7540 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 7541 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; 7542 else 7543 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 7544 } 7545 intel_de_write(dev_priv, reg, val); 7546 } 7547 7548 dev_priv->drrs.refresh_rate_type = index; 7549 7550 drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n", 7551 refresh_rate); 7552 } 7553 7554 static void 7555 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp) 7556 { 7557 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 7558 7559 dev_priv->drrs.busy_frontbuffer_bits = 0; 7560 dev_priv->drrs.dp = intel_dp; 7561 } 7562 7563 /** 7564 * intel_edp_drrs_enable - init drrs struct if supported 7565 * @intel_dp: DP struct 7566 * @crtc_state: A pointer to the active crtc state. 7567 * 7568 * Initializes frontbuffer_bits and drrs.dp 7569 */ 7570 void intel_edp_drrs_enable(struct intel_dp *intel_dp, 7571 const struct intel_crtc_state *crtc_state) 7572 { 7573 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 7574 7575 if (!crtc_state->has_drrs) 7576 return; 7577 7578 drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n"); 7579 7580 mutex_lock(&dev_priv->drrs.mutex); 7581 7582 if (dev_priv->drrs.dp) { 7583 drm_warn(&dev_priv->drm, "DRRS already enabled\n"); 7584 goto unlock; 7585 } 7586 7587 intel_edp_drrs_enable_locked(intel_dp); 7588 7589 unlock: 7590 mutex_unlock(&dev_priv->drrs.mutex); 7591 } 7592 7593 static void 7594 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp, 7595 const struct intel_crtc_state *crtc_state) 7596 { 7597 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 7598 7599 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) { 7600 int refresh; 7601 7602 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode); 7603 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh); 7604 } 7605 7606 dev_priv->drrs.dp = NULL; 7607 } 7608 7609 /** 7610 * intel_edp_drrs_disable - Disable DRRS 7611 * @intel_dp: DP struct 7612 * @old_crtc_state: Pointer to old crtc_state. 7613 * 7614 */ 7615 void intel_edp_drrs_disable(struct intel_dp *intel_dp, 7616 const struct intel_crtc_state *old_crtc_state) 7617 { 7618 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 7619 7620 if (!old_crtc_state->has_drrs) 7621 return; 7622 7623 mutex_lock(&dev_priv->drrs.mutex); 7624 if (!dev_priv->drrs.dp) { 7625 mutex_unlock(&dev_priv->drrs.mutex); 7626 return; 7627 } 7628 7629 intel_edp_drrs_disable_locked(intel_dp, old_crtc_state); 7630 mutex_unlock(&dev_priv->drrs.mutex); 7631 7632 cancel_delayed_work_sync(&dev_priv->drrs.work); 7633 } 7634 7635 /** 7636 * intel_edp_drrs_update - Update DRRS state 7637 * @intel_dp: Intel DP 7638 * @crtc_state: new CRTC state 7639 * 7640 * This function will update DRRS states, disabling or enabling DRRS when 7641 * executing fastsets. For full modeset, intel_edp_drrs_disable() and 7642 * intel_edp_drrs_enable() should be called instead. 7643 */ 7644 void 7645 intel_edp_drrs_update(struct intel_dp *intel_dp, 7646 const struct intel_crtc_state *crtc_state) 7647 { 7648 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 7649 7650 if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT) 7651 return; 7652 7653 mutex_lock(&dev_priv->drrs.mutex); 7654 7655 /* New state matches current one? */ 7656 if (crtc_state->has_drrs == !!dev_priv->drrs.dp) 7657 goto unlock; 7658 7659 if (crtc_state->has_drrs) 7660 intel_edp_drrs_enable_locked(intel_dp); 7661 else 7662 intel_edp_drrs_disable_locked(intel_dp, crtc_state); 7663 7664 unlock: 7665 mutex_unlock(&dev_priv->drrs.mutex); 7666 } 7667 7668 static void intel_edp_drrs_downclock_work(struct work_struct *work) 7669 { 7670 struct drm_i915_private *dev_priv = 7671 container_of(work, typeof(*dev_priv), drrs.work.work); 7672 struct intel_dp *intel_dp; 7673 7674 mutex_lock(&dev_priv->drrs.mutex); 7675 7676 intel_dp = dev_priv->drrs.dp; 7677 7678 if (!intel_dp) 7679 goto unlock; 7680 7681 /* 7682 * The delayed work can race with an invalidate hence we need to 7683 * recheck. 7684 */ 7685 7686 if (dev_priv->drrs.busy_frontbuffer_bits) 7687 goto unlock; 7688 7689 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { 7690 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 7691 7692 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 7693 drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode)); 7694 } 7695 7696 unlock: 7697 mutex_unlock(&dev_priv->drrs.mutex); 7698 } 7699 7700 /** 7701 * intel_edp_drrs_invalidate - Disable Idleness DRRS 7702 * @dev_priv: i915 device 7703 * @frontbuffer_bits: frontbuffer plane tracking bits 7704 * 7705 * This function gets called everytime rendering on the given planes start. 7706 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 7707 * 7708 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 7709 */ 7710 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, 7711 unsigned int frontbuffer_bits) 7712 { 7713 struct intel_dp *intel_dp; 7714 struct drm_crtc *crtc; 7715 enum pipe pipe; 7716 7717 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 7718 return; 7719 7720 cancel_delayed_work(&dev_priv->drrs.work); 7721 7722 mutex_lock(&dev_priv->drrs.mutex); 7723 7724 intel_dp = dev_priv->drrs.dp; 7725 if (!intel_dp) { 7726 mutex_unlock(&dev_priv->drrs.mutex); 7727 return; 7728 } 7729 7730 crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 7731 pipe = to_intel_crtc(crtc)->pipe; 7732 7733 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 7734 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 7735 7736 /* invalidate means busy screen hence upclock */ 7737 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 7738 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 7739 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode)); 7740 7741 mutex_unlock(&dev_priv->drrs.mutex); 7742 } 7743 7744 /** 7745 * intel_edp_drrs_flush - Restart Idleness DRRS 7746 * @dev_priv: i915 device 7747 * @frontbuffer_bits: frontbuffer plane tracking bits 7748 * 7749 * This function gets called every time rendering on the given planes has 7750 * completed or flip on a crtc is completed. So DRRS should be upclocked 7751 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 7752 * if no other planes are dirty. 7753 * 7754 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 7755 */ 7756 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, 7757 unsigned int frontbuffer_bits) 7758 { 7759 struct intel_dp *intel_dp; 7760 struct drm_crtc *crtc; 7761 enum pipe pipe; 7762 7763 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 7764 return; 7765 7766 cancel_delayed_work(&dev_priv->drrs.work); 7767 7768 mutex_lock(&dev_priv->drrs.mutex); 7769 7770 intel_dp = dev_priv->drrs.dp; 7771 if (!intel_dp) { 7772 mutex_unlock(&dev_priv->drrs.mutex); 7773 return; 7774 } 7775 7776 crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 7777 pipe = to_intel_crtc(crtc)->pipe; 7778 7779 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 7780 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 7781 7782 /* flush means busy screen hence upclock */ 7783 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 7784 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 7785 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode)); 7786 7787 /* 7788 * flush also means no more activity hence schedule downclock, if all 7789 * other fbs are quiescent too 7790 */ 7791 if (!dev_priv->drrs.busy_frontbuffer_bits) 7792 schedule_delayed_work(&dev_priv->drrs.work, 7793 msecs_to_jiffies(1000)); 7794 mutex_unlock(&dev_priv->drrs.mutex); 7795 } 7796 7797 /** 7798 * DOC: Display Refresh Rate Switching (DRRS) 7799 * 7800 * Display Refresh Rate Switching (DRRS) is a power conservation feature 7801 * which enables swtching between low and high refresh rates, 7802 * dynamically, based on the usage scenario. This feature is applicable 7803 * for internal panels. 7804 * 7805 * Indication that the panel supports DRRS is given by the panel EDID, which 7806 * would list multiple refresh rates for one resolution. 7807 * 7808 * DRRS is of 2 types - static and seamless. 7809 * Static DRRS involves changing refresh rate (RR) by doing a full modeset 7810 * (may appear as a blink on screen) and is used in dock-undock scenario. 7811 * Seamless DRRS involves changing RR without any visual effect to the user 7812 * and can be used during normal system usage. This is done by programming 7813 * certain registers. 7814 * 7815 * Support for static/seamless DRRS may be indicated in the VBT based on 7816 * inputs from the panel spec. 7817 * 7818 * DRRS saves power by switching to low RR based on usage scenarios. 7819 * 7820 * The implementation is based on frontbuffer tracking implementation. When 7821 * there is a disturbance on the screen triggered by user activity or a periodic 7822 * system activity, DRRS is disabled (RR is changed to high RR). When there is 7823 * no movement on screen, after a timeout of 1 second, a switch to low RR is 7824 * made. 7825 * 7826 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() 7827 * and intel_edp_drrs_flush() are called. 7828 * 7829 * DRRS can be further extended to support other internal panels and also 7830 * the scenario of video playback wherein RR is set based on the rate 7831 * requested by userspace. 7832 */ 7833 7834 /** 7835 * intel_dp_drrs_init - Init basic DRRS work and mutex. 7836 * @connector: eDP connector 7837 * @fixed_mode: preferred mode of panel 7838 * 7839 * This function is called only once at driver load to initialize basic 7840 * DRRS stuff. 7841 * 7842 * Returns: 7843 * Downclock mode if panel supports it, else return NULL. 7844 * DRRS support is determined by the presence of downclock mode (apart 7845 * from VBT setting). 7846 */ 7847 static struct drm_display_mode * 7848 intel_dp_drrs_init(struct intel_connector *connector, 7849 struct drm_display_mode *fixed_mode) 7850 { 7851 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 7852 struct drm_display_mode *downclock_mode = NULL; 7853 7854 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); 7855 mutex_init(&dev_priv->drrs.mutex); 7856 7857 if (INTEL_GEN(dev_priv) <= 6) { 7858 drm_dbg_kms(&dev_priv->drm, 7859 "DRRS supported for Gen7 and above\n"); 7860 return NULL; 7861 } 7862 7863 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 7864 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n"); 7865 return NULL; 7866 } 7867 7868 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); 7869 if (!downclock_mode) { 7870 drm_dbg_kms(&dev_priv->drm, 7871 "Downclock mode is not found. DRRS not supported\n"); 7872 return NULL; 7873 } 7874 7875 dev_priv->drrs.type = dev_priv->vbt.drrs_type; 7876 7877 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; 7878 drm_dbg_kms(&dev_priv->drm, 7879 "seamless DRRS supported for eDP panel.\n"); 7880 return downclock_mode; 7881 } 7882 7883 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 7884 struct intel_connector *intel_connector) 7885 { 7886 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 7887 struct drm_device *dev = &dev_priv->drm; 7888 struct drm_connector *connector = &intel_connector->base; 7889 struct drm_display_mode *fixed_mode = NULL; 7890 struct drm_display_mode *downclock_mode = NULL; 7891 bool has_dpcd; 7892 enum pipe pipe = INVALID_PIPE; 7893 intel_wakeref_t wakeref; 7894 struct edid *edid; 7895 7896 if (!intel_dp_is_edp(intel_dp)) 7897 return true; 7898 7899 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work); 7900 7901 /* 7902 * On IBX/CPT we may get here with LVDS already registered. Since the 7903 * driver uses the only internal power sequencer available for both 7904 * eDP and LVDS bail out early in this case to prevent interfering 7905 * with an already powered-on LVDS power sequencer. 7906 */ 7907 if (intel_get_lvds_encoder(dev_priv)) { 7908 drm_WARN_ON(dev, 7909 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 7910 drm_info(&dev_priv->drm, 7911 "LVDS was detected, not registering eDP\n"); 7912 7913 return false; 7914 } 7915 7916 with_pps_lock(intel_dp, wakeref) { 7917 intel_dp_init_panel_power_timestamps(intel_dp); 7918 intel_dp_pps_init(intel_dp); 7919 intel_edp_panel_vdd_sanitize(intel_dp); 7920 } 7921 7922 /* Cache DPCD and EDID for edp. */ 7923 has_dpcd = intel_edp_init_dpcd(intel_dp); 7924 7925 if (!has_dpcd) { 7926 /* if this fails, presume the device is a ghost */ 7927 drm_info(&dev_priv->drm, 7928 "failed to retrieve link info, disabling eDP\n"); 7929 goto out_vdd_off; 7930 } 7931 7932 mutex_lock(&dev->mode_config.mutex); 7933 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 7934 if (edid) { 7935 if (drm_add_edid_modes(connector, edid)) { 7936 drm_connector_update_edid_property(connector, edid); 7937 intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); 7938 } else { 7939 kfree(edid); 7940 edid = ERR_PTR(-EINVAL); 7941 } 7942 } else { 7943 edid = ERR_PTR(-ENOENT); 7944 } 7945 intel_connector->edid = edid; 7946 7947 fixed_mode = intel_panel_edid_fixed_mode(intel_connector); 7948 if (fixed_mode) 7949 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode); 7950 7951 /* fallback to VBT if available for eDP */ 7952 if (!fixed_mode) 7953 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 7954 mutex_unlock(&dev->mode_config.mutex); 7955 7956 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7957 /* 7958 * Figure out the current pipe for the initial backlight setup. 7959 * If the current pipe isn't valid, try the PPS pipe, and if that 7960 * fails just assume pipe A. 7961 */ 7962 pipe = vlv_active_pipe(intel_dp); 7963 7964 if (pipe != PIPE_A && pipe != PIPE_B) 7965 pipe = intel_dp->pps_pipe; 7966 7967 if (pipe != PIPE_A && pipe != PIPE_B) 7968 pipe = PIPE_A; 7969 7970 drm_dbg_kms(&dev_priv->drm, 7971 "using pipe %c for initial backlight setup\n", 7972 pipe_name(pipe)); 7973 } 7974 7975 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 7976 intel_connector->panel.backlight.power = intel_edp_backlight_power; 7977 intel_panel_setup_backlight(connector, pipe); 7978 7979 if (fixed_mode) { 7980 drm_connector_set_panel_orientation_with_quirk(connector, 7981 dev_priv->vbt.orientation, 7982 fixed_mode->hdisplay, fixed_mode->vdisplay); 7983 } 7984 7985 return true; 7986 7987 out_vdd_off: 7988 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 7989 /* 7990 * vdd might still be enabled do to the delayed vdd off. 7991 * Make sure vdd is actually turned off here. 7992 */ 7993 with_pps_lock(intel_dp, wakeref) 7994 edp_panel_vdd_off_sync(intel_dp); 7995 7996 return false; 7997 } 7998 7999 static void intel_dp_modeset_retry_work_fn(struct work_struct *work) 8000 { 8001 struct intel_connector *intel_connector; 8002 struct drm_connector *connector; 8003 8004 intel_connector = container_of(work, typeof(*intel_connector), 8005 modeset_retry_work); 8006 connector = &intel_connector->base; 8007 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, 8008 connector->name); 8009 8010 /* Grab the locks before changing connector property*/ 8011 mutex_lock(&connector->dev->mode_config.mutex); 8012 /* Set connector link status to BAD and send a Uevent to notify 8013 * userspace to do a modeset. 8014 */ 8015 drm_connector_set_link_status_property(connector, 8016 DRM_MODE_LINK_STATUS_BAD); 8017 mutex_unlock(&connector->dev->mode_config.mutex); 8018 /* Send Hotplug uevent so userspace can reprobe */ 8019 drm_kms_helper_hotplug_event(connector->dev); 8020 } 8021 8022 bool 8023 intel_dp_init_connector(struct intel_digital_port *dig_port, 8024 struct intel_connector *intel_connector) 8025 { 8026 struct drm_connector *connector = &intel_connector->base; 8027 struct intel_dp *intel_dp = &dig_port->dp; 8028 struct intel_encoder *intel_encoder = &dig_port->base; 8029 struct drm_device *dev = intel_encoder->base.dev; 8030 struct drm_i915_private *dev_priv = to_i915(dev); 8031 enum port port = intel_encoder->port; 8032 enum phy phy = intel_port_to_phy(dev_priv, port); 8033 int type; 8034 8035 /* Initialize the work for modeset in case of link train failure */ 8036 INIT_WORK(&intel_connector->modeset_retry_work, 8037 intel_dp_modeset_retry_work_fn); 8038 8039 if (drm_WARN(dev, dig_port->max_lanes < 1, 8040 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", 8041 dig_port->max_lanes, intel_encoder->base.base.id, 8042 intel_encoder->base.name)) 8043 return false; 8044 8045 intel_dp_set_source_rates(intel_dp); 8046 8047 intel_dp->reset_link_params = true; 8048 intel_dp->pps_pipe = INVALID_PIPE; 8049 intel_dp->active_pipe = INVALID_PIPE; 8050 8051 /* Preserve the current hw state. */ 8052 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); 8053 intel_dp->attached_connector = intel_connector; 8054 8055 if (intel_dp_is_port_edp(dev_priv, port)) { 8056 /* 8057 * Currently we don't support eDP on TypeC ports, although in 8058 * theory it could work on TypeC legacy ports. 8059 */ 8060 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy)); 8061 type = DRM_MODE_CONNECTOR_eDP; 8062 } else { 8063 type = DRM_MODE_CONNECTOR_DisplayPort; 8064 } 8065 8066 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 8067 intel_dp->active_pipe = vlv_active_pipe(intel_dp); 8068 8069 /* 8070 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 8071 * for DP the encoder type can be set by the caller to 8072 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 8073 */ 8074 if (type == DRM_MODE_CONNECTOR_eDP) 8075 intel_encoder->type = INTEL_OUTPUT_EDP; 8076 8077 /* eDP only on port B and/or C on vlv/chv */ 8078 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) || 8079 IS_CHERRYVIEW(dev_priv)) && 8080 intel_dp_is_edp(intel_dp) && 8081 port != PORT_B && port != PORT_C)) 8082 return false; 8083 8084 drm_dbg_kms(&dev_priv->drm, 8085 "Adding %s connector on [ENCODER:%d:%s]\n", 8086 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 8087 intel_encoder->base.base.id, intel_encoder->base.name); 8088 8089 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 8090 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 8091 8092 if (!HAS_GMCH(dev_priv)) 8093 connector->interlace_allowed = true; 8094 connector->doublescan_allowed = 0; 8095 8096 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 8097 8098 intel_dp_aux_init(intel_dp); 8099 8100 intel_connector_attach_encoder(intel_connector, intel_encoder); 8101 8102 if (HAS_DDI(dev_priv)) 8103 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 8104 else 8105 intel_connector->get_hw_state = intel_connector_get_hw_state; 8106 8107 /* init MST on ports that can support it */ 8108 intel_dp_mst_encoder_init(dig_port, 8109 intel_connector->base.base.id); 8110 8111 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 8112 intel_dp_aux_fini(intel_dp); 8113 intel_dp_mst_encoder_cleanup(dig_port); 8114 goto fail; 8115 } 8116 8117 intel_dp_add_properties(intel_dp, connector); 8118 8119 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { 8120 int ret = intel_dp_init_hdcp(dig_port, intel_connector); 8121 if (ret) 8122 drm_dbg_kms(&dev_priv->drm, 8123 "HDCP init failed, skipping.\n"); 8124 } 8125 8126 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 8127 * 0xd. Failure to do so will result in spurious interrupts being 8128 * generated on the port when a cable is not attached. 8129 */ 8130 if (IS_G45(dev_priv)) { 8131 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 8132 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 8133 (temp & ~0xf) | 0xd); 8134 } 8135 8136 return true; 8137 8138 fail: 8139 drm_connector_cleanup(connector); 8140 8141 return false; 8142 } 8143 8144 bool intel_dp_init(struct drm_i915_private *dev_priv, 8145 i915_reg_t output_reg, 8146 enum port port) 8147 { 8148 struct intel_digital_port *dig_port; 8149 struct intel_encoder *intel_encoder; 8150 struct drm_encoder *encoder; 8151 struct intel_connector *intel_connector; 8152 8153 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 8154 if (!dig_port) 8155 return false; 8156 8157 intel_connector = intel_connector_alloc(); 8158 if (!intel_connector) 8159 goto err_connector_alloc; 8160 8161 intel_encoder = &dig_port->base; 8162 encoder = &intel_encoder->base; 8163 8164 mutex_init(&dig_port->hdcp_mutex); 8165 8166 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 8167 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, 8168 "DP %c", port_name(port))) 8169 goto err_encoder_init; 8170 8171 intel_encoder->hotplug = intel_dp_hotplug; 8172 intel_encoder->compute_config = intel_dp_compute_config; 8173 intel_encoder->get_hw_state = intel_dp_get_hw_state; 8174 intel_encoder->get_config = intel_dp_get_config; 8175 intel_encoder->sync_state = intel_dp_sync_state; 8176 intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check; 8177 intel_encoder->update_pipe = intel_panel_update_backlight; 8178 intel_encoder->suspend = intel_dp_encoder_suspend; 8179 intel_encoder->shutdown = intel_dp_encoder_shutdown; 8180 if (IS_CHERRYVIEW(dev_priv)) { 8181 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 8182 intel_encoder->pre_enable = chv_pre_enable_dp; 8183 intel_encoder->enable = vlv_enable_dp; 8184 intel_encoder->disable = vlv_disable_dp; 8185 intel_encoder->post_disable = chv_post_disable_dp; 8186 intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 8187 } else if (IS_VALLEYVIEW(dev_priv)) { 8188 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 8189 intel_encoder->pre_enable = vlv_pre_enable_dp; 8190 intel_encoder->enable = vlv_enable_dp; 8191 intel_encoder->disable = vlv_disable_dp; 8192 intel_encoder->post_disable = vlv_post_disable_dp; 8193 } else { 8194 intel_encoder->pre_enable = g4x_pre_enable_dp; 8195 intel_encoder->enable = g4x_enable_dp; 8196 intel_encoder->disable = g4x_disable_dp; 8197 intel_encoder->post_disable = g4x_post_disable_dp; 8198 } 8199 8200 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || 8201 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) 8202 dig_port->dp.set_link_train = cpt_set_link_train; 8203 else 8204 dig_port->dp.set_link_train = g4x_set_link_train; 8205 8206 if (IS_CHERRYVIEW(dev_priv)) 8207 dig_port->dp.set_signal_levels = chv_set_signal_levels; 8208 else if (IS_VALLEYVIEW(dev_priv)) 8209 dig_port->dp.set_signal_levels = vlv_set_signal_levels; 8210 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) 8211 dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; 8212 else if (IS_GEN(dev_priv, 6) && port == PORT_A) 8213 dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; 8214 else 8215 dig_port->dp.set_signal_levels = g4x_set_signal_levels; 8216 8217 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || 8218 (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { 8219 dig_port->dp.preemph_max = intel_dp_preemph_max_3; 8220 dig_port->dp.voltage_max = intel_dp_voltage_max_3; 8221 } else { 8222 dig_port->dp.preemph_max = intel_dp_preemph_max_2; 8223 dig_port->dp.voltage_max = intel_dp_voltage_max_2; 8224 } 8225 8226 dig_port->dp.output_reg = output_reg; 8227 dig_port->max_lanes = 4; 8228 8229 intel_encoder->type = INTEL_OUTPUT_DP; 8230 intel_encoder->power_domain = intel_port_to_power_domain(port); 8231 if (IS_CHERRYVIEW(dev_priv)) { 8232 if (port == PORT_D) 8233 intel_encoder->pipe_mask = BIT(PIPE_C); 8234 else 8235 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 8236 } else { 8237 intel_encoder->pipe_mask = ~0; 8238 } 8239 intel_encoder->cloneable = 0; 8240 intel_encoder->port = port; 8241 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 8242 8243 dig_port->hpd_pulse = intel_dp_hpd_pulse; 8244 8245 if (HAS_GMCH(dev_priv)) { 8246 if (IS_GM45(dev_priv)) 8247 dig_port->connected = gm45_digital_port_connected; 8248 else 8249 dig_port->connected = g4x_digital_port_connected; 8250 } else { 8251 if (port == PORT_A) 8252 dig_port->connected = ilk_digital_port_connected; 8253 else 8254 dig_port->connected = ibx_digital_port_connected; 8255 } 8256 8257 if (port != PORT_A) 8258 intel_infoframe_init(dig_port); 8259 8260 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 8261 if (!intel_dp_init_connector(dig_port, intel_connector)) 8262 goto err_init_connector; 8263 8264 return true; 8265 8266 err_init_connector: 8267 drm_encoder_cleanup(encoder); 8268 err_encoder_init: 8269 kfree(intel_connector); 8270 err_connector_alloc: 8271 kfree(dig_port); 8272 return false; 8273 } 8274 8275 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) 8276 { 8277 struct intel_encoder *encoder; 8278 8279 for_each_intel_encoder(&dev_priv->drm, encoder) { 8280 struct intel_dp *intel_dp; 8281 8282 if (encoder->type != INTEL_OUTPUT_DDI) 8283 continue; 8284 8285 intel_dp = enc_to_intel_dp(encoder); 8286 8287 if (!intel_dp->can_mst) 8288 continue; 8289 8290 if (intel_dp->is_mst) 8291 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); 8292 } 8293 } 8294 8295 void intel_dp_mst_resume(struct drm_i915_private *dev_priv) 8296 { 8297 struct intel_encoder *encoder; 8298 8299 for_each_intel_encoder(&dev_priv->drm, encoder) { 8300 struct intel_dp *intel_dp; 8301 int ret; 8302 8303 if (encoder->type != INTEL_OUTPUT_DDI) 8304 continue; 8305 8306 intel_dp = enc_to_intel_dp(encoder); 8307 8308 if (!intel_dp->can_mst) 8309 continue; 8310 8311 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, 8312 true); 8313 if (ret) { 8314 intel_dp->is_mst = false; 8315 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 8316 false); 8317 } 8318 } 8319 } 8320