1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/export.h> 29 #include <linux/i2c.h> 30 #include <linux/notifier.h> 31 #include <linux/seq_buf.h> 32 #include <linux/slab.h> 33 #include <linux/sort.h> 34 #include <linux/string_helpers.h> 35 #include <linux/timekeeping.h> 36 #include <linux/types.h> 37 38 #include <asm/byteorder.h> 39 40 #include <drm/display/drm_dp_helper.h> 41 #include <drm/display/drm_dp_tunnel.h> 42 #include <drm/display/drm_dsc_helper.h> 43 #include <drm/display/drm_hdmi_helper.h> 44 #include <drm/drm_atomic_helper.h> 45 #include <drm/drm_crtc.h> 46 #include <drm/drm_edid.h> 47 #include <drm/drm_fixed.h> 48 #include <drm/drm_print.h> 49 #include <drm/drm_probe_helper.h> 50 51 #include "g4x_dp.h" 52 #include "i915_irq.h" 53 #include "i915_reg.h" 54 #include "i915_utils.h" 55 #include "intel_alpm.h" 56 #include "intel_atomic.h" 57 #include "intel_audio.h" 58 #include "intel_backlight.h" 59 #include "intel_combo_phy_regs.h" 60 #include "intel_connector.h" 61 #include "intel_crtc.h" 62 #include "intel_crtc_state_dump.h" 63 #include "intel_cx0_phy.h" 64 #include "intel_ddi.h" 65 #include "intel_de.h" 66 #include "intel_display_driver.h" 67 #include "intel_display_rpm.h" 68 #include "intel_display_types.h" 69 #include "intel_dp.h" 70 #include "intel_dp_aux.h" 71 #include "intel_dp_hdcp.h" 72 #include "intel_dp_link_training.h" 73 #include "intel_dp_mst.h" 74 #include "intel_dp_test.h" 75 #include "intel_dp_tunnel.h" 76 #include "intel_dpio_phy.h" 77 #include "intel_dpll.h" 78 #include "intel_drrs.h" 79 #include "intel_encoder.h" 80 #include "intel_fifo_underrun.h" 81 #include "intel_hdcp.h" 82 #include "intel_hdmi.h" 83 #include "intel_hotplug.h" 84 #include "intel_hotplug_irq.h" 85 #include "intel_lspcon.h" 86 #include "intel_lvds.h" 87 #include "intel_modeset_lock.h" 88 #include "intel_panel.h" 89 #include "intel_pch_display.h" 90 #include "intel_pfit.h" 91 #include "intel_pps.h" 92 #include "intel_psr.h" 93 #include "intel_quirks.h" 94 #include "intel_tc.h" 95 #include "intel_vdsc.h" 96 #include "intel_vrr.h" 97 98 /* DP DSC throughput values used for slice count calculations KPixels/s */ 99 #define DP_DSC_PEAK_PIXEL_RATE 2720000 100 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 101 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 102 103 /* Max DSC line buffer depth supported by HW. */ 104 #define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13 105 106 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ 107 #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530 108 109 /* Constants for DP DSC configurations */ 110 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 111 112 /* 113 * With Single pipe configuration, HW is capable of supporting maximum of: 114 * 2 slices per line for ICL, BMG 115 * 4 slices per line for other platforms. 116 * For now consider a max of 2 slices per line, which works for all platforms. 117 * With this we can have max of 4 DSC Slices per pipe. 118 * 119 * For higher resolutions where 12 slice support is required with 120 * ultrajoiner, only then each pipe can support 3 slices. 121 * 122 * #TODO Split this better to use 4 slices/dsc engine where supported. 123 */ 124 static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4}; 125 126 /** 127 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 128 * @intel_dp: DP struct 129 * 130 * If a CPU or PCH DP output is attached to an eDP panel, this function 131 * will return true, and false otherwise. 132 * 133 * This function is not safe to use prior to encoder type being set. 134 */ 135 bool intel_dp_is_edp(struct intel_dp *intel_dp) 136 { 137 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 138 139 return dig_port->base.type == INTEL_OUTPUT_EDP; 140 } 141 142 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 143 144 /* Is link rate UHBR and thus 128b/132b? */ 145 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) 146 { 147 return drm_dp_is_uhbr_rate(crtc_state->port_clock); 148 } 149 150 /** 151 * intel_dp_link_symbol_size - get the link symbol size for a given link rate 152 * @rate: link rate in 10kbit/s units 153 * 154 * Returns the link symbol size in bits/symbol units depending on the link 155 * rate -> channel coding. 156 */ 157 int intel_dp_link_symbol_size(int rate) 158 { 159 return drm_dp_is_uhbr_rate(rate) ? 32 : 10; 160 } 161 162 /** 163 * intel_dp_link_symbol_clock - convert link rate to link symbol clock 164 * @rate: link rate in 10kbit/s units 165 * 166 * Returns the link symbol clock frequency in kHz units depending on the 167 * link rate and channel coding. 168 */ 169 int intel_dp_link_symbol_clock(int rate) 170 { 171 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate)); 172 } 173 174 static int max_dprx_rate(struct intel_dp *intel_dp) 175 { 176 struct intel_display *display = to_intel_display(intel_dp); 177 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 178 int max_rate; 179 180 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 181 max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); 182 else 183 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 184 185 /* 186 * Some broken eDP sinks illegally declare support for 187 * HBR3 without TPS4, and are unable to produce a stable 188 * output. Reject HBR3 when TPS4 is not available. 189 */ 190 if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) { 191 drm_dbg_kms(display->drm, 192 "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n", 193 encoder->base.base.id, encoder->base.name); 194 max_rate = 540000; 195 } 196 197 return max_rate; 198 } 199 200 static int max_dprx_lane_count(struct intel_dp *intel_dp) 201 { 202 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 203 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel); 204 205 return drm_dp_max_lane_count(intel_dp->dpcd); 206 } 207 208 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) 209 { 210 intel_dp->sink_rates[0] = 162000; 211 intel_dp->num_sink_rates = 1; 212 } 213 214 /* update sink rates from dpcd */ 215 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) 216 { 217 static const int dp_rates[] = { 218 162000, 270000, 540000, 810000 219 }; 220 int i, max_rate; 221 int max_lttpr_rate; 222 223 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { 224 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ 225 static const int quirk_rates[] = { 162000, 270000, 324000 }; 226 227 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); 228 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); 229 230 return; 231 } 232 233 /* 234 * Sink rates for 8b/10b. 235 */ 236 max_rate = max_dprx_rate(intel_dp); 237 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); 238 if (max_lttpr_rate) 239 max_rate = min(max_rate, max_lttpr_rate); 240 241 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { 242 if (dp_rates[i] > max_rate) 243 break; 244 intel_dp->sink_rates[i] = dp_rates[i]; 245 } 246 247 /* 248 * Sink rates for 128b/132b. If set, sink should support all 8b/10b 249 * rates and 10 Gbps. 250 */ 251 if (drm_dp_128b132b_supported(intel_dp->dpcd)) { 252 u8 uhbr_rates = 0; 253 254 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); 255 256 drm_dp_dpcd_readb(&intel_dp->aux, 257 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates); 258 259 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) { 260 /* We have a repeater */ 261 if (intel_dp->lttpr_common_caps[0] >= 0x20 && 262 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 263 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] & 264 DP_PHY_REPEATER_128B132B_SUPPORTED) { 265 /* Repeater supports 128b/132b, valid UHBR rates */ 266 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES - 267 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 268 } else { 269 /* Does not support 128b/132b */ 270 uhbr_rates = 0; 271 } 272 } 273 274 if (uhbr_rates & DP_UHBR10) 275 intel_dp->sink_rates[i++] = 1000000; 276 if (uhbr_rates & DP_UHBR13_5) 277 intel_dp->sink_rates[i++] = 1350000; 278 if (uhbr_rates & DP_UHBR20) 279 intel_dp->sink_rates[i++] = 2000000; 280 } 281 282 intel_dp->num_sink_rates = i; 283 } 284 285 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 286 { 287 struct intel_display *display = to_intel_display(intel_dp); 288 struct intel_connector *connector = intel_dp->attached_connector; 289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 290 struct intel_encoder *encoder = &intel_dig_port->base; 291 292 intel_dp_set_dpcd_sink_rates(intel_dp); 293 294 if (intel_dp->num_sink_rates) 295 return; 296 297 drm_err(display->drm, 298 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", 299 connector->base.base.id, connector->base.name, 300 encoder->base.base.id, encoder->base.name); 301 302 intel_dp_set_default_sink_rates(intel_dp); 303 } 304 305 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp) 306 { 307 intel_dp->max_sink_lane_count = 1; 308 } 309 310 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp) 311 { 312 struct intel_display *display = to_intel_display(intel_dp); 313 struct intel_connector *connector = intel_dp->attached_connector; 314 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 315 struct intel_encoder *encoder = &intel_dig_port->base; 316 317 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp); 318 319 switch (intel_dp->max_sink_lane_count) { 320 case 1: 321 case 2: 322 case 4: 323 return; 324 } 325 326 drm_err(display->drm, 327 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", 328 connector->base.base.id, connector->base.name, 329 encoder->base.base.id, encoder->base.name, 330 intel_dp->max_sink_lane_count); 331 332 intel_dp_set_default_max_sink_lane_count(intel_dp); 333 } 334 335 /* Get length of rates array potentially limited by max_rate. */ 336 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) 337 { 338 int i; 339 340 /* Limit results by potentially reduced max rate */ 341 for (i = 0; i < len; i++) { 342 if (rates[len - i - 1] <= max_rate) 343 return len - i; 344 } 345 346 return 0; 347 } 348 349 /* Get length of common rates array potentially limited by max_rate. */ 350 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, 351 int max_rate) 352 { 353 return intel_dp_rate_limit_len(intel_dp->common_rates, 354 intel_dp->num_common_rates, max_rate); 355 } 356 357 int intel_dp_common_rate(struct intel_dp *intel_dp, int index) 358 { 359 struct intel_display *display = to_intel_display(intel_dp); 360 361 if (drm_WARN_ON(display->drm, 362 index < 0 || index >= intel_dp->num_common_rates)) 363 return 162000; 364 365 return intel_dp->common_rates[index]; 366 } 367 368 /* Theoretical max between source and sink */ 369 int intel_dp_max_common_rate(struct intel_dp *intel_dp) 370 { 371 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); 372 } 373 374 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) 375 { 376 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); 377 int max_lanes = dig_port->max_lanes; 378 379 if (vbt_max_lanes) 380 max_lanes = min(max_lanes, vbt_max_lanes); 381 382 return max_lanes; 383 } 384 385 /* Theoretical max between source and sink */ 386 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) 387 { 388 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 389 int source_max = intel_dp_max_source_lane_count(dig_port); 390 int sink_max = intel_dp->max_sink_lane_count; 391 int lane_max = intel_tc_port_max_lane_count(dig_port); 392 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); 393 394 if (lttpr_max) 395 sink_max = min(sink_max, lttpr_max); 396 397 return min3(source_max, sink_max, lane_max); 398 } 399 400 static int forced_lane_count(struct intel_dp *intel_dp) 401 { 402 return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp)); 403 } 404 405 int intel_dp_max_lane_count(struct intel_dp *intel_dp) 406 { 407 int lane_count; 408 409 if (intel_dp->link.force_lane_count) 410 lane_count = forced_lane_count(intel_dp); 411 else 412 lane_count = intel_dp->link.max_lane_count; 413 414 switch (lane_count) { 415 case 1: 416 case 2: 417 case 4: 418 return lane_count; 419 default: 420 MISSING_CASE(lane_count); 421 return 1; 422 } 423 } 424 425 static int intel_dp_min_lane_count(struct intel_dp *intel_dp) 426 { 427 if (intel_dp->link.force_lane_count) 428 return forced_lane_count(intel_dp); 429 430 return 1; 431 } 432 433 /* 434 * The required data bandwidth for a mode with given pixel clock and bpp. This 435 * is the required net bandwidth independent of the data bandwidth efficiency. 436 * 437 * TODO: check if callers of this functions should use 438 * intel_dp_effective_data_rate() instead. 439 */ 440 int 441 intel_dp_link_required(int pixel_clock, int bpp) 442 { 443 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 444 return DIV_ROUND_UP(pixel_clock * bpp, 8); 445 } 446 447 /** 448 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead 449 * @pixel_clock: pixel clock in kHz 450 * @bpp_x16: bits per pixel .4 fixed point format 451 * @bw_overhead: BW allocation overhead in 1ppm units 452 * 453 * Return the effective pixel data rate in kB/sec units taking into account 454 * the provided SSC, FEC, DSC BW allocation overhead. 455 */ 456 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 457 int bw_overhead) 458 { 459 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead), 460 1000000 * 16 * 8); 461 } 462 463 /** 464 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params 465 * @intel_dp: Intel DP object 466 * @max_dprx_rate: Maximum data rate of the DPRX 467 * @max_dprx_lanes: Maximum lane count of the DPRX 468 * 469 * Calculate the maximum data rate for the provided link parameters taking into 470 * account any BW limitations by a DP tunnel attached to @intel_dp. 471 * 472 * Returns the maximum data rate in kBps units. 473 */ 474 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, 475 int max_dprx_rate, int max_dprx_lanes) 476 { 477 int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes); 478 479 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 480 max_rate = min(max_rate, 481 drm_dp_tunnel_available_bw(intel_dp->tunnel)); 482 483 return max_rate; 484 } 485 486 bool intel_dp_has_joiner(struct intel_dp *intel_dp) 487 { 488 struct intel_display *display = to_intel_display(intel_dp); 489 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 490 struct intel_encoder *encoder = &intel_dig_port->base; 491 492 /* eDP MSO is not compatible with joiner */ 493 if (intel_dp->mso_link_count) 494 return false; 495 496 return DISPLAY_VER(display) >= 12 || 497 (DISPLAY_VER(display) == 11 && 498 encoder->port != PORT_A); 499 } 500 501 static int dg2_max_source_rate(struct intel_dp *intel_dp) 502 { 503 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000; 504 } 505 506 static int icl_max_source_rate(struct intel_dp *intel_dp) 507 { 508 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 509 510 if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp)) 511 return 540000; 512 513 return 810000; 514 } 515 516 static int ehl_max_source_rate(struct intel_dp *intel_dp) 517 { 518 if (intel_dp_is_edp(intel_dp)) 519 return 540000; 520 521 return 810000; 522 } 523 524 static int mtl_max_source_rate(struct intel_dp *intel_dp) 525 { 526 struct intel_display *display = to_intel_display(intel_dp); 527 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 528 529 if (intel_encoder_is_c10phy(encoder)) 530 return 810000; 531 532 if (DISPLAY_VERx100(display) == 1401) 533 return 1350000; 534 535 return 2000000; 536 } 537 538 static int vbt_max_link_rate(struct intel_dp *intel_dp) 539 { 540 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 541 int max_rate; 542 543 max_rate = intel_bios_dp_max_link_rate(encoder->devdata); 544 545 if (intel_dp_is_edp(intel_dp)) { 546 struct intel_connector *connector = intel_dp->attached_connector; 547 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; 548 549 if (max_rate && edp_max_rate) 550 max_rate = min(max_rate, edp_max_rate); 551 else if (edp_max_rate) 552 max_rate = edp_max_rate; 553 } 554 555 return max_rate; 556 } 557 558 static void 559 intel_dp_set_source_rates(struct intel_dp *intel_dp) 560 { 561 /* The values must be in increasing order */ 562 static const int bmg_rates[] = { 563 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 564 810000, 1000000, 1350000, 565 }; 566 static const int mtl_rates[] = { 567 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 568 810000, 1000000, 2000000, 569 }; 570 static const int icl_rates[] = { 571 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000, 572 1000000, 1350000, 573 }; 574 static const int bxt_rates[] = { 575 162000, 216000, 243000, 270000, 324000, 432000, 540000 576 }; 577 static const int skl_rates[] = { 578 162000, 216000, 270000, 324000, 432000, 540000 579 }; 580 static const int hsw_rates[] = { 581 162000, 270000, 540000 582 }; 583 static const int g4x_rates[] = { 584 162000, 270000 585 }; 586 struct intel_display *display = to_intel_display(intel_dp); 587 const int *source_rates; 588 int size, max_rate = 0, vbt_max_rate; 589 590 /* This should only be done once */ 591 drm_WARN_ON(display->drm, 592 intel_dp->source_rates || intel_dp->num_source_rates); 593 594 if (DISPLAY_VER(display) >= 14) { 595 if (display->platform.battlemage) { 596 source_rates = bmg_rates; 597 size = ARRAY_SIZE(bmg_rates); 598 } else { 599 source_rates = mtl_rates; 600 size = ARRAY_SIZE(mtl_rates); 601 } 602 max_rate = mtl_max_source_rate(intel_dp); 603 } else if (DISPLAY_VER(display) >= 11) { 604 source_rates = icl_rates; 605 size = ARRAY_SIZE(icl_rates); 606 if (display->platform.dg2) 607 max_rate = dg2_max_source_rate(intel_dp); 608 else if (display->platform.alderlake_p || display->platform.alderlake_s || 609 display->platform.dg1 || display->platform.rocketlake) 610 max_rate = 810000; 611 else if (display->platform.jasperlake || display->platform.elkhartlake) 612 max_rate = ehl_max_source_rate(intel_dp); 613 else 614 max_rate = icl_max_source_rate(intel_dp); 615 } else if (display->platform.geminilake || display->platform.broxton) { 616 source_rates = bxt_rates; 617 size = ARRAY_SIZE(bxt_rates); 618 } else if (DISPLAY_VER(display) == 9) { 619 source_rates = skl_rates; 620 size = ARRAY_SIZE(skl_rates); 621 } else if ((display->platform.haswell && !display->platform.haswell_ulx) || 622 display->platform.broadwell) { 623 source_rates = hsw_rates; 624 size = ARRAY_SIZE(hsw_rates); 625 } else { 626 source_rates = g4x_rates; 627 size = ARRAY_SIZE(g4x_rates); 628 } 629 630 vbt_max_rate = vbt_max_link_rate(intel_dp); 631 if (max_rate && vbt_max_rate) 632 max_rate = min(max_rate, vbt_max_rate); 633 else if (vbt_max_rate) 634 max_rate = vbt_max_rate; 635 636 if (max_rate) 637 size = intel_dp_rate_limit_len(source_rates, size, max_rate); 638 639 intel_dp->source_rates = source_rates; 640 intel_dp->num_source_rates = size; 641 } 642 643 static int intersect_rates(const int *source_rates, int source_len, 644 const int *sink_rates, int sink_len, 645 int *common_rates) 646 { 647 int i = 0, j = 0, k = 0; 648 649 while (i < source_len && j < sink_len) { 650 if (source_rates[i] == sink_rates[j]) { 651 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 652 return k; 653 common_rates[k] = source_rates[i]; 654 ++k; 655 ++i; 656 ++j; 657 } else if (source_rates[i] < sink_rates[j]) { 658 ++i; 659 } else { 660 ++j; 661 } 662 } 663 return k; 664 } 665 666 /* return index of rate in rates array, or -1 if not found */ 667 int intel_dp_rate_index(const int *rates, int len, int rate) 668 { 669 int i; 670 671 for (i = 0; i < len; i++) 672 if (rate == rates[i]) 673 return i; 674 675 return -1; 676 } 677 678 static int intel_dp_link_config_rate(struct intel_dp *intel_dp, 679 const struct intel_dp_link_config *lc) 680 { 681 return intel_dp_common_rate(intel_dp, lc->link_rate_idx); 682 } 683 684 static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc) 685 { 686 return 1 << lc->lane_count_exp; 687 } 688 689 static int intel_dp_link_config_bw(struct intel_dp *intel_dp, 690 const struct intel_dp_link_config *lc) 691 { 692 return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc), 693 intel_dp_link_config_lane_count(lc)); 694 } 695 696 static int link_config_cmp_by_bw(const void *a, const void *b, const void *p) 697 { 698 struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */ 699 const struct intel_dp_link_config *lc_a = a; 700 const struct intel_dp_link_config *lc_b = b; 701 int bw_a = intel_dp_link_config_bw(intel_dp, lc_a); 702 int bw_b = intel_dp_link_config_bw(intel_dp, lc_b); 703 704 if (bw_a != bw_b) 705 return bw_a - bw_b; 706 707 return intel_dp_link_config_rate(intel_dp, lc_a) - 708 intel_dp_link_config_rate(intel_dp, lc_b); 709 } 710 711 static void intel_dp_link_config_init(struct intel_dp *intel_dp) 712 { 713 struct intel_display *display = to_intel_display(intel_dp); 714 struct intel_dp_link_config *lc; 715 int num_common_lane_configs; 716 int i; 717 int j; 718 719 if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp)))) 720 return; 721 722 num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1; 723 724 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs > 725 ARRAY_SIZE(intel_dp->link.configs))) 726 return; 727 728 intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs; 729 730 lc = &intel_dp->link.configs[0]; 731 for (i = 0; i < intel_dp->num_common_rates; i++) { 732 for (j = 0; j < num_common_lane_configs; j++) { 733 lc->lane_count_exp = j; 734 lc->link_rate_idx = i; 735 736 lc++; 737 } 738 } 739 740 sort_r(intel_dp->link.configs, intel_dp->link.num_configs, 741 sizeof(intel_dp->link.configs[0]), 742 link_config_cmp_by_bw, NULL, 743 intel_dp); 744 } 745 746 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) 747 { 748 struct intel_display *display = to_intel_display(intel_dp); 749 const struct intel_dp_link_config *lc; 750 751 if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs)) 752 idx = 0; 753 754 lc = &intel_dp->link.configs[idx]; 755 756 *link_rate = intel_dp_link_config_rate(intel_dp, lc); 757 *lane_count = intel_dp_link_config_lane_count(lc); 758 } 759 760 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) 761 { 762 int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, 763 link_rate); 764 int lane_count_exp = ilog2(lane_count); 765 int i; 766 767 for (i = 0; i < intel_dp->link.num_configs; i++) { 768 const struct intel_dp_link_config *lc = &intel_dp->link.configs[i]; 769 770 if (lc->lane_count_exp == lane_count_exp && 771 lc->link_rate_idx == link_rate_idx) 772 return i; 773 } 774 775 return -1; 776 } 777 778 static void intel_dp_set_common_rates(struct intel_dp *intel_dp) 779 { 780 struct intel_display *display = to_intel_display(intel_dp); 781 782 drm_WARN_ON(display->drm, 783 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); 784 785 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, 786 intel_dp->num_source_rates, 787 intel_dp->sink_rates, 788 intel_dp->num_sink_rates, 789 intel_dp->common_rates); 790 791 /* Paranoia, there should always be something in common. */ 792 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) { 793 intel_dp->common_rates[0] = 162000; 794 intel_dp->num_common_rates = 1; 795 } 796 797 intel_dp_link_config_init(intel_dp); 798 } 799 800 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 801 u8 lane_count) 802 { 803 /* 804 * FIXME: we need to synchronize the current link parameters with 805 * hardware readout. Currently fast link training doesn't work on 806 * boot-up. 807 */ 808 if (link_rate == 0 || 809 link_rate > intel_dp->link.max_rate) 810 return false; 811 812 if (lane_count == 0 || 813 lane_count > intel_dp_max_lane_count(intel_dp)) 814 return false; 815 816 return true; 817 } 818 819 u32 intel_dp_mode_to_fec_clock(u32 mode_clock) 820 { 821 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), 822 1000000U); 823 } 824 825 int intel_dp_bw_fec_overhead(bool fec_enabled) 826 { 827 /* 828 * TODO: Calculate the actual overhead for a given mode. 829 * The hard-coded 1/0.972261=2.853% overhead factor 830 * corresponds (for instance) to the 8b/10b DP FEC 2.4% + 831 * 0.453% DSC overhead. This is enough for a 3840 width mode, 832 * which has a DSC overhead of up to ~0.2%, but may not be 833 * enough for a 1024 width mode where this is ~0.8% (on a 4 834 * lane DP link, with 2 DSC slices and 8 bpp color depth). 835 */ 836 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000; 837 } 838 839 static int 840 small_joiner_ram_size_bits(struct intel_display *display) 841 { 842 if (DISPLAY_VER(display) >= 13) 843 return 17280 * 8; 844 else if (DISPLAY_VER(display) >= 11) 845 return 7680 * 8; 846 else 847 return 6144 * 8; 848 } 849 850 u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) 851 { 852 u32 bits_per_pixel = bpp; 853 int i; 854 855 /* Error out if the max bpp is less than smallest allowed valid bpp */ 856 if (bits_per_pixel < valid_dsc_bpp[0]) { 857 drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n", 858 bits_per_pixel, valid_dsc_bpp[0]); 859 return 0; 860 } 861 862 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ 863 if (DISPLAY_VER(display) >= 13) { 864 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); 865 866 /* 867 * According to BSpec, 27 is the max DSC output bpp, 868 * 8 is the min DSC output bpp. 869 * While we can still clamp higher bpp values to 27, saving bandwidth, 870 * if it is required to oompress up to bpp < 8, means we can't do 871 * that and probably means we can't fit the required mode, even with 872 * DSC enabled. 873 */ 874 if (bits_per_pixel < 8) { 875 drm_dbg_kms(display->drm, 876 "Unsupported BPP %u, min 8\n", 877 bits_per_pixel); 878 return 0; 879 } 880 bits_per_pixel = min_t(u32, bits_per_pixel, 27); 881 } else { 882 /* Find the nearest match in the array of known BPPs from VESA */ 883 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { 884 if (bits_per_pixel < valid_dsc_bpp[i + 1]) 885 break; 886 } 887 drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n", 888 bits_per_pixel, valid_dsc_bpp[i]); 889 890 bits_per_pixel = valid_dsc_bpp[i]; 891 } 892 893 return bits_per_pixel; 894 } 895 896 static int bigjoiner_interface_bits(struct intel_display *display) 897 { 898 return DISPLAY_VER(display) >= 14 ? 36 : 24; 899 } 900 901 static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock, 902 int num_joined_pipes) 903 { 904 u32 max_bpp; 905 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ 906 int ppc = 2; 907 int num_big_joiners = num_joined_pipes / 2; 908 909 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) / 910 intel_dp_mode_to_fec_clock(mode_clock); 911 912 max_bpp *= num_big_joiners; 913 914 return max_bpp; 915 916 } 917 918 static u32 small_joiner_ram_max_bpp(struct intel_display *display, 919 u32 mode_hdisplay, 920 int num_joined_pipes) 921 { 922 u32 max_bpp; 923 924 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ 925 max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay; 926 927 max_bpp *= num_joined_pipes; 928 929 return max_bpp; 930 } 931 932 static int ultrajoiner_ram_bits(void) 933 { 934 return 4 * 72 * 512; 935 } 936 937 static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay) 938 { 939 return ultrajoiner_ram_bits() / mode_hdisplay; 940 } 941 942 static 943 u32 get_max_compressed_bpp_with_joiner(struct intel_display *display, 944 u32 mode_clock, u32 mode_hdisplay, 945 int num_joined_pipes) 946 { 947 u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes); 948 949 if (num_joined_pipes > 1) 950 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock, 951 num_joined_pipes)); 952 if (num_joined_pipes == 4) 953 max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay)); 954 955 return max_bpp; 956 } 957 958 u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display, 959 u32 link_clock, u32 lane_count, 960 u32 mode_clock, u32 mode_hdisplay, 961 int num_joined_pipes, 962 enum intel_output_format output_format, 963 u32 pipe_bpp, 964 u32 timeslots) 965 { 966 u32 bits_per_pixel, joiner_max_bpp; 967 968 /* 969 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* 970 * (LinkSymbolClock)* 8 * (TimeSlots / 64) 971 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) 972 * for MST -> TimeSlots has to be calculated, based on mode requirements 973 * 974 * Due to FEC overhead, the available bw is reduced to 97.2261%. 975 * To support the given mode: 976 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead 977 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead 978 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock 979 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) / 980 * (ModeClock / FEC Overhead) 981 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) / 982 * (ModeClock / FEC Overhead * 8) 983 */ 984 bits_per_pixel = ((link_clock * lane_count) * timeslots) / 985 (intel_dp_mode_to_fec_clock(mode_clock) * 8); 986 987 /* Bandwidth required for 420 is half, that of 444 format */ 988 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 989 bits_per_pixel *= 2; 990 991 /* 992 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum 993 * supported PPS value can be 63.9375 and with the further 994 * mention that for 420, 422 formats, bpp should be programmed double 995 * the target bpp restricting our target bpp to be 31.9375 at max. 996 */ 997 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 998 bits_per_pixel = min_t(u32, bits_per_pixel, 31); 999 1000 drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots " 1001 "total bw %u pixel clock %u\n", 1002 bits_per_pixel, timeslots, 1003 (link_clock * lane_count * 8), 1004 intel_dp_mode_to_fec_clock(mode_clock)); 1005 1006 joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock, 1007 mode_hdisplay, num_joined_pipes); 1008 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); 1009 1010 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp); 1011 1012 return bits_per_pixel; 1013 } 1014 1015 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 1016 int mode_clock, int mode_hdisplay, 1017 int num_joined_pipes) 1018 { 1019 struct intel_display *display = to_intel_display(connector); 1020 u8 min_slice_count, i; 1021 int max_slice_width; 1022 1023 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) 1024 min_slice_count = DIV_ROUND_UP(mode_clock, 1025 DP_DSC_MAX_ENC_THROUGHPUT_0); 1026 else 1027 min_slice_count = DIV_ROUND_UP(mode_clock, 1028 DP_DSC_MAX_ENC_THROUGHPUT_1); 1029 1030 /* 1031 * Due to some DSC engine BW limitations, we need to enable second 1032 * slice and VDSC engine, whenever we approach close enough to max CDCLK 1033 */ 1034 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100)) 1035 min_slice_count = max_t(u8, min_slice_count, 2); 1036 1037 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); 1038 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { 1039 drm_dbg_kms(display->drm, 1040 "Unsupported slice width %d by DP DSC Sink device\n", 1041 max_slice_width); 1042 return 0; 1043 } 1044 /* Also take into account max slice width */ 1045 min_slice_count = max_t(u8, min_slice_count, 1046 DIV_ROUND_UP(mode_hdisplay, 1047 max_slice_width)); 1048 1049 /* Find the closest match to the valid slice count values */ 1050 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { 1051 u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes; 1052 1053 /* 1054 * 3 DSC Slices per pipe need 3 DSC engines, which is supported only 1055 * with Ultrajoiner only for some platforms. 1056 */ 1057 if (valid_dsc_slicecount[i] == 3 && 1058 (!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4)) 1059 continue; 1060 1061 if (test_slice_count > 1062 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) 1063 break; 1064 1065 /* 1066 * Bigjoiner needs small joiner to be enabled. 1067 * So there should be at least 2 dsc slices per pipe, 1068 * whenever bigjoiner is enabled. 1069 */ 1070 if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2) 1071 continue; 1072 1073 if (mode_hdisplay % test_slice_count) 1074 continue; 1075 1076 if (min_slice_count <= test_slice_count) 1077 return test_slice_count; 1078 } 1079 1080 drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n", 1081 min_slice_count); 1082 return 0; 1083 } 1084 1085 static bool source_can_output(struct intel_dp *intel_dp, 1086 enum intel_output_format format) 1087 { 1088 struct intel_display *display = to_intel_display(intel_dp); 1089 1090 switch (format) { 1091 case INTEL_OUTPUT_FORMAT_RGB: 1092 return true; 1093 1094 case INTEL_OUTPUT_FORMAT_YCBCR444: 1095 /* 1096 * No YCbCr output support on gmch platforms. 1097 * Also, ILK doesn't seem capable of DP YCbCr output. 1098 * The displayed image is severely corrupted. SNB+ is fine. 1099 */ 1100 return !HAS_GMCH(display) && !display->platform.ironlake; 1101 1102 case INTEL_OUTPUT_FORMAT_YCBCR420: 1103 /* Platform < Gen 11 cannot output YCbCr420 format */ 1104 return DISPLAY_VER(display) >= 11; 1105 1106 default: 1107 MISSING_CASE(format); 1108 return false; 1109 } 1110 } 1111 1112 static bool 1113 dfp_can_convert_from_rgb(struct intel_dp *intel_dp, 1114 enum intel_output_format sink_format) 1115 { 1116 if (!drm_dp_is_branch(intel_dp->dpcd)) 1117 return false; 1118 1119 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1120 return intel_dp->dfp.rgb_to_ycbcr; 1121 1122 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1123 return intel_dp->dfp.rgb_to_ycbcr && 1124 intel_dp->dfp.ycbcr_444_to_420; 1125 1126 return false; 1127 } 1128 1129 static bool 1130 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, 1131 enum intel_output_format sink_format) 1132 { 1133 if (!drm_dp_is_branch(intel_dp->dpcd)) 1134 return false; 1135 1136 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1137 return intel_dp->dfp.ycbcr_444_to_420; 1138 1139 return false; 1140 } 1141 1142 static bool 1143 dfp_can_convert(struct intel_dp *intel_dp, 1144 enum intel_output_format output_format, 1145 enum intel_output_format sink_format) 1146 { 1147 switch (output_format) { 1148 case INTEL_OUTPUT_FORMAT_RGB: 1149 return dfp_can_convert_from_rgb(intel_dp, sink_format); 1150 case INTEL_OUTPUT_FORMAT_YCBCR444: 1151 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format); 1152 default: 1153 MISSING_CASE(output_format); 1154 return false; 1155 } 1156 1157 return false; 1158 } 1159 1160 static enum intel_output_format 1161 intel_dp_output_format(struct intel_connector *connector, 1162 enum intel_output_format sink_format) 1163 { 1164 struct intel_display *display = to_intel_display(connector); 1165 struct intel_dp *intel_dp = intel_attached_dp(connector); 1166 enum intel_output_format force_dsc_output_format = 1167 intel_dp->force_dsc_output_format; 1168 enum intel_output_format output_format; 1169 if (force_dsc_output_format) { 1170 if (source_can_output(intel_dp, force_dsc_output_format) && 1171 (!drm_dp_is_branch(intel_dp->dpcd) || 1172 sink_format != force_dsc_output_format || 1173 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format))) 1174 return force_dsc_output_format; 1175 1176 drm_dbg_kms(display->drm, "Cannot force DSC output format\n"); 1177 } 1178 1179 if (sink_format == INTEL_OUTPUT_FORMAT_RGB || 1180 dfp_can_convert_from_rgb(intel_dp, sink_format)) 1181 output_format = INTEL_OUTPUT_FORMAT_RGB; 1182 1183 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 1184 dfp_can_convert_from_ycbcr444(intel_dp, sink_format)) 1185 output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 1186 1187 else 1188 output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1189 1190 drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format)); 1191 1192 return output_format; 1193 } 1194 1195 int intel_dp_min_bpp(enum intel_output_format output_format) 1196 { 1197 if (output_format == INTEL_OUTPUT_FORMAT_RGB) 1198 return 6 * 3; 1199 else 1200 return 8 * 3; 1201 } 1202 1203 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) 1204 { 1205 /* 1206 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output 1207 * format of the number of bytes per pixel will be half the number 1208 * of bytes of RGB pixel. 1209 */ 1210 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1211 bpp /= 2; 1212 1213 return bpp; 1214 } 1215 1216 static enum intel_output_format 1217 intel_dp_sink_format(struct intel_connector *connector, 1218 const struct drm_display_mode *mode) 1219 { 1220 const struct drm_display_info *info = &connector->base.display_info; 1221 1222 if (drm_mode_is_420_only(info, mode)) 1223 return INTEL_OUTPUT_FORMAT_YCBCR420; 1224 1225 return INTEL_OUTPUT_FORMAT_RGB; 1226 } 1227 1228 static int 1229 intel_dp_mode_min_output_bpp(struct intel_connector *connector, 1230 const struct drm_display_mode *mode) 1231 { 1232 enum intel_output_format output_format, sink_format; 1233 1234 sink_format = intel_dp_sink_format(connector, mode); 1235 1236 output_format = intel_dp_output_format(connector, sink_format); 1237 1238 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); 1239 } 1240 1241 static bool intel_dp_hdisplay_bad(struct intel_display *display, 1242 int hdisplay) 1243 { 1244 /* 1245 * Older platforms don't like hdisplay==4096 with DP. 1246 * 1247 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline 1248 * and frame counter increment), but we don't get vblank interrupts, 1249 * and the pipe underruns immediately. The link also doesn't seem 1250 * to get trained properly. 1251 * 1252 * On CHV the vblank interrupts don't seem to disappear but 1253 * otherwise the symptoms are similar. 1254 * 1255 * TODO: confirm the behaviour on HSW+ 1256 */ 1257 return hdisplay == 4096 && !HAS_DDI(display); 1258 } 1259 1260 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp) 1261 { 1262 struct intel_connector *connector = intel_dp->attached_connector; 1263 const struct drm_display_info *info = &connector->base.display_info; 1264 int max_tmds_clock = intel_dp->dfp.max_tmds_clock; 1265 1266 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */ 1267 if (max_tmds_clock && info->max_tmds_clock) 1268 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); 1269 1270 return max_tmds_clock; 1271 } 1272 1273 static enum drm_mode_status 1274 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, 1275 int clock, int bpc, 1276 enum intel_output_format sink_format, 1277 bool respect_downstream_limits) 1278 { 1279 int tmds_clock, min_tmds_clock, max_tmds_clock; 1280 1281 if (!respect_downstream_limits) 1282 return MODE_OK; 1283 1284 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1285 1286 min_tmds_clock = intel_dp->dfp.min_tmds_clock; 1287 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp); 1288 1289 if (min_tmds_clock && tmds_clock < min_tmds_clock) 1290 return MODE_CLOCK_LOW; 1291 1292 if (max_tmds_clock && tmds_clock > max_tmds_clock) 1293 return MODE_CLOCK_HIGH; 1294 1295 return MODE_OK; 1296 } 1297 1298 static enum drm_mode_status 1299 intel_dp_mode_valid_downstream(struct intel_connector *connector, 1300 const struct drm_display_mode *mode, 1301 int target_clock) 1302 { 1303 struct intel_dp *intel_dp = intel_attached_dp(connector); 1304 const struct drm_display_info *info = &connector->base.display_info; 1305 enum drm_mode_status status; 1306 enum intel_output_format sink_format; 1307 1308 /* If PCON supports FRL MODE, check FRL bandwidth constraints */ 1309 if (intel_dp->dfp.pcon_max_frl_bw) { 1310 int target_bw; 1311 int max_frl_bw; 1312 int bpp = intel_dp_mode_min_output_bpp(connector, mode); 1313 1314 target_bw = bpp * target_clock; 1315 1316 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 1317 1318 /* converting bw from Gbps to Kbps*/ 1319 max_frl_bw = max_frl_bw * 1000000; 1320 1321 if (target_bw > max_frl_bw) 1322 return MODE_CLOCK_HIGH; 1323 1324 return MODE_OK; 1325 } 1326 1327 if (intel_dp->dfp.max_dotclock && 1328 target_clock > intel_dp->dfp.max_dotclock) 1329 return MODE_CLOCK_HIGH; 1330 1331 sink_format = intel_dp_sink_format(connector, mode); 1332 1333 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ 1334 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1335 8, sink_format, true); 1336 1337 if (status != MODE_OK) { 1338 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 1339 !connector->base.ycbcr_420_allowed || 1340 !drm_mode_is_420_also(info, mode)) 1341 return status; 1342 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1343 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1344 8, sink_format, true); 1345 if (status != MODE_OK) 1346 return status; 1347 } 1348 1349 return MODE_OK; 1350 } 1351 1352 static 1353 bool intel_dp_needs_joiner(struct intel_dp *intel_dp, 1354 struct intel_connector *connector, 1355 int hdisplay, int clock, 1356 int num_joined_pipes) 1357 { 1358 struct intel_display *display = to_intel_display(intel_dp); 1359 int hdisplay_limit; 1360 1361 if (!intel_dp_has_joiner(intel_dp)) 1362 return false; 1363 1364 num_joined_pipes /= 2; 1365 1366 hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120; 1367 1368 return clock > num_joined_pipes * display->cdclk.max_dotclk_freq || 1369 hdisplay > num_joined_pipes * hdisplay_limit; 1370 } 1371 1372 int intel_dp_num_joined_pipes(struct intel_dp *intel_dp, 1373 struct intel_connector *connector, 1374 int hdisplay, int clock) 1375 { 1376 struct intel_display *display = to_intel_display(intel_dp); 1377 1378 if (connector->force_joined_pipes) 1379 return connector->force_joined_pipes; 1380 1381 if (HAS_ULTRAJOINER(display) && 1382 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4)) 1383 return 4; 1384 1385 if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) && 1386 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2)) 1387 return 2; 1388 1389 return 1; 1390 } 1391 1392 bool intel_dp_has_dsc(const struct intel_connector *connector) 1393 { 1394 struct intel_display *display = to_intel_display(connector); 1395 1396 if (!HAS_DSC(display)) 1397 return false; 1398 1399 if (connector->mst.dp && !HAS_DSC_MST(display)) 1400 return false; 1401 1402 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && 1403 connector->panel.vbt.edp.dsc_disable) 1404 return false; 1405 1406 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) 1407 return false; 1408 1409 return true; 1410 } 1411 1412 static enum drm_mode_status 1413 intel_dp_mode_valid(struct drm_connector *_connector, 1414 const struct drm_display_mode *mode) 1415 { 1416 struct intel_display *display = to_intel_display(_connector->dev); 1417 struct intel_connector *connector = to_intel_connector(_connector); 1418 struct intel_dp *intel_dp = intel_attached_dp(connector); 1419 const struct drm_display_mode *fixed_mode; 1420 int target_clock = mode->clock; 1421 int max_rate, mode_rate, max_lanes, max_link_clock; 1422 int max_dotclk = display->cdclk.max_dotclk_freq; 1423 u16 dsc_max_compressed_bpp = 0; 1424 u8 dsc_slice_count = 0; 1425 enum drm_mode_status status; 1426 bool dsc = false; 1427 int num_joined_pipes; 1428 1429 status = intel_cpu_transcoder_mode_valid(display, mode); 1430 if (status != MODE_OK) 1431 return status; 1432 1433 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1434 return MODE_H_ILLEGAL; 1435 1436 if (mode->clock < 10000) 1437 return MODE_CLOCK_LOW; 1438 1439 fixed_mode = intel_panel_fixed_mode(connector, mode); 1440 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 1441 status = intel_panel_mode_valid(connector, mode); 1442 if (status != MODE_OK) 1443 return status; 1444 1445 target_clock = fixed_mode->clock; 1446 } 1447 1448 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, 1449 mode->hdisplay, target_clock); 1450 max_dotclk *= num_joined_pipes; 1451 1452 if (target_clock > max_dotclk) 1453 return MODE_CLOCK_HIGH; 1454 1455 if (intel_dp_hdisplay_bad(display, mode->hdisplay)) 1456 return MODE_H_ILLEGAL; 1457 1458 max_link_clock = intel_dp_max_link_rate(intel_dp); 1459 max_lanes = intel_dp_max_lane_count(intel_dp); 1460 1461 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); 1462 1463 mode_rate = intel_dp_link_required(target_clock, 1464 intel_dp_mode_min_output_bpp(connector, mode)); 1465 1466 if (intel_dp_has_dsc(connector)) { 1467 enum intel_output_format sink_format, output_format; 1468 int pipe_bpp; 1469 1470 sink_format = intel_dp_sink_format(connector, mode); 1471 output_format = intel_dp_output_format(connector, sink_format); 1472 /* 1473 * TBD pass the connector BPC, 1474 * for now U8_MAX so that max BPC on that platform would be picked 1475 */ 1476 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); 1477 1478 /* 1479 * Output bpp is stored in 6.4 format so right shift by 4 to get the 1480 * integer value since we support only integer values of bpp. 1481 */ 1482 if (intel_dp_is_edp(intel_dp)) { 1483 dsc_max_compressed_bpp = 1484 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; 1485 dsc_slice_count = 1486 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 1487 true); 1488 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { 1489 dsc_max_compressed_bpp = 1490 intel_dp_dsc_get_max_compressed_bpp(display, 1491 max_link_clock, 1492 max_lanes, 1493 target_clock, 1494 mode->hdisplay, 1495 num_joined_pipes, 1496 output_format, 1497 pipe_bpp, 64); 1498 dsc_slice_count = 1499 intel_dp_dsc_get_slice_count(connector, 1500 target_clock, 1501 mode->hdisplay, 1502 num_joined_pipes); 1503 } 1504 1505 dsc = dsc_max_compressed_bpp && dsc_slice_count; 1506 } 1507 1508 if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) 1509 return MODE_CLOCK_HIGH; 1510 1511 if (mode_rate > max_rate && !dsc) 1512 return MODE_CLOCK_HIGH; 1513 1514 status = intel_dp_mode_valid_downstream(connector, mode, target_clock); 1515 if (status != MODE_OK) 1516 return status; 1517 1518 return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes); 1519 } 1520 1521 bool intel_dp_source_supports_tps3(struct intel_display *display) 1522 { 1523 return DISPLAY_VER(display) >= 9 || 1524 display->platform.broadwell || display->platform.haswell; 1525 } 1526 1527 bool intel_dp_source_supports_tps4(struct intel_display *display) 1528 { 1529 return DISPLAY_VER(display) >= 10; 1530 } 1531 1532 static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem) 1533 { 1534 int i; 1535 1536 for (i = 0; i < nelem; i++) 1537 seq_buf_printf(s, "%s%d", i ? ", " : "", array[i]); 1538 } 1539 1540 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1541 { 1542 struct intel_display *display = to_intel_display(intel_dp); 1543 DECLARE_SEQ_BUF(s, 128); /* FIXME: too big for stack? */ 1544 1545 if (!drm_debug_enabled(DRM_UT_KMS)) 1546 return; 1547 1548 seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates); 1549 drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s)); 1550 1551 seq_buf_clear(&s); 1552 seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates); 1553 drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s)); 1554 1555 seq_buf_clear(&s); 1556 seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates); 1557 drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s)); 1558 } 1559 1560 static int forced_link_rate(struct intel_dp *intel_dp) 1561 { 1562 int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate); 1563 1564 if (len == 0) 1565 return intel_dp_common_rate(intel_dp, 0); 1566 1567 return intel_dp_common_rate(intel_dp, len - 1); 1568 } 1569 1570 int 1571 intel_dp_max_link_rate(struct intel_dp *intel_dp) 1572 { 1573 int len; 1574 1575 if (intel_dp->link.force_rate) 1576 return forced_link_rate(intel_dp); 1577 1578 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate); 1579 1580 return intel_dp_common_rate(intel_dp, len - 1); 1581 } 1582 1583 static int 1584 intel_dp_min_link_rate(struct intel_dp *intel_dp) 1585 { 1586 if (intel_dp->link.force_rate) 1587 return forced_link_rate(intel_dp); 1588 1589 return intel_dp_common_rate(intel_dp, 0); 1590 } 1591 1592 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1593 { 1594 struct intel_display *display = to_intel_display(intel_dp); 1595 int i = intel_dp_rate_index(intel_dp->sink_rates, 1596 intel_dp->num_sink_rates, rate); 1597 1598 if (drm_WARN_ON(display->drm, i < 0)) 1599 i = 0; 1600 1601 return i; 1602 } 1603 1604 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1605 u8 *link_bw, u8 *rate_select) 1606 { 1607 struct intel_display *display = to_intel_display(intel_dp); 1608 1609 /* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */ 1610 if (display->platform.g4x && port_clock == 268800) 1611 port_clock = 270000; 1612 1613 /* eDP 1.4 rate select method. */ 1614 if (intel_dp->use_rate_select) { 1615 *link_bw = 0; 1616 *rate_select = 1617 intel_dp_rate_select(intel_dp, port_clock); 1618 } else { 1619 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1620 *rate_select = 0; 1621 } 1622 } 1623 1624 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp) 1625 { 1626 struct intel_connector *connector = intel_dp->attached_connector; 1627 1628 return connector->base.display_info.is_hdmi; 1629 } 1630 1631 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 1632 const struct intel_crtc_state *pipe_config) 1633 { 1634 struct intel_display *display = to_intel_display(intel_dp); 1635 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1636 1637 if (DISPLAY_VER(display) >= 12) 1638 return true; 1639 1640 if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A && 1641 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) 1642 return true; 1643 1644 return false; 1645 } 1646 1647 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 1648 const struct intel_connector *connector, 1649 const struct intel_crtc_state *pipe_config) 1650 { 1651 return intel_dp_source_supports_fec(intel_dp, pipe_config) && 1652 drm_dp_sink_supports_fec(connector->dp.fec_capability); 1653 } 1654 1655 bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 1656 const struct intel_connector *connector, 1657 const struct intel_crtc_state *crtc_state) 1658 { 1659 if (!intel_dp_has_dsc(connector)) 1660 return false; 1661 1662 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && 1663 !intel_dp_supports_fec(intel_dp, connector, crtc_state)) 1664 return false; 1665 1666 return intel_dsc_source_support(crtc_state); 1667 } 1668 1669 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, 1670 const struct intel_crtc_state *crtc_state, 1671 int bpc, bool respect_downstream_limits) 1672 { 1673 int clock = crtc_state->hw.adjusted_mode.crtc_clock; 1674 1675 /* 1676 * Current bpc could already be below 8bpc due to 1677 * FDI bandwidth constraints or other limits. 1678 * HDMI minimum is 8bpc however. 1679 */ 1680 bpc = max(bpc, 8); 1681 1682 /* 1683 * We will never exceed downstream TMDS clock limits while 1684 * attempting deep color. If the user insists on forcing an 1685 * out of spec mode they will have to be satisfied with 8bpc. 1686 */ 1687 if (!respect_downstream_limits) 1688 bpc = 8; 1689 1690 for (; bpc >= 8; bpc -= 2) { 1691 if (intel_hdmi_bpc_possible(crtc_state, bpc, 1692 intel_dp_has_hdmi_sink(intel_dp)) && 1693 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, 1694 respect_downstream_limits) == MODE_OK) 1695 return bpc; 1696 } 1697 1698 return -EINVAL; 1699 } 1700 1701 static int intel_dp_max_bpp(struct intel_dp *intel_dp, 1702 const struct intel_crtc_state *crtc_state, 1703 bool respect_downstream_limits) 1704 { 1705 struct intel_display *display = to_intel_display(intel_dp); 1706 struct intel_connector *connector = intel_dp->attached_connector; 1707 int bpp, bpc; 1708 1709 bpc = crtc_state->pipe_bpp / 3; 1710 1711 if (intel_dp->dfp.max_bpc) 1712 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); 1713 1714 if (intel_dp->dfp.min_tmds_clock) { 1715 int max_hdmi_bpc; 1716 1717 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc, 1718 respect_downstream_limits); 1719 if (max_hdmi_bpc < 0) 1720 return 0; 1721 1722 bpc = min(bpc, max_hdmi_bpc); 1723 } 1724 1725 bpp = bpc * 3; 1726 if (intel_dp_is_edp(intel_dp)) { 1727 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1728 if (connector->base.display_info.bpc == 0 && 1729 connector->panel.vbt.edp.bpp && 1730 connector->panel.vbt.edp.bpp < bpp) { 1731 drm_dbg_kms(display->drm, 1732 "clamping bpp for eDP panel to BIOS-provided %i\n", 1733 connector->panel.vbt.edp.bpp); 1734 bpp = connector->panel.vbt.edp.bpp; 1735 } 1736 } 1737 1738 return bpp; 1739 } 1740 1741 static bool has_seamless_m_n(struct intel_connector *connector) 1742 { 1743 struct intel_display *display = to_intel_display(connector); 1744 1745 /* 1746 * Seamless M/N reprogramming only implemented 1747 * for BDW+ double buffered M/N registers so far. 1748 */ 1749 return HAS_DOUBLE_BUFFERED_M_N(display) && 1750 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 1751 } 1752 1753 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state, 1754 const struct drm_connector_state *conn_state) 1755 { 1756 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1757 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1758 1759 /* FIXME a bit of a mess wrt clock vs. crtc_clock */ 1760 if (has_seamless_m_n(connector)) 1761 return intel_panel_highest_mode(connector, adjusted_mode)->clock; 1762 else 1763 return adjusted_mode->crtc_clock; 1764 } 1765 1766 /* Optimize link config in order: max bpp, min clock, min lanes */ 1767 static int 1768 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 1769 struct intel_crtc_state *pipe_config, 1770 const struct drm_connector_state *conn_state, 1771 const struct link_config_limits *limits) 1772 { 1773 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); 1774 int mode_rate, link_rate, link_avail; 1775 1776 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 1777 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); 1778 bpp -= 2 * 3) { 1779 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 1780 1781 mode_rate = intel_dp_link_required(clock, link_bpp); 1782 1783 for (i = 0; i < intel_dp->num_common_rates; i++) { 1784 link_rate = intel_dp_common_rate(intel_dp, i); 1785 if (link_rate < limits->min_rate || 1786 link_rate > limits->max_rate) 1787 continue; 1788 1789 for (lane_count = limits->min_lane_count; 1790 lane_count <= limits->max_lane_count; 1791 lane_count <<= 1) { 1792 link_avail = intel_dp_max_link_data_rate(intel_dp, 1793 link_rate, 1794 lane_count); 1795 1796 1797 if (mode_rate <= link_avail) { 1798 pipe_config->lane_count = lane_count; 1799 pipe_config->pipe_bpp = bpp; 1800 pipe_config->port_clock = link_rate; 1801 1802 return 0; 1803 } 1804 } 1805 } 1806 } 1807 1808 return -EINVAL; 1809 } 1810 1811 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display) 1812 { 1813 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 1814 if (DISPLAY_VER(display) >= 12) 1815 return 12; 1816 if (DISPLAY_VER(display) == 11) 1817 return 10; 1818 1819 return intel_dp_dsc_min_src_input_bpc(); 1820 } 1821 1822 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 1823 u8 max_req_bpc) 1824 { 1825 struct intel_display *display = to_intel_display(connector); 1826 int i, num_bpc; 1827 u8 dsc_bpc[3] = {}; 1828 int dsc_max_bpc; 1829 1830 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 1831 1832 if (!dsc_max_bpc) 1833 return dsc_max_bpc; 1834 1835 dsc_max_bpc = min(dsc_max_bpc, max_req_bpc); 1836 1837 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, 1838 dsc_bpc); 1839 for (i = 0; i < num_bpc; i++) { 1840 if (dsc_max_bpc >= dsc_bpc[i]) 1841 return dsc_bpc[i] * 3; 1842 } 1843 1844 return 0; 1845 } 1846 1847 static int intel_dp_source_dsc_version_minor(struct intel_display *display) 1848 { 1849 return DISPLAY_VER(display) >= 14 ? 2 : 1; 1850 } 1851 1852 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 1853 { 1854 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> 1855 DP_DSC_MINOR_SHIFT; 1856 } 1857 1858 static int intel_dp_get_slice_height(int vactive) 1859 { 1860 int slice_height; 1861 1862 /* 1863 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108 1864 * lines is an optimal slice height, but any size can be used as long as 1865 * vertical active integer multiple and maximum vertical slice count 1866 * requirements are met. 1867 */ 1868 for (slice_height = 108; slice_height <= vactive; slice_height += 2) 1869 if (vactive % slice_height == 0) 1870 return slice_height; 1871 1872 /* 1873 * Highly unlikely we reach here as most of the resolutions will end up 1874 * finding appropriate slice_height in above loop but returning 1875 * slice_height as 2 here as it should work with all resolutions. 1876 */ 1877 return 2; 1878 } 1879 1880 static int intel_dp_dsc_compute_params(const struct intel_connector *connector, 1881 struct intel_crtc_state *crtc_state) 1882 { 1883 struct intel_display *display = to_intel_display(connector); 1884 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1885 int ret; 1886 1887 /* 1888 * RC_MODEL_SIZE is currently a constant across all configurations. 1889 * 1890 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and 1891 * DP_DSC_RC_BUF_SIZE for this. 1892 */ 1893 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1894 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1895 1896 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); 1897 1898 ret = intel_dsc_compute_params(crtc_state); 1899 if (ret) 1900 return ret; 1901 1902 vdsc_cfg->dsc_version_major = 1903 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 1904 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; 1905 vdsc_cfg->dsc_version_minor = 1906 min(intel_dp_source_dsc_version_minor(display), 1907 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)); 1908 if (vdsc_cfg->convert_rgb) 1909 vdsc_cfg->convert_rgb = 1910 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & 1911 DP_DSC_RGB; 1912 1913 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, 1914 drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd)); 1915 if (!vdsc_cfg->line_buf_depth) { 1916 drm_dbg_kms(display->drm, 1917 "DSC Sink Line Buffer Depth invalid\n"); 1918 return -EINVAL; 1919 } 1920 1921 vdsc_cfg->block_pred_enable = 1922 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & 1923 DP_DSC_BLK_PREDICTION_IS_SUPPORTED; 1924 1925 return drm_dsc_compute_rc_parameters(vdsc_cfg); 1926 } 1927 1928 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, 1929 enum intel_output_format output_format) 1930 { 1931 struct intel_display *display = to_intel_display(connector); 1932 u8 sink_dsc_format; 1933 1934 switch (output_format) { 1935 case INTEL_OUTPUT_FORMAT_RGB: 1936 sink_dsc_format = DP_DSC_RGB; 1937 break; 1938 case INTEL_OUTPUT_FORMAT_YCBCR444: 1939 sink_dsc_format = DP_DSC_YCbCr444; 1940 break; 1941 case INTEL_OUTPUT_FORMAT_YCBCR420: 1942 if (min(intel_dp_source_dsc_version_minor(display), 1943 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2) 1944 return false; 1945 sink_dsc_format = DP_DSC_YCbCr420_Native; 1946 break; 1947 default: 1948 return false; 1949 } 1950 1951 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); 1952 } 1953 1954 static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock, 1955 u32 lane_count, u32 mode_clock, 1956 enum intel_output_format output_format, 1957 int timeslots) 1958 { 1959 u32 available_bw, required_bw; 1960 1961 available_bw = (link_clock * lane_count * timeslots * 16) / 8; 1962 required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock)); 1963 1964 return available_bw > required_bw; 1965 } 1966 1967 static int dsc_compute_link_config(struct intel_dp *intel_dp, 1968 struct intel_crtc_state *pipe_config, 1969 struct drm_connector_state *conn_state, 1970 const struct link_config_limits *limits, 1971 int dsc_bpp_x16, 1972 int timeslots) 1973 { 1974 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1975 int link_rate, lane_count; 1976 int i; 1977 1978 for (i = 0; i < intel_dp->num_common_rates; i++) { 1979 link_rate = intel_dp_common_rate(intel_dp, i); 1980 if (link_rate < limits->min_rate || link_rate > limits->max_rate) 1981 continue; 1982 1983 for (lane_count = limits->min_lane_count; 1984 lane_count <= limits->max_lane_count; 1985 lane_count <<= 1) { 1986 1987 /* 1988 * FIXME: intel_dp_mtp_tu_compute_config() requires 1989 * ->lane_count and ->port_clock set before we know 1990 * they'll work. If we end up failing altogether, 1991 * they'll remain in crtc state. This shouldn't matter, 1992 * as we'd then bail out from compute config, but it's 1993 * just ugly. 1994 */ 1995 pipe_config->lane_count = lane_count; 1996 pipe_config->port_clock = link_rate; 1997 1998 if (drm_dp_is_uhbr_rate(link_rate)) { 1999 int ret; 2000 2001 ret = intel_dp_mtp_tu_compute_config(intel_dp, 2002 pipe_config, 2003 conn_state, 2004 dsc_bpp_x16, 2005 dsc_bpp_x16, 2006 0, true); 2007 if (ret) 2008 continue; 2009 } else { 2010 if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate, 2011 lane_count, adjusted_mode->clock, 2012 pipe_config->output_format, 2013 timeslots)) 2014 continue; 2015 } 2016 2017 return 0; 2018 } 2019 } 2020 2021 return -EINVAL; 2022 } 2023 2024 static 2025 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, 2026 const struct intel_crtc_state *pipe_config, 2027 int bpc) 2028 { 2029 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); 2030 2031 if (max_bppx16) 2032 return max_bppx16; 2033 /* 2034 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate 2035 * values as given in spec Table 2-157 DP v2.0 2036 */ 2037 switch (pipe_config->output_format) { 2038 case INTEL_OUTPUT_FORMAT_RGB: 2039 case INTEL_OUTPUT_FORMAT_YCBCR444: 2040 return (3 * bpc) << 4; 2041 case INTEL_OUTPUT_FORMAT_YCBCR420: 2042 return (3 * (bpc / 2)) << 4; 2043 default: 2044 MISSING_CASE(pipe_config->output_format); 2045 break; 2046 } 2047 2048 return 0; 2049 } 2050 2051 int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config) 2052 { 2053 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ 2054 switch (pipe_config->output_format) { 2055 case INTEL_OUTPUT_FORMAT_RGB: 2056 case INTEL_OUTPUT_FORMAT_YCBCR444: 2057 return 8; 2058 case INTEL_OUTPUT_FORMAT_YCBCR420: 2059 return 6; 2060 default: 2061 MISSING_CASE(pipe_config->output_format); 2062 break; 2063 } 2064 2065 return 0; 2066 } 2067 2068 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, 2069 const struct intel_crtc_state *pipe_config, 2070 int bpc) 2071 { 2072 return intel_dp_dsc_max_sink_compressed_bppx16(connector, 2073 pipe_config, bpc) >> 4; 2074 } 2075 2076 static int dsc_src_min_compressed_bpp(void) 2077 { 2078 /* Min Compressed bpp supported by source is 8 */ 2079 return 8; 2080 } 2081 2082 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) 2083 { 2084 struct intel_display *display = to_intel_display(intel_dp); 2085 2086 /* 2087 * Forcing DSC and using the platform's max compressed bpp is seen to cause 2088 * underruns. Since DSC isn't needed in these cases, limit the 2089 * max compressed bpp to 18, which is a safe value across platforms with different 2090 * pipe bpps. 2091 */ 2092 if (intel_dp->force_dsc_en) 2093 return 18; 2094 2095 /* 2096 * Max Compressed bpp for Gen 13+ is 27bpp. 2097 * For earlier platform is 23bpp. (Bspec:49259). 2098 */ 2099 if (DISPLAY_VER(display) < 13) 2100 return 23; 2101 else 2102 return 27; 2103 } 2104 2105 /* 2106 * Note: for pre-13 display you still need to check the validity of each step. 2107 */ 2108 static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) 2109 { 2110 struct intel_display *display = to_intel_display(connector); 2111 u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); 2112 2113 if (DISPLAY_VER(display) < 14 || !incr) 2114 return fxp_q4_from_int(1); 2115 2116 /* fxp q4 */ 2117 return fxp_q4_from_int(1) / incr; 2118 } 2119 2120 /* Note: This is not universally usable! */ 2121 static bool intel_dp_dsc_valid_bpp(struct intel_dp *intel_dp, int bpp_x16) 2122 { 2123 struct intel_display *display = to_intel_display(intel_dp); 2124 int i; 2125 2126 if (DISPLAY_VER(display) >= 13) { 2127 if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16)) 2128 return false; 2129 2130 return true; 2131 } 2132 2133 if (fxp_q4_to_frac(bpp_x16)) 2134 return false; 2135 2136 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { 2137 if (fxp_q4_to_int(bpp_x16) == valid_dsc_bpp[i]) 2138 return true; 2139 } 2140 2141 return false; 2142 } 2143 2144 /* 2145 * Find the max compressed BPP we can find a link configuration for. The BPPs to 2146 * try depend on the source (platform) and sink. 2147 */ 2148 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, 2149 struct intel_crtc_state *pipe_config, 2150 struct drm_connector_state *conn_state, 2151 const struct link_config_limits *limits, 2152 int pipe_bpp, 2153 int timeslots) 2154 { 2155 struct intel_display *display = to_intel_display(intel_dp); 2156 const struct intel_connector *connector = to_intel_connector(conn_state->connector); 2157 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2158 int output_bpp; 2159 int dsc_min_bpp; 2160 int dsc_max_bpp; 2161 int min_bpp_x16, max_bpp_x16, bpp_step_x16; 2162 int dsc_joiner_max_bpp; 2163 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2164 int bpp_x16; 2165 int ret; 2166 2167 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); 2168 2169 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock, 2170 adjusted_mode->hdisplay, 2171 num_joined_pipes); 2172 dsc_max_bpp = min(dsc_joiner_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16)); 2173 2174 /* FIXME: remove the round trip via integers */ 2175 min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); 2176 max_bpp_x16 = fxp_q4_from_int(dsc_max_bpp); 2177 2178 bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); 2179 2180 /* Compressed BPP should be less than the Input DSC bpp */ 2181 output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); 2182 max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16); 2183 2184 for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { 2185 if (!intel_dp_dsc_valid_bpp(intel_dp, bpp_x16)) 2186 continue; 2187 2188 ret = dsc_compute_link_config(intel_dp, 2189 pipe_config, 2190 conn_state, 2191 limits, 2192 bpp_x16, 2193 timeslots); 2194 if (ret == 0) { 2195 pipe_config->dsc.compressed_bpp_x16 = bpp_x16; 2196 if (intel_dp->force_dsc_fractional_bpp_en && 2197 fxp_q4_to_frac(bpp_x16)) 2198 drm_dbg_kms(display->drm, 2199 "Forcing DSC fractional bpp\n"); 2200 2201 return 0; 2202 } 2203 } 2204 2205 return -EINVAL; 2206 } 2207 2208 int intel_dp_dsc_min_src_input_bpc(void) 2209 { 2210 /* Min DSC Input BPC for ICL+ is 8 */ 2211 return 8; 2212 } 2213 2214 static 2215 bool is_dsc_pipe_bpp_sufficient(const struct link_config_limits *limits, 2216 int pipe_bpp) 2217 { 2218 return pipe_bpp >= limits->pipe.min_bpp && 2219 pipe_bpp <= limits->pipe.max_bpp; 2220 } 2221 2222 static 2223 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, 2224 const struct link_config_limits *limits) 2225 { 2226 struct intel_display *display = to_intel_display(intel_dp); 2227 int forced_bpp; 2228 2229 if (!intel_dp->force_dsc_bpc) 2230 return 0; 2231 2232 forced_bpp = intel_dp->force_dsc_bpc * 3; 2233 2234 if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) { 2235 drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n", 2236 intel_dp->force_dsc_bpc); 2237 return forced_bpp; 2238 } 2239 2240 drm_dbg_kms(display->drm, 2241 "Cannot force DSC BPC:%d, due to DSC BPC limits\n", 2242 intel_dp->force_dsc_bpc); 2243 2244 return 0; 2245 } 2246 2247 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2248 struct intel_crtc_state *pipe_config, 2249 struct drm_connector_state *conn_state, 2250 const struct link_config_limits *limits, 2251 int timeslots) 2252 { 2253 const struct intel_connector *connector = 2254 to_intel_connector(conn_state->connector); 2255 u8 dsc_bpc[3] = {}; 2256 int forced_bpp, pipe_bpp; 2257 int num_bpc, i, ret; 2258 2259 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); 2260 2261 if (forced_bpp) { 2262 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, 2263 limits, forced_bpp, timeslots); 2264 if (ret == 0) { 2265 pipe_config->pipe_bpp = forced_bpp; 2266 return 0; 2267 } 2268 } 2269 2270 /* 2271 * Get the maximum DSC bpc that will be supported by any valid 2272 * link configuration and compressed bpp. 2273 */ 2274 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); 2275 for (i = 0; i < num_bpc; i++) { 2276 pipe_bpp = dsc_bpc[i] * 3; 2277 if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp) 2278 continue; 2279 2280 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, 2281 limits, pipe_bpp, timeslots); 2282 if (ret == 0) { 2283 pipe_config->pipe_bpp = pipe_bpp; 2284 return 0; 2285 } 2286 } 2287 2288 return -EINVAL; 2289 } 2290 2291 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2292 struct intel_crtc_state *pipe_config, 2293 struct drm_connector_state *conn_state, 2294 const struct link_config_limits *limits) 2295 { 2296 struct intel_display *display = to_intel_display(intel_dp); 2297 struct intel_connector *connector = 2298 to_intel_connector(conn_state->connector); 2299 int pipe_bpp, forced_bpp; 2300 int dsc_min_bpp; 2301 int dsc_max_bpp; 2302 2303 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); 2304 2305 if (forced_bpp) { 2306 pipe_bpp = forced_bpp; 2307 } else { 2308 int max_bpc = limits->pipe.max_bpp / 3; 2309 2310 /* For eDP use max bpp that can be supported with DSC. */ 2311 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); 2312 if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) { 2313 drm_dbg_kms(display->drm, 2314 "Computed BPC is not in DSC BPC limits\n"); 2315 return -EINVAL; 2316 } 2317 } 2318 pipe_config->port_clock = limits->max_rate; 2319 pipe_config->lane_count = limits->max_lane_count; 2320 2321 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); 2322 2323 dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 2324 2325 /* Compressed BPP should be less than the Input DSC bpp */ 2326 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 2327 2328 pipe_config->dsc.compressed_bpp_x16 = 2329 fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp)); 2330 2331 pipe_config->pipe_bpp = pipe_bpp; 2332 2333 return 0; 2334 } 2335 2336 static void intel_dp_fec_compute_config(struct intel_dp *intel_dp, 2337 struct intel_crtc_state *crtc_state) 2338 { 2339 if (crtc_state->fec_enable) 2340 return; 2341 2342 /* 2343 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional. 2344 * Since, FEC is a bandwidth overhead, continue to not enable it for 2345 * eDP. Until, there is a good reason to do so. 2346 */ 2347 if (intel_dp_is_edp(intel_dp)) 2348 return; 2349 2350 if (intel_dp_is_uhbr(crtc_state)) 2351 return; 2352 2353 crtc_state->fec_enable = true; 2354 } 2355 2356 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 2357 struct intel_crtc_state *pipe_config, 2358 struct drm_connector_state *conn_state, 2359 const struct link_config_limits *limits, 2360 int timeslots) 2361 { 2362 struct intel_display *display = to_intel_display(intel_dp); 2363 const struct intel_connector *connector = 2364 to_intel_connector(conn_state->connector); 2365 const struct drm_display_mode *adjusted_mode = 2366 &pipe_config->hw.adjusted_mode; 2367 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2368 bool is_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST); 2369 int ret; 2370 2371 intel_dp_fec_compute_config(intel_dp, pipe_config); 2372 2373 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format)) 2374 return -EINVAL; 2375 2376 /* 2377 * Link parameters, pipe bpp and compressed bpp have already been 2378 * figured out for DP MST DSC. 2379 */ 2380 if (!is_mst) { 2381 if (intel_dp_is_edp(intel_dp)) 2382 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2383 conn_state, limits); 2384 else 2385 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2386 conn_state, limits, timeslots); 2387 if (ret) { 2388 drm_dbg_kms(display->drm, 2389 "No Valid pipe bpp for given mode ret = %d\n", ret); 2390 return ret; 2391 } 2392 } 2393 2394 /* Calculate Slice count */ 2395 if (intel_dp_is_edp(intel_dp)) { 2396 pipe_config->dsc.slice_count = 2397 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 2398 true); 2399 if (!pipe_config->dsc.slice_count) { 2400 drm_dbg_kms(display->drm, 2401 "Unsupported Slice Count %d\n", 2402 pipe_config->dsc.slice_count); 2403 return -EINVAL; 2404 } 2405 } else { 2406 u8 dsc_dp_slice_count; 2407 2408 dsc_dp_slice_count = 2409 intel_dp_dsc_get_slice_count(connector, 2410 adjusted_mode->crtc_clock, 2411 adjusted_mode->crtc_hdisplay, 2412 num_joined_pipes); 2413 if (!dsc_dp_slice_count) { 2414 drm_dbg_kms(display->drm, 2415 "Compressed Slice Count not supported\n"); 2416 return -EINVAL; 2417 } 2418 2419 pipe_config->dsc.slice_count = dsc_dp_slice_count; 2420 } 2421 /* 2422 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate 2423 * is greater than the maximum Cdclock and if slice count is even 2424 * then we need to use 2 VDSC instances. 2425 * In case of Ultrajoiner along with 12 slices we need to use 3 2426 * VDSC instances. 2427 */ 2428 if (pipe_config->joiner_pipes && num_joined_pipes == 4 && 2429 pipe_config->dsc.slice_count == 12) 2430 pipe_config->dsc.num_streams = 3; 2431 else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) 2432 pipe_config->dsc.num_streams = 2; 2433 else 2434 pipe_config->dsc.num_streams = 1; 2435 2436 ret = intel_dp_dsc_compute_params(connector, pipe_config); 2437 if (ret < 0) { 2438 drm_dbg_kms(display->drm, 2439 "Cannot compute valid DSC parameters for Input Bpp = %d" 2440 "Compressed BPP = " FXP_Q4_FMT "\n", 2441 pipe_config->pipe_bpp, 2442 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16)); 2443 return ret; 2444 } 2445 2446 pipe_config->dsc.compression_enable = true; 2447 drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d " 2448 "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n", 2449 pipe_config->pipe_bpp, 2450 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2451 pipe_config->dsc.slice_count); 2452 2453 return 0; 2454 } 2455 2456 /* 2457 * Calculate the output link min, max bpp values in limits based on the pipe bpp 2458 * range, crtc_state and dsc mode. Return true on success. 2459 */ 2460 static bool 2461 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, 2462 const struct intel_connector *connector, 2463 const struct intel_crtc_state *crtc_state, 2464 bool dsc, 2465 struct link_config_limits *limits) 2466 { 2467 struct intel_display *display = to_intel_display(intel_dp); 2468 const struct drm_display_mode *adjusted_mode = 2469 &crtc_state->hw.adjusted_mode; 2470 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2471 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2472 int max_link_bpp_x16; 2473 2474 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, 2475 fxp_q4_from_int(limits->pipe.max_bpp)); 2476 2477 if (!dsc) { 2478 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3)); 2479 2480 if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp)) 2481 return false; 2482 2483 limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp); 2484 } else { 2485 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; 2486 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; 2487 2488 dsc_src_min_bpp = dsc_src_min_compressed_bpp(); 2489 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state); 2490 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 2491 limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); 2492 2493 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2494 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, 2495 crtc_state, 2496 limits->pipe.max_bpp / 3); 2497 dsc_max_bpp = dsc_sink_max_bpp ? 2498 min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; 2499 2500 max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp)); 2501 } 2502 2503 limits->link.max_bpp_x16 = max_link_bpp_x16; 2504 2505 drm_dbg_kms(display->drm, 2506 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n", 2507 encoder->base.base.id, encoder->base.name, 2508 crtc->base.base.id, crtc->base.name, 2509 adjusted_mode->crtc_clock, 2510 str_on_off(dsc), 2511 limits->max_lane_count, 2512 limits->max_rate, 2513 limits->pipe.max_bpp, 2514 FXP_Q4_ARGS(limits->link.max_bpp_x16)); 2515 2516 return true; 2517 } 2518 2519 static void 2520 intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp, 2521 struct link_config_limits *limits) 2522 { 2523 struct intel_display *display = to_intel_display(intel_dp); 2524 int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(); 2525 int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 2526 2527 limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); 2528 limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); 2529 } 2530 2531 bool 2532 intel_dp_compute_config_limits(struct intel_dp *intel_dp, 2533 struct intel_connector *connector, 2534 struct intel_crtc_state *crtc_state, 2535 bool respect_downstream_limits, 2536 bool dsc, 2537 struct link_config_limits *limits) 2538 { 2539 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2540 2541 limits->min_rate = intel_dp_min_link_rate(intel_dp); 2542 limits->max_rate = intel_dp_max_link_rate(intel_dp); 2543 2544 limits->min_rate = min(limits->min_rate, limits->max_rate); 2545 2546 limits->min_lane_count = intel_dp_min_lane_count(intel_dp); 2547 limits->max_lane_count = intel_dp_max_lane_count(intel_dp); 2548 2549 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); 2550 if (is_mst) { 2551 /* 2552 * FIXME: If all the streams can't fit into the link with their 2553 * current pipe_bpp we should reduce pipe_bpp across the board 2554 * until things start to fit. Until then we limit to <= 8bpc 2555 * since that's what was hardcoded for all MST streams 2556 * previously. This hack should be removed once we have the 2557 * proper retry logic in place. 2558 */ 2559 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24); 2560 } else { 2561 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, 2562 respect_downstream_limits); 2563 } 2564 2565 if (dsc) 2566 intel_dp_dsc_compute_pipe_bpp_limits(intel_dp, limits); 2567 2568 if (is_mst || intel_dp->use_max_params) { 2569 /* 2570 * For MST we always configure max link bw - the spec doesn't 2571 * seem to suggest we should do otherwise. 2572 * 2573 * Use the maximum clock and number of lanes the eDP panel 2574 * advertizes being capable of in case the initial fast 2575 * optimal params failed us. The panels are generally 2576 * designed to support only a single clock and lane 2577 * configuration, and typically on older panels these 2578 * values correspond to the native resolution of the panel. 2579 */ 2580 limits->min_lane_count = limits->max_lane_count; 2581 limits->min_rate = limits->max_rate; 2582 } 2583 2584 intel_dp_test_compute_config(intel_dp, crtc_state, limits); 2585 2586 return intel_dp_compute_config_link_bpp_limits(intel_dp, 2587 connector, 2588 crtc_state, 2589 dsc, 2590 limits); 2591 } 2592 2593 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state) 2594 { 2595 const struct drm_display_mode *adjusted_mode = 2596 &crtc_state->hw.adjusted_mode; 2597 int bpp = crtc_state->dsc.compression_enable ? 2598 fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) : 2599 crtc_state->pipe_bpp; 2600 2601 return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); 2602 } 2603 2604 bool intel_dp_joiner_needs_dsc(struct intel_display *display, 2605 int num_joined_pipes) 2606 { 2607 /* 2608 * Pipe joiner needs compression up to display 12 due to bandwidth 2609 * limitation. DG2 onwards pipe joiner can be enabled without 2610 * compression. 2611 * Ultrajoiner always needs compression. 2612 */ 2613 return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) || 2614 num_joined_pipes == 4; 2615 } 2616 2617 static int 2618 intel_dp_compute_link_config(struct intel_encoder *encoder, 2619 struct intel_crtc_state *pipe_config, 2620 struct drm_connector_state *conn_state, 2621 bool respect_downstream_limits) 2622 { 2623 struct intel_display *display = to_intel_display(encoder); 2624 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2625 struct intel_connector *connector = 2626 to_intel_connector(conn_state->connector); 2627 const struct drm_display_mode *adjusted_mode = 2628 &pipe_config->hw.adjusted_mode; 2629 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2630 struct link_config_limits limits; 2631 bool dsc_needed, joiner_needs_dsc; 2632 int num_joined_pipes; 2633 int ret = 0; 2634 2635 if (pipe_config->fec_enable && 2636 !intel_dp_supports_fec(intel_dp, connector, pipe_config)) 2637 return -EINVAL; 2638 2639 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, 2640 adjusted_mode->crtc_hdisplay, 2641 adjusted_mode->crtc_clock); 2642 if (num_joined_pipes > 1) 2643 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe); 2644 2645 joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes); 2646 2647 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || 2648 !intel_dp_compute_config_limits(intel_dp, connector, pipe_config, 2649 respect_downstream_limits, 2650 false, 2651 &limits); 2652 2653 if (!dsc_needed) { 2654 /* 2655 * Optimize for slow and wide for everything, because there are some 2656 * eDP 1.3 and 1.4 panels don't work well with fast and narrow. 2657 */ 2658 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, 2659 conn_state, &limits); 2660 if (!ret && intel_dp_is_uhbr(pipe_config)) 2661 ret = intel_dp_mtp_tu_compute_config(intel_dp, 2662 pipe_config, 2663 conn_state, 2664 fxp_q4_from_int(pipe_config->pipe_bpp), 2665 fxp_q4_from_int(pipe_config->pipe_bpp), 2666 0, false); 2667 if (ret) 2668 dsc_needed = true; 2669 } 2670 2671 if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) { 2672 drm_dbg_kms(display->drm, "DSC required but not available\n"); 2673 return -EINVAL; 2674 } 2675 2676 if (dsc_needed) { 2677 drm_dbg_kms(display->drm, 2678 "Try DSC (fallback=%s, joiner=%s, force=%s)\n", 2679 str_yes_no(ret), str_yes_no(joiner_needs_dsc), 2680 str_yes_no(intel_dp->force_dsc_en)); 2681 2682 if (!intel_dp_compute_config_limits(intel_dp, connector, pipe_config, 2683 respect_downstream_limits, 2684 true, 2685 &limits)) 2686 return -EINVAL; 2687 2688 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 2689 conn_state, &limits, 64); 2690 if (ret < 0) 2691 return ret; 2692 } 2693 2694 drm_dbg_kms(display->drm, 2695 "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n", 2696 pipe_config->lane_count, pipe_config->port_clock, 2697 pipe_config->pipe_bpp, 2698 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2699 intel_dp_config_required_rate(pipe_config), 2700 intel_dp_max_link_data_rate(intel_dp, 2701 pipe_config->port_clock, 2702 pipe_config->lane_count)); 2703 2704 return 0; 2705 } 2706 2707 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 2708 const struct drm_connector_state *conn_state) 2709 { 2710 const struct intel_digital_connector_state *intel_conn_state = 2711 to_intel_digital_connector_state(conn_state); 2712 const struct drm_display_mode *adjusted_mode = 2713 &crtc_state->hw.adjusted_mode; 2714 2715 /* 2716 * Our YCbCr output is always limited range. 2717 * crtc_state->limited_color_range only applies to RGB, 2718 * and it must never be set for YCbCr or we risk setting 2719 * some conflicting bits in TRANSCONF which will mess up 2720 * the colors on the monitor. 2721 */ 2722 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2723 return false; 2724 2725 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2726 /* 2727 * See: 2728 * CEA-861-E - 5.1 Default Encoding Parameters 2729 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 2730 */ 2731 return crtc_state->pipe_bpp != 18 && 2732 drm_default_rgb_quant_range(adjusted_mode) == 2733 HDMI_QUANTIZATION_RANGE_LIMITED; 2734 } else { 2735 return intel_conn_state->broadcast_rgb == 2736 INTEL_BROADCAST_RGB_LIMITED; 2737 } 2738 } 2739 2740 static bool intel_dp_port_has_audio(struct intel_display *display, enum port port) 2741 { 2742 if (display->platform.g4x) 2743 return false; 2744 if (DISPLAY_VER(display) < 12 && port == PORT_A) 2745 return false; 2746 2747 return true; 2748 } 2749 2750 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, 2751 const struct drm_connector_state *conn_state, 2752 struct drm_dp_vsc_sdp *vsc) 2753 { 2754 struct intel_display *display = to_intel_display(crtc_state); 2755 2756 if (crtc_state->has_panel_replay) { 2757 /* 2758 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2759 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel 2760 * Encoding/Colorimetry Format indication. 2761 */ 2762 vsc->revision = 0x7; 2763 } else { 2764 /* 2765 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2766 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ 2767 * Colorimetry Format indication. 2768 */ 2769 vsc->revision = 0x5; 2770 } 2771 2772 vsc->length = 0x13; 2773 2774 /* DP 1.4a spec, Table 2-120 */ 2775 switch (crtc_state->output_format) { 2776 case INTEL_OUTPUT_FORMAT_YCBCR444: 2777 vsc->pixelformat = DP_PIXELFORMAT_YUV444; 2778 break; 2779 case INTEL_OUTPUT_FORMAT_YCBCR420: 2780 vsc->pixelformat = DP_PIXELFORMAT_YUV420; 2781 break; 2782 case INTEL_OUTPUT_FORMAT_RGB: 2783 default: 2784 vsc->pixelformat = DP_PIXELFORMAT_RGB; 2785 } 2786 2787 switch (conn_state->colorspace) { 2788 case DRM_MODE_COLORIMETRY_BT709_YCC: 2789 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2790 break; 2791 case DRM_MODE_COLORIMETRY_XVYCC_601: 2792 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; 2793 break; 2794 case DRM_MODE_COLORIMETRY_XVYCC_709: 2795 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; 2796 break; 2797 case DRM_MODE_COLORIMETRY_SYCC_601: 2798 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; 2799 break; 2800 case DRM_MODE_COLORIMETRY_OPYCC_601: 2801 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; 2802 break; 2803 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 2804 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; 2805 break; 2806 case DRM_MODE_COLORIMETRY_BT2020_RGB: 2807 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; 2808 break; 2809 case DRM_MODE_COLORIMETRY_BT2020_YCC: 2810 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; 2811 break; 2812 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 2813 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 2814 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; 2815 break; 2816 default: 2817 /* 2818 * RGB->YCBCR color conversion uses the BT.709 2819 * color space. 2820 */ 2821 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2822 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2823 else 2824 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; 2825 break; 2826 } 2827 2828 vsc->bpc = crtc_state->pipe_bpp / 3; 2829 2830 /* only RGB pixelformat supports 6 bpc */ 2831 drm_WARN_ON(display->drm, 2832 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); 2833 2834 /* all YCbCr are always limited range */ 2835 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; 2836 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; 2837 } 2838 2839 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, 2840 struct intel_crtc_state *crtc_state) 2841 { 2842 struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; 2843 const struct drm_display_mode *adjusted_mode = 2844 &crtc_state->hw.adjusted_mode; 2845 2846 if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported) 2847 return; 2848 2849 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); 2850 2851 as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; 2852 as_sdp->length = 0x9; 2853 as_sdp->duration_incr_ms = 0; 2854 as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state); 2855 2856 if (crtc_state->cmrr.enable) { 2857 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; 2858 as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode); 2859 as_sdp->target_rr_divider = true; 2860 } else { 2861 as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL; 2862 as_sdp->target_rr = 0; 2863 } 2864 } 2865 2866 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, 2867 struct intel_crtc_state *crtc_state, 2868 const struct drm_connector_state *conn_state) 2869 { 2870 struct drm_dp_vsc_sdp *vsc; 2871 2872 if ((!intel_dp->colorimetry_support || 2873 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) && 2874 !crtc_state->has_psr) 2875 return; 2876 2877 vsc = &crtc_state->infoframes.vsc; 2878 2879 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 2880 vsc->sdp_type = DP_SDP_VSC; 2881 2882 /* Needs colorimetry */ 2883 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { 2884 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 2885 vsc); 2886 } else if (crtc_state->has_panel_replay) { 2887 /* 2888 * [Panel Replay without colorimetry info] 2889 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2890 * VSC SDP supporting 3D stereo + Panel Replay. 2891 */ 2892 vsc->revision = 0x6; 2893 vsc->length = 0x10; 2894 } else if (crtc_state->has_sel_update) { 2895 /* 2896 * [PSR2 without colorimetry] 2897 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 2898 * 3D stereo + PSR/PSR2 + Y-coordinate. 2899 */ 2900 vsc->revision = 0x4; 2901 vsc->length = 0xe; 2902 } else { 2903 /* 2904 * [PSR1] 2905 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2906 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or 2907 * higher). 2908 */ 2909 vsc->revision = 0x2; 2910 vsc->length = 0x8; 2911 } 2912 } 2913 2914 static void 2915 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, 2916 struct intel_crtc_state *crtc_state, 2917 const struct drm_connector_state *conn_state) 2918 { 2919 struct intel_display *display = to_intel_display(intel_dp); 2920 int ret; 2921 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; 2922 2923 if (!conn_state->hdr_output_metadata) 2924 return; 2925 2926 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); 2927 2928 if (ret) { 2929 drm_dbg_kms(display->drm, 2930 "couldn't set HDR metadata in infoframe\n"); 2931 return; 2932 } 2933 2934 crtc_state->infoframes.enable |= 2935 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 2936 } 2937 2938 static bool can_enable_drrs(struct intel_connector *connector, 2939 const struct intel_crtc_state *pipe_config, 2940 const struct drm_display_mode *downclock_mode) 2941 { 2942 struct intel_display *display = to_intel_display(connector); 2943 2944 if (pipe_config->vrr.enable) 2945 return false; 2946 2947 /* 2948 * DRRS and PSR can't be enable together, so giving preference to PSR 2949 * as it allows more power-savings by complete shutting down display, 2950 * so to guarantee this, intel_drrs_compute_config() must be called 2951 * after intel_psr_compute_config(). 2952 */ 2953 if (pipe_config->has_psr) 2954 return false; 2955 2956 /* FIXME missing FDI M2/N2 etc. */ 2957 if (pipe_config->has_pch_encoder) 2958 return false; 2959 2960 if (!intel_cpu_transcoder_has_drrs(display, pipe_config->cpu_transcoder)) 2961 return false; 2962 2963 return downclock_mode && 2964 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 2965 } 2966 2967 static void 2968 intel_dp_drrs_compute_config(struct intel_connector *connector, 2969 struct intel_crtc_state *pipe_config, 2970 int link_bpp_x16) 2971 { 2972 struct intel_display *display = to_intel_display(connector); 2973 const struct drm_display_mode *downclock_mode = 2974 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 2975 int pixel_clock; 2976 2977 /* 2978 * FIXME all joined pipes share the same transcoder. 2979 * Need to account for that when updating M/N live. 2980 */ 2981 if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes) 2982 pipe_config->update_m_n = true; 2983 2984 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { 2985 if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder)) 2986 intel_zero_m_n(&pipe_config->dp_m2_n2); 2987 return; 2988 } 2989 2990 if (display->platform.ironlake || display->platform.sandybridge || 2991 display->platform.ivybridge) 2992 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; 2993 2994 pipe_config->has_drrs = true; 2995 2996 pixel_clock = downclock_mode->clock; 2997 if (pipe_config->splitter.enable) 2998 pixel_clock /= pipe_config->splitter.link_count; 2999 3000 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock, 3001 pipe_config->port_clock, 3002 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 3003 &pipe_config->dp_m2_n2); 3004 3005 /* FIXME: abstract this better */ 3006 if (pipe_config->splitter.enable) 3007 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 3008 } 3009 3010 static bool intel_dp_has_audio(struct intel_encoder *encoder, 3011 const struct drm_connector_state *conn_state) 3012 { 3013 struct intel_display *display = to_intel_display(encoder); 3014 const struct intel_digital_connector_state *intel_conn_state = 3015 to_intel_digital_connector_state(conn_state); 3016 struct intel_connector *connector = 3017 to_intel_connector(conn_state->connector); 3018 3019 if (!intel_dp_port_has_audio(display, encoder->port)) 3020 return false; 3021 3022 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 3023 return connector->base.display_info.has_audio; 3024 else 3025 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 3026 } 3027 3028 static int 3029 intel_dp_compute_output_format(struct intel_encoder *encoder, 3030 struct intel_crtc_state *crtc_state, 3031 struct drm_connector_state *conn_state, 3032 bool respect_downstream_limits) 3033 { 3034 struct intel_display *display = to_intel_display(encoder); 3035 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3036 struct intel_connector *connector = intel_dp->attached_connector; 3037 const struct drm_display_info *info = &connector->base.display_info; 3038 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3039 bool ycbcr_420_only; 3040 int ret; 3041 3042 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 3043 3044 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { 3045 drm_dbg_kms(display->drm, 3046 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 3047 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 3048 } else { 3049 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode); 3050 } 3051 3052 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); 3053 3054 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 3055 respect_downstream_limits); 3056 if (ret) { 3057 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3058 !connector->base.ycbcr_420_allowed || 3059 !drm_mode_is_420_also(info, adjusted_mode)) 3060 return ret; 3061 3062 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 3063 crtc_state->output_format = intel_dp_output_format(connector, 3064 crtc_state->sink_format); 3065 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 3066 respect_downstream_limits); 3067 } 3068 3069 return ret; 3070 } 3071 3072 void 3073 intel_dp_audio_compute_config(struct intel_encoder *encoder, 3074 struct intel_crtc_state *pipe_config, 3075 struct drm_connector_state *conn_state) 3076 { 3077 pipe_config->has_audio = 3078 intel_dp_has_audio(encoder, conn_state) && 3079 intel_audio_compute_config(encoder, pipe_config, conn_state); 3080 3081 pipe_config->sdp_split_enable = pipe_config->has_audio && 3082 intel_dp_is_uhbr(pipe_config); 3083 } 3084 3085 void 3086 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, 3087 struct intel_encoder *encoder, 3088 const struct intel_crtc_state *crtc_state) 3089 { 3090 struct intel_connector *connector; 3091 struct intel_digital_connector_state *conn_state; 3092 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3093 int i; 3094 3095 if (intel_dp->needs_modeset_retry) 3096 return; 3097 3098 intel_dp->needs_modeset_retry = true; 3099 3100 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3101 intel_connector_queue_modeset_retry_work(intel_dp->attached_connector); 3102 3103 return; 3104 } 3105 3106 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { 3107 if (!conn_state->base.crtc) 3108 continue; 3109 3110 if (connector->mst.dp == intel_dp) 3111 intel_connector_queue_modeset_retry_work(connector); 3112 } 3113 } 3114 3115 int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, 3116 const struct drm_connector_state *conn_state) 3117 { 3118 struct intel_display *display = to_intel_display(crtc_state); 3119 const struct drm_display_mode *adjusted_mode = 3120 &crtc_state->hw.adjusted_mode; 3121 struct intel_connector *connector = to_intel_connector(conn_state->connector); 3122 int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8; 3123 /* 3124 * min symbol cycles is 3(BS,VBID, BE) for 128b/132b and 3125 * 5(BS, VBID, MVID, MAUD, BE) for 8b/10b 3126 */ 3127 int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5; 3128 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3129 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state); 3130 int min_hblank; 3131 int max_lane_count = 4; 3132 int hactive_sym_cycles, htotal_sym_cycles; 3133 int dsc_slices = 0; 3134 int link_bpp_x16; 3135 3136 if (DISPLAY_VER(display) < 30) 3137 return 0; 3138 3139 /* MIN_HBLANK should be set only for 8b/10b MST or for 128b/132b SST/MST */ 3140 if (!is_mst && !intel_dp_is_uhbr(crtc_state)) 3141 return 0; 3142 3143 if (crtc_state->dsc.compression_enable) { 3144 dsc_slices = intel_dp_dsc_get_slice_count(connector, 3145 adjusted_mode->crtc_clock, 3146 adjusted_mode->crtc_hdisplay, 3147 num_joined_pipes); 3148 if (!dsc_slices) { 3149 drm_dbg(display->drm, "failed to calculate dsc slice count\n"); 3150 return -EINVAL; 3151 } 3152 } 3153 3154 if (crtc_state->dsc.compression_enable) 3155 link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; 3156 else 3157 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, 3158 crtc_state->pipe_bpp)); 3159 3160 /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ 3161 hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count, 3162 adjusted_mode->hdisplay, 3163 dsc_slices, 3164 link_bpp_x16, 3165 symbol_size, is_mst); 3166 htotal_sym_cycles = adjusted_mode->htotal * hactive_sym_cycles / 3167 adjusted_mode->hdisplay; 3168 3169 min_hblank = htotal_sym_cycles - hactive_sym_cycles; 3170 /* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */ 3171 min_hblank = max(min_hblank, min_sym_cycles); 3172 3173 /* 3174 * adjust the BlankingStart/BlankingEnd framing control from 3175 * the calculated value 3176 */ 3177 min_hblank = min_hblank - 2; 3178 3179 min_hblank = min(10, min_hblank); 3180 crtc_state->min_hblank = min_hblank; 3181 3182 return 0; 3183 } 3184 3185 int 3186 intel_dp_compute_config(struct intel_encoder *encoder, 3187 struct intel_crtc_state *pipe_config, 3188 struct drm_connector_state *conn_state) 3189 { 3190 struct intel_display *display = to_intel_display(encoder); 3191 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); 3192 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 3193 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3194 const struct drm_display_mode *fixed_mode; 3195 struct intel_connector *connector = intel_dp->attached_connector; 3196 int ret = 0, link_bpp_x16; 3197 3198 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode); 3199 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 3200 ret = intel_panel_compute_config(connector, adjusted_mode); 3201 if (ret) 3202 return ret; 3203 } 3204 3205 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 3206 return -EINVAL; 3207 3208 if (!connector->base.interlace_allowed && 3209 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 3210 return -EINVAL; 3211 3212 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 3213 return -EINVAL; 3214 3215 if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay)) 3216 return -EINVAL; 3217 3218 /* 3219 * Try to respect downstream TMDS clock limits first, if 3220 * that fails assume the user might know something we don't. 3221 */ 3222 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true); 3223 if (ret) 3224 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false); 3225 if (ret) 3226 return ret; 3227 3228 if ((intel_dp_is_edp(intel_dp) && fixed_mode) || 3229 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3230 ret = intel_pfit_compute_config(pipe_config, conn_state); 3231 if (ret) 3232 return ret; 3233 } 3234 3235 pipe_config->limited_color_range = 3236 intel_dp_limited_color_range(pipe_config, conn_state); 3237 3238 if (intel_dp_is_uhbr(pipe_config)) { 3239 /* 128b/132b SST also needs this */ 3240 pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder; 3241 } else { 3242 pipe_config->enhanced_framing = 3243 drm_dp_enhanced_frame_cap(intel_dp->dpcd); 3244 } 3245 3246 if (pipe_config->dsc.compression_enable) 3247 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; 3248 else 3249 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format, 3250 pipe_config->pipe_bpp)); 3251 3252 if (intel_dp->mso_link_count) { 3253 int n = intel_dp->mso_link_count; 3254 int overlap = intel_dp->mso_pixel_overlap; 3255 3256 pipe_config->splitter.enable = true; 3257 pipe_config->splitter.link_count = n; 3258 pipe_config->splitter.pixel_overlap = overlap; 3259 3260 drm_dbg_kms(display->drm, 3261 "MSO link count %d, pixel overlap %d\n", 3262 n, overlap); 3263 3264 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; 3265 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; 3266 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; 3267 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; 3268 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; 3269 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; 3270 adjusted_mode->crtc_clock /= n; 3271 } 3272 3273 intel_dp_audio_compute_config(encoder, pipe_config, conn_state); 3274 3275 if (!intel_dp_is_uhbr(pipe_config)) { 3276 intel_link_compute_m_n(link_bpp_x16, 3277 pipe_config->lane_count, 3278 adjusted_mode->crtc_clock, 3279 pipe_config->port_clock, 3280 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 3281 &pipe_config->dp_m_n); 3282 } 3283 3284 ret = intel_dp_compute_min_hblank(pipe_config, conn_state); 3285 if (ret) 3286 return ret; 3287 3288 /* FIXME: abstract this better */ 3289 if (pipe_config->splitter.enable) 3290 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; 3291 3292 intel_vrr_compute_config(pipe_config, conn_state); 3293 intel_dp_compute_as_sdp(intel_dp, pipe_config); 3294 intel_psr_compute_config(intel_dp, pipe_config, conn_state); 3295 intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state); 3296 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); 3297 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); 3298 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); 3299 3300 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector, 3301 pipe_config); 3302 } 3303 3304 void intel_dp_set_link_params(struct intel_dp *intel_dp, 3305 int link_rate, int lane_count) 3306 { 3307 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 3308 intel_dp->link.active = false; 3309 intel_dp->needs_modeset_retry = false; 3310 intel_dp->link_rate = link_rate; 3311 intel_dp->lane_count = lane_count; 3312 } 3313 3314 void intel_dp_reset_link_params(struct intel_dp *intel_dp) 3315 { 3316 intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); 3317 intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); 3318 intel_dp->link.mst_probed_lane_count = 0; 3319 intel_dp->link.mst_probed_rate = 0; 3320 intel_dp->link.retrain_disabled = false; 3321 intel_dp->link.seq_train_failures = 0; 3322 } 3323 3324 /* Enable backlight PWM and backlight PP control. */ 3325 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 3326 const struct drm_connector_state *conn_state) 3327 { 3328 struct intel_display *display = to_intel_display(crtc_state); 3329 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); 3330 3331 if (!intel_dp_is_edp(intel_dp)) 3332 return; 3333 3334 drm_dbg_kms(display->drm, "\n"); 3335 3336 intel_backlight_enable(crtc_state, conn_state); 3337 intel_pps_backlight_on(intel_dp); 3338 } 3339 3340 /* Disable backlight PP control and backlight PWM. */ 3341 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) 3342 { 3343 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); 3344 struct intel_display *display = to_intel_display(intel_dp); 3345 3346 if (!intel_dp_is_edp(intel_dp)) 3347 return; 3348 3349 drm_dbg_kms(display->drm, "\n"); 3350 3351 intel_pps_backlight_off(intel_dp); 3352 intel_backlight_disable(old_conn_state); 3353 } 3354 3355 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) 3356 { 3357 /* 3358 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus 3359 * be capable of signalling downstream hpd with a long pulse. 3360 * Whether or not that means D3 is safe to use is not clear, 3361 * but let's assume so until proven otherwise. 3362 * 3363 * FIXME should really check all downstream ports... 3364 */ 3365 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 3366 drm_dp_is_branch(intel_dp->dpcd) && 3367 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; 3368 } 3369 3370 static int 3371 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set) 3372 { 3373 int err; 3374 u8 val; 3375 3376 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val); 3377 if (err < 0) 3378 return err; 3379 3380 if (set) 3381 val |= flag; 3382 else 3383 val &= ~flag; 3384 3385 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val); 3386 } 3387 3388 static void 3389 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, 3390 bool enable) 3391 { 3392 struct intel_display *display = to_intel_display(connector); 3393 3394 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux, 3395 DP_DECOMPRESSION_EN, enable) < 0) 3396 drm_dbg_kms(display->drm, 3397 "Failed to %s sink decompression state\n", 3398 str_enable_disable(enable)); 3399 } 3400 3401 static void 3402 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, 3403 bool enable) 3404 { 3405 struct intel_display *display = to_intel_display(connector); 3406 struct drm_dp_aux *aux = connector->mst.port ? 3407 connector->mst.port->passthrough_aux : NULL; 3408 3409 if (!aux) 3410 return; 3411 3412 if (write_dsc_decompression_flag(aux, 3413 DP_DSC_PASSTHROUGH_EN, enable) < 0) 3414 drm_dbg_kms(display->drm, 3415 "Failed to %s sink compression passthrough state\n", 3416 str_enable_disable(enable)); 3417 } 3418 3419 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, 3420 const struct intel_connector *connector, 3421 bool for_get_ref) 3422 { 3423 struct intel_display *display = to_intel_display(state); 3424 struct drm_connector *_connector_iter; 3425 struct drm_connector_state *old_conn_state; 3426 struct drm_connector_state *new_conn_state; 3427 int ref_count = 0; 3428 int i; 3429 3430 /* 3431 * On SST the decompression AUX device won't be shared, each connector 3432 * uses for this its own AUX targeting the sink device. 3433 */ 3434 if (!connector->mst.dp) 3435 return connector->dp.dsc_decompression_enabled ? 1 : 0; 3436 3437 for_each_oldnew_connector_in_state(&state->base, _connector_iter, 3438 old_conn_state, new_conn_state, i) { 3439 const struct intel_connector * 3440 connector_iter = to_intel_connector(_connector_iter); 3441 3442 if (connector_iter->mst.dp != connector->mst.dp) 3443 continue; 3444 3445 if (!connector_iter->dp.dsc_decompression_enabled) 3446 continue; 3447 3448 drm_WARN_ON(display->drm, 3449 (for_get_ref && !new_conn_state->crtc) || 3450 (!for_get_ref && !old_conn_state->crtc)); 3451 3452 if (connector_iter->dp.dsc_decompression_aux == 3453 connector->dp.dsc_decompression_aux) 3454 ref_count++; 3455 } 3456 3457 return ref_count; 3458 } 3459 3460 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state, 3461 struct intel_connector *connector) 3462 { 3463 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0; 3464 3465 connector->dp.dsc_decompression_enabled = true; 3466 3467 return ret; 3468 } 3469 3470 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state, 3471 struct intel_connector *connector) 3472 { 3473 connector->dp.dsc_decompression_enabled = false; 3474 3475 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0; 3476 } 3477 3478 /** 3479 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device 3480 * @state: atomic state 3481 * @connector: connector to enable the decompression for 3482 * @new_crtc_state: new state for the CRTC driving @connector 3483 * 3484 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3485 * register of the appropriate sink/branch device. On SST this is always the 3486 * sink device, whereas on MST based on each device's DSC capabilities it's 3487 * either the last branch device (enabling decompression in it) or both the 3488 * last branch device (enabling passthrough in it) and the sink device 3489 * (enabling decompression in it). 3490 */ 3491 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, 3492 struct intel_connector *connector, 3493 const struct intel_crtc_state *new_crtc_state) 3494 { 3495 struct intel_display *display = to_intel_display(state); 3496 3497 if (!new_crtc_state->dsc.compression_enable) 3498 return; 3499 3500 if (drm_WARN_ON(display->drm, 3501 !connector->dp.dsc_decompression_aux || 3502 connector->dp.dsc_decompression_enabled)) 3503 return; 3504 3505 if (!intel_dp_dsc_aux_get_ref(state, connector)) 3506 return; 3507 3508 intel_dp_sink_set_dsc_passthrough(connector, true); 3509 intel_dp_sink_set_dsc_decompression(connector, true); 3510 } 3511 3512 /** 3513 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device 3514 * @state: atomic state 3515 * @connector: connector to disable the decompression for 3516 * @old_crtc_state: old state for the CRTC driving @connector 3517 * 3518 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3519 * register of the appropriate sink/branch device, corresponding to the 3520 * sequence in intel_dp_sink_enable_decompression(). 3521 */ 3522 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, 3523 struct intel_connector *connector, 3524 const struct intel_crtc_state *old_crtc_state) 3525 { 3526 struct intel_display *display = to_intel_display(state); 3527 3528 if (!old_crtc_state->dsc.compression_enable) 3529 return; 3530 3531 if (drm_WARN_ON(display->drm, 3532 !connector->dp.dsc_decompression_aux || 3533 !connector->dp.dsc_decompression_enabled)) 3534 return; 3535 3536 if (!intel_dp_dsc_aux_put_ref(state, connector)) 3537 return; 3538 3539 intel_dp_sink_set_dsc_decompression(connector, false); 3540 intel_dp_sink_set_dsc_passthrough(connector, false); 3541 } 3542 3543 static void 3544 intel_dp_init_source_oui(struct intel_dp *intel_dp) 3545 { 3546 struct intel_display *display = to_intel_display(intel_dp); 3547 u8 oui[] = { 0x00, 0xaa, 0x01 }; 3548 u8 buf[3] = {}; 3549 3550 if (READ_ONCE(intel_dp->oui_valid)) 3551 return; 3552 3553 WRITE_ONCE(intel_dp->oui_valid, true); 3554 3555 /* 3556 * During driver init, we want to be careful and avoid changing the source OUI if it's 3557 * already set to what we want, so as to avoid clearing any state by accident 3558 */ 3559 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) 3560 drm_dbg_kms(display->drm, "Failed to read source OUI\n"); 3561 3562 if (memcmp(oui, buf, sizeof(oui)) == 0) { 3563 /* Assume the OUI was written now. */ 3564 intel_dp->last_oui_write = jiffies; 3565 return; 3566 } 3567 3568 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) { 3569 drm_dbg_kms(display->drm, "Failed to write source OUI\n"); 3570 WRITE_ONCE(intel_dp->oui_valid, false); 3571 } 3572 3573 intel_dp->last_oui_write = jiffies; 3574 } 3575 3576 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp) 3577 { 3578 WRITE_ONCE(intel_dp->oui_valid, false); 3579 } 3580 3581 void intel_dp_wait_source_oui(struct intel_dp *intel_dp) 3582 { 3583 struct intel_display *display = to_intel_display(intel_dp); 3584 struct intel_connector *connector = intel_dp->attached_connector; 3585 3586 drm_dbg_kms(display->drm, 3587 "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n", 3588 connector->base.base.id, connector->base.name, 3589 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3590 3591 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 3592 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3593 } 3594 3595 /* If the device supports it, try to set the power state appropriately */ 3596 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) 3597 { 3598 struct intel_display *display = to_intel_display(intel_dp); 3599 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3600 int ret, i; 3601 3602 /* Should have a valid DPCD by this point */ 3603 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 3604 return; 3605 3606 if (mode != DP_SET_POWER_D0) { 3607 if (downstream_hpd_needs_d0(intel_dp)) 3608 return; 3609 3610 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3611 } else { 3612 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3613 3614 intel_lspcon_resume(dig_port); 3615 3616 /* Write the source OUI as early as possible */ 3617 intel_dp_init_source_oui(intel_dp); 3618 3619 /* 3620 * When turning on, we need to retry for 1ms to give the sink 3621 * time to wake up. 3622 */ 3623 for (i = 0; i < 3; i++) { 3624 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3625 if (ret == 1) 3626 break; 3627 msleep(1); 3628 } 3629 3630 if (ret == 1 && intel_lspcon_active(dig_port)) 3631 intel_lspcon_wait_pcon_mode(dig_port); 3632 } 3633 3634 if (ret != 1) 3635 drm_dbg_kms(display->drm, 3636 "[ENCODER:%d:%s] Set power to %s failed\n", 3637 encoder->base.base.id, encoder->base.name, 3638 mode == DP_SET_POWER_D0 ? "D0" : "D3"); 3639 } 3640 3641 static bool 3642 intel_dp_get_dpcd(struct intel_dp *intel_dp); 3643 3644 /** 3645 * intel_dp_sync_state - sync the encoder state during init/resume 3646 * @encoder: intel encoder to sync 3647 * @crtc_state: state for the CRTC connected to the encoder 3648 * 3649 * Sync any state stored in the encoder wrt. HW state during driver init 3650 * and system resume. 3651 */ 3652 void intel_dp_sync_state(struct intel_encoder *encoder, 3653 const struct intel_crtc_state *crtc_state) 3654 { 3655 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3656 bool dpcd_updated = false; 3657 3658 /* 3659 * Don't clobber DPCD if it's been already read out during output 3660 * setup (eDP) or detect. 3661 */ 3662 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) { 3663 intel_dp_get_dpcd(intel_dp); 3664 dpcd_updated = true; 3665 } 3666 3667 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); 3668 3669 if (crtc_state) { 3670 intel_dp_reset_link_params(intel_dp); 3671 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 3672 intel_dp->link.active = true; 3673 } 3674 } 3675 3676 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 3677 struct intel_crtc_state *crtc_state) 3678 { 3679 struct intel_display *display = to_intel_display(encoder); 3680 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3681 bool fastset = true; 3682 3683 /* 3684 * If BIOS has set an unsupported or non-standard link rate for some 3685 * reason force an encoder recompute and full modeset. 3686 */ 3687 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, 3688 crtc_state->port_clock) < 0) { 3689 drm_dbg_kms(display->drm, 3690 "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n", 3691 encoder->base.base.id, encoder->base.name); 3692 crtc_state->uapi.connectors_changed = true; 3693 fastset = false; 3694 } 3695 3696 /* 3697 * FIXME hack to force full modeset when DSC is being used. 3698 * 3699 * As long as we do not have full state readout and config comparison 3700 * of crtc_state->dsc, we have no way to ensure reliable fastset. 3701 * Remove once we have readout for DSC. 3702 */ 3703 if (crtc_state->dsc.compression_enable) { 3704 drm_dbg_kms(display->drm, 3705 "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n", 3706 encoder->base.base.id, encoder->base.name); 3707 crtc_state->uapi.mode_changed = true; 3708 fastset = false; 3709 } 3710 3711 if (CAN_PANEL_REPLAY(intel_dp)) { 3712 drm_dbg_kms(display->drm, 3713 "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n", 3714 encoder->base.base.id, encoder->base.name); 3715 crtc_state->uapi.mode_changed = true; 3716 fastset = false; 3717 } 3718 3719 return fastset; 3720 } 3721 3722 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) 3723 { 3724 struct intel_display *display = to_intel_display(intel_dp); 3725 3726 /* Clear the cached register set to avoid using stale values */ 3727 3728 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); 3729 3730 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, 3731 intel_dp->pcon_dsc_dpcd, 3732 sizeof(intel_dp->pcon_dsc_dpcd)) < 0) 3733 drm_err(display->drm, "Failed to read DPCD register 0x%x\n", 3734 DP_PCON_DSC_ENCODER); 3735 3736 drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n", 3737 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); 3738 } 3739 3740 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) 3741 { 3742 static const int bw_gbps[] = {9, 18, 24, 32, 40, 48}; 3743 int i; 3744 3745 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { 3746 if (frl_bw_mask & (1 << i)) 3747 return bw_gbps[i]; 3748 } 3749 return 0; 3750 } 3751 3752 static int intel_dp_pcon_set_frl_mask(int max_frl) 3753 { 3754 switch (max_frl) { 3755 case 48: 3756 return DP_PCON_FRL_BW_MASK_48GBPS; 3757 case 40: 3758 return DP_PCON_FRL_BW_MASK_40GBPS; 3759 case 32: 3760 return DP_PCON_FRL_BW_MASK_32GBPS; 3761 case 24: 3762 return DP_PCON_FRL_BW_MASK_24GBPS; 3763 case 18: 3764 return DP_PCON_FRL_BW_MASK_18GBPS; 3765 case 9: 3766 return DP_PCON_FRL_BW_MASK_9GBPS; 3767 } 3768 3769 return 0; 3770 } 3771 3772 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) 3773 { 3774 struct intel_connector *connector = intel_dp->attached_connector; 3775 const struct drm_display_info *info = &connector->base.display_info; 3776 int max_frl_rate; 3777 int max_lanes, rate_per_lane; 3778 int max_dsc_lanes, dsc_rate_per_lane; 3779 3780 max_lanes = info->hdmi.max_lanes; 3781 rate_per_lane = info->hdmi.max_frl_rate_per_lane; 3782 max_frl_rate = max_lanes * rate_per_lane; 3783 3784 if (info->hdmi.dsc_cap.v_1p2) { 3785 max_dsc_lanes = info->hdmi.dsc_cap.max_lanes; 3786 dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane; 3787 if (max_dsc_lanes && dsc_rate_per_lane) 3788 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane); 3789 } 3790 3791 return max_frl_rate; 3792 } 3793 3794 static bool 3795 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp, 3796 u8 max_frl_bw_mask, u8 *frl_trained_mask) 3797 { 3798 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) && 3799 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL && 3800 *frl_trained_mask >= max_frl_bw_mask) 3801 return true; 3802 3803 return false; 3804 } 3805 3806 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) 3807 { 3808 struct intel_display *display = to_intel_display(intel_dp); 3809 #define TIMEOUT_FRL_READY_MS 500 3810 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 3811 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret; 3812 u8 max_frl_bw_mask = 0, frl_trained_mask; 3813 bool is_active; 3814 3815 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 3816 drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); 3817 3818 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp); 3819 drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n", 3820 max_edid_frl_bw); 3821 3822 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw); 3823 3824 if (max_frl_bw <= 0) 3825 return -EINVAL; 3826 3827 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); 3828 drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask); 3829 3830 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask)) 3831 goto frl_trained; 3832 3833 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); 3834 if (ret < 0) 3835 return ret; 3836 /* Wait for PCON to be FRL Ready */ 3837 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS); 3838 3839 if (!is_active) 3840 return -ETIMEDOUT; 3841 3842 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, 3843 DP_PCON_ENABLE_SEQUENTIAL_LINK); 3844 if (ret < 0) 3845 return ret; 3846 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, 3847 DP_PCON_FRL_LINK_TRAIN_NORMAL); 3848 if (ret < 0) 3849 return ret; 3850 ret = drm_dp_pcon_frl_enable(&intel_dp->aux); 3851 if (ret < 0) 3852 return ret; 3853 /* 3854 * Wait for FRL to be completed 3855 * Check if the HDMI Link is up and active. 3856 */ 3857 wait_for(is_active = 3858 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask), 3859 TIMEOUT_HDMI_LINK_ACTIVE_MS); 3860 3861 if (!is_active) 3862 return -ETIMEDOUT; 3863 3864 frl_trained: 3865 drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask); 3866 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); 3867 intel_dp->frl.is_trained = true; 3868 drm_dbg(display->drm, "FRL trained with : %d Gbps\n", 3869 intel_dp->frl.trained_rate_gbps); 3870 3871 return 0; 3872 } 3873 3874 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) 3875 { 3876 if (drm_dp_is_branch(intel_dp->dpcd) && 3877 intel_dp_has_hdmi_sink(intel_dp) && 3878 intel_dp_hdmi_sink_max_frl(intel_dp) > 0) 3879 return true; 3880 3881 return false; 3882 } 3883 3884 static 3885 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp) 3886 { 3887 int ret; 3888 u8 buf = 0; 3889 3890 /* Set PCON source control mode */ 3891 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE; 3892 3893 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3894 if (ret < 0) 3895 return ret; 3896 3897 /* Set HDMI LINK ENABLE */ 3898 buf |= DP_PCON_ENABLE_HDMI_LINK; 3899 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3900 if (ret < 0) 3901 return ret; 3902 3903 return 0; 3904 } 3905 3906 void intel_dp_check_frl_training(struct intel_dp *intel_dp) 3907 { 3908 struct intel_display *display = to_intel_display(intel_dp); 3909 3910 /* 3911 * Always go for FRL training if: 3912 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) 3913 * -sink is HDMI2.1 3914 */ 3915 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || 3916 !intel_dp_is_hdmi_2_1_sink(intel_dp) || 3917 intel_dp->frl.is_trained) 3918 return; 3919 3920 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) { 3921 int ret, mode; 3922 3923 drm_dbg(display->drm, 3924 "Couldn't set FRL mode, continuing with TMDS mode\n"); 3925 ret = intel_dp_pcon_set_tmds_mode(intel_dp); 3926 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); 3927 3928 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS) 3929 drm_dbg(display->drm, 3930 "Issue with PCON, cannot set TMDS mode\n"); 3931 } else { 3932 drm_dbg(display->drm, "FRL training Completed\n"); 3933 } 3934 } 3935 3936 static int 3937 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state) 3938 { 3939 int vactive = crtc_state->hw.adjusted_mode.vdisplay; 3940 3941 return intel_hdmi_dsc_get_slice_height(vactive); 3942 } 3943 3944 static int 3945 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, 3946 const struct intel_crtc_state *crtc_state) 3947 { 3948 struct intel_connector *connector = intel_dp->attached_connector; 3949 const struct drm_display_info *info = &connector->base.display_info; 3950 int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice; 3951 int hdmi_max_slices = info->hdmi.dsc_cap.max_slices; 3952 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); 3953 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); 3954 3955 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, 3956 pcon_max_slice_width, 3957 hdmi_max_slices, hdmi_throughput); 3958 } 3959 3960 static int 3961 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, 3962 const struct intel_crtc_state *crtc_state, 3963 int num_slices, int slice_width) 3964 { 3965 struct intel_connector *connector = intel_dp->attached_connector; 3966 const struct drm_display_info *info = &connector->base.display_info; 3967 int output_format = crtc_state->output_format; 3968 bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp; 3969 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); 3970 int hdmi_max_chunk_bytes = 3971 info->hdmi.dsc_cap.total_chunk_kbytes * 1024; 3972 3973 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, 3974 num_slices, output_format, hdmi_all_bpp, 3975 hdmi_max_chunk_bytes); 3976 } 3977 3978 void 3979 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 3980 const struct intel_crtc_state *crtc_state) 3981 { 3982 struct intel_display *display = to_intel_display(intel_dp); 3983 struct intel_connector *connector = intel_dp->attached_connector; 3984 const struct drm_display_info *info; 3985 u8 pps_param[6]; 3986 int slice_height; 3987 int slice_width; 3988 int num_slices; 3989 int bits_per_pixel; 3990 int ret; 3991 bool hdmi_is_dsc_1_2; 3992 3993 if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) 3994 return; 3995 3996 if (!connector) 3997 return; 3998 3999 info = &connector->base.display_info; 4000 4001 hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2; 4002 4003 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || 4004 !hdmi_is_dsc_1_2) 4005 return; 4006 4007 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); 4008 if (!slice_height) 4009 return; 4010 4011 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); 4012 if (!num_slices) 4013 return; 4014 4015 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, 4016 num_slices); 4017 4018 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, 4019 num_slices, slice_width); 4020 if (!bits_per_pixel) 4021 return; 4022 4023 pps_param[0] = slice_height & 0xFF; 4024 pps_param[1] = slice_height >> 8; 4025 pps_param[2] = slice_width & 0xFF; 4026 pps_param[3] = slice_width >> 8; 4027 pps_param[4] = bits_per_pixel & 0xFF; 4028 pps_param[5] = (bits_per_pixel >> 8) & 0x3; 4029 4030 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); 4031 if (ret < 0) 4032 drm_dbg_kms(display->drm, "Failed to set pcon DSC\n"); 4033 } 4034 4035 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 4036 const struct intel_crtc_state *crtc_state) 4037 { 4038 struct intel_display *display = to_intel_display(intel_dp); 4039 bool ycbcr444_to_420 = false; 4040 bool rgb_to_ycbcr = false; 4041 u8 tmp; 4042 4043 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) 4044 return; 4045 4046 if (!drm_dp_is_branch(intel_dp->dpcd)) 4047 return; 4048 4049 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0; 4050 4051 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4052 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) 4053 drm_dbg_kms(display->drm, 4054 "Failed to %s protocol converter HDMI mode\n", 4055 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp))); 4056 4057 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 4058 switch (crtc_state->output_format) { 4059 case INTEL_OUTPUT_FORMAT_YCBCR420: 4060 break; 4061 case INTEL_OUTPUT_FORMAT_YCBCR444: 4062 ycbcr444_to_420 = true; 4063 break; 4064 case INTEL_OUTPUT_FORMAT_RGB: 4065 rgb_to_ycbcr = true; 4066 ycbcr444_to_420 = true; 4067 break; 4068 default: 4069 MISSING_CASE(crtc_state->output_format); 4070 break; 4071 } 4072 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 4073 switch (crtc_state->output_format) { 4074 case INTEL_OUTPUT_FORMAT_YCBCR444: 4075 break; 4076 case INTEL_OUTPUT_FORMAT_RGB: 4077 rgb_to_ycbcr = true; 4078 break; 4079 default: 4080 MISSING_CASE(crtc_state->output_format); 4081 break; 4082 } 4083 } 4084 4085 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; 4086 4087 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4088 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) 4089 drm_dbg_kms(display->drm, 4090 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", 4091 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); 4092 4093 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; 4094 4095 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) 4096 drm_dbg_kms(display->drm, 4097 "Failed to %s protocol converter RGB->YCbCr conversion mode\n", 4098 str_enable_disable(tmp)); 4099 } 4100 4101 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) 4102 { 4103 u8 dprx = 0; 4104 4105 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 4106 &dprx) != 1) 4107 return false; 4108 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; 4109 } 4110 4111 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, 4112 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 4113 { 4114 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, 4115 DP_DSC_RECEIVER_CAP_SIZE) < 0) { 4116 drm_err(aux->drm_dev, 4117 "Failed to read DPCD register 0x%x\n", 4118 DP_DSC_SUPPORT); 4119 return; 4120 } 4121 4122 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", 4123 DP_DSC_RECEIVER_CAP_SIZE, 4124 dsc_dpcd); 4125 } 4126 4127 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector) 4128 { 4129 struct intel_display *display = to_intel_display(connector); 4130 4131 /* 4132 * Clear the cached register set to avoid using stale values 4133 * for the sinks that do not support DSC. 4134 */ 4135 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 4136 4137 /* Clear fec_capable to avoid using stale values */ 4138 connector->dp.fec_capability = 0; 4139 4140 if (dpcd_rev < DP_DPCD_REV_14) 4141 return; 4142 4143 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, 4144 connector->dp.dsc_dpcd); 4145 4146 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, 4147 &connector->dp.fec_capability) < 0) { 4148 drm_err(display->drm, "Failed to read FEC DPCD register\n"); 4149 return; 4150 } 4151 4152 drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n", 4153 connector->dp.fec_capability); 4154 } 4155 4156 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) 4157 { 4158 if (edp_dpcd_rev < DP_EDP_14) 4159 return; 4160 4161 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); 4162 } 4163 4164 static void 4165 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) 4166 { 4167 struct intel_display *display = to_intel_display(intel_dp); 4168 4169 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ 4170 if (!HAS_DSC(display)) 4171 return; 4172 4173 if (intel_dp_is_edp(intel_dp)) 4174 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], 4175 connector); 4176 else 4177 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], 4178 connector); 4179 } 4180 4181 static void intel_edp_mso_mode_fixup(struct intel_connector *connector, 4182 struct drm_display_mode *mode) 4183 { 4184 struct intel_display *display = to_intel_display(connector); 4185 struct intel_dp *intel_dp = intel_attached_dp(connector); 4186 int n = intel_dp->mso_link_count; 4187 int overlap = intel_dp->mso_pixel_overlap; 4188 4189 if (!mode || !n) 4190 return; 4191 4192 mode->hdisplay = (mode->hdisplay - overlap) * n; 4193 mode->hsync_start = (mode->hsync_start - overlap) * n; 4194 mode->hsync_end = (mode->hsync_end - overlap) * n; 4195 mode->htotal = (mode->htotal - overlap) * n; 4196 mode->clock *= n; 4197 4198 drm_mode_set_name(mode); 4199 4200 drm_dbg_kms(display->drm, 4201 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n", 4202 connector->base.base.id, connector->base.name, 4203 DRM_MODE_ARG(mode)); 4204 } 4205 4206 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) 4207 { 4208 struct intel_display *display = to_intel_display(encoder); 4209 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4210 struct intel_connector *connector = intel_dp->attached_connector; 4211 4212 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { 4213 /* 4214 * This is a big fat ugly hack. 4215 * 4216 * Some machines in UEFI boot mode provide us a VBT that has 18 4217 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4218 * unknown we fail to light up. Yet the same BIOS boots up with 4219 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4220 * max, not what it tells us to use. 4221 * 4222 * Note: This will still be broken if the eDP panel is not lit 4223 * up by the BIOS, and thus we can't get the mode at module 4224 * load. 4225 */ 4226 drm_dbg_kms(display->drm, 4227 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4228 pipe_bpp, connector->panel.vbt.edp.bpp); 4229 connector->panel.vbt.edp.bpp = pipe_bpp; 4230 } 4231 } 4232 4233 static void intel_edp_mso_init(struct intel_dp *intel_dp) 4234 { 4235 struct intel_display *display = to_intel_display(intel_dp); 4236 struct intel_connector *connector = intel_dp->attached_connector; 4237 struct drm_display_info *info = &connector->base.display_info; 4238 u8 mso; 4239 4240 if (intel_dp->edp_dpcd[0] < DP_EDP_14) 4241 return; 4242 4243 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { 4244 drm_err(display->drm, "Failed to read MSO cap\n"); 4245 return; 4246 } 4247 4248 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ 4249 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; 4250 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { 4251 drm_err(display->drm, "Invalid MSO link count cap %u\n", mso); 4252 mso = 0; 4253 } 4254 4255 if (mso) { 4256 drm_dbg_kms(display->drm, 4257 "Sink MSO %ux%u configuration, pixel overlap %u\n", 4258 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, 4259 info->mso_pixel_overlap); 4260 if (!HAS_MSO(display)) { 4261 drm_err(display->drm, 4262 "No source MSO support, disabling\n"); 4263 mso = 0; 4264 } 4265 } 4266 4267 intel_dp->mso_link_count = mso; 4268 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; 4269 } 4270 4271 static void 4272 intel_edp_set_sink_rates(struct intel_dp *intel_dp) 4273 { 4274 struct intel_display *display = to_intel_display(intel_dp); 4275 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4276 4277 intel_dp->num_sink_rates = 0; 4278 4279 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { 4280 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 4281 int i; 4282 4283 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 4284 sink_rates, sizeof(sink_rates)); 4285 4286 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 4287 int rate; 4288 4289 /* Value read multiplied by 200kHz gives the per-lane 4290 * link rate in kHz. The source rates are, however, 4291 * stored in terms of LS_Clk kHz. The full conversion 4292 * back to symbols is 4293 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) 4294 */ 4295 rate = le16_to_cpu(sink_rates[i]) * 200 / 10; 4296 4297 if (rate == 0) 4298 break; 4299 4300 /* 4301 * Some broken eDP sinks illegally declare support for 4302 * HBR3 without TPS4, and are unable to produce a stable 4303 * output. Reject HBR3 when TPS4 is not available. 4304 */ 4305 if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) { 4306 drm_dbg_kms(display->drm, 4307 "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n", 4308 encoder->base.base.id, encoder->base.name); 4309 break; 4310 } 4311 4312 intel_dp->sink_rates[i] = rate; 4313 } 4314 intel_dp->num_sink_rates = i; 4315 } 4316 4317 /* 4318 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, 4319 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. 4320 */ 4321 if (intel_dp->num_sink_rates) 4322 intel_dp->use_rate_select = true; 4323 else 4324 intel_dp_set_sink_rates(intel_dp); 4325 } 4326 4327 static bool 4328 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 4329 { 4330 struct intel_display *display = to_intel_display(intel_dp); 4331 4332 /* this function is meant to be called only once */ 4333 drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); 4334 4335 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) 4336 return false; 4337 4338 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4339 drm_dp_is_branch(intel_dp->dpcd)); 4340 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4341 4342 intel_dp->colorimetry_support = 4343 intel_dp_get_colorimetry_status(intel_dp); 4344 4345 /* 4346 * Read the eDP display control registers. 4347 * 4348 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in 4349 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it 4350 * set, but require eDP 1.4+ detection (e.g. for supported link rates 4351 * method). The display control registers should read zero if they're 4352 * not supported anyway. 4353 */ 4354 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 4355 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 4356 sizeof(intel_dp->edp_dpcd)) { 4357 drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n", 4358 (int)sizeof(intel_dp->edp_dpcd), 4359 intel_dp->edp_dpcd); 4360 4361 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; 4362 } 4363 4364 /* 4365 * If needed, program our source OUI so we can make various Intel-specific AUX services 4366 * available (such as HDR backlight controls) 4367 */ 4368 intel_dp_init_source_oui(intel_dp); 4369 4370 /* 4371 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 4372 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 4373 */ 4374 intel_psr_init_dpcd(intel_dp); 4375 4376 intel_edp_set_sink_rates(intel_dp); 4377 intel_dp_set_max_sink_lane_count(intel_dp); 4378 4379 /* Read the eDP DSC DPCD registers */ 4380 intel_dp_detect_dsc_caps(intel_dp, connector); 4381 4382 return true; 4383 } 4384 4385 static bool 4386 intel_dp_has_sink_count(struct intel_dp *intel_dp) 4387 { 4388 if (!intel_dp->attached_connector) 4389 return false; 4390 4391 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, 4392 intel_dp->dpcd, 4393 &intel_dp->desc); 4394 } 4395 4396 void intel_dp_update_sink_caps(struct intel_dp *intel_dp) 4397 { 4398 intel_dp_set_sink_rates(intel_dp); 4399 intel_dp_set_max_sink_lane_count(intel_dp); 4400 intel_dp_set_common_rates(intel_dp); 4401 } 4402 4403 static bool 4404 intel_dp_get_dpcd(struct intel_dp *intel_dp) 4405 { 4406 int ret; 4407 4408 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) 4409 return false; 4410 4411 /* 4412 * Don't clobber cached eDP rates. Also skip re-reading 4413 * the OUI/ID since we know it won't change. 4414 */ 4415 if (!intel_dp_is_edp(intel_dp)) { 4416 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4417 drm_dp_is_branch(intel_dp->dpcd)); 4418 4419 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4420 4421 intel_dp->colorimetry_support = 4422 intel_dp_get_colorimetry_status(intel_dp); 4423 4424 intel_dp_update_sink_caps(intel_dp); 4425 } 4426 4427 if (intel_dp_has_sink_count(intel_dp)) { 4428 ret = drm_dp_read_sink_count(&intel_dp->aux); 4429 if (ret < 0) 4430 return false; 4431 4432 /* 4433 * Sink count can change between short pulse hpd hence 4434 * a member variable in intel_dp will track any changes 4435 * between short pulse interrupts. 4436 */ 4437 intel_dp->sink_count = ret; 4438 4439 /* 4440 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 4441 * a dongle is present but no display. Unless we require to know 4442 * if a dongle is present or not, we don't need to update 4443 * downstream port information. So, an early return here saves 4444 * time from performing other operations which are not required. 4445 */ 4446 if (!intel_dp->sink_count) 4447 return false; 4448 } 4449 4450 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, 4451 intel_dp->downstream_ports) == 0; 4452 } 4453 4454 static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode) 4455 { 4456 if (mst_mode == DRM_DP_MST) 4457 return "MST"; 4458 else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG) 4459 return "SST w/ sideband messaging"; 4460 else 4461 return "SST"; 4462 } 4463 4464 static enum drm_dp_mst_mode 4465 intel_dp_mst_mode_choose(struct intel_dp *intel_dp, 4466 enum drm_dp_mst_mode sink_mst_mode) 4467 { 4468 struct intel_display *display = to_intel_display(intel_dp); 4469 4470 if (!display->params.enable_dp_mst) 4471 return DRM_DP_SST; 4472 4473 if (!intel_dp_mst_source_support(intel_dp)) 4474 return DRM_DP_SST; 4475 4476 if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG && 4477 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)) 4478 return DRM_DP_SST; 4479 4480 return sink_mst_mode; 4481 } 4482 4483 static enum drm_dp_mst_mode 4484 intel_dp_mst_detect(struct intel_dp *intel_dp) 4485 { 4486 struct intel_display *display = to_intel_display(intel_dp); 4487 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4488 enum drm_dp_mst_mode sink_mst_mode; 4489 enum drm_dp_mst_mode mst_detect; 4490 4491 sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 4492 4493 mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode); 4494 4495 drm_dbg_kms(display->drm, 4496 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n", 4497 encoder->base.base.id, encoder->base.name, 4498 str_yes_no(intel_dp_mst_source_support(intel_dp)), 4499 intel_dp_mst_mode_str(sink_mst_mode), 4500 str_yes_no(display->params.enable_dp_mst), 4501 intel_dp_mst_mode_str(mst_detect)); 4502 4503 return mst_detect; 4504 } 4505 4506 static void 4507 intel_dp_mst_configure(struct intel_dp *intel_dp) 4508 { 4509 if (!intel_dp_mst_source_support(intel_dp)) 4510 return; 4511 4512 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST; 4513 4514 if (intel_dp->is_mst) 4515 intel_dp_mst_prepare_probe(intel_dp); 4516 4517 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst); 4518 4519 /* Avoid stale info on the next detect cycle. */ 4520 intel_dp->mst_detect = DRM_DP_SST; 4521 } 4522 4523 static void 4524 intel_dp_mst_disconnect(struct intel_dp *intel_dp) 4525 { 4526 struct intel_display *display = to_intel_display(intel_dp); 4527 4528 if (!intel_dp->is_mst) 4529 return; 4530 4531 drm_dbg_kms(display->drm, 4532 "MST device may have disappeared %d vs %d\n", 4533 intel_dp->is_mst, intel_dp->mst.mgr.mst_state); 4534 intel_dp->is_mst = false; 4535 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst); 4536 } 4537 4538 static bool 4539 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi) 4540 { 4541 struct intel_display *display = to_intel_display(intel_dp); 4542 4543 /* 4544 * Display WA for HSD #13013007775: mtl/arl/lnl 4545 * Read the sink count and link service IRQ registers in separate 4546 * transactions to prevent disconnecting the sink on a TBT link 4547 * inadvertently. 4548 */ 4549 if (IS_DISPLAY_VER(display, 14, 20) && !display->platform.battlemage) { 4550 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 3) != 3) 4551 return false; 4552 4553 /* DP_SINK_COUNT_ESI + 3 == DP_LINK_SERVICE_IRQ_VECTOR_ESI0 */ 4554 return drm_dp_dpcd_readb(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, 4555 &esi[3]) == 1; 4556 } 4557 4558 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; 4559 } 4560 4561 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4]) 4562 { 4563 int retry; 4564 4565 for (retry = 0; retry < 3; retry++) { 4566 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1, 4567 &esi[1], 3) == 3) 4568 return true; 4569 } 4570 4571 return false; 4572 } 4573 4574 bool 4575 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 4576 const struct drm_connector_state *conn_state) 4577 { 4578 /* 4579 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 4580 * of Color Encoding Format and Content Color Gamut], in order to 4581 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. 4582 */ 4583 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 4584 return true; 4585 4586 switch (conn_state->colorspace) { 4587 case DRM_MODE_COLORIMETRY_SYCC_601: 4588 case DRM_MODE_COLORIMETRY_OPYCC_601: 4589 case DRM_MODE_COLORIMETRY_BT2020_YCC: 4590 case DRM_MODE_COLORIMETRY_BT2020_RGB: 4591 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 4592 return true; 4593 default: 4594 break; 4595 } 4596 4597 return false; 4598 } 4599 4600 static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, 4601 struct dp_sdp *sdp, size_t size) 4602 { 4603 size_t length = sizeof(struct dp_sdp); 4604 4605 if (size < length) 4606 return -ENOSPC; 4607 4608 memset(sdp, 0, size); 4609 4610 /* Prepare AS (Adaptive Sync) SDP Header */ 4611 sdp->sdp_header.HB0 = 0; 4612 sdp->sdp_header.HB1 = as_sdp->sdp_type; 4613 sdp->sdp_header.HB2 = 0x02; 4614 sdp->sdp_header.HB3 = as_sdp->length; 4615 4616 /* Fill AS (Adaptive Sync) SDP Payload */ 4617 sdp->db[0] = as_sdp->mode; 4618 sdp->db[1] = as_sdp->vtotal & 0xFF; 4619 sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF; 4620 sdp->db[3] = as_sdp->target_rr & 0xFF; 4621 sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; 4622 4623 if (as_sdp->target_rr_divider) 4624 sdp->db[4] |= 0x20; 4625 4626 return length; 4627 } 4628 4629 static ssize_t 4630 intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display, 4631 const struct hdmi_drm_infoframe *drm_infoframe, 4632 struct dp_sdp *sdp, 4633 size_t size) 4634 { 4635 size_t length = sizeof(struct dp_sdp); 4636 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; 4637 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; 4638 ssize_t len; 4639 4640 if (size < length) 4641 return -ENOSPC; 4642 4643 memset(sdp, 0, size); 4644 4645 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); 4646 if (len < 0) { 4647 drm_dbg_kms(display->drm, 4648 "buffer size is smaller than hdr metadata infoframe\n"); 4649 return -ENOSPC; 4650 } 4651 4652 if (len != infoframe_size) { 4653 drm_dbg_kms(display->drm, "wrong static hdr metadata size\n"); 4654 return -ENOSPC; 4655 } 4656 4657 /* 4658 * Set up the infoframe sdp packet for HDR static metadata. 4659 * Prepare VSC Header for SU as per DP 1.4a spec, 4660 * Table 2-100 and Table 2-101 4661 */ 4662 4663 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ 4664 sdp->sdp_header.HB0 = 0; 4665 /* 4666 * Packet Type 80h + Non-audio INFOFRAME Type value 4667 * HDMI_INFOFRAME_TYPE_DRM: 0x87 4668 * - 80h + Non-audio INFOFRAME Type value 4669 * - InfoFrame Type: 0x07 4670 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] 4671 */ 4672 sdp->sdp_header.HB1 = drm_infoframe->type; 4673 /* 4674 * Least Significant Eight Bits of (Data Byte Count – 1) 4675 * infoframe_size - 1 4676 */ 4677 sdp->sdp_header.HB2 = 0x1D; 4678 /* INFOFRAME SDP Version Number */ 4679 sdp->sdp_header.HB3 = (0x13 << 2); 4680 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4681 sdp->db[0] = drm_infoframe->version; 4682 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4683 sdp->db[1] = drm_infoframe->length; 4684 /* 4685 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after 4686 * HDMI_INFOFRAME_HEADER_SIZE 4687 */ 4688 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); 4689 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], 4690 HDMI_DRM_INFOFRAME_SIZE); 4691 4692 /* 4693 * Size of DP infoframe sdp packet for HDR static metadata consists of 4694 * - DP SDP Header(struct dp_sdp_header): 4 bytes 4695 * - Two Data Blocks: 2 bytes 4696 * CTA Header Byte2 (INFOFRAME Version Number) 4697 * CTA Header Byte3 (Length of INFOFRAME) 4698 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes 4699 * 4700 * Prior to GEN11's GMP register size is identical to DP HDR static metadata 4701 * infoframe size. But GEN11+ has larger than that size, write_infoframe 4702 * will pad rest of the size. 4703 */ 4704 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; 4705 } 4706 4707 static void intel_write_dp_sdp(struct intel_encoder *encoder, 4708 const struct intel_crtc_state *crtc_state, 4709 unsigned int type) 4710 { 4711 struct intel_display *display = to_intel_display(encoder); 4712 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4713 struct dp_sdp sdp = {}; 4714 ssize_t len; 4715 4716 if ((crtc_state->infoframes.enable & 4717 intel_hdmi_infoframe_enable(type)) == 0) 4718 return; 4719 4720 switch (type) { 4721 case DP_SDP_VSC: 4722 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp); 4723 break; 4724 case HDMI_PACKET_TYPE_GAMUT_METADATA: 4725 len = intel_dp_hdr_metadata_infoframe_sdp_pack(display, 4726 &crtc_state->infoframes.drm.drm, 4727 &sdp, sizeof(sdp)); 4728 break; 4729 case DP_SDP_ADAPTIVE_SYNC: 4730 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp, 4731 sizeof(sdp)); 4732 break; 4733 default: 4734 MISSING_CASE(type); 4735 return; 4736 } 4737 4738 if (drm_WARN_ON(display->drm, len < 0)) 4739 return; 4740 4741 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); 4742 } 4743 4744 void intel_dp_set_infoframes(struct intel_encoder *encoder, 4745 bool enable, 4746 const struct intel_crtc_state *crtc_state, 4747 const struct drm_connector_state *conn_state) 4748 { 4749 struct intel_display *display = to_intel_display(encoder); 4750 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); 4751 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 4752 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | 4753 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; 4754 4755 if (HAS_AS_SDP(display)) 4756 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL; 4757 4758 u32 val = intel_de_read(display, reg) & ~dip_enable; 4759 4760 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ 4761 if (!enable && HAS_DSC(display)) 4762 val &= ~VDIP_ENABLE_PPS; 4763 4764 /* 4765 * This routine disables VSC DIP if the function is called 4766 * to disable SDP or if it does not have PSR 4767 */ 4768 if (!enable || !crtc_state->has_psr) 4769 val &= ~VIDEO_DIP_ENABLE_VSC_HSW; 4770 4771 intel_de_write(display, reg, val); 4772 intel_de_posting_read(display, reg); 4773 4774 if (!enable) 4775 return; 4776 4777 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); 4778 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); 4779 4780 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); 4781 } 4782 4783 static 4784 int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, 4785 const void *buffer, size_t size) 4786 { 4787 const struct dp_sdp *sdp = buffer; 4788 4789 if (size < sizeof(struct dp_sdp)) 4790 return -EINVAL; 4791 4792 memset(as_sdp, 0, sizeof(*as_sdp)); 4793 4794 if (sdp->sdp_header.HB0 != 0) 4795 return -EINVAL; 4796 4797 if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC) 4798 return -EINVAL; 4799 4800 if (sdp->sdp_header.HB2 != 0x02) 4801 return -EINVAL; 4802 4803 if ((sdp->sdp_header.HB3 & 0x3F) != 9) 4804 return -EINVAL; 4805 4806 as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH; 4807 as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; 4808 as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; 4809 as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); 4810 as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; 4811 4812 return 0; 4813 } 4814 4815 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, 4816 const void *buffer, size_t size) 4817 { 4818 const struct dp_sdp *sdp = buffer; 4819 4820 if (size < sizeof(struct dp_sdp)) 4821 return -EINVAL; 4822 4823 memset(vsc, 0, sizeof(*vsc)); 4824 4825 if (sdp->sdp_header.HB0 != 0) 4826 return -EINVAL; 4827 4828 if (sdp->sdp_header.HB1 != DP_SDP_VSC) 4829 return -EINVAL; 4830 4831 vsc->sdp_type = sdp->sdp_header.HB1; 4832 vsc->revision = sdp->sdp_header.HB2; 4833 vsc->length = sdp->sdp_header.HB3; 4834 4835 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || 4836 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) || 4837 (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) { 4838 /* 4839 * - HB2 = 0x2, HB3 = 0x8 4840 * VSC SDP supporting 3D stereo + PSR 4841 * - HB2 = 0x4, HB3 = 0xe 4842 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of 4843 * first scan line of the SU region (applies to eDP v1.4b 4844 * and higher). 4845 * - HB2 = 0x6, HB3 = 0x10 4846 * VSC SDP supporting 3D stereo + Panel Replay. 4847 */ 4848 return 0; 4849 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { 4850 /* 4851 * - HB2 = 0x5, HB3 = 0x13 4852 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry 4853 * Format. 4854 */ 4855 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; 4856 vsc->colorimetry = sdp->db[16] & 0xf; 4857 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; 4858 4859 switch (sdp->db[17] & 0x7) { 4860 case 0x0: 4861 vsc->bpc = 6; 4862 break; 4863 case 0x1: 4864 vsc->bpc = 8; 4865 break; 4866 case 0x2: 4867 vsc->bpc = 10; 4868 break; 4869 case 0x3: 4870 vsc->bpc = 12; 4871 break; 4872 case 0x4: 4873 vsc->bpc = 16; 4874 break; 4875 default: 4876 MISSING_CASE(sdp->db[17] & 0x7); 4877 return -EINVAL; 4878 } 4879 4880 vsc->content_type = sdp->db[18] & 0x7; 4881 } else { 4882 return -EINVAL; 4883 } 4884 4885 return 0; 4886 } 4887 4888 static void 4889 intel_read_dp_as_sdp(struct intel_encoder *encoder, 4890 struct intel_crtc_state *crtc_state, 4891 struct drm_dp_as_sdp *as_sdp) 4892 { 4893 struct intel_display *display = to_intel_display(encoder); 4894 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4895 unsigned int type = DP_SDP_ADAPTIVE_SYNC; 4896 struct dp_sdp sdp = {}; 4897 int ret; 4898 4899 if ((crtc_state->infoframes.enable & 4900 intel_hdmi_infoframe_enable(type)) == 0) 4901 return; 4902 4903 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 4904 sizeof(sdp)); 4905 4906 ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp)); 4907 if (ret) 4908 drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n"); 4909 } 4910 4911 static int 4912 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, 4913 const void *buffer, size_t size) 4914 { 4915 int ret; 4916 4917 const struct dp_sdp *sdp = buffer; 4918 4919 if (size < sizeof(struct dp_sdp)) 4920 return -EINVAL; 4921 4922 if (sdp->sdp_header.HB0 != 0) 4923 return -EINVAL; 4924 4925 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) 4926 return -EINVAL; 4927 4928 /* 4929 * Least Significant Eight Bits of (Data Byte Count – 1) 4930 * 1Dh (i.e., Data Byte Count = 30 bytes). 4931 */ 4932 if (sdp->sdp_header.HB2 != 0x1D) 4933 return -EINVAL; 4934 4935 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ 4936 if ((sdp->sdp_header.HB3 & 0x3) != 0) 4937 return -EINVAL; 4938 4939 /* INFOFRAME SDP Version Number */ 4940 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) 4941 return -EINVAL; 4942 4943 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4944 if (sdp->db[0] != 1) 4945 return -EINVAL; 4946 4947 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4948 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) 4949 return -EINVAL; 4950 4951 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], 4952 HDMI_DRM_INFOFRAME_SIZE); 4953 4954 return ret; 4955 } 4956 4957 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, 4958 struct intel_crtc_state *crtc_state, 4959 struct drm_dp_vsc_sdp *vsc) 4960 { 4961 struct intel_display *display = to_intel_display(encoder); 4962 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4963 unsigned int type = DP_SDP_VSC; 4964 struct dp_sdp sdp = {}; 4965 int ret; 4966 4967 if ((crtc_state->infoframes.enable & 4968 intel_hdmi_infoframe_enable(type)) == 0) 4969 return; 4970 4971 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); 4972 4973 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); 4974 4975 if (ret) 4976 drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n"); 4977 } 4978 4979 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, 4980 struct intel_crtc_state *crtc_state, 4981 struct hdmi_drm_infoframe *drm_infoframe) 4982 { 4983 struct intel_display *display = to_intel_display(encoder); 4984 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4985 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; 4986 struct dp_sdp sdp = {}; 4987 int ret; 4988 4989 if ((crtc_state->infoframes.enable & 4990 intel_hdmi_infoframe_enable(type)) == 0) 4991 return; 4992 4993 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 4994 sizeof(sdp)); 4995 4996 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, 4997 sizeof(sdp)); 4998 4999 if (ret) 5000 drm_dbg_kms(display->drm, 5001 "Failed to unpack DP HDR Metadata Infoframe SDP\n"); 5002 } 5003 5004 void intel_read_dp_sdp(struct intel_encoder *encoder, 5005 struct intel_crtc_state *crtc_state, 5006 unsigned int type) 5007 { 5008 switch (type) { 5009 case DP_SDP_VSC: 5010 intel_read_dp_vsc_sdp(encoder, crtc_state, 5011 &crtc_state->infoframes.vsc); 5012 break; 5013 case HDMI_PACKET_TYPE_GAMUT_METADATA: 5014 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, 5015 &crtc_state->infoframes.drm.drm); 5016 break; 5017 case DP_SDP_ADAPTIVE_SYNC: 5018 intel_read_dp_as_sdp(encoder, crtc_state, 5019 &crtc_state->infoframes.as_sdp); 5020 break; 5021 default: 5022 MISSING_CASE(type); 5023 break; 5024 } 5025 } 5026 5027 static bool intel_dp_link_ok(struct intel_dp *intel_dp, 5028 u8 link_status[DP_LINK_STATUS_SIZE]) 5029 { 5030 struct intel_display *display = to_intel_display(intel_dp); 5031 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5032 bool uhbr = intel_dp->link_rate >= 1000000; 5033 bool ok; 5034 5035 if (uhbr) 5036 ok = drm_dp_128b132b_lane_channel_eq_done(link_status, 5037 intel_dp->lane_count); 5038 else 5039 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); 5040 5041 if (ok) 5042 return true; 5043 5044 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 5045 drm_dbg_kms(display->drm, 5046 "[ENCODER:%d:%s] %s link not ok, retraining\n", 5047 encoder->base.base.id, encoder->base.name, 5048 uhbr ? "128b/132b" : "8b/10b"); 5049 5050 return false; 5051 } 5052 5053 static void 5054 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) 5055 { 5056 bool handled = false; 5057 5058 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst.mgr, esi, ack, &handled); 5059 5060 if (esi[1] & DP_CP_IRQ) { 5061 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5062 ack[1] |= DP_CP_IRQ; 5063 } 5064 } 5065 5066 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp) 5067 { 5068 struct intel_display *display = to_intel_display(intel_dp); 5069 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5070 u8 link_status[DP_LINK_STATUS_SIZE] = {}; 5071 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2; 5072 5073 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status, 5074 esi_link_status_size) != esi_link_status_size) { 5075 drm_err(display->drm, 5076 "[ENCODER:%d:%s] Failed to read link status\n", 5077 encoder->base.base.id, encoder->base.name); 5078 return false; 5079 } 5080 5081 return intel_dp_link_ok(intel_dp, link_status); 5082 } 5083 5084 /** 5085 * intel_dp_check_mst_status - service any pending MST interrupts, check link status 5086 * @intel_dp: Intel DP struct 5087 * 5088 * Read any pending MST interrupts, call MST core to handle these and ack the 5089 * interrupts. Check if the main and AUX link state is ok. 5090 * 5091 * Returns: 5092 * - %true if pending interrupts were serviced (or no interrupts were 5093 * pending) w/o detecting an error condition. 5094 * - %false if an error condition - like AUX failure or a loss of link - is 5095 * detected, or another condition - like a DP tunnel BW state change - needs 5096 * servicing from the hotplug work. 5097 */ 5098 static bool 5099 intel_dp_check_mst_status(struct intel_dp *intel_dp) 5100 { 5101 struct intel_display *display = to_intel_display(intel_dp); 5102 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5103 struct intel_encoder *encoder = &dig_port->base; 5104 bool link_ok = true; 5105 bool reprobe_needed = false; 5106 5107 for (;;) { 5108 u8 esi[4] = {}; 5109 u8 ack[4] = {}; 5110 5111 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { 5112 drm_dbg_kms(display->drm, 5113 "failed to get ESI - device may have failed\n"); 5114 link_ok = false; 5115 5116 break; 5117 } 5118 5119 drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi); 5120 5121 if (intel_dp_mst_active_streams(intel_dp) > 0 && link_ok && 5122 esi[3] & LINK_STATUS_CHANGED) { 5123 if (!intel_dp_mst_link_status(intel_dp)) 5124 link_ok = false; 5125 ack[3] |= LINK_STATUS_CHANGED; 5126 } 5127 5128 intel_dp_mst_hpd_irq(intel_dp, esi, ack); 5129 5130 if (esi[3] & DP_TUNNELING_IRQ) { 5131 if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr, 5132 &intel_dp->aux)) 5133 reprobe_needed = true; 5134 ack[3] |= DP_TUNNELING_IRQ; 5135 } 5136 5137 if (mem_is_zero(ack, sizeof(ack))) 5138 break; 5139 5140 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack)) 5141 drm_dbg_kms(display->drm, "Failed to ack ESI\n"); 5142 5143 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY)) 5144 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst.mgr); 5145 } 5146 5147 if (!link_ok || intel_dp->link.force_retrain) 5148 intel_encoder_link_check_queue_work(encoder, 0); 5149 5150 return !reprobe_needed; 5151 } 5152 5153 static void 5154 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) 5155 { 5156 bool is_active; 5157 u8 buf = 0; 5158 5159 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); 5160 if (intel_dp->frl.is_trained && !is_active) { 5161 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) 5162 return; 5163 5164 buf &= ~DP_PCON_ENABLE_HDMI_LINK; 5165 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) 5166 return; 5167 5168 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); 5169 5170 intel_dp->frl.is_trained = false; 5171 5172 /* Restart FRL training or fall back to TMDS mode */ 5173 intel_dp_check_frl_training(intel_dp); 5174 } 5175 } 5176 5177 static bool 5178 intel_dp_needs_link_retrain(struct intel_dp *intel_dp) 5179 { 5180 u8 link_status[DP_LINK_STATUS_SIZE]; 5181 5182 if (!intel_dp->link.active) 5183 return false; 5184 5185 /* 5186 * While PSR source HW is enabled, it will control main-link sending 5187 * frames, enabling and disabling it so trying to do a retrain will fail 5188 * as the link would or not be on or it could mix training patterns 5189 * and frame data at the same time causing retrain to fail. 5190 * Also when exiting PSR, HW will retrain the link anyways fixing 5191 * any link status error. 5192 */ 5193 if (intel_psr_enabled(intel_dp)) 5194 return false; 5195 5196 if (intel_dp->link.force_retrain) 5197 return true; 5198 5199 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 5200 link_status) < 0) 5201 return false; 5202 5203 /* 5204 * Validate the cached values of intel_dp->link_rate and 5205 * intel_dp->lane_count before attempting to retrain. 5206 * 5207 * FIXME would be nice to user the crtc state here, but since 5208 * we need to call this from the short HPD handler that seems 5209 * a bit hard. 5210 */ 5211 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, 5212 intel_dp->lane_count)) 5213 return false; 5214 5215 if (intel_dp->link.retrain_disabled) 5216 return false; 5217 5218 if (intel_dp->link.seq_train_failures) 5219 return true; 5220 5221 /* Retrain if link not ok */ 5222 return !intel_dp_link_ok(intel_dp, link_status) && 5223 !intel_psr_link_ok(intel_dp); 5224 } 5225 5226 bool intel_dp_has_connector(struct intel_dp *intel_dp, 5227 const struct drm_connector_state *conn_state) 5228 { 5229 struct intel_display *display = to_intel_display(intel_dp); 5230 struct intel_encoder *encoder; 5231 enum pipe pipe; 5232 5233 if (!conn_state->best_encoder) 5234 return false; 5235 5236 /* SST */ 5237 encoder = &dp_to_dig_port(intel_dp)->base; 5238 if (conn_state->best_encoder == &encoder->base) 5239 return true; 5240 5241 /* MST */ 5242 for_each_pipe(display, pipe) { 5243 encoder = &intel_dp->mst.stream_encoders[pipe]->base; 5244 if (conn_state->best_encoder == &encoder->base) 5245 return true; 5246 } 5247 5248 return false; 5249 } 5250 5251 static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state) 5252 { 5253 struct intel_connector *connector = to_intel_connector(conn_state->connector); 5254 struct intel_display *display = to_intel_display(connector); 5255 5256 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); 5257 5258 if (!conn_state->commit) 5259 return; 5260 5261 drm_WARN_ON(display->drm, 5262 !wait_for_completion_timeout(&conn_state->commit->hw_done, 5263 msecs_to_jiffies(5000))); 5264 } 5265 5266 int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 5267 struct drm_modeset_acquire_ctx *ctx, 5268 u8 *pipe_mask) 5269 { 5270 struct intel_display *display = to_intel_display(intel_dp); 5271 struct drm_connector_list_iter conn_iter; 5272 struct intel_connector *connector; 5273 int ret = 0; 5274 5275 *pipe_mask = 0; 5276 5277 drm_connector_list_iter_begin(display->drm, &conn_iter); 5278 for_each_intel_connector_iter(connector, &conn_iter) { 5279 struct drm_connector_state *conn_state = 5280 connector->base.state; 5281 struct intel_crtc_state *crtc_state; 5282 struct intel_crtc *crtc; 5283 5284 if (!intel_dp_has_connector(intel_dp, conn_state)) 5285 continue; 5286 5287 crtc = to_intel_crtc(conn_state->crtc); 5288 if (!crtc) 5289 continue; 5290 5291 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 5292 if (ret) 5293 break; 5294 5295 crtc_state = to_intel_crtc_state(crtc->base.state); 5296 5297 drm_WARN_ON(display->drm, 5298 !intel_crtc_has_dp_encoder(crtc_state)); 5299 5300 if (!crtc_state->hw.active) 5301 continue; 5302 5303 wait_for_connector_hw_done(conn_state); 5304 5305 *pipe_mask |= BIT(crtc->pipe); 5306 } 5307 drm_connector_list_iter_end(&conn_iter); 5308 5309 return ret; 5310 } 5311 5312 void intel_dp_flush_connector_commits(struct intel_connector *connector) 5313 { 5314 wait_for_connector_hw_done(connector->base.state); 5315 } 5316 5317 static bool intel_dp_is_connected(struct intel_dp *intel_dp) 5318 { 5319 struct intel_connector *connector = intel_dp->attached_connector; 5320 5321 return connector->base.status == connector_status_connected || 5322 intel_dp->is_mst; 5323 } 5324 5325 static int intel_dp_retrain_link(struct intel_encoder *encoder, 5326 struct drm_modeset_acquire_ctx *ctx) 5327 { 5328 struct intel_display *display = to_intel_display(encoder); 5329 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5330 u8 pipe_mask; 5331 int ret; 5332 5333 if (!intel_dp_is_connected(intel_dp)) 5334 return 0; 5335 5336 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 5337 ctx); 5338 if (ret) 5339 return ret; 5340 5341 if (!intel_dp_needs_link_retrain(intel_dp)) 5342 return 0; 5343 5344 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); 5345 if (ret) 5346 return ret; 5347 5348 if (pipe_mask == 0) 5349 return 0; 5350 5351 if (!intel_dp_needs_link_retrain(intel_dp)) 5352 return 0; 5353 5354 drm_dbg_kms(display->drm, 5355 "[ENCODER:%d:%s] retraining link (forced %s)\n", 5356 encoder->base.base.id, encoder->base.name, 5357 str_yes_no(intel_dp->link.force_retrain)); 5358 5359 ret = intel_modeset_commit_pipes(display, pipe_mask, ctx); 5360 if (ret == -EDEADLK) 5361 return ret; 5362 5363 intel_dp->link.force_retrain = false; 5364 5365 if (ret) 5366 drm_dbg_kms(display->drm, 5367 "[ENCODER:%d:%s] link retraining failed: %pe\n", 5368 encoder->base.base.id, encoder->base.name, 5369 ERR_PTR(ret)); 5370 5371 return ret; 5372 } 5373 5374 void intel_dp_link_check(struct intel_encoder *encoder) 5375 { 5376 struct drm_modeset_acquire_ctx ctx; 5377 int ret; 5378 5379 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 5380 ret = intel_dp_retrain_link(encoder, &ctx); 5381 } 5382 5383 void intel_dp_check_link_state(struct intel_dp *intel_dp) 5384 { 5385 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5386 struct intel_encoder *encoder = &dig_port->base; 5387 5388 if (!intel_dp_is_connected(intel_dp)) 5389 return; 5390 5391 if (!intel_dp_needs_link_retrain(intel_dp)) 5392 return; 5393 5394 intel_encoder_link_check_queue_work(encoder, 0); 5395 } 5396 5397 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp) 5398 { 5399 struct intel_display *display = to_intel_display(intel_dp); 5400 u8 val; 5401 5402 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5403 return; 5404 5405 if (drm_dp_dpcd_readb(&intel_dp->aux, 5406 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) 5407 return; 5408 5409 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); 5410 5411 if (val & DP_AUTOMATED_TEST_REQUEST) 5412 intel_dp_test_request(intel_dp); 5413 5414 if (val & DP_CP_IRQ) 5415 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5416 5417 if (val & DP_SINK_SPECIFIC_IRQ) 5418 drm_dbg_kms(display->drm, "Sink specific irq unhandled\n"); 5419 } 5420 5421 static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp) 5422 { 5423 struct intel_display *display = to_intel_display(intel_dp); 5424 bool reprobe_needed = false; 5425 u8 val; 5426 5427 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5428 return false; 5429 5430 if (drm_dp_dpcd_readb(&intel_dp->aux, 5431 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) 5432 return false; 5433 5434 if ((val & DP_TUNNELING_IRQ) && 5435 drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr, 5436 &intel_dp->aux)) 5437 reprobe_needed = true; 5438 5439 if (drm_dp_dpcd_writeb(&intel_dp->aux, 5440 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) 5441 return reprobe_needed; 5442 5443 if (val & HDMI_LINK_STATUS_CHANGED) 5444 intel_dp_handle_hdmi_link_status_change(intel_dp); 5445 5446 return reprobe_needed; 5447 } 5448 5449 /* 5450 * According to DP spec 5451 * 5.1.2: 5452 * 1. Read DPCD 5453 * 2. Configure link according to Receiver Capabilities 5454 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 5455 * 4. Check link status on receipt of hot-plug interrupt 5456 * 5457 * intel_dp_short_pulse - handles short pulse interrupts 5458 * when full detection is not required. 5459 * Returns %true if short pulse is handled and full detection 5460 * is NOT required and %false otherwise. 5461 */ 5462 static bool 5463 intel_dp_short_pulse(struct intel_dp *intel_dp) 5464 { 5465 u8 old_sink_count = intel_dp->sink_count; 5466 bool reprobe_needed = false; 5467 bool ret; 5468 5469 intel_dp_test_reset(intel_dp); 5470 5471 /* 5472 * Now read the DPCD to see if it's actually running 5473 * If the current value of sink count doesn't match with 5474 * the value that was stored earlier or dpcd read failed 5475 * we need to do full detection 5476 */ 5477 ret = intel_dp_get_dpcd(intel_dp); 5478 5479 if ((old_sink_count != intel_dp->sink_count) || !ret) { 5480 /* No need to proceed if we are going to do full detect */ 5481 return false; 5482 } 5483 5484 intel_dp_check_device_service_irq(intel_dp); 5485 reprobe_needed = intel_dp_check_link_service_irq(intel_dp); 5486 5487 /* Handle CEC interrupts, if any */ 5488 drm_dp_cec_irq(&intel_dp->aux); 5489 5490 intel_dp_check_link_state(intel_dp); 5491 5492 intel_psr_short_pulse(intel_dp); 5493 5494 if (intel_alpm_get_error(intel_dp)) { 5495 intel_alpm_disable(intel_dp); 5496 intel_dp->alpm_parameters.sink_alpm_error = true; 5497 } 5498 5499 if (intel_dp_test_short_pulse(intel_dp)) 5500 reprobe_needed = true; 5501 5502 return !reprobe_needed; 5503 } 5504 5505 /* XXX this is probably wrong for multiple downstream ports */ 5506 static enum drm_connector_status 5507 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 5508 { 5509 struct intel_display *display = to_intel_display(intel_dp); 5510 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5511 u8 *dpcd = intel_dp->dpcd; 5512 u8 type; 5513 5514 if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp))) 5515 return connector_status_connected; 5516 5517 intel_lspcon_resume(dig_port); 5518 5519 if (!intel_dp_get_dpcd(intel_dp)) 5520 return connector_status_disconnected; 5521 5522 intel_dp->mst_detect = intel_dp_mst_detect(intel_dp); 5523 5524 /* if there's no downstream port, we're done */ 5525 if (!drm_dp_is_branch(dpcd)) 5526 return connector_status_connected; 5527 5528 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 5529 if (intel_dp_has_sink_count(intel_dp) && 5530 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 5531 return intel_dp->sink_count ? 5532 connector_status_connected : connector_status_disconnected; 5533 } 5534 5535 if (intel_dp->mst_detect == DRM_DP_MST) 5536 return connector_status_connected; 5537 5538 /* If no HPD, poke DDC gently */ 5539 if (drm_probe_ddc(&intel_dp->aux.ddc)) 5540 return connector_status_connected; 5541 5542 /* Well we tried, say unknown for unreliable port types */ 5543 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 5544 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 5545 if (type == DP_DS_PORT_TYPE_VGA || 5546 type == DP_DS_PORT_TYPE_NON_EDID) 5547 return connector_status_unknown; 5548 } else { 5549 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 5550 DP_DWN_STRM_PORT_TYPE_MASK; 5551 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 5552 type == DP_DWN_STRM_PORT_TYPE_OTHER) 5553 return connector_status_unknown; 5554 } 5555 5556 /* Anything else is out of spec, warn and ignore */ 5557 drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n"); 5558 return connector_status_disconnected; 5559 } 5560 5561 static enum drm_connector_status 5562 edp_detect(struct intel_dp *intel_dp) 5563 { 5564 return connector_status_connected; 5565 } 5566 5567 void intel_digital_port_lock(struct intel_encoder *encoder) 5568 { 5569 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5570 5571 if (dig_port->lock) 5572 dig_port->lock(dig_port); 5573 } 5574 5575 void intel_digital_port_unlock(struct intel_encoder *encoder) 5576 { 5577 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5578 5579 if (dig_port->unlock) 5580 dig_port->unlock(dig_port); 5581 } 5582 5583 /* 5584 * intel_digital_port_connected_locked - is the specified port connected? 5585 * @encoder: intel_encoder 5586 * 5587 * In cases where there's a connector physically connected but it can't be used 5588 * by our hardware we also return false, since the rest of the driver should 5589 * pretty much treat the port as disconnected. This is relevant for type-C 5590 * (starting on ICL) where there's ownership involved. 5591 * 5592 * The caller must hold the lock acquired by calling intel_digital_port_lock() 5593 * when calling this function. 5594 * 5595 * Return %true if port is connected, %false otherwise. 5596 */ 5597 bool intel_digital_port_connected_locked(struct intel_encoder *encoder) 5598 { 5599 struct intel_display *display = to_intel_display(encoder); 5600 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5601 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); 5602 bool is_connected = false; 5603 intel_wakeref_t wakeref; 5604 5605 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { 5606 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4); 5607 5608 do { 5609 is_connected = dig_port->connected(encoder); 5610 if (is_connected || is_glitch_free) 5611 break; 5612 usleep_range(10, 30); 5613 } while (time_before(jiffies, wait_expires)); 5614 } 5615 5616 return is_connected; 5617 } 5618 5619 bool intel_digital_port_connected(struct intel_encoder *encoder) 5620 { 5621 bool ret; 5622 5623 intel_digital_port_lock(encoder); 5624 ret = intel_digital_port_connected_locked(encoder); 5625 intel_digital_port_unlock(encoder); 5626 5627 return ret; 5628 } 5629 5630 static const struct drm_edid * 5631 intel_dp_get_edid(struct intel_dp *intel_dp) 5632 { 5633 struct intel_connector *connector = intel_dp->attached_connector; 5634 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 5635 5636 /* Use panel fixed edid if we have one */ 5637 if (fixed_edid) { 5638 /* invalid edid */ 5639 if (IS_ERR(fixed_edid)) 5640 return NULL; 5641 5642 return drm_edid_dup(fixed_edid); 5643 } 5644 5645 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc); 5646 } 5647 5648 static void 5649 intel_dp_update_dfp(struct intel_dp *intel_dp, 5650 const struct drm_edid *drm_edid) 5651 { 5652 struct intel_display *display = to_intel_display(intel_dp); 5653 struct intel_connector *connector = intel_dp->attached_connector; 5654 5655 intel_dp->dfp.max_bpc = 5656 drm_dp_downstream_max_bpc(intel_dp->dpcd, 5657 intel_dp->downstream_ports, drm_edid); 5658 5659 intel_dp->dfp.max_dotclock = 5660 drm_dp_downstream_max_dotclock(intel_dp->dpcd, 5661 intel_dp->downstream_ports); 5662 5663 intel_dp->dfp.min_tmds_clock = 5664 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, 5665 intel_dp->downstream_ports, 5666 drm_edid); 5667 intel_dp->dfp.max_tmds_clock = 5668 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, 5669 intel_dp->downstream_ports, 5670 drm_edid); 5671 5672 intel_dp->dfp.pcon_max_frl_bw = 5673 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, 5674 intel_dp->downstream_ports); 5675 5676 drm_dbg_kms(display->drm, 5677 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", 5678 connector->base.base.id, connector->base.name, 5679 intel_dp->dfp.max_bpc, 5680 intel_dp->dfp.max_dotclock, 5681 intel_dp->dfp.min_tmds_clock, 5682 intel_dp->dfp.max_tmds_clock, 5683 intel_dp->dfp.pcon_max_frl_bw); 5684 5685 intel_dp_get_pcon_dsc_cap(intel_dp); 5686 } 5687 5688 static bool 5689 intel_dp_can_ycbcr420(struct intel_dp *intel_dp) 5690 { 5691 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) && 5692 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough)) 5693 return true; 5694 5695 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) && 5696 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5697 return true; 5698 5699 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) && 5700 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5701 return true; 5702 5703 return false; 5704 } 5705 5706 static void 5707 intel_dp_update_420(struct intel_dp *intel_dp) 5708 { 5709 struct intel_display *display = to_intel_display(intel_dp); 5710 struct intel_connector *connector = intel_dp->attached_connector; 5711 5712 intel_dp->dfp.ycbcr420_passthrough = 5713 drm_dp_downstream_420_passthrough(intel_dp->dpcd, 5714 intel_dp->downstream_ports); 5715 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ 5716 intel_dp->dfp.ycbcr_444_to_420 = 5717 intel_lspcon_active(dp_to_dig_port(intel_dp)) || 5718 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, 5719 intel_dp->downstream_ports); 5720 intel_dp->dfp.rgb_to_ycbcr = 5721 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, 5722 intel_dp->downstream_ports, 5723 DP_DS_HDMI_BT709_RGB_YCBCR_CONV); 5724 5725 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp); 5726 5727 drm_dbg_kms(display->drm, 5728 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", 5729 connector->base.base.id, connector->base.name, 5730 str_yes_no(intel_dp->dfp.rgb_to_ycbcr), 5731 str_yes_no(connector->base.ycbcr_420_allowed), 5732 str_yes_no(intel_dp->dfp.ycbcr_444_to_420)); 5733 } 5734 5735 static void 5736 intel_dp_set_edid(struct intel_dp *intel_dp) 5737 { 5738 struct intel_display *display = to_intel_display(intel_dp); 5739 struct intel_connector *connector = intel_dp->attached_connector; 5740 const struct drm_edid *drm_edid; 5741 bool vrr_capable; 5742 5743 intel_dp_unset_edid(intel_dp); 5744 drm_edid = intel_dp_get_edid(intel_dp); 5745 connector->detect_edid = drm_edid; 5746 5747 /* Below we depend on display info having been updated */ 5748 drm_edid_connector_update(&connector->base, drm_edid); 5749 5750 vrr_capable = intel_vrr_is_capable(connector); 5751 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n", 5752 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable)); 5753 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable); 5754 5755 intel_dp_update_dfp(intel_dp, drm_edid); 5756 intel_dp_update_420(intel_dp); 5757 5758 drm_dp_cec_attach(&intel_dp->aux, 5759 connector->base.display_info.source_physical_address); 5760 } 5761 5762 static void 5763 intel_dp_unset_edid(struct intel_dp *intel_dp) 5764 { 5765 struct intel_connector *connector = intel_dp->attached_connector; 5766 5767 drm_dp_cec_unset_edid(&intel_dp->aux); 5768 drm_edid_free(connector->detect_edid); 5769 connector->detect_edid = NULL; 5770 5771 intel_dp->dfp.max_bpc = 0; 5772 intel_dp->dfp.max_dotclock = 0; 5773 intel_dp->dfp.min_tmds_clock = 0; 5774 intel_dp->dfp.max_tmds_clock = 0; 5775 5776 intel_dp->dfp.pcon_max_frl_bw = 0; 5777 5778 intel_dp->dfp.ycbcr_444_to_420 = false; 5779 connector->base.ycbcr_420_allowed = false; 5780 5781 drm_connector_set_vrr_capable_property(&connector->base, 5782 false); 5783 } 5784 5785 static void 5786 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) 5787 { 5788 struct intel_display *display = to_intel_display(intel_dp); 5789 5790 intel_dp->as_sdp_supported = HAS_AS_SDP(display) && 5791 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); 5792 } 5793 5794 static int 5795 intel_dp_detect(struct drm_connector *_connector, 5796 struct drm_modeset_acquire_ctx *ctx, 5797 bool force) 5798 { 5799 struct intel_display *display = to_intel_display(_connector->dev); 5800 struct intel_connector *connector = to_intel_connector(_connector); 5801 struct intel_dp *intel_dp = intel_attached_dp(connector); 5802 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5803 struct intel_encoder *encoder = &dig_port->base; 5804 enum drm_connector_status status; 5805 int ret; 5806 5807 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 5808 connector->base.base.id, connector->base.name); 5809 drm_WARN_ON(display->drm, 5810 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 5811 5812 if (!intel_display_device_enabled(display)) 5813 return connector_status_disconnected; 5814 5815 if (!intel_display_driver_check_access(display)) 5816 return connector->base.status; 5817 5818 intel_dp_flush_connector_commits(connector); 5819 5820 intel_pps_vdd_on(intel_dp); 5821 5822 /* Can't disconnect eDP */ 5823 if (intel_dp_is_edp(intel_dp)) 5824 status = edp_detect(intel_dp); 5825 else if (intel_digital_port_connected(encoder)) 5826 status = intel_dp_detect_dpcd(intel_dp); 5827 else 5828 status = connector_status_disconnected; 5829 5830 if (status != connector_status_disconnected && 5831 !intel_dp_mst_verify_dpcd_state(intel_dp)) 5832 /* 5833 * This requires retrying detection for instance to re-enable 5834 * the MST mode that got reset via a long HPD pulse. The retry 5835 * will happen either via the hotplug handler's retry logic, 5836 * ensured by setting the connector here to SST/disconnected, 5837 * or via a userspace connector probing in response to the 5838 * hotplug uevent sent when removing the MST connectors. 5839 */ 5840 status = connector_status_disconnected; 5841 5842 if (status == connector_status_disconnected) { 5843 intel_dp_test_reset(intel_dp); 5844 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 5845 intel_dp->psr.sink_panel_replay_support = false; 5846 intel_dp->psr.sink_panel_replay_su_support = false; 5847 5848 intel_dp_mst_disconnect(intel_dp); 5849 5850 intel_dp_tunnel_disconnect(intel_dp); 5851 5852 goto out_unset_edid; 5853 } 5854 5855 intel_dp_init_source_oui(intel_dp); 5856 5857 ret = intel_dp_tunnel_detect(intel_dp, ctx); 5858 if (ret == -EDEADLK) { 5859 status = ret; 5860 5861 goto out_vdd_off; 5862 } 5863 5864 if (ret == 1) 5865 connector->base.epoch_counter++; 5866 5867 if (!intel_dp_is_edp(intel_dp)) 5868 intel_psr_init_dpcd(intel_dp); 5869 5870 intel_dp_detect_dsc_caps(intel_dp, connector); 5871 5872 intel_dp_detect_sdp_caps(intel_dp); 5873 5874 if (intel_dp->reset_link_params) { 5875 intel_dp_reset_link_params(intel_dp); 5876 intel_dp->reset_link_params = false; 5877 } 5878 5879 intel_dp_mst_configure(intel_dp); 5880 5881 intel_dp_print_rates(intel_dp); 5882 5883 if (intel_dp->is_mst) { 5884 /* 5885 * If we are in MST mode then this connector 5886 * won't appear connected or have anything 5887 * with EDID on it 5888 */ 5889 status = connector_status_disconnected; 5890 goto out_unset_edid; 5891 } 5892 5893 /* 5894 * Some external monitors do not signal loss of link synchronization 5895 * with an IRQ_HPD, so force a link status check. 5896 * 5897 * TODO: this probably became redundant, so remove it: the link state 5898 * is rechecked/recovered now after modesets, where the loss of 5899 * synchronization tends to occur. 5900 */ 5901 if (!intel_dp_is_edp(intel_dp)) 5902 intel_dp_check_link_state(intel_dp); 5903 5904 /* 5905 * Clearing NACK and defer counts to get their exact values 5906 * while reading EDID which are required by Compliance tests 5907 * 4.2.2.4 and 4.2.2.5 5908 */ 5909 intel_dp->aux.i2c_nack_count = 0; 5910 intel_dp->aux.i2c_defer_count = 0; 5911 5912 intel_dp_set_edid(intel_dp); 5913 if (intel_dp_is_edp(intel_dp) || connector->detect_edid) 5914 status = connector_status_connected; 5915 5916 intel_dp_check_device_service_irq(intel_dp); 5917 5918 out_unset_edid: 5919 if (status != connector_status_connected && !intel_dp->is_mst) 5920 intel_dp_unset_edid(intel_dp); 5921 5922 if (!intel_dp_is_edp(intel_dp)) 5923 drm_dp_set_subconnector_property(&connector->base, 5924 status, 5925 intel_dp->dpcd, 5926 intel_dp->downstream_ports); 5927 out_vdd_off: 5928 intel_pps_vdd_off(intel_dp); 5929 5930 return status; 5931 } 5932 5933 static void 5934 intel_dp_force(struct drm_connector *_connector) 5935 { 5936 struct intel_connector *connector = to_intel_connector(_connector); 5937 struct intel_display *display = to_intel_display(connector); 5938 struct intel_dp *intel_dp = intel_attached_dp(connector); 5939 5940 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 5941 connector->base.base.id, connector->base.name); 5942 5943 if (!intel_display_driver_check_access(display)) 5944 return; 5945 5946 intel_dp_unset_edid(intel_dp); 5947 5948 if (connector->base.status != connector_status_connected) 5949 return; 5950 5951 intel_dp_set_edid(intel_dp); 5952 } 5953 5954 static int intel_dp_get_modes(struct drm_connector *_connector) 5955 { 5956 struct intel_display *display = to_intel_display(_connector->dev); 5957 struct intel_connector *connector = to_intel_connector(_connector); 5958 struct intel_dp *intel_dp = intel_attached_dp(connector); 5959 int num_modes; 5960 5961 /* drm_edid_connector_update() done in ->detect() or ->force() */ 5962 num_modes = drm_edid_connector_add_modes(&connector->base); 5963 5964 /* Also add fixed mode, which may or may not be present in EDID */ 5965 if (intel_dp_is_edp(intel_dp)) 5966 num_modes += intel_panel_get_modes(connector); 5967 5968 if (num_modes) 5969 return num_modes; 5970 5971 if (!connector->detect_edid) { 5972 struct drm_display_mode *mode; 5973 5974 mode = drm_dp_downstream_mode(display->drm, 5975 intel_dp->dpcd, 5976 intel_dp->downstream_ports); 5977 if (mode) { 5978 drm_mode_probed_add(&connector->base, mode); 5979 num_modes++; 5980 } 5981 } 5982 5983 return num_modes; 5984 } 5985 5986 static int 5987 intel_dp_connector_register(struct drm_connector *_connector) 5988 { 5989 struct intel_connector *connector = to_intel_connector(_connector); 5990 struct intel_display *display = to_intel_display(connector); 5991 struct intel_dp *intel_dp = intel_attached_dp(connector); 5992 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5993 int ret; 5994 5995 ret = intel_connector_register(&connector->base); 5996 if (ret) 5997 return ret; 5998 5999 drm_dbg_kms(display->drm, "registering %s bus for %s\n", 6000 intel_dp->aux.name, connector->base.kdev->kobj.name); 6001 6002 intel_dp->aux.dev = connector->base.kdev; 6003 ret = drm_dp_aux_register(&intel_dp->aux); 6004 if (!ret) 6005 drm_dp_cec_register_connector(&intel_dp->aux, &connector->base); 6006 6007 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) 6008 return ret; 6009 6010 /* 6011 * ToDo: Clean this up to handle lspcon init and resume more 6012 * efficiently and streamlined. 6013 */ 6014 if (intel_lspcon_init(dig_port)) { 6015 if (intel_lspcon_detect_hdr_capability(dig_port)) 6016 drm_connector_attach_hdr_output_metadata_property(&connector->base); 6017 } 6018 6019 return ret; 6020 } 6021 6022 static void 6023 intel_dp_connector_unregister(struct drm_connector *_connector) 6024 { 6025 struct intel_connector *connector = to_intel_connector(_connector); 6026 struct intel_dp *intel_dp = intel_attached_dp(connector); 6027 6028 drm_dp_cec_unregister_connector(&intel_dp->aux); 6029 drm_dp_aux_unregister(&intel_dp->aux); 6030 intel_connector_unregister(&connector->base); 6031 } 6032 6033 void intel_dp_connector_sync_state(struct intel_connector *connector, 6034 const struct intel_crtc_state *crtc_state) 6035 { 6036 struct intel_display *display = to_intel_display(connector); 6037 6038 if (crtc_state && crtc_state->dsc.compression_enable) { 6039 drm_WARN_ON(display->drm, 6040 !connector->dp.dsc_decompression_aux); 6041 connector->dp.dsc_decompression_enabled = true; 6042 } else { 6043 connector->dp.dsc_decompression_enabled = false; 6044 } 6045 } 6046 6047 void intel_dp_encoder_flush_work(struct drm_encoder *_encoder) 6048 { 6049 struct intel_encoder *encoder = to_intel_encoder(_encoder); 6050 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 6051 struct intel_dp *intel_dp = &dig_port->dp; 6052 6053 intel_encoder_link_check_flush_work(encoder); 6054 6055 intel_dp_mst_encoder_cleanup(dig_port); 6056 6057 intel_dp_tunnel_destroy(intel_dp); 6058 6059 intel_pps_vdd_off_sync(intel_dp); 6060 6061 /* 6062 * Ensure power off delay is respected on module remove, so that we can 6063 * reduce delays at driver probe. See pps_init_timestamps(). 6064 */ 6065 intel_pps_wait_power_cycle(intel_dp); 6066 6067 intel_dp_aux_fini(intel_dp); 6068 } 6069 6070 void intel_dp_encoder_suspend(struct intel_encoder *encoder) 6071 { 6072 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 6073 6074 intel_pps_vdd_off_sync(intel_dp); 6075 6076 intel_dp_tunnel_suspend(intel_dp); 6077 } 6078 6079 void intel_dp_encoder_shutdown(struct intel_encoder *encoder) 6080 { 6081 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 6082 6083 intel_pps_wait_power_cycle(intel_dp); 6084 } 6085 6086 static int intel_modeset_tile_group(struct intel_atomic_state *state, 6087 int tile_group_id) 6088 { 6089 struct intel_display *display = to_intel_display(state); 6090 struct drm_connector_list_iter conn_iter; 6091 struct intel_connector *connector; 6092 int ret = 0; 6093 6094 drm_connector_list_iter_begin(display->drm, &conn_iter); 6095 for_each_intel_connector_iter(connector, &conn_iter) { 6096 struct drm_connector_state *conn_state; 6097 struct intel_crtc_state *crtc_state; 6098 struct intel_crtc *crtc; 6099 6100 if (!connector->base.has_tile || 6101 connector->base.tile_group->id != tile_group_id) 6102 continue; 6103 6104 conn_state = drm_atomic_get_connector_state(&state->base, 6105 &connector->base); 6106 if (IS_ERR(conn_state)) { 6107 ret = PTR_ERR(conn_state); 6108 break; 6109 } 6110 6111 crtc = to_intel_crtc(conn_state->crtc); 6112 6113 if (!crtc) 6114 continue; 6115 6116 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6117 crtc_state->uapi.mode_changed = true; 6118 6119 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6120 if (ret) 6121 break; 6122 } 6123 drm_connector_list_iter_end(&conn_iter); 6124 6125 return ret; 6126 } 6127 6128 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) 6129 { 6130 struct intel_display *display = to_intel_display(state); 6131 struct intel_crtc *crtc; 6132 6133 if (transcoders == 0) 6134 return 0; 6135 6136 for_each_intel_crtc(display->drm, crtc) { 6137 struct intel_crtc_state *crtc_state; 6138 int ret; 6139 6140 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6141 if (IS_ERR(crtc_state)) 6142 return PTR_ERR(crtc_state); 6143 6144 if (!crtc_state->hw.enable) 6145 continue; 6146 6147 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) 6148 continue; 6149 6150 crtc_state->uapi.mode_changed = true; 6151 6152 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6153 if (ret) 6154 return ret; 6155 6156 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6157 if (ret) 6158 return ret; 6159 6160 transcoders &= ~BIT(crtc_state->cpu_transcoder); 6161 } 6162 6163 drm_WARN_ON(display->drm, transcoders != 0); 6164 6165 return 0; 6166 } 6167 6168 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, 6169 struct drm_connector *_connector) 6170 { 6171 struct intel_connector *connector = to_intel_connector(_connector); 6172 const struct drm_connector_state *old_conn_state = 6173 drm_atomic_get_old_connector_state(&state->base, &connector->base); 6174 const struct intel_crtc_state *old_crtc_state; 6175 struct intel_crtc *crtc; 6176 u8 transcoders; 6177 6178 crtc = to_intel_crtc(old_conn_state->crtc); 6179 if (!crtc) 6180 return 0; 6181 6182 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6183 6184 if (!old_crtc_state->hw.active) 6185 return 0; 6186 6187 transcoders = old_crtc_state->sync_mode_slaves_mask; 6188 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) 6189 transcoders |= BIT(old_crtc_state->master_transcoder); 6190 6191 return intel_modeset_affected_transcoders(state, 6192 transcoders); 6193 } 6194 6195 static int intel_dp_connector_atomic_check(struct drm_connector *_connector, 6196 struct drm_atomic_state *_state) 6197 { 6198 struct intel_connector *connector = to_intel_connector(_connector); 6199 struct intel_display *display = to_intel_display(connector); 6200 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6201 struct drm_connector_state *conn_state = 6202 drm_atomic_get_new_connector_state(_state, &connector->base); 6203 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 6204 int ret; 6205 6206 ret = intel_digital_connector_atomic_check(&connector->base, &state->base); 6207 if (ret) 6208 return ret; 6209 6210 if (intel_dp_mst_source_support(intel_dp)) { 6211 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst.mgr); 6212 if (ret) 6213 return ret; 6214 } 6215 6216 if (!intel_connector_needs_modeset(state, &connector->base)) 6217 return 0; 6218 6219 ret = intel_dp_tunnel_atomic_check_state(state, 6220 intel_dp, 6221 connector); 6222 if (ret) 6223 return ret; 6224 6225 /* 6226 * We don't enable port sync on BDW due to missing w/as and 6227 * due to not having adjusted the modeset sequence appropriately. 6228 */ 6229 if (DISPLAY_VER(display) < 9) 6230 return 0; 6231 6232 if (connector->base.has_tile) { 6233 ret = intel_modeset_tile_group(state, connector->base.tile_group->id); 6234 if (ret) 6235 return ret; 6236 } 6237 6238 return intel_modeset_synced_crtcs(state, &connector->base); 6239 } 6240 6241 static void intel_dp_oob_hotplug_event(struct drm_connector *_connector, 6242 enum drm_connector_status hpd_state) 6243 { 6244 struct intel_connector *connector = to_intel_connector(_connector); 6245 struct intel_display *display = to_intel_display(connector); 6246 struct intel_encoder *encoder = intel_attached_encoder(connector); 6247 bool hpd_high = hpd_state == connector_status_connected; 6248 unsigned int hpd_pin = encoder->hpd_pin; 6249 bool need_work = false; 6250 6251 spin_lock_irq(&display->irq.lock); 6252 if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) { 6253 display->hotplug.event_bits |= BIT(hpd_pin); 6254 6255 __assign_bit(hpd_pin, 6256 &display->hotplug.oob_hotplug_last_state, 6257 hpd_high); 6258 need_work = true; 6259 } 6260 spin_unlock_irq(&display->irq.lock); 6261 6262 if (need_work) 6263 intel_hpd_schedule_detection(display); 6264 } 6265 6266 static const struct drm_connector_funcs intel_dp_connector_funcs = { 6267 .force = intel_dp_force, 6268 .fill_modes = drm_helper_probe_single_connector_modes, 6269 .atomic_get_property = intel_digital_connector_atomic_get_property, 6270 .atomic_set_property = intel_digital_connector_atomic_set_property, 6271 .late_register = intel_dp_connector_register, 6272 .early_unregister = intel_dp_connector_unregister, 6273 .destroy = intel_connector_destroy, 6274 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6275 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 6276 .oob_hotplug_event = intel_dp_oob_hotplug_event, 6277 }; 6278 6279 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 6280 .detect_ctx = intel_dp_detect, 6281 .get_modes = intel_dp_get_modes, 6282 .mode_valid = intel_dp_mode_valid, 6283 .atomic_check = intel_dp_connector_atomic_check, 6284 }; 6285 6286 enum irqreturn 6287 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) 6288 { 6289 struct intel_display *display = to_intel_display(dig_port); 6290 struct intel_dp *intel_dp = &dig_port->dp; 6291 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 6292 6293 if (dig_port->base.type == INTEL_OUTPUT_EDP && 6294 (long_hpd || 6295 intel_display_rpm_suspended(display) || 6296 !intel_pps_have_panel_power_or_vdd(intel_dp))) { 6297 /* 6298 * vdd off can generate a long/short pulse on eDP which 6299 * would require vdd on to handle it, and thus we 6300 * would end up in an endless cycle of 6301 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." 6302 */ 6303 drm_dbg_kms(display->drm, 6304 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", 6305 long_hpd ? "long" : "short", 6306 dig_port->base.base.base.id, 6307 dig_port->base.base.name); 6308 return IRQ_HANDLED; 6309 } 6310 6311 drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", 6312 dig_port->base.base.base.id, 6313 dig_port->base.base.name, 6314 long_hpd ? "long" : "short"); 6315 6316 /* 6317 * TBT DP tunnels require the GFX driver to read out the DPRX caps in 6318 * response to long HPD pulses. The DP hotplug handler does that, 6319 * however the hotplug handler may be blocked by another 6320 * connector's/encoder's hotplug handler. Since the TBT CM may not 6321 * complete the DP tunnel BW request for the latter connector/encoder 6322 * waiting for this encoder's DPRX read, perform a dummy read here. 6323 */ 6324 if (long_hpd) 6325 intel_dp_read_dprx_caps(intel_dp, dpcd); 6326 6327 if (long_hpd) { 6328 intel_dp->reset_link_params = true; 6329 intel_dp_invalidate_source_oui(intel_dp); 6330 6331 return IRQ_NONE; 6332 } 6333 6334 if (intel_dp->is_mst) { 6335 if (!intel_dp_check_mst_status(intel_dp)) 6336 return IRQ_NONE; 6337 } else if (!intel_dp_short_pulse(intel_dp)) { 6338 return IRQ_NONE; 6339 } 6340 6341 return IRQ_HANDLED; 6342 } 6343 6344 static bool _intel_dp_is_port_edp(struct intel_display *display, 6345 const struct intel_bios_encoder_data *devdata, 6346 enum port port) 6347 { 6348 /* 6349 * eDP not supported on g4x. so bail out early just 6350 * for a bit extra safety in case the VBT is bonkers. 6351 */ 6352 if (DISPLAY_VER(display) < 5) 6353 return false; 6354 6355 if (DISPLAY_VER(display) < 9 && port == PORT_A) 6356 return true; 6357 6358 return devdata && intel_bios_encoder_supports_edp(devdata); 6359 } 6360 6361 bool intel_dp_is_port_edp(struct intel_display *display, enum port port) 6362 { 6363 const struct intel_bios_encoder_data *devdata = 6364 intel_bios_encoder_data_lookup(display, port); 6365 6366 return _intel_dp_is_port_edp(display, devdata, port); 6367 } 6368 6369 bool 6370 intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder) 6371 { 6372 struct intel_display *display = to_intel_display(encoder); 6373 enum port port = encoder->port; 6374 6375 if (intel_bios_encoder_is_lspcon(encoder->devdata)) 6376 return false; 6377 6378 if (DISPLAY_VER(display) >= 11) 6379 return true; 6380 6381 if (port == PORT_A) 6382 return false; 6383 6384 if (display->platform.haswell || display->platform.broadwell || 6385 DISPLAY_VER(display) >= 9) 6386 return true; 6387 6388 return false; 6389 } 6390 6391 static void 6392 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *_connector) 6393 { 6394 struct intel_connector *connector = to_intel_connector(_connector); 6395 struct intel_display *display = to_intel_display(intel_dp); 6396 enum port port = dp_to_dig_port(intel_dp)->base.port; 6397 6398 if (!intel_dp_is_edp(intel_dp)) 6399 drm_connector_attach_dp_subconnector_property(&connector->base); 6400 6401 if (!display->platform.g4x && port != PORT_A) 6402 intel_attach_force_audio_property(&connector->base); 6403 6404 intel_attach_broadcast_rgb_property(&connector->base); 6405 if (HAS_GMCH(display)) 6406 drm_connector_attach_max_bpc_property(&connector->base, 6, 10); 6407 else if (DISPLAY_VER(display) >= 5) 6408 drm_connector_attach_max_bpc_property(&connector->base, 6, 12); 6409 6410 /* Register HDMI colorspace for case of lspcon */ 6411 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) { 6412 drm_connector_attach_content_type_property(&connector->base); 6413 intel_attach_hdmi_colorspace_property(&connector->base); 6414 } else { 6415 intel_attach_dp_colorspace_property(&connector->base); 6416 } 6417 6418 if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) 6419 drm_connector_attach_hdr_output_metadata_property(&connector->base); 6420 6421 if (HAS_VRR(display)) 6422 drm_connector_attach_vrr_capable_property(&connector->base); 6423 } 6424 6425 static void 6426 intel_edp_add_properties(struct intel_dp *intel_dp) 6427 { 6428 struct intel_display *display = to_intel_display(intel_dp); 6429 struct intel_connector *connector = intel_dp->attached_connector; 6430 const struct drm_display_mode *fixed_mode = 6431 intel_panel_preferred_fixed_mode(connector); 6432 6433 intel_attach_scaling_mode_property(&connector->base); 6434 6435 drm_connector_set_panel_orientation_with_quirk(&connector->base, 6436 display->vbt.orientation, 6437 fixed_mode->hdisplay, 6438 fixed_mode->vdisplay); 6439 } 6440 6441 static void intel_edp_backlight_setup(struct intel_dp *intel_dp, 6442 struct intel_connector *connector) 6443 { 6444 struct intel_display *display = to_intel_display(intel_dp); 6445 enum pipe pipe = INVALID_PIPE; 6446 6447 if (display->platform.valleyview || display->platform.cherryview) 6448 pipe = vlv_pps_backlight_initial_pipe(intel_dp); 6449 6450 intel_backlight_setup(connector, pipe); 6451 } 6452 6453 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 6454 struct intel_connector *connector) 6455 { 6456 struct intel_display *display = to_intel_display(intel_dp); 6457 struct drm_display_mode *fixed_mode; 6458 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 6459 bool has_dpcd; 6460 const struct drm_edid *drm_edid; 6461 6462 if (!intel_dp_is_edp(intel_dp)) 6463 return true; 6464 6465 /* 6466 * On IBX/CPT we may get here with LVDS already registered. Since the 6467 * driver uses the only internal power sequencer available for both 6468 * eDP and LVDS bail out early in this case to prevent interfering 6469 * with an already powered-on LVDS power sequencer. 6470 */ 6471 if (intel_get_lvds_encoder(display)) { 6472 drm_WARN_ON(display->drm, 6473 !(HAS_PCH_IBX(display) || HAS_PCH_CPT(display))); 6474 drm_info(display->drm, 6475 "LVDS was detected, not registering eDP\n"); 6476 6477 return false; 6478 } 6479 6480 intel_bios_init_panel_early(display, &connector->panel, 6481 encoder->devdata); 6482 6483 if (!intel_pps_init(intel_dp)) { 6484 drm_info(display->drm, 6485 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n", 6486 encoder->base.base.id, encoder->base.name); 6487 /* 6488 * The BIOS may have still enabled VDD on the PPS even 6489 * though it's unusable. Make sure we turn it back off 6490 * and to release the power domain references/etc. 6491 */ 6492 goto out_vdd_off; 6493 } 6494 6495 /* 6496 * Enable HPD sense for live status check. 6497 * intel_hpd_irq_setup() will turn it off again 6498 * if it's no longer needed later. 6499 * 6500 * The DPCD probe below will make sure VDD is on. 6501 */ 6502 intel_hpd_enable_detection(encoder); 6503 6504 intel_alpm_init(intel_dp); 6505 6506 /* Cache DPCD and EDID for edp. */ 6507 has_dpcd = intel_edp_init_dpcd(intel_dp, connector); 6508 6509 if (!has_dpcd) { 6510 /* if this fails, presume the device is a ghost */ 6511 drm_info(display->drm, 6512 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n", 6513 encoder->base.base.id, encoder->base.name); 6514 goto out_vdd_off; 6515 } 6516 6517 /* 6518 * VBT and straps are liars. Also check HPD as that seems 6519 * to be the most reliable piece of information available. 6520 * 6521 * ... expect on devices that forgot to hook HPD up for eDP 6522 * (eg. Acer Chromebook C710), so we'll check it only if multiple 6523 * ports are attempting to use the same AUX CH, according to VBT. 6524 */ 6525 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) { 6526 /* 6527 * If this fails, presume the DPCD answer came 6528 * from some other port using the same AUX CH. 6529 * 6530 * FIXME maybe cleaner to check this before the 6531 * DPCD read? Would need sort out the VDD handling... 6532 */ 6533 if (!intel_digital_port_connected(encoder)) { 6534 drm_info(display->drm, 6535 "[ENCODER:%d:%s] HPD is down, disabling eDP\n", 6536 encoder->base.base.id, encoder->base.name); 6537 goto out_vdd_off; 6538 } 6539 6540 /* 6541 * Unfortunately even the HPD based detection fails on 6542 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall 6543 * back to checking for a VGA branch device. Only do this 6544 * on known affected platforms to minimize false positives. 6545 */ 6546 if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) && 6547 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) == 6548 DP_DWN_STRM_PORT_TYPE_ANALOG) { 6549 drm_info(display->drm, 6550 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n", 6551 encoder->base.base.id, encoder->base.name); 6552 goto out_vdd_off; 6553 } 6554 } 6555 6556 mutex_lock(&display->drm->mode_config.mutex); 6557 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc); 6558 if (!drm_edid) { 6559 /* Fallback to EDID from ACPI OpRegion, if any */ 6560 drm_edid = intel_opregion_get_edid(connector); 6561 if (drm_edid) 6562 drm_dbg_kms(display->drm, 6563 "[CONNECTOR:%d:%s] Using OpRegion EDID\n", 6564 connector->base.base.id, connector->base.name); 6565 } 6566 if (drm_edid) { 6567 if (drm_edid_connector_update(&connector->base, drm_edid) || 6568 !drm_edid_connector_add_modes(&connector->base)) { 6569 drm_edid_connector_update(&connector->base, NULL); 6570 drm_edid_free(drm_edid); 6571 drm_edid = ERR_PTR(-EINVAL); 6572 } 6573 } else { 6574 drm_edid = ERR_PTR(-ENOENT); 6575 } 6576 6577 intel_bios_init_panel_late(display, &connector->panel, encoder->devdata, 6578 IS_ERR(drm_edid) ? NULL : drm_edid); 6579 6580 intel_panel_add_edid_fixed_modes(connector, true); 6581 6582 /* MSO requires information from the EDID */ 6583 intel_edp_mso_init(intel_dp); 6584 6585 /* multiply the mode clock and horizontal timings for MSO */ 6586 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) 6587 intel_edp_mso_mode_fixup(connector, fixed_mode); 6588 6589 /* fallback to VBT if available for eDP */ 6590 if (!intel_panel_preferred_fixed_mode(connector)) 6591 intel_panel_add_vbt_lfp_fixed_mode(connector); 6592 6593 mutex_unlock(&display->drm->mode_config.mutex); 6594 6595 if (!intel_panel_preferred_fixed_mode(connector)) { 6596 drm_info(display->drm, 6597 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n", 6598 encoder->base.base.id, encoder->base.name); 6599 goto out_vdd_off; 6600 } 6601 6602 intel_panel_init(connector, drm_edid); 6603 6604 intel_edp_backlight_setup(intel_dp, connector); 6605 6606 intel_edp_add_properties(intel_dp); 6607 6608 intel_pps_init_late(intel_dp); 6609 6610 return true; 6611 6612 out_vdd_off: 6613 intel_pps_vdd_off_sync(intel_dp); 6614 intel_bios_fini_panel(&connector->panel); 6615 6616 return false; 6617 } 6618 6619 bool 6620 intel_dp_init_connector(struct intel_digital_port *dig_port, 6621 struct intel_connector *connector) 6622 { 6623 struct intel_display *display = to_intel_display(dig_port); 6624 struct intel_dp *intel_dp = &dig_port->dp; 6625 struct intel_encoder *encoder = &dig_port->base; 6626 struct drm_device *dev = encoder->base.dev; 6627 enum port port = encoder->port; 6628 int type; 6629 6630 if (drm_WARN(dev, dig_port->max_lanes < 1, 6631 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", 6632 dig_port->max_lanes, encoder->base.base.id, 6633 encoder->base.name)) 6634 return false; 6635 6636 intel_dp->reset_link_params = true; 6637 6638 /* Preserve the current hw state. */ 6639 intel_dp->DP = intel_de_read(display, intel_dp->output_reg); 6640 intel_dp->attached_connector = connector; 6641 6642 if (_intel_dp_is_port_edp(display, encoder->devdata, port)) { 6643 /* 6644 * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30, 6645 * although in theory it could work on TypeC legacy ports. 6646 */ 6647 drm_WARN_ON(dev, intel_encoder_is_tc(encoder) && 6648 DISPLAY_VER(display) < 30); 6649 type = DRM_MODE_CONNECTOR_eDP; 6650 encoder->type = INTEL_OUTPUT_EDP; 6651 6652 /* eDP only on port B and/or C on vlv/chv */ 6653 if (drm_WARN_ON(dev, (display->platform.valleyview || 6654 display->platform.cherryview) && 6655 port != PORT_B && port != PORT_C)) 6656 return false; 6657 } else { 6658 type = DRM_MODE_CONNECTOR_DisplayPort; 6659 } 6660 6661 intel_dp_set_default_sink_rates(intel_dp); 6662 intel_dp_set_default_max_sink_lane_count(intel_dp); 6663 6664 if (display->platform.valleyview || display->platform.cherryview) 6665 vlv_pps_pipe_init(intel_dp); 6666 6667 intel_dp_aux_init(intel_dp); 6668 connector->dp.dsc_decompression_aux = &intel_dp->aux; 6669 6670 drm_dbg_kms(display->drm, 6671 "Adding %s connector on [ENCODER:%d:%s]\n", 6672 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 6673 encoder->base.base.id, encoder->base.name); 6674 6675 drm_connector_init_with_ddc(dev, &connector->base, &intel_dp_connector_funcs, 6676 type, &intel_dp->aux.ddc); 6677 drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs); 6678 6679 if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12) 6680 connector->base.interlace_allowed = true; 6681 6682 if (type != DRM_MODE_CONNECTOR_eDP) 6683 connector->polled = DRM_CONNECTOR_POLL_HPD; 6684 connector->base.polled = connector->polled; 6685 6686 intel_connector_attach_encoder(connector, encoder); 6687 6688 if (HAS_DDI(display)) 6689 connector->get_hw_state = intel_ddi_connector_get_hw_state; 6690 else 6691 connector->get_hw_state = intel_connector_get_hw_state; 6692 connector->sync_state = intel_dp_connector_sync_state; 6693 6694 if (!intel_edp_init_connector(intel_dp, connector)) { 6695 intel_dp_aux_fini(intel_dp); 6696 goto fail; 6697 } 6698 6699 intel_dp_set_source_rates(intel_dp); 6700 intel_dp_set_common_rates(intel_dp); 6701 intel_dp_reset_link_params(intel_dp); 6702 6703 /* init MST on ports that can support it */ 6704 intel_dp_mst_encoder_init(dig_port, connector->base.base.id); 6705 6706 intel_dp_add_properties(intel_dp, &connector->base); 6707 6708 if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) { 6709 int ret = intel_dp_hdcp_init(dig_port, connector); 6710 if (ret) 6711 drm_dbg_kms(display->drm, 6712 "HDCP init failed, skipping.\n"); 6713 } 6714 6715 intel_dp->frl.is_trained = false; 6716 intel_dp->frl.trained_rate_gbps = 0; 6717 6718 intel_psr_init(intel_dp); 6719 6720 return true; 6721 6722 fail: 6723 intel_display_power_flush_work(display); 6724 drm_connector_cleanup(&connector->base); 6725 6726 return false; 6727 } 6728 6729 void intel_dp_mst_suspend(struct intel_display *display) 6730 { 6731 struct intel_encoder *encoder; 6732 6733 if (!HAS_DISPLAY(display)) 6734 return; 6735 6736 for_each_intel_encoder(display->drm, encoder) { 6737 struct intel_dp *intel_dp; 6738 6739 if (encoder->type != INTEL_OUTPUT_DDI) 6740 continue; 6741 6742 intel_dp = enc_to_intel_dp(encoder); 6743 6744 if (!intel_dp_mst_source_support(intel_dp)) 6745 continue; 6746 6747 if (intel_dp->is_mst) 6748 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst.mgr); 6749 } 6750 } 6751 6752 void intel_dp_mst_resume(struct intel_display *display) 6753 { 6754 struct intel_encoder *encoder; 6755 6756 if (!HAS_DISPLAY(display)) 6757 return; 6758 6759 for_each_intel_encoder(display->drm, encoder) { 6760 struct intel_dp *intel_dp; 6761 int ret; 6762 6763 if (encoder->type != INTEL_OUTPUT_DDI) 6764 continue; 6765 6766 intel_dp = enc_to_intel_dp(encoder); 6767 6768 if (!intel_dp_mst_source_support(intel_dp)) 6769 continue; 6770 6771 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst.mgr, true); 6772 if (ret) { 6773 intel_dp->is_mst = false; 6774 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, false); 6775 } 6776 } 6777 } 6778