1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/export.h> 29 #include <linux/i2c.h> 30 #include <linux/notifier.h> 31 #include <linux/seq_buf.h> 32 #include <linux/slab.h> 33 #include <linux/sort.h> 34 #include <linux/string_helpers.h> 35 #include <linux/timekeeping.h> 36 #include <linux/types.h> 37 38 #include <asm/byteorder.h> 39 40 #include <drm/display/drm_dp_helper.h> 41 #include <drm/display/drm_dp_tunnel.h> 42 #include <drm/display/drm_dsc_helper.h> 43 #include <drm/display/drm_hdmi_helper.h> 44 #include <drm/drm_atomic_helper.h> 45 #include <drm/drm_crtc.h> 46 #include <drm/drm_edid.h> 47 #include <drm/drm_fixed.h> 48 #include <drm/drm_print.h> 49 #include <drm/drm_probe_helper.h> 50 51 #include "g4x_dp.h" 52 #include "i915_irq.h" 53 #include "i915_reg.h" 54 #include "i915_utils.h" 55 #include "intel_alpm.h" 56 #include "intel_atomic.h" 57 #include "intel_audio.h" 58 #include "intel_backlight.h" 59 #include "intel_combo_phy_regs.h" 60 #include "intel_connector.h" 61 #include "intel_crtc.h" 62 #include "intel_crtc_state_dump.h" 63 #include "intel_cx0_phy.h" 64 #include "intel_ddi.h" 65 #include "intel_de.h" 66 #include "intel_display_driver.h" 67 #include "intel_display_rpm.h" 68 #include "intel_display_types.h" 69 #include "intel_dp.h" 70 #include "intel_dp_aux.h" 71 #include "intel_dp_hdcp.h" 72 #include "intel_dp_link_training.h" 73 #include "intel_dp_mst.h" 74 #include "intel_dp_test.h" 75 #include "intel_dp_tunnel.h" 76 #include "intel_dpio_phy.h" 77 #include "intel_dpll.h" 78 #include "intel_drrs.h" 79 #include "intel_encoder.h" 80 #include "intel_fifo_underrun.h" 81 #include "intel_hdcp.h" 82 #include "intel_hdmi.h" 83 #include "intel_hotplug.h" 84 #include "intel_hotplug_irq.h" 85 #include "intel_lspcon.h" 86 #include "intel_lvds.h" 87 #include "intel_modeset_lock.h" 88 #include "intel_panel.h" 89 #include "intel_pch_display.h" 90 #include "intel_pfit.h" 91 #include "intel_pps.h" 92 #include "intel_psr.h" 93 #include "intel_quirks.h" 94 #include "intel_tc.h" 95 #include "intel_vdsc.h" 96 #include "intel_vrr.h" 97 98 /* DP DSC throughput values used for slice count calculations KPixels/s */ 99 #define DP_DSC_PEAK_PIXEL_RATE 2720000 100 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 101 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 102 103 /* Max DSC line buffer depth supported by HW. */ 104 #define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13 105 106 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ 107 #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530 108 109 /* Constants for DP DSC configurations */ 110 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 111 112 /* 113 * With Single pipe configuration, HW is capable of supporting maximum of: 114 * 2 slices per line for ICL, BMG 115 * 4 slices per line for other platforms. 116 * For now consider a max of 2 slices per line, which works for all platforms. 117 * With this we can have max of 4 DSC Slices per pipe. 118 * 119 * For higher resolutions where 12 slice support is required with 120 * ultrajoiner, only then each pipe can support 3 slices. 121 * 122 * #TODO Split this better to use 4 slices/dsc engine where supported. 123 */ 124 static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4}; 125 126 /** 127 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 128 * @intel_dp: DP struct 129 * 130 * If a CPU or PCH DP output is attached to an eDP panel, this function 131 * will return true, and false otherwise. 132 * 133 * This function is not safe to use prior to encoder type being set. 134 */ 135 bool intel_dp_is_edp(struct intel_dp *intel_dp) 136 { 137 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 138 139 return dig_port->base.type == INTEL_OUTPUT_EDP; 140 } 141 142 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 143 144 /* Is link rate UHBR and thus 128b/132b? */ 145 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) 146 { 147 return drm_dp_is_uhbr_rate(crtc_state->port_clock); 148 } 149 150 /** 151 * intel_dp_link_symbol_size - get the link symbol size for a given link rate 152 * @rate: link rate in 10kbit/s units 153 * 154 * Returns the link symbol size in bits/symbol units depending on the link 155 * rate -> channel coding. 156 */ 157 int intel_dp_link_symbol_size(int rate) 158 { 159 return drm_dp_is_uhbr_rate(rate) ? 32 : 10; 160 } 161 162 /** 163 * intel_dp_link_symbol_clock - convert link rate to link symbol clock 164 * @rate: link rate in 10kbit/s units 165 * 166 * Returns the link symbol clock frequency in kHz units depending on the 167 * link rate and channel coding. 168 */ 169 int intel_dp_link_symbol_clock(int rate) 170 { 171 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate)); 172 } 173 174 static int max_dprx_rate(struct intel_dp *intel_dp) 175 { 176 struct intel_display *display = to_intel_display(intel_dp); 177 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 178 int max_rate; 179 180 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 181 max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); 182 else 183 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 184 185 /* 186 * Some broken eDP sinks illegally declare support for 187 * HBR3 without TPS4, and are unable to produce a stable 188 * output. Reject HBR3 when TPS4 is not available. 189 */ 190 if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) { 191 drm_dbg_kms(display->drm, 192 "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n", 193 encoder->base.base.id, encoder->base.name); 194 max_rate = 540000; 195 } 196 197 return max_rate; 198 } 199 200 static int max_dprx_lane_count(struct intel_dp *intel_dp) 201 { 202 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 203 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel); 204 205 return drm_dp_max_lane_count(intel_dp->dpcd); 206 } 207 208 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) 209 { 210 intel_dp->sink_rates[0] = 162000; 211 intel_dp->num_sink_rates = 1; 212 } 213 214 /* update sink rates from dpcd */ 215 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) 216 { 217 static const int dp_rates[] = { 218 162000, 270000, 540000, 810000 219 }; 220 int i, max_rate; 221 int max_lttpr_rate; 222 223 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { 224 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ 225 static const int quirk_rates[] = { 162000, 270000, 324000 }; 226 227 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); 228 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); 229 230 return; 231 } 232 233 /* 234 * Sink rates for 8b/10b. 235 */ 236 max_rate = max_dprx_rate(intel_dp); 237 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); 238 if (max_lttpr_rate) 239 max_rate = min(max_rate, max_lttpr_rate); 240 241 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { 242 if (dp_rates[i] > max_rate) 243 break; 244 intel_dp->sink_rates[i] = dp_rates[i]; 245 } 246 247 /* 248 * Sink rates for 128b/132b. If set, sink should support all 8b/10b 249 * rates and 10 Gbps. 250 */ 251 if (drm_dp_128b132b_supported(intel_dp->dpcd)) { 252 u8 uhbr_rates = 0; 253 254 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); 255 256 drm_dp_dpcd_readb(&intel_dp->aux, 257 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates); 258 259 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) { 260 /* We have a repeater */ 261 if (intel_dp->lttpr_common_caps[0] >= 0x20 && 262 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 263 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] & 264 DP_PHY_REPEATER_128B132B_SUPPORTED) { 265 /* Repeater supports 128b/132b, valid UHBR rates */ 266 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES - 267 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 268 } else { 269 /* Does not support 128b/132b */ 270 uhbr_rates = 0; 271 } 272 } 273 274 if (uhbr_rates & DP_UHBR10) 275 intel_dp->sink_rates[i++] = 1000000; 276 if (uhbr_rates & DP_UHBR13_5) 277 intel_dp->sink_rates[i++] = 1350000; 278 if (uhbr_rates & DP_UHBR20) 279 intel_dp->sink_rates[i++] = 2000000; 280 } 281 282 intel_dp->num_sink_rates = i; 283 } 284 285 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 286 { 287 struct intel_display *display = to_intel_display(intel_dp); 288 struct intel_connector *connector = intel_dp->attached_connector; 289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 290 struct intel_encoder *encoder = &intel_dig_port->base; 291 292 intel_dp_set_dpcd_sink_rates(intel_dp); 293 294 if (intel_dp->num_sink_rates) 295 return; 296 297 drm_err(display->drm, 298 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", 299 connector->base.base.id, connector->base.name, 300 encoder->base.base.id, encoder->base.name); 301 302 intel_dp_set_default_sink_rates(intel_dp); 303 } 304 305 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp) 306 { 307 intel_dp->max_sink_lane_count = 1; 308 } 309 310 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp) 311 { 312 struct intel_display *display = to_intel_display(intel_dp); 313 struct intel_connector *connector = intel_dp->attached_connector; 314 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 315 struct intel_encoder *encoder = &intel_dig_port->base; 316 317 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp); 318 319 switch (intel_dp->max_sink_lane_count) { 320 case 1: 321 case 2: 322 case 4: 323 return; 324 } 325 326 drm_err(display->drm, 327 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", 328 connector->base.base.id, connector->base.name, 329 encoder->base.base.id, encoder->base.name, 330 intel_dp->max_sink_lane_count); 331 332 intel_dp_set_default_max_sink_lane_count(intel_dp); 333 } 334 335 /* Get length of rates array potentially limited by max_rate. */ 336 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) 337 { 338 int i; 339 340 /* Limit results by potentially reduced max rate */ 341 for (i = 0; i < len; i++) { 342 if (rates[len - i - 1] <= max_rate) 343 return len - i; 344 } 345 346 return 0; 347 } 348 349 /* Get length of common rates array potentially limited by max_rate. */ 350 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, 351 int max_rate) 352 { 353 return intel_dp_rate_limit_len(intel_dp->common_rates, 354 intel_dp->num_common_rates, max_rate); 355 } 356 357 int intel_dp_common_rate(struct intel_dp *intel_dp, int index) 358 { 359 struct intel_display *display = to_intel_display(intel_dp); 360 361 if (drm_WARN_ON(display->drm, 362 index < 0 || index >= intel_dp->num_common_rates)) 363 return 162000; 364 365 return intel_dp->common_rates[index]; 366 } 367 368 /* Theoretical max between source and sink */ 369 int intel_dp_max_common_rate(struct intel_dp *intel_dp) 370 { 371 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); 372 } 373 374 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) 375 { 376 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); 377 int max_lanes = dig_port->max_lanes; 378 379 if (vbt_max_lanes) 380 max_lanes = min(max_lanes, vbt_max_lanes); 381 382 return max_lanes; 383 } 384 385 /* Theoretical max between source and sink */ 386 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) 387 { 388 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 389 int source_max = intel_dp_max_source_lane_count(dig_port); 390 int sink_max = intel_dp->max_sink_lane_count; 391 int lane_max = intel_tc_port_max_lane_count(dig_port); 392 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); 393 394 if (lttpr_max) 395 sink_max = min(sink_max, lttpr_max); 396 397 return min3(source_max, sink_max, lane_max); 398 } 399 400 static int forced_lane_count(struct intel_dp *intel_dp) 401 { 402 return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp)); 403 } 404 405 int intel_dp_max_lane_count(struct intel_dp *intel_dp) 406 { 407 int lane_count; 408 409 if (intel_dp->link.force_lane_count) 410 lane_count = forced_lane_count(intel_dp); 411 else 412 lane_count = intel_dp->link.max_lane_count; 413 414 switch (lane_count) { 415 case 1: 416 case 2: 417 case 4: 418 return lane_count; 419 default: 420 MISSING_CASE(lane_count); 421 return 1; 422 } 423 } 424 425 static int intel_dp_min_lane_count(struct intel_dp *intel_dp) 426 { 427 if (intel_dp->link.force_lane_count) 428 return forced_lane_count(intel_dp); 429 430 return 1; 431 } 432 433 /* 434 * The required data bandwidth for a mode with given pixel clock and bpp. This 435 * is the required net bandwidth independent of the data bandwidth efficiency. 436 * 437 * TODO: check if callers of this functions should use 438 * intel_dp_effective_data_rate() instead. 439 */ 440 int 441 intel_dp_link_required(int pixel_clock, int bpp) 442 { 443 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 444 return DIV_ROUND_UP(pixel_clock * bpp, 8); 445 } 446 447 /** 448 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead 449 * @pixel_clock: pixel clock in kHz 450 * @bpp_x16: bits per pixel .4 fixed point format 451 * @bw_overhead: BW allocation overhead in 1ppm units 452 * 453 * Return the effective pixel data rate in kB/sec units taking into account 454 * the provided SSC, FEC, DSC BW allocation overhead. 455 */ 456 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 457 int bw_overhead) 458 { 459 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead), 460 1000000 * 16 * 8); 461 } 462 463 /** 464 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params 465 * @intel_dp: Intel DP object 466 * @max_dprx_rate: Maximum data rate of the DPRX 467 * @max_dprx_lanes: Maximum lane count of the DPRX 468 * 469 * Calculate the maximum data rate for the provided link parameters taking into 470 * account any BW limitations by a DP tunnel attached to @intel_dp. 471 * 472 * Returns the maximum data rate in kBps units. 473 */ 474 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, 475 int max_dprx_rate, int max_dprx_lanes) 476 { 477 int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes); 478 479 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 480 max_rate = min(max_rate, 481 drm_dp_tunnel_available_bw(intel_dp->tunnel)); 482 483 return max_rate; 484 } 485 486 bool intel_dp_has_joiner(struct intel_dp *intel_dp) 487 { 488 struct intel_display *display = to_intel_display(intel_dp); 489 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 490 struct intel_encoder *encoder = &intel_dig_port->base; 491 492 /* eDP MSO is not compatible with joiner */ 493 if (intel_dp->mso_link_count) 494 return false; 495 496 return DISPLAY_VER(display) >= 12 || 497 (DISPLAY_VER(display) == 11 && 498 encoder->port != PORT_A); 499 } 500 501 static int dg2_max_source_rate(struct intel_dp *intel_dp) 502 { 503 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000; 504 } 505 506 static int icl_max_source_rate(struct intel_dp *intel_dp) 507 { 508 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 509 510 if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp)) 511 return 540000; 512 513 return 810000; 514 } 515 516 static int ehl_max_source_rate(struct intel_dp *intel_dp) 517 { 518 if (intel_dp_is_edp(intel_dp)) 519 return 540000; 520 521 return 810000; 522 } 523 524 static int mtl_max_source_rate(struct intel_dp *intel_dp) 525 { 526 struct intel_display *display = to_intel_display(intel_dp); 527 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 528 529 if (intel_encoder_is_c10phy(encoder)) 530 return 810000; 531 532 if (DISPLAY_VERx100(display) == 1401) 533 return 1350000; 534 535 return 2000000; 536 } 537 538 static int vbt_max_link_rate(struct intel_dp *intel_dp) 539 { 540 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 541 int max_rate; 542 543 max_rate = intel_bios_dp_max_link_rate(encoder->devdata); 544 545 if (intel_dp_is_edp(intel_dp)) { 546 struct intel_connector *connector = intel_dp->attached_connector; 547 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; 548 549 if (max_rate && edp_max_rate) 550 max_rate = min(max_rate, edp_max_rate); 551 else if (edp_max_rate) 552 max_rate = edp_max_rate; 553 } 554 555 return max_rate; 556 } 557 558 static void 559 intel_dp_set_source_rates(struct intel_dp *intel_dp) 560 { 561 /* The values must be in increasing order */ 562 static const int bmg_rates[] = { 563 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 564 810000, 1000000, 1350000, 565 }; 566 static const int mtl_rates[] = { 567 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 568 810000, 1000000, 2000000, 569 }; 570 static const int icl_rates[] = { 571 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000, 572 1000000, 1350000, 573 }; 574 static const int bxt_rates[] = { 575 162000, 216000, 243000, 270000, 324000, 432000, 540000 576 }; 577 static const int skl_rates[] = { 578 162000, 216000, 270000, 324000, 432000, 540000 579 }; 580 static const int hsw_rates[] = { 581 162000, 270000, 540000 582 }; 583 static const int g4x_rates[] = { 584 162000, 270000 585 }; 586 struct intel_display *display = to_intel_display(intel_dp); 587 const int *source_rates; 588 int size, max_rate = 0, vbt_max_rate; 589 590 /* This should only be done once */ 591 drm_WARN_ON(display->drm, 592 intel_dp->source_rates || intel_dp->num_source_rates); 593 594 if (DISPLAY_VER(display) >= 14) { 595 if (display->platform.battlemage) { 596 source_rates = bmg_rates; 597 size = ARRAY_SIZE(bmg_rates); 598 } else { 599 source_rates = mtl_rates; 600 size = ARRAY_SIZE(mtl_rates); 601 } 602 max_rate = mtl_max_source_rate(intel_dp); 603 } else if (DISPLAY_VER(display) >= 11) { 604 source_rates = icl_rates; 605 size = ARRAY_SIZE(icl_rates); 606 if (display->platform.dg2) 607 max_rate = dg2_max_source_rate(intel_dp); 608 else if (display->platform.alderlake_p || display->platform.alderlake_s || 609 display->platform.dg1 || display->platform.rocketlake) 610 max_rate = 810000; 611 else if (display->platform.jasperlake || display->platform.elkhartlake) 612 max_rate = ehl_max_source_rate(intel_dp); 613 else 614 max_rate = icl_max_source_rate(intel_dp); 615 } else if (display->platform.geminilake || display->platform.broxton) { 616 source_rates = bxt_rates; 617 size = ARRAY_SIZE(bxt_rates); 618 } else if (DISPLAY_VER(display) == 9) { 619 source_rates = skl_rates; 620 size = ARRAY_SIZE(skl_rates); 621 } else if ((display->platform.haswell && !display->platform.haswell_ulx) || 622 display->platform.broadwell) { 623 source_rates = hsw_rates; 624 size = ARRAY_SIZE(hsw_rates); 625 } else { 626 source_rates = g4x_rates; 627 size = ARRAY_SIZE(g4x_rates); 628 } 629 630 vbt_max_rate = vbt_max_link_rate(intel_dp); 631 if (max_rate && vbt_max_rate) 632 max_rate = min(max_rate, vbt_max_rate); 633 else if (vbt_max_rate) 634 max_rate = vbt_max_rate; 635 636 if (max_rate) 637 size = intel_dp_rate_limit_len(source_rates, size, max_rate); 638 639 intel_dp->source_rates = source_rates; 640 intel_dp->num_source_rates = size; 641 } 642 643 static int intersect_rates(const int *source_rates, int source_len, 644 const int *sink_rates, int sink_len, 645 int *common_rates) 646 { 647 int i = 0, j = 0, k = 0; 648 649 while (i < source_len && j < sink_len) { 650 if (source_rates[i] == sink_rates[j]) { 651 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 652 return k; 653 common_rates[k] = source_rates[i]; 654 ++k; 655 ++i; 656 ++j; 657 } else if (source_rates[i] < sink_rates[j]) { 658 ++i; 659 } else { 660 ++j; 661 } 662 } 663 return k; 664 } 665 666 /* return index of rate in rates array, or -1 if not found */ 667 int intel_dp_rate_index(const int *rates, int len, int rate) 668 { 669 int i; 670 671 for (i = 0; i < len; i++) 672 if (rate == rates[i]) 673 return i; 674 675 return -1; 676 } 677 678 static int intel_dp_link_config_rate(struct intel_dp *intel_dp, 679 const struct intel_dp_link_config *lc) 680 { 681 return intel_dp_common_rate(intel_dp, lc->link_rate_idx); 682 } 683 684 static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc) 685 { 686 return 1 << lc->lane_count_exp; 687 } 688 689 static int intel_dp_link_config_bw(struct intel_dp *intel_dp, 690 const struct intel_dp_link_config *lc) 691 { 692 return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc), 693 intel_dp_link_config_lane_count(lc)); 694 } 695 696 static int link_config_cmp_by_bw(const void *a, const void *b, const void *p) 697 { 698 struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */ 699 const struct intel_dp_link_config *lc_a = a; 700 const struct intel_dp_link_config *lc_b = b; 701 int bw_a = intel_dp_link_config_bw(intel_dp, lc_a); 702 int bw_b = intel_dp_link_config_bw(intel_dp, lc_b); 703 704 if (bw_a != bw_b) 705 return bw_a - bw_b; 706 707 return intel_dp_link_config_rate(intel_dp, lc_a) - 708 intel_dp_link_config_rate(intel_dp, lc_b); 709 } 710 711 static void intel_dp_link_config_init(struct intel_dp *intel_dp) 712 { 713 struct intel_display *display = to_intel_display(intel_dp); 714 struct intel_dp_link_config *lc; 715 int num_common_lane_configs; 716 int i; 717 int j; 718 719 if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp)))) 720 return; 721 722 num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1; 723 724 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs > 725 ARRAY_SIZE(intel_dp->link.configs))) 726 return; 727 728 intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs; 729 730 lc = &intel_dp->link.configs[0]; 731 for (i = 0; i < intel_dp->num_common_rates; i++) { 732 for (j = 0; j < num_common_lane_configs; j++) { 733 lc->lane_count_exp = j; 734 lc->link_rate_idx = i; 735 736 lc++; 737 } 738 } 739 740 sort_r(intel_dp->link.configs, intel_dp->link.num_configs, 741 sizeof(intel_dp->link.configs[0]), 742 link_config_cmp_by_bw, NULL, 743 intel_dp); 744 } 745 746 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) 747 { 748 struct intel_display *display = to_intel_display(intel_dp); 749 const struct intel_dp_link_config *lc; 750 751 if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs)) 752 idx = 0; 753 754 lc = &intel_dp->link.configs[idx]; 755 756 *link_rate = intel_dp_link_config_rate(intel_dp, lc); 757 *lane_count = intel_dp_link_config_lane_count(lc); 758 } 759 760 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) 761 { 762 int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, 763 link_rate); 764 int lane_count_exp = ilog2(lane_count); 765 int i; 766 767 for (i = 0; i < intel_dp->link.num_configs; i++) { 768 const struct intel_dp_link_config *lc = &intel_dp->link.configs[i]; 769 770 if (lc->lane_count_exp == lane_count_exp && 771 lc->link_rate_idx == link_rate_idx) 772 return i; 773 } 774 775 return -1; 776 } 777 778 static void intel_dp_set_common_rates(struct intel_dp *intel_dp) 779 { 780 struct intel_display *display = to_intel_display(intel_dp); 781 782 drm_WARN_ON(display->drm, 783 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); 784 785 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, 786 intel_dp->num_source_rates, 787 intel_dp->sink_rates, 788 intel_dp->num_sink_rates, 789 intel_dp->common_rates); 790 791 /* Paranoia, there should always be something in common. */ 792 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) { 793 intel_dp->common_rates[0] = 162000; 794 intel_dp->num_common_rates = 1; 795 } 796 797 intel_dp_link_config_init(intel_dp); 798 } 799 800 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 801 u8 lane_count) 802 { 803 /* 804 * FIXME: we need to synchronize the current link parameters with 805 * hardware readout. Currently fast link training doesn't work on 806 * boot-up. 807 */ 808 if (link_rate == 0 || 809 link_rate > intel_dp->link.max_rate) 810 return false; 811 812 if (lane_count == 0 || 813 lane_count > intel_dp_max_lane_count(intel_dp)) 814 return false; 815 816 return true; 817 } 818 819 u32 intel_dp_mode_to_fec_clock(u32 mode_clock) 820 { 821 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), 822 1000000U); 823 } 824 825 int intel_dp_bw_fec_overhead(bool fec_enabled) 826 { 827 /* 828 * TODO: Calculate the actual overhead for a given mode. 829 * The hard-coded 1/0.972261=2.853% overhead factor 830 * corresponds (for instance) to the 8b/10b DP FEC 2.4% + 831 * 0.453% DSC overhead. This is enough for a 3840 width mode, 832 * which has a DSC overhead of up to ~0.2%, but may not be 833 * enough for a 1024 width mode where this is ~0.8% (on a 4 834 * lane DP link, with 2 DSC slices and 8 bpp color depth). 835 */ 836 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000; 837 } 838 839 static int 840 small_joiner_ram_size_bits(struct intel_display *display) 841 { 842 if (DISPLAY_VER(display) >= 13) 843 return 17280 * 8; 844 else if (DISPLAY_VER(display) >= 11) 845 return 7680 * 8; 846 else 847 return 6144 * 8; 848 } 849 850 u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) 851 { 852 u32 bits_per_pixel = bpp; 853 int i; 854 855 /* Error out if the max bpp is less than smallest allowed valid bpp */ 856 if (bits_per_pixel < valid_dsc_bpp[0]) { 857 drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n", 858 bits_per_pixel, valid_dsc_bpp[0]); 859 return 0; 860 } 861 862 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ 863 if (DISPLAY_VER(display) >= 13) { 864 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); 865 866 /* 867 * According to BSpec, 27 is the max DSC output bpp, 868 * 8 is the min DSC output bpp. 869 * While we can still clamp higher bpp values to 27, saving bandwidth, 870 * if it is required to oompress up to bpp < 8, means we can't do 871 * that and probably means we can't fit the required mode, even with 872 * DSC enabled. 873 */ 874 if (bits_per_pixel < 8) { 875 drm_dbg_kms(display->drm, 876 "Unsupported BPP %u, min 8\n", 877 bits_per_pixel); 878 return 0; 879 } 880 bits_per_pixel = min_t(u32, bits_per_pixel, 27); 881 } else { 882 /* Find the nearest match in the array of known BPPs from VESA */ 883 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { 884 if (bits_per_pixel < valid_dsc_bpp[i + 1]) 885 break; 886 } 887 drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n", 888 bits_per_pixel, valid_dsc_bpp[i]); 889 890 bits_per_pixel = valid_dsc_bpp[i]; 891 } 892 893 return bits_per_pixel; 894 } 895 896 static int bigjoiner_interface_bits(struct intel_display *display) 897 { 898 return DISPLAY_VER(display) >= 14 ? 36 : 24; 899 } 900 901 static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock, 902 int num_joined_pipes) 903 { 904 u32 max_bpp; 905 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ 906 int ppc = 2; 907 int num_big_joiners = num_joined_pipes / 2; 908 909 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) / 910 intel_dp_mode_to_fec_clock(mode_clock); 911 912 max_bpp *= num_big_joiners; 913 914 return max_bpp; 915 916 } 917 918 static u32 small_joiner_ram_max_bpp(struct intel_display *display, 919 u32 mode_hdisplay, 920 int num_joined_pipes) 921 { 922 u32 max_bpp; 923 924 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ 925 max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay; 926 927 max_bpp *= num_joined_pipes; 928 929 return max_bpp; 930 } 931 932 static int ultrajoiner_ram_bits(void) 933 { 934 return 4 * 72 * 512; 935 } 936 937 static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay) 938 { 939 return ultrajoiner_ram_bits() / mode_hdisplay; 940 } 941 942 static 943 u32 get_max_compressed_bpp_with_joiner(struct intel_display *display, 944 u32 mode_clock, u32 mode_hdisplay, 945 int num_joined_pipes) 946 { 947 u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes); 948 949 if (num_joined_pipes > 1) 950 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock, 951 num_joined_pipes)); 952 if (num_joined_pipes == 4) 953 max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay)); 954 955 return max_bpp; 956 } 957 958 u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display, 959 u32 link_clock, u32 lane_count, 960 u32 mode_clock, u32 mode_hdisplay, 961 int num_joined_pipes, 962 enum intel_output_format output_format, 963 u32 pipe_bpp, 964 u32 timeslots) 965 { 966 u32 bits_per_pixel, joiner_max_bpp; 967 968 /* 969 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* 970 * (LinkSymbolClock)* 8 * (TimeSlots / 64) 971 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) 972 * for MST -> TimeSlots has to be calculated, based on mode requirements 973 * 974 * Due to FEC overhead, the available bw is reduced to 97.2261%. 975 * To support the given mode: 976 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead 977 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead 978 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock 979 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) / 980 * (ModeClock / FEC Overhead) 981 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) / 982 * (ModeClock / FEC Overhead * 8) 983 */ 984 bits_per_pixel = ((link_clock * lane_count) * timeslots) / 985 (intel_dp_mode_to_fec_clock(mode_clock) * 8); 986 987 /* Bandwidth required for 420 is half, that of 444 format */ 988 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 989 bits_per_pixel *= 2; 990 991 /* 992 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum 993 * supported PPS value can be 63.9375 and with the further 994 * mention that for 420, 422 formats, bpp should be programmed double 995 * the target bpp restricting our target bpp to be 31.9375 at max. 996 */ 997 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 998 bits_per_pixel = min_t(u32, bits_per_pixel, 31); 999 1000 drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots " 1001 "total bw %u pixel clock %u\n", 1002 bits_per_pixel, timeslots, 1003 (link_clock * lane_count * 8), 1004 intel_dp_mode_to_fec_clock(mode_clock)); 1005 1006 joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock, 1007 mode_hdisplay, num_joined_pipes); 1008 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); 1009 1010 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp); 1011 1012 return bits_per_pixel; 1013 } 1014 1015 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 1016 int mode_clock, int mode_hdisplay, 1017 int num_joined_pipes) 1018 { 1019 struct intel_display *display = to_intel_display(connector); 1020 u8 min_slice_count, i; 1021 int max_slice_width; 1022 1023 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) 1024 min_slice_count = DIV_ROUND_UP(mode_clock, 1025 DP_DSC_MAX_ENC_THROUGHPUT_0); 1026 else 1027 min_slice_count = DIV_ROUND_UP(mode_clock, 1028 DP_DSC_MAX_ENC_THROUGHPUT_1); 1029 1030 /* 1031 * Due to some DSC engine BW limitations, we need to enable second 1032 * slice and VDSC engine, whenever we approach close enough to max CDCLK 1033 */ 1034 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100)) 1035 min_slice_count = max_t(u8, min_slice_count, 2); 1036 1037 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); 1038 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { 1039 drm_dbg_kms(display->drm, 1040 "Unsupported slice width %d by DP DSC Sink device\n", 1041 max_slice_width); 1042 return 0; 1043 } 1044 /* Also take into account max slice width */ 1045 min_slice_count = max_t(u8, min_slice_count, 1046 DIV_ROUND_UP(mode_hdisplay, 1047 max_slice_width)); 1048 1049 /* Find the closest match to the valid slice count values */ 1050 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { 1051 u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes; 1052 1053 /* 1054 * 3 DSC Slices per pipe need 3 DSC engines, which is supported only 1055 * with Ultrajoiner only for some platforms. 1056 */ 1057 if (valid_dsc_slicecount[i] == 3 && 1058 (!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4)) 1059 continue; 1060 1061 if (test_slice_count > 1062 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) 1063 break; 1064 1065 /* 1066 * Bigjoiner needs small joiner to be enabled. 1067 * So there should be at least 2 dsc slices per pipe, 1068 * whenever bigjoiner is enabled. 1069 */ 1070 if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2) 1071 continue; 1072 1073 if (mode_hdisplay % test_slice_count) 1074 continue; 1075 1076 if (min_slice_count <= test_slice_count) 1077 return test_slice_count; 1078 } 1079 1080 drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n", 1081 min_slice_count); 1082 return 0; 1083 } 1084 1085 static bool source_can_output(struct intel_dp *intel_dp, 1086 enum intel_output_format format) 1087 { 1088 struct intel_display *display = to_intel_display(intel_dp); 1089 1090 switch (format) { 1091 case INTEL_OUTPUT_FORMAT_RGB: 1092 return true; 1093 1094 case INTEL_OUTPUT_FORMAT_YCBCR444: 1095 /* 1096 * No YCbCr output support on gmch platforms. 1097 * Also, ILK doesn't seem capable of DP YCbCr output. 1098 * The displayed image is severely corrupted. SNB+ is fine. 1099 */ 1100 return !HAS_GMCH(display) && !display->platform.ironlake; 1101 1102 case INTEL_OUTPUT_FORMAT_YCBCR420: 1103 /* Platform < Gen 11 cannot output YCbCr420 format */ 1104 return DISPLAY_VER(display) >= 11; 1105 1106 default: 1107 MISSING_CASE(format); 1108 return false; 1109 } 1110 } 1111 1112 static bool 1113 dfp_can_convert_from_rgb(struct intel_dp *intel_dp, 1114 enum intel_output_format sink_format) 1115 { 1116 if (!drm_dp_is_branch(intel_dp->dpcd)) 1117 return false; 1118 1119 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1120 return intel_dp->dfp.rgb_to_ycbcr; 1121 1122 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1123 return intel_dp->dfp.rgb_to_ycbcr && 1124 intel_dp->dfp.ycbcr_444_to_420; 1125 1126 return false; 1127 } 1128 1129 static bool 1130 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, 1131 enum intel_output_format sink_format) 1132 { 1133 if (!drm_dp_is_branch(intel_dp->dpcd)) 1134 return false; 1135 1136 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1137 return intel_dp->dfp.ycbcr_444_to_420; 1138 1139 return false; 1140 } 1141 1142 static bool 1143 dfp_can_convert(struct intel_dp *intel_dp, 1144 enum intel_output_format output_format, 1145 enum intel_output_format sink_format) 1146 { 1147 switch (output_format) { 1148 case INTEL_OUTPUT_FORMAT_RGB: 1149 return dfp_can_convert_from_rgb(intel_dp, sink_format); 1150 case INTEL_OUTPUT_FORMAT_YCBCR444: 1151 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format); 1152 default: 1153 MISSING_CASE(output_format); 1154 return false; 1155 } 1156 1157 return false; 1158 } 1159 1160 static enum intel_output_format 1161 intel_dp_output_format(struct intel_connector *connector, 1162 enum intel_output_format sink_format) 1163 { 1164 struct intel_display *display = to_intel_display(connector); 1165 struct intel_dp *intel_dp = intel_attached_dp(connector); 1166 enum intel_output_format force_dsc_output_format = 1167 intel_dp->force_dsc_output_format; 1168 enum intel_output_format output_format; 1169 if (force_dsc_output_format) { 1170 if (source_can_output(intel_dp, force_dsc_output_format) && 1171 (!drm_dp_is_branch(intel_dp->dpcd) || 1172 sink_format != force_dsc_output_format || 1173 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format))) 1174 return force_dsc_output_format; 1175 1176 drm_dbg_kms(display->drm, "Cannot force DSC output format\n"); 1177 } 1178 1179 if (sink_format == INTEL_OUTPUT_FORMAT_RGB || 1180 dfp_can_convert_from_rgb(intel_dp, sink_format)) 1181 output_format = INTEL_OUTPUT_FORMAT_RGB; 1182 1183 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 1184 dfp_can_convert_from_ycbcr444(intel_dp, sink_format)) 1185 output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 1186 1187 else 1188 output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1189 1190 drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format)); 1191 1192 return output_format; 1193 } 1194 1195 int intel_dp_min_bpp(enum intel_output_format output_format) 1196 { 1197 if (output_format == INTEL_OUTPUT_FORMAT_RGB) 1198 return 6 * 3; 1199 else 1200 return 8 * 3; 1201 } 1202 1203 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) 1204 { 1205 /* 1206 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output 1207 * format of the number of bytes per pixel will be half the number 1208 * of bytes of RGB pixel. 1209 */ 1210 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1211 bpp /= 2; 1212 1213 return bpp; 1214 } 1215 1216 static enum intel_output_format 1217 intel_dp_sink_format(struct intel_connector *connector, 1218 const struct drm_display_mode *mode) 1219 { 1220 const struct drm_display_info *info = &connector->base.display_info; 1221 1222 if (drm_mode_is_420_only(info, mode)) 1223 return INTEL_OUTPUT_FORMAT_YCBCR420; 1224 1225 return INTEL_OUTPUT_FORMAT_RGB; 1226 } 1227 1228 static int 1229 intel_dp_mode_min_output_bpp(struct intel_connector *connector, 1230 const struct drm_display_mode *mode) 1231 { 1232 enum intel_output_format output_format, sink_format; 1233 1234 sink_format = intel_dp_sink_format(connector, mode); 1235 1236 output_format = intel_dp_output_format(connector, sink_format); 1237 1238 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); 1239 } 1240 1241 static bool intel_dp_hdisplay_bad(struct intel_display *display, 1242 int hdisplay) 1243 { 1244 /* 1245 * Older platforms don't like hdisplay==4096 with DP. 1246 * 1247 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline 1248 * and frame counter increment), but we don't get vblank interrupts, 1249 * and the pipe underruns immediately. The link also doesn't seem 1250 * to get trained properly. 1251 * 1252 * On CHV the vblank interrupts don't seem to disappear but 1253 * otherwise the symptoms are similar. 1254 * 1255 * TODO: confirm the behaviour on HSW+ 1256 */ 1257 return hdisplay == 4096 && !HAS_DDI(display); 1258 } 1259 1260 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp) 1261 { 1262 struct intel_connector *connector = intel_dp->attached_connector; 1263 const struct drm_display_info *info = &connector->base.display_info; 1264 int max_tmds_clock = intel_dp->dfp.max_tmds_clock; 1265 1266 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */ 1267 if (max_tmds_clock && info->max_tmds_clock) 1268 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); 1269 1270 return max_tmds_clock; 1271 } 1272 1273 static enum drm_mode_status 1274 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, 1275 int clock, int bpc, 1276 enum intel_output_format sink_format, 1277 bool respect_downstream_limits) 1278 { 1279 int tmds_clock, min_tmds_clock, max_tmds_clock; 1280 1281 if (!respect_downstream_limits) 1282 return MODE_OK; 1283 1284 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1285 1286 min_tmds_clock = intel_dp->dfp.min_tmds_clock; 1287 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp); 1288 1289 if (min_tmds_clock && tmds_clock < min_tmds_clock) 1290 return MODE_CLOCK_LOW; 1291 1292 if (max_tmds_clock && tmds_clock > max_tmds_clock) 1293 return MODE_CLOCK_HIGH; 1294 1295 return MODE_OK; 1296 } 1297 1298 static enum drm_mode_status 1299 intel_dp_mode_valid_downstream(struct intel_connector *connector, 1300 const struct drm_display_mode *mode, 1301 int target_clock) 1302 { 1303 struct intel_dp *intel_dp = intel_attached_dp(connector); 1304 const struct drm_display_info *info = &connector->base.display_info; 1305 enum drm_mode_status status; 1306 enum intel_output_format sink_format; 1307 1308 /* If PCON supports FRL MODE, check FRL bandwidth constraints */ 1309 if (intel_dp->dfp.pcon_max_frl_bw) { 1310 int target_bw; 1311 int max_frl_bw; 1312 int bpp = intel_dp_mode_min_output_bpp(connector, mode); 1313 1314 target_bw = bpp * target_clock; 1315 1316 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 1317 1318 /* converting bw from Gbps to Kbps*/ 1319 max_frl_bw = max_frl_bw * 1000000; 1320 1321 if (target_bw > max_frl_bw) 1322 return MODE_CLOCK_HIGH; 1323 1324 return MODE_OK; 1325 } 1326 1327 if (intel_dp->dfp.max_dotclock && 1328 target_clock > intel_dp->dfp.max_dotclock) 1329 return MODE_CLOCK_HIGH; 1330 1331 sink_format = intel_dp_sink_format(connector, mode); 1332 1333 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ 1334 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1335 8, sink_format, true); 1336 1337 if (status != MODE_OK) { 1338 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 1339 !connector->base.ycbcr_420_allowed || 1340 !drm_mode_is_420_also(info, mode)) 1341 return status; 1342 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1343 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1344 8, sink_format, true); 1345 if (status != MODE_OK) 1346 return status; 1347 } 1348 1349 return MODE_OK; 1350 } 1351 1352 static 1353 bool intel_dp_needs_joiner(struct intel_dp *intel_dp, 1354 struct intel_connector *connector, 1355 int hdisplay, int clock, 1356 int num_joined_pipes) 1357 { 1358 struct intel_display *display = to_intel_display(intel_dp); 1359 int hdisplay_limit; 1360 1361 if (!intel_dp_has_joiner(intel_dp)) 1362 return false; 1363 1364 num_joined_pipes /= 2; 1365 1366 hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120; 1367 1368 return clock > num_joined_pipes * display->cdclk.max_dotclk_freq || 1369 hdisplay > num_joined_pipes * hdisplay_limit; 1370 } 1371 1372 int intel_dp_num_joined_pipes(struct intel_dp *intel_dp, 1373 struct intel_connector *connector, 1374 int hdisplay, int clock) 1375 { 1376 struct intel_display *display = to_intel_display(intel_dp); 1377 1378 if (connector->force_joined_pipes) 1379 return connector->force_joined_pipes; 1380 1381 if (HAS_ULTRAJOINER(display) && 1382 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4)) 1383 return 4; 1384 1385 if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) && 1386 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2)) 1387 return 2; 1388 1389 return 1; 1390 } 1391 1392 bool intel_dp_has_dsc(const struct intel_connector *connector) 1393 { 1394 struct intel_display *display = to_intel_display(connector); 1395 1396 if (!HAS_DSC(display)) 1397 return false; 1398 1399 if (connector->mst.dp && !HAS_DSC_MST(display)) 1400 return false; 1401 1402 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && 1403 connector->panel.vbt.edp.dsc_disable) 1404 return false; 1405 1406 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) 1407 return false; 1408 1409 return true; 1410 } 1411 1412 static enum drm_mode_status 1413 intel_dp_mode_valid(struct drm_connector *_connector, 1414 const struct drm_display_mode *mode) 1415 { 1416 struct intel_display *display = to_intel_display(_connector->dev); 1417 struct intel_connector *connector = to_intel_connector(_connector); 1418 struct intel_dp *intel_dp = intel_attached_dp(connector); 1419 const struct drm_display_mode *fixed_mode; 1420 int target_clock = mode->clock; 1421 int max_rate, mode_rate, max_lanes, max_link_clock; 1422 int max_dotclk = display->cdclk.max_dotclk_freq; 1423 u16 dsc_max_compressed_bpp = 0; 1424 u8 dsc_slice_count = 0; 1425 enum drm_mode_status status; 1426 bool dsc = false; 1427 int num_joined_pipes; 1428 1429 status = intel_cpu_transcoder_mode_valid(display, mode); 1430 if (status != MODE_OK) 1431 return status; 1432 1433 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1434 return MODE_H_ILLEGAL; 1435 1436 if (mode->clock < 10000) 1437 return MODE_CLOCK_LOW; 1438 1439 fixed_mode = intel_panel_fixed_mode(connector, mode); 1440 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 1441 status = intel_panel_mode_valid(connector, mode); 1442 if (status != MODE_OK) 1443 return status; 1444 1445 target_clock = fixed_mode->clock; 1446 } 1447 1448 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, 1449 mode->hdisplay, target_clock); 1450 max_dotclk *= num_joined_pipes; 1451 1452 if (target_clock > max_dotclk) 1453 return MODE_CLOCK_HIGH; 1454 1455 if (intel_dp_hdisplay_bad(display, mode->hdisplay)) 1456 return MODE_H_ILLEGAL; 1457 1458 max_link_clock = intel_dp_max_link_rate(intel_dp); 1459 max_lanes = intel_dp_max_lane_count(intel_dp); 1460 1461 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); 1462 1463 mode_rate = intel_dp_link_required(target_clock, 1464 intel_dp_mode_min_output_bpp(connector, mode)); 1465 1466 if (intel_dp_has_dsc(connector)) { 1467 enum intel_output_format sink_format, output_format; 1468 int pipe_bpp; 1469 1470 sink_format = intel_dp_sink_format(connector, mode); 1471 output_format = intel_dp_output_format(connector, sink_format); 1472 /* 1473 * TBD pass the connector BPC, 1474 * for now U8_MAX so that max BPC on that platform would be picked 1475 */ 1476 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); 1477 1478 /* 1479 * Output bpp is stored in 6.4 format so right shift by 4 to get the 1480 * integer value since we support only integer values of bpp. 1481 */ 1482 if (intel_dp_is_edp(intel_dp)) { 1483 dsc_max_compressed_bpp = 1484 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; 1485 dsc_slice_count = 1486 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 1487 true); 1488 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { 1489 dsc_max_compressed_bpp = 1490 intel_dp_dsc_get_max_compressed_bpp(display, 1491 max_link_clock, 1492 max_lanes, 1493 target_clock, 1494 mode->hdisplay, 1495 num_joined_pipes, 1496 output_format, 1497 pipe_bpp, 64); 1498 dsc_slice_count = 1499 intel_dp_dsc_get_slice_count(connector, 1500 target_clock, 1501 mode->hdisplay, 1502 num_joined_pipes); 1503 } 1504 1505 dsc = dsc_max_compressed_bpp && dsc_slice_count; 1506 } 1507 1508 if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) 1509 return MODE_CLOCK_HIGH; 1510 1511 if (mode_rate > max_rate && !dsc) 1512 return MODE_CLOCK_HIGH; 1513 1514 status = intel_dp_mode_valid_downstream(connector, mode, target_clock); 1515 if (status != MODE_OK) 1516 return status; 1517 1518 return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes); 1519 } 1520 1521 bool intel_dp_source_supports_tps3(struct intel_display *display) 1522 { 1523 return DISPLAY_VER(display) >= 9 || 1524 display->platform.broadwell || display->platform.haswell; 1525 } 1526 1527 bool intel_dp_source_supports_tps4(struct intel_display *display) 1528 { 1529 return DISPLAY_VER(display) >= 10; 1530 } 1531 1532 static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem) 1533 { 1534 int i; 1535 1536 for (i = 0; i < nelem; i++) 1537 seq_buf_printf(s, "%s%d", i ? ", " : "", array[i]); 1538 } 1539 1540 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1541 { 1542 struct intel_display *display = to_intel_display(intel_dp); 1543 DECLARE_SEQ_BUF(s, 128); /* FIXME: too big for stack? */ 1544 1545 if (!drm_debug_enabled(DRM_UT_KMS)) 1546 return; 1547 1548 seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates); 1549 drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s)); 1550 1551 seq_buf_clear(&s); 1552 seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates); 1553 drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s)); 1554 1555 seq_buf_clear(&s); 1556 seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates); 1557 drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s)); 1558 } 1559 1560 static int forced_link_rate(struct intel_dp *intel_dp) 1561 { 1562 int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate); 1563 1564 if (len == 0) 1565 return intel_dp_common_rate(intel_dp, 0); 1566 1567 return intel_dp_common_rate(intel_dp, len - 1); 1568 } 1569 1570 int 1571 intel_dp_max_link_rate(struct intel_dp *intel_dp) 1572 { 1573 int len; 1574 1575 if (intel_dp->link.force_rate) 1576 return forced_link_rate(intel_dp); 1577 1578 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate); 1579 1580 return intel_dp_common_rate(intel_dp, len - 1); 1581 } 1582 1583 static int 1584 intel_dp_min_link_rate(struct intel_dp *intel_dp) 1585 { 1586 if (intel_dp->link.force_rate) 1587 return forced_link_rate(intel_dp); 1588 1589 return intel_dp_common_rate(intel_dp, 0); 1590 } 1591 1592 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1593 { 1594 struct intel_display *display = to_intel_display(intel_dp); 1595 int i = intel_dp_rate_index(intel_dp->sink_rates, 1596 intel_dp->num_sink_rates, rate); 1597 1598 if (drm_WARN_ON(display->drm, i < 0)) 1599 i = 0; 1600 1601 return i; 1602 } 1603 1604 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1605 u8 *link_bw, u8 *rate_select) 1606 { 1607 /* eDP 1.4 rate select method. */ 1608 if (intel_dp->use_rate_select) { 1609 *link_bw = 0; 1610 *rate_select = 1611 intel_dp_rate_select(intel_dp, port_clock); 1612 } else { 1613 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1614 *rate_select = 0; 1615 } 1616 } 1617 1618 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp) 1619 { 1620 struct intel_connector *connector = intel_dp->attached_connector; 1621 1622 return connector->base.display_info.is_hdmi; 1623 } 1624 1625 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 1626 const struct intel_crtc_state *pipe_config) 1627 { 1628 struct intel_display *display = to_intel_display(intel_dp); 1629 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1630 1631 if (DISPLAY_VER(display) >= 12) 1632 return true; 1633 1634 if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A && 1635 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) 1636 return true; 1637 1638 return false; 1639 } 1640 1641 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 1642 const struct intel_connector *connector, 1643 const struct intel_crtc_state *pipe_config) 1644 { 1645 return intel_dp_source_supports_fec(intel_dp, pipe_config) && 1646 drm_dp_sink_supports_fec(connector->dp.fec_capability); 1647 } 1648 1649 bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 1650 const struct intel_connector *connector, 1651 const struct intel_crtc_state *crtc_state) 1652 { 1653 if (!intel_dp_has_dsc(connector)) 1654 return false; 1655 1656 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && 1657 !intel_dp_supports_fec(intel_dp, connector, crtc_state)) 1658 return false; 1659 1660 return intel_dsc_source_support(crtc_state); 1661 } 1662 1663 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, 1664 const struct intel_crtc_state *crtc_state, 1665 int bpc, bool respect_downstream_limits) 1666 { 1667 int clock = crtc_state->hw.adjusted_mode.crtc_clock; 1668 1669 /* 1670 * Current bpc could already be below 8bpc due to 1671 * FDI bandwidth constraints or other limits. 1672 * HDMI minimum is 8bpc however. 1673 */ 1674 bpc = max(bpc, 8); 1675 1676 /* 1677 * We will never exceed downstream TMDS clock limits while 1678 * attempting deep color. If the user insists on forcing an 1679 * out of spec mode they will have to be satisfied with 8bpc. 1680 */ 1681 if (!respect_downstream_limits) 1682 bpc = 8; 1683 1684 for (; bpc >= 8; bpc -= 2) { 1685 if (intel_hdmi_bpc_possible(crtc_state, bpc, 1686 intel_dp_has_hdmi_sink(intel_dp)) && 1687 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, 1688 respect_downstream_limits) == MODE_OK) 1689 return bpc; 1690 } 1691 1692 return -EINVAL; 1693 } 1694 1695 static int intel_dp_max_bpp(struct intel_dp *intel_dp, 1696 const struct intel_crtc_state *crtc_state, 1697 bool respect_downstream_limits) 1698 { 1699 struct intel_display *display = to_intel_display(intel_dp); 1700 struct intel_connector *connector = intel_dp->attached_connector; 1701 int bpp, bpc; 1702 1703 bpc = crtc_state->pipe_bpp / 3; 1704 1705 if (intel_dp->dfp.max_bpc) 1706 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); 1707 1708 if (intel_dp->dfp.min_tmds_clock) { 1709 int max_hdmi_bpc; 1710 1711 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc, 1712 respect_downstream_limits); 1713 if (max_hdmi_bpc < 0) 1714 return 0; 1715 1716 bpc = min(bpc, max_hdmi_bpc); 1717 } 1718 1719 bpp = bpc * 3; 1720 if (intel_dp_is_edp(intel_dp)) { 1721 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1722 if (connector->base.display_info.bpc == 0 && 1723 connector->panel.vbt.edp.bpp && 1724 connector->panel.vbt.edp.bpp < bpp) { 1725 drm_dbg_kms(display->drm, 1726 "clamping bpp for eDP panel to BIOS-provided %i\n", 1727 connector->panel.vbt.edp.bpp); 1728 bpp = connector->panel.vbt.edp.bpp; 1729 } 1730 } 1731 1732 return bpp; 1733 } 1734 1735 static bool has_seamless_m_n(struct intel_connector *connector) 1736 { 1737 struct intel_display *display = to_intel_display(connector); 1738 1739 /* 1740 * Seamless M/N reprogramming only implemented 1741 * for BDW+ double buffered M/N registers so far. 1742 */ 1743 return HAS_DOUBLE_BUFFERED_M_N(display) && 1744 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 1745 } 1746 1747 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state, 1748 const struct drm_connector_state *conn_state) 1749 { 1750 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1751 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1752 1753 /* FIXME a bit of a mess wrt clock vs. crtc_clock */ 1754 if (has_seamless_m_n(connector)) 1755 return intel_panel_highest_mode(connector, adjusted_mode)->clock; 1756 else 1757 return adjusted_mode->crtc_clock; 1758 } 1759 1760 /* Optimize link config in order: max bpp, min clock, min lanes */ 1761 static int 1762 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 1763 struct intel_crtc_state *pipe_config, 1764 const struct drm_connector_state *conn_state, 1765 const struct link_config_limits *limits) 1766 { 1767 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); 1768 int mode_rate, link_rate, link_avail; 1769 1770 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 1771 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); 1772 bpp -= 2 * 3) { 1773 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 1774 1775 mode_rate = intel_dp_link_required(clock, link_bpp); 1776 1777 for (i = 0; i < intel_dp->num_common_rates; i++) { 1778 link_rate = intel_dp_common_rate(intel_dp, i); 1779 if (link_rate < limits->min_rate || 1780 link_rate > limits->max_rate) 1781 continue; 1782 1783 for (lane_count = limits->min_lane_count; 1784 lane_count <= limits->max_lane_count; 1785 lane_count <<= 1) { 1786 link_avail = intel_dp_max_link_data_rate(intel_dp, 1787 link_rate, 1788 lane_count); 1789 1790 1791 if (mode_rate <= link_avail) { 1792 pipe_config->lane_count = lane_count; 1793 pipe_config->pipe_bpp = bpp; 1794 pipe_config->port_clock = link_rate; 1795 1796 return 0; 1797 } 1798 } 1799 } 1800 } 1801 1802 return -EINVAL; 1803 } 1804 1805 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display) 1806 { 1807 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 1808 if (DISPLAY_VER(display) >= 12) 1809 return 12; 1810 if (DISPLAY_VER(display) == 11) 1811 return 10; 1812 1813 return intel_dp_dsc_min_src_input_bpc(); 1814 } 1815 1816 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 1817 u8 max_req_bpc) 1818 { 1819 struct intel_display *display = to_intel_display(connector); 1820 int i, num_bpc; 1821 u8 dsc_bpc[3] = {}; 1822 int dsc_max_bpc; 1823 1824 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 1825 1826 if (!dsc_max_bpc) 1827 return dsc_max_bpc; 1828 1829 dsc_max_bpc = min(dsc_max_bpc, max_req_bpc); 1830 1831 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, 1832 dsc_bpc); 1833 for (i = 0; i < num_bpc; i++) { 1834 if (dsc_max_bpc >= dsc_bpc[i]) 1835 return dsc_bpc[i] * 3; 1836 } 1837 1838 return 0; 1839 } 1840 1841 static int intel_dp_source_dsc_version_minor(struct intel_display *display) 1842 { 1843 return DISPLAY_VER(display) >= 14 ? 2 : 1; 1844 } 1845 1846 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 1847 { 1848 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> 1849 DP_DSC_MINOR_SHIFT; 1850 } 1851 1852 static int intel_dp_get_slice_height(int vactive) 1853 { 1854 int slice_height; 1855 1856 /* 1857 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108 1858 * lines is an optimal slice height, but any size can be used as long as 1859 * vertical active integer multiple and maximum vertical slice count 1860 * requirements are met. 1861 */ 1862 for (slice_height = 108; slice_height <= vactive; slice_height += 2) 1863 if (vactive % slice_height == 0) 1864 return slice_height; 1865 1866 /* 1867 * Highly unlikely we reach here as most of the resolutions will end up 1868 * finding appropriate slice_height in above loop but returning 1869 * slice_height as 2 here as it should work with all resolutions. 1870 */ 1871 return 2; 1872 } 1873 1874 static int intel_dp_dsc_compute_params(const struct intel_connector *connector, 1875 struct intel_crtc_state *crtc_state) 1876 { 1877 struct intel_display *display = to_intel_display(connector); 1878 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1879 int ret; 1880 1881 /* 1882 * RC_MODEL_SIZE is currently a constant across all configurations. 1883 * 1884 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and 1885 * DP_DSC_RC_BUF_SIZE for this. 1886 */ 1887 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1888 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1889 1890 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); 1891 1892 ret = intel_dsc_compute_params(crtc_state); 1893 if (ret) 1894 return ret; 1895 1896 vdsc_cfg->dsc_version_major = 1897 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 1898 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; 1899 vdsc_cfg->dsc_version_minor = 1900 min(intel_dp_source_dsc_version_minor(display), 1901 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)); 1902 if (vdsc_cfg->convert_rgb) 1903 vdsc_cfg->convert_rgb = 1904 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & 1905 DP_DSC_RGB; 1906 1907 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, 1908 drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd)); 1909 if (!vdsc_cfg->line_buf_depth) { 1910 drm_dbg_kms(display->drm, 1911 "DSC Sink Line Buffer Depth invalid\n"); 1912 return -EINVAL; 1913 } 1914 1915 vdsc_cfg->block_pred_enable = 1916 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & 1917 DP_DSC_BLK_PREDICTION_IS_SUPPORTED; 1918 1919 return drm_dsc_compute_rc_parameters(vdsc_cfg); 1920 } 1921 1922 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, 1923 enum intel_output_format output_format) 1924 { 1925 struct intel_display *display = to_intel_display(connector); 1926 u8 sink_dsc_format; 1927 1928 switch (output_format) { 1929 case INTEL_OUTPUT_FORMAT_RGB: 1930 sink_dsc_format = DP_DSC_RGB; 1931 break; 1932 case INTEL_OUTPUT_FORMAT_YCBCR444: 1933 sink_dsc_format = DP_DSC_YCbCr444; 1934 break; 1935 case INTEL_OUTPUT_FORMAT_YCBCR420: 1936 if (min(intel_dp_source_dsc_version_minor(display), 1937 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2) 1938 return false; 1939 sink_dsc_format = DP_DSC_YCbCr420_Native; 1940 break; 1941 default: 1942 return false; 1943 } 1944 1945 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); 1946 } 1947 1948 static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock, 1949 u32 lane_count, u32 mode_clock, 1950 enum intel_output_format output_format, 1951 int timeslots) 1952 { 1953 u32 available_bw, required_bw; 1954 1955 available_bw = (link_clock * lane_count * timeslots * 16) / 8; 1956 required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock)); 1957 1958 return available_bw > required_bw; 1959 } 1960 1961 static int dsc_compute_link_config(struct intel_dp *intel_dp, 1962 struct intel_crtc_state *pipe_config, 1963 struct drm_connector_state *conn_state, 1964 const struct link_config_limits *limits, 1965 int dsc_bpp_x16, 1966 int timeslots) 1967 { 1968 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1969 int link_rate, lane_count; 1970 int i; 1971 1972 for (i = 0; i < intel_dp->num_common_rates; i++) { 1973 link_rate = intel_dp_common_rate(intel_dp, i); 1974 if (link_rate < limits->min_rate || link_rate > limits->max_rate) 1975 continue; 1976 1977 for (lane_count = limits->min_lane_count; 1978 lane_count <= limits->max_lane_count; 1979 lane_count <<= 1) { 1980 1981 /* 1982 * FIXME: intel_dp_mtp_tu_compute_config() requires 1983 * ->lane_count and ->port_clock set before we know 1984 * they'll work. If we end up failing altogether, 1985 * they'll remain in crtc state. This shouldn't matter, 1986 * as we'd then bail out from compute config, but it's 1987 * just ugly. 1988 */ 1989 pipe_config->lane_count = lane_count; 1990 pipe_config->port_clock = link_rate; 1991 1992 if (drm_dp_is_uhbr_rate(link_rate)) { 1993 int ret; 1994 1995 ret = intel_dp_mtp_tu_compute_config(intel_dp, 1996 pipe_config, 1997 conn_state, 1998 dsc_bpp_x16, 1999 dsc_bpp_x16, 2000 0, true); 2001 if (ret) 2002 continue; 2003 } else { 2004 if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate, 2005 lane_count, adjusted_mode->clock, 2006 pipe_config->output_format, 2007 timeslots)) 2008 continue; 2009 } 2010 2011 return 0; 2012 } 2013 } 2014 2015 return -EINVAL; 2016 } 2017 2018 static 2019 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, 2020 const struct intel_crtc_state *pipe_config, 2021 int bpc) 2022 { 2023 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); 2024 2025 if (max_bppx16) 2026 return max_bppx16; 2027 /* 2028 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate 2029 * values as given in spec Table 2-157 DP v2.0 2030 */ 2031 switch (pipe_config->output_format) { 2032 case INTEL_OUTPUT_FORMAT_RGB: 2033 case INTEL_OUTPUT_FORMAT_YCBCR444: 2034 return (3 * bpc) << 4; 2035 case INTEL_OUTPUT_FORMAT_YCBCR420: 2036 return (3 * (bpc / 2)) << 4; 2037 default: 2038 MISSING_CASE(pipe_config->output_format); 2039 break; 2040 } 2041 2042 return 0; 2043 } 2044 2045 int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config) 2046 { 2047 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ 2048 switch (pipe_config->output_format) { 2049 case INTEL_OUTPUT_FORMAT_RGB: 2050 case INTEL_OUTPUT_FORMAT_YCBCR444: 2051 return 8; 2052 case INTEL_OUTPUT_FORMAT_YCBCR420: 2053 return 6; 2054 default: 2055 MISSING_CASE(pipe_config->output_format); 2056 break; 2057 } 2058 2059 return 0; 2060 } 2061 2062 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, 2063 const struct intel_crtc_state *pipe_config, 2064 int bpc) 2065 { 2066 return intel_dp_dsc_max_sink_compressed_bppx16(connector, 2067 pipe_config, bpc) >> 4; 2068 } 2069 2070 static int dsc_src_min_compressed_bpp(void) 2071 { 2072 /* Min Compressed bpp supported by source is 8 */ 2073 return 8; 2074 } 2075 2076 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) 2077 { 2078 struct intel_display *display = to_intel_display(intel_dp); 2079 2080 /* 2081 * Forcing DSC and using the platform's max compressed bpp is seen to cause 2082 * underruns. Since DSC isn't needed in these cases, limit the 2083 * max compressed bpp to 18, which is a safe value across platforms with different 2084 * pipe bpps. 2085 */ 2086 if (intel_dp->force_dsc_en) 2087 return 18; 2088 2089 /* 2090 * Max Compressed bpp for Gen 13+ is 27bpp. 2091 * For earlier platform is 23bpp. (Bspec:49259). 2092 */ 2093 if (DISPLAY_VER(display) < 13) 2094 return 23; 2095 else 2096 return 27; 2097 } 2098 2099 /* 2100 * Note: for pre-13 display you still need to check the validity of each step. 2101 */ 2102 static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) 2103 { 2104 struct intel_display *display = to_intel_display(connector); 2105 u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); 2106 2107 if (DISPLAY_VER(display) < 14 || !incr) 2108 return fxp_q4_from_int(1); 2109 2110 /* fxp q4 */ 2111 return fxp_q4_from_int(1) / incr; 2112 } 2113 2114 /* Note: This is not universally usable! */ 2115 static bool intel_dp_dsc_valid_bpp(struct intel_dp *intel_dp, int bpp_x16) 2116 { 2117 struct intel_display *display = to_intel_display(intel_dp); 2118 int i; 2119 2120 if (DISPLAY_VER(display) >= 13) { 2121 if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16)) 2122 return false; 2123 2124 return true; 2125 } 2126 2127 if (fxp_q4_to_frac(bpp_x16)) 2128 return false; 2129 2130 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { 2131 if (fxp_q4_to_int(bpp_x16) == valid_dsc_bpp[i]) 2132 return true; 2133 } 2134 2135 return false; 2136 } 2137 2138 /* 2139 * Find the max compressed BPP we can find a link configuration for. The BPPs to 2140 * try depend on the source (platform) and sink. 2141 */ 2142 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, 2143 struct intel_crtc_state *pipe_config, 2144 struct drm_connector_state *conn_state, 2145 const struct link_config_limits *limits, 2146 int pipe_bpp, 2147 int timeslots) 2148 { 2149 struct intel_display *display = to_intel_display(intel_dp); 2150 const struct intel_connector *connector = to_intel_connector(conn_state->connector); 2151 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2152 int output_bpp; 2153 int dsc_min_bpp; 2154 int dsc_max_bpp; 2155 int min_bpp_x16, max_bpp_x16, bpp_step_x16; 2156 int dsc_joiner_max_bpp; 2157 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2158 int bpp_x16; 2159 int ret; 2160 2161 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); 2162 2163 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock, 2164 adjusted_mode->hdisplay, 2165 num_joined_pipes); 2166 dsc_max_bpp = min(dsc_joiner_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16)); 2167 2168 /* FIXME: remove the round trip via integers */ 2169 min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); 2170 max_bpp_x16 = fxp_q4_from_int(dsc_max_bpp); 2171 2172 bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); 2173 2174 /* Compressed BPP should be less than the Input DSC bpp */ 2175 output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); 2176 max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16); 2177 2178 for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { 2179 if (!intel_dp_dsc_valid_bpp(intel_dp, bpp_x16)) 2180 continue; 2181 2182 ret = dsc_compute_link_config(intel_dp, 2183 pipe_config, 2184 conn_state, 2185 limits, 2186 bpp_x16, 2187 timeslots); 2188 if (ret == 0) { 2189 pipe_config->dsc.compressed_bpp_x16 = bpp_x16; 2190 if (intel_dp->force_dsc_fractional_bpp_en && 2191 fxp_q4_to_frac(bpp_x16)) 2192 drm_dbg_kms(display->drm, 2193 "Forcing DSC fractional bpp\n"); 2194 2195 return 0; 2196 } 2197 } 2198 2199 return -EINVAL; 2200 } 2201 2202 int intel_dp_dsc_min_src_input_bpc(void) 2203 { 2204 /* Min DSC Input BPC for ICL+ is 8 */ 2205 return 8; 2206 } 2207 2208 static 2209 bool is_dsc_pipe_bpp_sufficient(const struct link_config_limits *limits, 2210 int pipe_bpp) 2211 { 2212 return pipe_bpp >= limits->pipe.min_bpp && 2213 pipe_bpp <= limits->pipe.max_bpp; 2214 } 2215 2216 static 2217 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, 2218 const struct link_config_limits *limits) 2219 { 2220 struct intel_display *display = to_intel_display(intel_dp); 2221 int forced_bpp; 2222 2223 if (!intel_dp->force_dsc_bpc) 2224 return 0; 2225 2226 forced_bpp = intel_dp->force_dsc_bpc * 3; 2227 2228 if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) { 2229 drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n", 2230 intel_dp->force_dsc_bpc); 2231 return forced_bpp; 2232 } 2233 2234 drm_dbg_kms(display->drm, 2235 "Cannot force DSC BPC:%d, due to DSC BPC limits\n", 2236 intel_dp->force_dsc_bpc); 2237 2238 return 0; 2239 } 2240 2241 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2242 struct intel_crtc_state *pipe_config, 2243 struct drm_connector_state *conn_state, 2244 const struct link_config_limits *limits, 2245 int timeslots) 2246 { 2247 const struct intel_connector *connector = 2248 to_intel_connector(conn_state->connector); 2249 u8 dsc_bpc[3] = {}; 2250 int forced_bpp, pipe_bpp; 2251 int num_bpc, i, ret; 2252 2253 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); 2254 2255 if (forced_bpp) { 2256 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, 2257 limits, forced_bpp, timeslots); 2258 if (ret == 0) { 2259 pipe_config->pipe_bpp = forced_bpp; 2260 return 0; 2261 } 2262 } 2263 2264 /* 2265 * Get the maximum DSC bpc that will be supported by any valid 2266 * link configuration and compressed bpp. 2267 */ 2268 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); 2269 for (i = 0; i < num_bpc; i++) { 2270 pipe_bpp = dsc_bpc[i] * 3; 2271 if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp) 2272 continue; 2273 2274 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, 2275 limits, pipe_bpp, timeslots); 2276 if (ret == 0) { 2277 pipe_config->pipe_bpp = pipe_bpp; 2278 return 0; 2279 } 2280 } 2281 2282 return -EINVAL; 2283 } 2284 2285 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2286 struct intel_crtc_state *pipe_config, 2287 struct drm_connector_state *conn_state, 2288 const struct link_config_limits *limits) 2289 { 2290 struct intel_display *display = to_intel_display(intel_dp); 2291 struct intel_connector *connector = 2292 to_intel_connector(conn_state->connector); 2293 int pipe_bpp, forced_bpp; 2294 int dsc_min_bpp; 2295 int dsc_max_bpp; 2296 2297 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); 2298 2299 if (forced_bpp) { 2300 pipe_bpp = forced_bpp; 2301 } else { 2302 int max_bpc = limits->pipe.max_bpp / 3; 2303 2304 /* For eDP use max bpp that can be supported with DSC. */ 2305 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); 2306 if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) { 2307 drm_dbg_kms(display->drm, 2308 "Computed BPC is not in DSC BPC limits\n"); 2309 return -EINVAL; 2310 } 2311 } 2312 pipe_config->port_clock = limits->max_rate; 2313 pipe_config->lane_count = limits->max_lane_count; 2314 2315 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); 2316 2317 dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 2318 2319 /* Compressed BPP should be less than the Input DSC bpp */ 2320 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 2321 2322 pipe_config->dsc.compressed_bpp_x16 = 2323 fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp)); 2324 2325 pipe_config->pipe_bpp = pipe_bpp; 2326 2327 return 0; 2328 } 2329 2330 static void intel_dp_fec_compute_config(struct intel_dp *intel_dp, 2331 struct intel_crtc_state *crtc_state) 2332 { 2333 if (crtc_state->fec_enable) 2334 return; 2335 2336 /* 2337 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional. 2338 * Since, FEC is a bandwidth overhead, continue to not enable it for 2339 * eDP. Until, there is a good reason to do so. 2340 */ 2341 if (intel_dp_is_edp(intel_dp)) 2342 return; 2343 2344 if (intel_dp_is_uhbr(crtc_state)) 2345 return; 2346 2347 crtc_state->fec_enable = true; 2348 } 2349 2350 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 2351 struct intel_crtc_state *pipe_config, 2352 struct drm_connector_state *conn_state, 2353 const struct link_config_limits *limits, 2354 int timeslots) 2355 { 2356 struct intel_display *display = to_intel_display(intel_dp); 2357 const struct intel_connector *connector = 2358 to_intel_connector(conn_state->connector); 2359 const struct drm_display_mode *adjusted_mode = 2360 &pipe_config->hw.adjusted_mode; 2361 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2362 bool is_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST); 2363 int ret; 2364 2365 intel_dp_fec_compute_config(intel_dp, pipe_config); 2366 2367 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format)) 2368 return -EINVAL; 2369 2370 /* 2371 * Link parameters, pipe bpp and compressed bpp have already been 2372 * figured out for DP MST DSC. 2373 */ 2374 if (!is_mst) { 2375 if (intel_dp_is_edp(intel_dp)) 2376 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2377 conn_state, limits); 2378 else 2379 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2380 conn_state, limits, timeslots); 2381 if (ret) { 2382 drm_dbg_kms(display->drm, 2383 "No Valid pipe bpp for given mode ret = %d\n", ret); 2384 return ret; 2385 } 2386 } 2387 2388 /* Calculate Slice count */ 2389 if (intel_dp_is_edp(intel_dp)) { 2390 pipe_config->dsc.slice_count = 2391 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 2392 true); 2393 if (!pipe_config->dsc.slice_count) { 2394 drm_dbg_kms(display->drm, 2395 "Unsupported Slice Count %d\n", 2396 pipe_config->dsc.slice_count); 2397 return -EINVAL; 2398 } 2399 } else { 2400 u8 dsc_dp_slice_count; 2401 2402 dsc_dp_slice_count = 2403 intel_dp_dsc_get_slice_count(connector, 2404 adjusted_mode->crtc_clock, 2405 adjusted_mode->crtc_hdisplay, 2406 num_joined_pipes); 2407 if (!dsc_dp_slice_count) { 2408 drm_dbg_kms(display->drm, 2409 "Compressed Slice Count not supported\n"); 2410 return -EINVAL; 2411 } 2412 2413 pipe_config->dsc.slice_count = dsc_dp_slice_count; 2414 } 2415 /* 2416 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate 2417 * is greater than the maximum Cdclock and if slice count is even 2418 * then we need to use 2 VDSC instances. 2419 * In case of Ultrajoiner along with 12 slices we need to use 3 2420 * VDSC instances. 2421 */ 2422 if (pipe_config->joiner_pipes && num_joined_pipes == 4 && 2423 pipe_config->dsc.slice_count == 12) 2424 pipe_config->dsc.num_streams = 3; 2425 else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) 2426 pipe_config->dsc.num_streams = 2; 2427 else 2428 pipe_config->dsc.num_streams = 1; 2429 2430 ret = intel_dp_dsc_compute_params(connector, pipe_config); 2431 if (ret < 0) { 2432 drm_dbg_kms(display->drm, 2433 "Cannot compute valid DSC parameters for Input Bpp = %d" 2434 "Compressed BPP = " FXP_Q4_FMT "\n", 2435 pipe_config->pipe_bpp, 2436 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16)); 2437 return ret; 2438 } 2439 2440 pipe_config->dsc.compression_enable = true; 2441 drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d " 2442 "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n", 2443 pipe_config->pipe_bpp, 2444 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2445 pipe_config->dsc.slice_count); 2446 2447 return 0; 2448 } 2449 2450 /* 2451 * Calculate the output link min, max bpp values in limits based on the pipe bpp 2452 * range, crtc_state and dsc mode. Return true on success. 2453 */ 2454 static bool 2455 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, 2456 const struct intel_connector *connector, 2457 const struct intel_crtc_state *crtc_state, 2458 bool dsc, 2459 struct link_config_limits *limits) 2460 { 2461 struct intel_display *display = to_intel_display(intel_dp); 2462 const struct drm_display_mode *adjusted_mode = 2463 &crtc_state->hw.adjusted_mode; 2464 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2465 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2466 int max_link_bpp_x16; 2467 2468 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, 2469 fxp_q4_from_int(limits->pipe.max_bpp)); 2470 2471 if (!dsc) { 2472 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3)); 2473 2474 if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp)) 2475 return false; 2476 2477 limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp); 2478 } else { 2479 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; 2480 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; 2481 2482 dsc_src_min_bpp = dsc_src_min_compressed_bpp(); 2483 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state); 2484 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 2485 limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); 2486 2487 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2488 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, 2489 crtc_state, 2490 limits->pipe.max_bpp / 3); 2491 dsc_max_bpp = dsc_sink_max_bpp ? 2492 min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; 2493 2494 max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp)); 2495 } 2496 2497 limits->link.max_bpp_x16 = max_link_bpp_x16; 2498 2499 drm_dbg_kms(display->drm, 2500 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n", 2501 encoder->base.base.id, encoder->base.name, 2502 crtc->base.base.id, crtc->base.name, 2503 adjusted_mode->crtc_clock, 2504 str_on_off(dsc), 2505 limits->max_lane_count, 2506 limits->max_rate, 2507 limits->pipe.max_bpp, 2508 FXP_Q4_ARGS(limits->link.max_bpp_x16)); 2509 2510 return true; 2511 } 2512 2513 static void 2514 intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp, 2515 struct link_config_limits *limits) 2516 { 2517 struct intel_display *display = to_intel_display(intel_dp); 2518 int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(); 2519 int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 2520 2521 limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); 2522 limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); 2523 } 2524 2525 bool 2526 intel_dp_compute_config_limits(struct intel_dp *intel_dp, 2527 struct intel_connector *connector, 2528 struct intel_crtc_state *crtc_state, 2529 bool respect_downstream_limits, 2530 bool dsc, 2531 struct link_config_limits *limits) 2532 { 2533 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2534 2535 limits->min_rate = intel_dp_min_link_rate(intel_dp); 2536 limits->max_rate = intel_dp_max_link_rate(intel_dp); 2537 2538 limits->min_rate = min(limits->min_rate, limits->max_rate); 2539 2540 limits->min_lane_count = intel_dp_min_lane_count(intel_dp); 2541 limits->max_lane_count = intel_dp_max_lane_count(intel_dp); 2542 2543 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); 2544 if (is_mst) { 2545 /* 2546 * FIXME: If all the streams can't fit into the link with their 2547 * current pipe_bpp we should reduce pipe_bpp across the board 2548 * until things start to fit. Until then we limit to <= 8bpc 2549 * since that's what was hardcoded for all MST streams 2550 * previously. This hack should be removed once we have the 2551 * proper retry logic in place. 2552 */ 2553 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24); 2554 } else { 2555 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, 2556 respect_downstream_limits); 2557 } 2558 2559 if (dsc) 2560 intel_dp_dsc_compute_pipe_bpp_limits(intel_dp, limits); 2561 2562 if (is_mst || intel_dp->use_max_params) { 2563 /* 2564 * For MST we always configure max link bw - the spec doesn't 2565 * seem to suggest we should do otherwise. 2566 * 2567 * Use the maximum clock and number of lanes the eDP panel 2568 * advertizes being capable of in case the initial fast 2569 * optimal params failed us. The panels are generally 2570 * designed to support only a single clock and lane 2571 * configuration, and typically on older panels these 2572 * values correspond to the native resolution of the panel. 2573 */ 2574 limits->min_lane_count = limits->max_lane_count; 2575 limits->min_rate = limits->max_rate; 2576 } 2577 2578 intel_dp_test_compute_config(intel_dp, crtc_state, limits); 2579 2580 return intel_dp_compute_config_link_bpp_limits(intel_dp, 2581 connector, 2582 crtc_state, 2583 dsc, 2584 limits); 2585 } 2586 2587 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state) 2588 { 2589 const struct drm_display_mode *adjusted_mode = 2590 &crtc_state->hw.adjusted_mode; 2591 int bpp = crtc_state->dsc.compression_enable ? 2592 fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) : 2593 crtc_state->pipe_bpp; 2594 2595 return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); 2596 } 2597 2598 bool intel_dp_joiner_needs_dsc(struct intel_display *display, 2599 int num_joined_pipes) 2600 { 2601 /* 2602 * Pipe joiner needs compression up to display 12 due to bandwidth 2603 * limitation. DG2 onwards pipe joiner can be enabled without 2604 * compression. 2605 * Ultrajoiner always needs compression. 2606 */ 2607 return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) || 2608 num_joined_pipes == 4; 2609 } 2610 2611 static int 2612 intel_dp_compute_link_config(struct intel_encoder *encoder, 2613 struct intel_crtc_state *pipe_config, 2614 struct drm_connector_state *conn_state, 2615 bool respect_downstream_limits) 2616 { 2617 struct intel_display *display = to_intel_display(encoder); 2618 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2619 struct intel_connector *connector = 2620 to_intel_connector(conn_state->connector); 2621 const struct drm_display_mode *adjusted_mode = 2622 &pipe_config->hw.adjusted_mode; 2623 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2624 struct link_config_limits limits; 2625 bool dsc_needed, joiner_needs_dsc; 2626 int num_joined_pipes; 2627 int ret = 0; 2628 2629 if (pipe_config->fec_enable && 2630 !intel_dp_supports_fec(intel_dp, connector, pipe_config)) 2631 return -EINVAL; 2632 2633 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, 2634 adjusted_mode->crtc_hdisplay, 2635 adjusted_mode->crtc_clock); 2636 if (num_joined_pipes > 1) 2637 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe); 2638 2639 joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes); 2640 2641 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || 2642 !intel_dp_compute_config_limits(intel_dp, connector, pipe_config, 2643 respect_downstream_limits, 2644 false, 2645 &limits); 2646 2647 if (!dsc_needed) { 2648 /* 2649 * Optimize for slow and wide for everything, because there are some 2650 * eDP 1.3 and 1.4 panels don't work well with fast and narrow. 2651 */ 2652 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, 2653 conn_state, &limits); 2654 if (!ret && intel_dp_is_uhbr(pipe_config)) 2655 ret = intel_dp_mtp_tu_compute_config(intel_dp, 2656 pipe_config, 2657 conn_state, 2658 fxp_q4_from_int(pipe_config->pipe_bpp), 2659 fxp_q4_from_int(pipe_config->pipe_bpp), 2660 0, false); 2661 if (ret) 2662 dsc_needed = true; 2663 } 2664 2665 if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) { 2666 drm_dbg_kms(display->drm, "DSC required but not available\n"); 2667 return -EINVAL; 2668 } 2669 2670 if (dsc_needed) { 2671 drm_dbg_kms(display->drm, 2672 "Try DSC (fallback=%s, joiner=%s, force=%s)\n", 2673 str_yes_no(ret), str_yes_no(joiner_needs_dsc), 2674 str_yes_no(intel_dp->force_dsc_en)); 2675 2676 if (!intel_dp_compute_config_limits(intel_dp, connector, pipe_config, 2677 respect_downstream_limits, 2678 true, 2679 &limits)) 2680 return -EINVAL; 2681 2682 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 2683 conn_state, &limits, 64); 2684 if (ret < 0) 2685 return ret; 2686 } 2687 2688 drm_dbg_kms(display->drm, 2689 "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n", 2690 pipe_config->lane_count, pipe_config->port_clock, 2691 pipe_config->pipe_bpp, 2692 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2693 intel_dp_config_required_rate(pipe_config), 2694 intel_dp_max_link_data_rate(intel_dp, 2695 pipe_config->port_clock, 2696 pipe_config->lane_count)); 2697 2698 return 0; 2699 } 2700 2701 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 2702 const struct drm_connector_state *conn_state) 2703 { 2704 const struct intel_digital_connector_state *intel_conn_state = 2705 to_intel_digital_connector_state(conn_state); 2706 const struct drm_display_mode *adjusted_mode = 2707 &crtc_state->hw.adjusted_mode; 2708 2709 /* 2710 * Our YCbCr output is always limited range. 2711 * crtc_state->limited_color_range only applies to RGB, 2712 * and it must never be set for YCbCr or we risk setting 2713 * some conflicting bits in TRANSCONF which will mess up 2714 * the colors on the monitor. 2715 */ 2716 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2717 return false; 2718 2719 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2720 /* 2721 * See: 2722 * CEA-861-E - 5.1 Default Encoding Parameters 2723 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 2724 */ 2725 return crtc_state->pipe_bpp != 18 && 2726 drm_default_rgb_quant_range(adjusted_mode) == 2727 HDMI_QUANTIZATION_RANGE_LIMITED; 2728 } else { 2729 return intel_conn_state->broadcast_rgb == 2730 INTEL_BROADCAST_RGB_LIMITED; 2731 } 2732 } 2733 2734 static bool intel_dp_port_has_audio(struct intel_display *display, enum port port) 2735 { 2736 if (display->platform.g4x) 2737 return false; 2738 if (DISPLAY_VER(display) < 12 && port == PORT_A) 2739 return false; 2740 2741 return true; 2742 } 2743 2744 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, 2745 const struct drm_connector_state *conn_state, 2746 struct drm_dp_vsc_sdp *vsc) 2747 { 2748 struct intel_display *display = to_intel_display(crtc_state); 2749 2750 if (crtc_state->has_panel_replay) { 2751 /* 2752 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2753 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel 2754 * Encoding/Colorimetry Format indication. 2755 */ 2756 vsc->revision = 0x7; 2757 } else { 2758 /* 2759 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2760 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ 2761 * Colorimetry Format indication. 2762 */ 2763 vsc->revision = 0x5; 2764 } 2765 2766 vsc->length = 0x13; 2767 2768 /* DP 1.4a spec, Table 2-120 */ 2769 switch (crtc_state->output_format) { 2770 case INTEL_OUTPUT_FORMAT_YCBCR444: 2771 vsc->pixelformat = DP_PIXELFORMAT_YUV444; 2772 break; 2773 case INTEL_OUTPUT_FORMAT_YCBCR420: 2774 vsc->pixelformat = DP_PIXELFORMAT_YUV420; 2775 break; 2776 case INTEL_OUTPUT_FORMAT_RGB: 2777 default: 2778 vsc->pixelformat = DP_PIXELFORMAT_RGB; 2779 } 2780 2781 switch (conn_state->colorspace) { 2782 case DRM_MODE_COLORIMETRY_BT709_YCC: 2783 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2784 break; 2785 case DRM_MODE_COLORIMETRY_XVYCC_601: 2786 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; 2787 break; 2788 case DRM_MODE_COLORIMETRY_XVYCC_709: 2789 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; 2790 break; 2791 case DRM_MODE_COLORIMETRY_SYCC_601: 2792 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; 2793 break; 2794 case DRM_MODE_COLORIMETRY_OPYCC_601: 2795 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; 2796 break; 2797 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 2798 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; 2799 break; 2800 case DRM_MODE_COLORIMETRY_BT2020_RGB: 2801 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; 2802 break; 2803 case DRM_MODE_COLORIMETRY_BT2020_YCC: 2804 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; 2805 break; 2806 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 2807 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 2808 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; 2809 break; 2810 default: 2811 /* 2812 * RGB->YCBCR color conversion uses the BT.709 2813 * color space. 2814 */ 2815 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2816 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2817 else 2818 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; 2819 break; 2820 } 2821 2822 vsc->bpc = crtc_state->pipe_bpp / 3; 2823 2824 /* only RGB pixelformat supports 6 bpc */ 2825 drm_WARN_ON(display->drm, 2826 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); 2827 2828 /* all YCbCr are always limited range */ 2829 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; 2830 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; 2831 } 2832 2833 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, 2834 struct intel_crtc_state *crtc_state) 2835 { 2836 struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; 2837 const struct drm_display_mode *adjusted_mode = 2838 &crtc_state->hw.adjusted_mode; 2839 2840 if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported) 2841 return; 2842 2843 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); 2844 2845 as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; 2846 as_sdp->length = 0x9; 2847 as_sdp->duration_incr_ms = 0; 2848 as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state); 2849 2850 if (crtc_state->cmrr.enable) { 2851 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; 2852 as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode); 2853 as_sdp->target_rr_divider = true; 2854 } else { 2855 as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL; 2856 as_sdp->target_rr = 0; 2857 } 2858 } 2859 2860 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, 2861 struct intel_crtc_state *crtc_state, 2862 const struct drm_connector_state *conn_state) 2863 { 2864 struct drm_dp_vsc_sdp *vsc; 2865 2866 if ((!intel_dp->colorimetry_support || 2867 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) && 2868 !crtc_state->has_psr) 2869 return; 2870 2871 vsc = &crtc_state->infoframes.vsc; 2872 2873 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 2874 vsc->sdp_type = DP_SDP_VSC; 2875 2876 /* Needs colorimetry */ 2877 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { 2878 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 2879 vsc); 2880 } else if (crtc_state->has_panel_replay) { 2881 /* 2882 * [Panel Replay without colorimetry info] 2883 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2884 * VSC SDP supporting 3D stereo + Panel Replay. 2885 */ 2886 vsc->revision = 0x6; 2887 vsc->length = 0x10; 2888 } else if (crtc_state->has_sel_update) { 2889 /* 2890 * [PSR2 without colorimetry] 2891 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 2892 * 3D stereo + PSR/PSR2 + Y-coordinate. 2893 */ 2894 vsc->revision = 0x4; 2895 vsc->length = 0xe; 2896 } else { 2897 /* 2898 * [PSR1] 2899 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2900 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or 2901 * higher). 2902 */ 2903 vsc->revision = 0x2; 2904 vsc->length = 0x8; 2905 } 2906 } 2907 2908 static void 2909 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, 2910 struct intel_crtc_state *crtc_state, 2911 const struct drm_connector_state *conn_state) 2912 { 2913 struct intel_display *display = to_intel_display(intel_dp); 2914 int ret; 2915 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; 2916 2917 if (!conn_state->hdr_output_metadata) 2918 return; 2919 2920 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); 2921 2922 if (ret) { 2923 drm_dbg_kms(display->drm, 2924 "couldn't set HDR metadata in infoframe\n"); 2925 return; 2926 } 2927 2928 crtc_state->infoframes.enable |= 2929 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 2930 } 2931 2932 static bool can_enable_drrs(struct intel_connector *connector, 2933 const struct intel_crtc_state *pipe_config, 2934 const struct drm_display_mode *downclock_mode) 2935 { 2936 struct intel_display *display = to_intel_display(connector); 2937 2938 if (pipe_config->vrr.enable) 2939 return false; 2940 2941 /* 2942 * DRRS and PSR can't be enable together, so giving preference to PSR 2943 * as it allows more power-savings by complete shutting down display, 2944 * so to guarantee this, intel_drrs_compute_config() must be called 2945 * after intel_psr_compute_config(). 2946 */ 2947 if (pipe_config->has_psr) 2948 return false; 2949 2950 /* FIXME missing FDI M2/N2 etc. */ 2951 if (pipe_config->has_pch_encoder) 2952 return false; 2953 2954 if (!intel_cpu_transcoder_has_drrs(display, pipe_config->cpu_transcoder)) 2955 return false; 2956 2957 return downclock_mode && 2958 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 2959 } 2960 2961 static void 2962 intel_dp_drrs_compute_config(struct intel_connector *connector, 2963 struct intel_crtc_state *pipe_config, 2964 int link_bpp_x16) 2965 { 2966 struct intel_display *display = to_intel_display(connector); 2967 const struct drm_display_mode *downclock_mode = 2968 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 2969 int pixel_clock; 2970 2971 /* 2972 * FIXME all joined pipes share the same transcoder. 2973 * Need to account for that when updating M/N live. 2974 */ 2975 if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes) 2976 pipe_config->update_m_n = true; 2977 2978 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { 2979 if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder)) 2980 intel_zero_m_n(&pipe_config->dp_m2_n2); 2981 return; 2982 } 2983 2984 if (display->platform.ironlake || display->platform.sandybridge || 2985 display->platform.ivybridge) 2986 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; 2987 2988 pipe_config->has_drrs = true; 2989 2990 pixel_clock = downclock_mode->clock; 2991 if (pipe_config->splitter.enable) 2992 pixel_clock /= pipe_config->splitter.link_count; 2993 2994 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock, 2995 pipe_config->port_clock, 2996 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 2997 &pipe_config->dp_m2_n2); 2998 2999 /* FIXME: abstract this better */ 3000 if (pipe_config->splitter.enable) 3001 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 3002 } 3003 3004 static bool intel_dp_has_audio(struct intel_encoder *encoder, 3005 const struct drm_connector_state *conn_state) 3006 { 3007 struct intel_display *display = to_intel_display(encoder); 3008 const struct intel_digital_connector_state *intel_conn_state = 3009 to_intel_digital_connector_state(conn_state); 3010 struct intel_connector *connector = 3011 to_intel_connector(conn_state->connector); 3012 3013 if (!intel_dp_port_has_audio(display, encoder->port)) 3014 return false; 3015 3016 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 3017 return connector->base.display_info.has_audio; 3018 else 3019 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 3020 } 3021 3022 static int 3023 intel_dp_compute_output_format(struct intel_encoder *encoder, 3024 struct intel_crtc_state *crtc_state, 3025 struct drm_connector_state *conn_state, 3026 bool respect_downstream_limits) 3027 { 3028 struct intel_display *display = to_intel_display(encoder); 3029 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3030 struct intel_connector *connector = intel_dp->attached_connector; 3031 const struct drm_display_info *info = &connector->base.display_info; 3032 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3033 bool ycbcr_420_only; 3034 int ret; 3035 3036 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 3037 3038 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { 3039 drm_dbg_kms(display->drm, 3040 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 3041 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 3042 } else { 3043 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode); 3044 } 3045 3046 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); 3047 3048 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 3049 respect_downstream_limits); 3050 if (ret) { 3051 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3052 !connector->base.ycbcr_420_allowed || 3053 !drm_mode_is_420_also(info, adjusted_mode)) 3054 return ret; 3055 3056 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 3057 crtc_state->output_format = intel_dp_output_format(connector, 3058 crtc_state->sink_format); 3059 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 3060 respect_downstream_limits); 3061 } 3062 3063 return ret; 3064 } 3065 3066 void 3067 intel_dp_audio_compute_config(struct intel_encoder *encoder, 3068 struct intel_crtc_state *pipe_config, 3069 struct drm_connector_state *conn_state) 3070 { 3071 pipe_config->has_audio = 3072 intel_dp_has_audio(encoder, conn_state) && 3073 intel_audio_compute_config(encoder, pipe_config, conn_state); 3074 3075 pipe_config->sdp_split_enable = pipe_config->has_audio && 3076 intel_dp_is_uhbr(pipe_config); 3077 } 3078 3079 void 3080 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, 3081 struct intel_encoder *encoder, 3082 const struct intel_crtc_state *crtc_state) 3083 { 3084 struct intel_connector *connector; 3085 struct intel_digital_connector_state *conn_state; 3086 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3087 int i; 3088 3089 if (intel_dp->needs_modeset_retry) 3090 return; 3091 3092 intel_dp->needs_modeset_retry = true; 3093 3094 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3095 intel_connector_queue_modeset_retry_work(intel_dp->attached_connector); 3096 3097 return; 3098 } 3099 3100 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { 3101 if (!conn_state->base.crtc) 3102 continue; 3103 3104 if (connector->mst.dp == intel_dp) 3105 intel_connector_queue_modeset_retry_work(connector); 3106 } 3107 } 3108 3109 int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, 3110 const struct drm_connector_state *conn_state) 3111 { 3112 struct intel_display *display = to_intel_display(crtc_state); 3113 const struct drm_display_mode *adjusted_mode = 3114 &crtc_state->hw.adjusted_mode; 3115 struct intel_connector *connector = to_intel_connector(conn_state->connector); 3116 int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8; 3117 /* 3118 * min symbol cycles is 3(BS,VBID, BE) for 128b/132b and 3119 * 5(BS, VBID, MVID, MAUD, BE) for 8b/10b 3120 */ 3121 int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5; 3122 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3123 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state); 3124 int min_hblank; 3125 int max_lane_count = 4; 3126 int hactive_sym_cycles, htotal_sym_cycles; 3127 int dsc_slices = 0; 3128 int link_bpp_x16; 3129 3130 if (DISPLAY_VER(display) < 30) 3131 return 0; 3132 3133 /* MIN_HBLANK should be set only for 8b/10b MST or for 128b/132b SST/MST */ 3134 if (!is_mst && !intel_dp_is_uhbr(crtc_state)) 3135 return 0; 3136 3137 if (crtc_state->dsc.compression_enable) { 3138 dsc_slices = intel_dp_dsc_get_slice_count(connector, 3139 adjusted_mode->crtc_clock, 3140 adjusted_mode->crtc_hdisplay, 3141 num_joined_pipes); 3142 if (!dsc_slices) { 3143 drm_dbg(display->drm, "failed to calculate dsc slice count\n"); 3144 return -EINVAL; 3145 } 3146 } 3147 3148 if (crtc_state->dsc.compression_enable) 3149 link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; 3150 else 3151 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, 3152 crtc_state->pipe_bpp)); 3153 3154 /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ 3155 hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count, 3156 adjusted_mode->hdisplay, 3157 dsc_slices, 3158 link_bpp_x16, 3159 symbol_size, is_mst); 3160 htotal_sym_cycles = adjusted_mode->htotal * hactive_sym_cycles / 3161 adjusted_mode->hdisplay; 3162 3163 min_hblank = htotal_sym_cycles - hactive_sym_cycles; 3164 /* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */ 3165 min_hblank = max(min_hblank, min_sym_cycles); 3166 3167 /* 3168 * adjust the BlankingStart/BlankingEnd framing control from 3169 * the calculated value 3170 */ 3171 min_hblank = min_hblank - 2; 3172 3173 min_hblank = min(10, min_hblank); 3174 crtc_state->min_hblank = min_hblank; 3175 3176 return 0; 3177 } 3178 3179 int 3180 intel_dp_compute_config(struct intel_encoder *encoder, 3181 struct intel_crtc_state *pipe_config, 3182 struct drm_connector_state *conn_state) 3183 { 3184 struct intel_display *display = to_intel_display(encoder); 3185 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); 3186 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 3187 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3188 const struct drm_display_mode *fixed_mode; 3189 struct intel_connector *connector = intel_dp->attached_connector; 3190 int ret = 0, link_bpp_x16; 3191 3192 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode); 3193 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 3194 ret = intel_panel_compute_config(connector, adjusted_mode); 3195 if (ret) 3196 return ret; 3197 } 3198 3199 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 3200 return -EINVAL; 3201 3202 if (!connector->base.interlace_allowed && 3203 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 3204 return -EINVAL; 3205 3206 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 3207 return -EINVAL; 3208 3209 if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay)) 3210 return -EINVAL; 3211 3212 /* 3213 * Try to respect downstream TMDS clock limits first, if 3214 * that fails assume the user might know something we don't. 3215 */ 3216 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true); 3217 if (ret) 3218 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false); 3219 if (ret) 3220 return ret; 3221 3222 if ((intel_dp_is_edp(intel_dp) && fixed_mode) || 3223 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3224 ret = intel_pfit_compute_config(pipe_config, conn_state); 3225 if (ret) 3226 return ret; 3227 } 3228 3229 pipe_config->limited_color_range = 3230 intel_dp_limited_color_range(pipe_config, conn_state); 3231 3232 if (intel_dp_is_uhbr(pipe_config)) { 3233 /* 128b/132b SST also needs this */ 3234 pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder; 3235 } else { 3236 pipe_config->enhanced_framing = 3237 drm_dp_enhanced_frame_cap(intel_dp->dpcd); 3238 } 3239 3240 if (pipe_config->dsc.compression_enable) 3241 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; 3242 else 3243 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format, 3244 pipe_config->pipe_bpp)); 3245 3246 if (intel_dp->mso_link_count) { 3247 int n = intel_dp->mso_link_count; 3248 int overlap = intel_dp->mso_pixel_overlap; 3249 3250 pipe_config->splitter.enable = true; 3251 pipe_config->splitter.link_count = n; 3252 pipe_config->splitter.pixel_overlap = overlap; 3253 3254 drm_dbg_kms(display->drm, 3255 "MSO link count %d, pixel overlap %d\n", 3256 n, overlap); 3257 3258 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; 3259 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; 3260 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; 3261 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; 3262 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; 3263 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; 3264 adjusted_mode->crtc_clock /= n; 3265 } 3266 3267 intel_dp_audio_compute_config(encoder, pipe_config, conn_state); 3268 3269 if (!intel_dp_is_uhbr(pipe_config)) { 3270 intel_link_compute_m_n(link_bpp_x16, 3271 pipe_config->lane_count, 3272 adjusted_mode->crtc_clock, 3273 pipe_config->port_clock, 3274 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 3275 &pipe_config->dp_m_n); 3276 } 3277 3278 ret = intel_dp_compute_min_hblank(pipe_config, conn_state); 3279 if (ret) 3280 return ret; 3281 3282 /* FIXME: abstract this better */ 3283 if (pipe_config->splitter.enable) 3284 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; 3285 3286 intel_vrr_compute_config(pipe_config, conn_state); 3287 intel_dp_compute_as_sdp(intel_dp, pipe_config); 3288 intel_psr_compute_config(intel_dp, pipe_config, conn_state); 3289 intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state); 3290 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); 3291 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); 3292 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); 3293 3294 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector, 3295 pipe_config); 3296 } 3297 3298 void intel_dp_set_link_params(struct intel_dp *intel_dp, 3299 int link_rate, int lane_count) 3300 { 3301 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 3302 intel_dp->link.active = false; 3303 intel_dp->needs_modeset_retry = false; 3304 intel_dp->link_rate = link_rate; 3305 intel_dp->lane_count = lane_count; 3306 } 3307 3308 void intel_dp_reset_link_params(struct intel_dp *intel_dp) 3309 { 3310 intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); 3311 intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); 3312 intel_dp->link.mst_probed_lane_count = 0; 3313 intel_dp->link.mst_probed_rate = 0; 3314 intel_dp->link.retrain_disabled = false; 3315 intel_dp->link.seq_train_failures = 0; 3316 } 3317 3318 /* Enable backlight PWM and backlight PP control. */ 3319 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 3320 const struct drm_connector_state *conn_state) 3321 { 3322 struct intel_display *display = to_intel_display(crtc_state); 3323 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); 3324 3325 if (!intel_dp_is_edp(intel_dp)) 3326 return; 3327 3328 drm_dbg_kms(display->drm, "\n"); 3329 3330 intel_backlight_enable(crtc_state, conn_state); 3331 intel_pps_backlight_on(intel_dp); 3332 } 3333 3334 /* Disable backlight PP control and backlight PWM. */ 3335 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) 3336 { 3337 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); 3338 struct intel_display *display = to_intel_display(intel_dp); 3339 3340 if (!intel_dp_is_edp(intel_dp)) 3341 return; 3342 3343 drm_dbg_kms(display->drm, "\n"); 3344 3345 intel_pps_backlight_off(intel_dp); 3346 intel_backlight_disable(old_conn_state); 3347 } 3348 3349 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) 3350 { 3351 /* 3352 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus 3353 * be capable of signalling downstream hpd with a long pulse. 3354 * Whether or not that means D3 is safe to use is not clear, 3355 * but let's assume so until proven otherwise. 3356 * 3357 * FIXME should really check all downstream ports... 3358 */ 3359 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 3360 drm_dp_is_branch(intel_dp->dpcd) && 3361 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; 3362 } 3363 3364 static int 3365 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set) 3366 { 3367 int err; 3368 u8 val; 3369 3370 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val); 3371 if (err < 0) 3372 return err; 3373 3374 if (set) 3375 val |= flag; 3376 else 3377 val &= ~flag; 3378 3379 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val); 3380 } 3381 3382 static void 3383 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, 3384 bool enable) 3385 { 3386 struct intel_display *display = to_intel_display(connector); 3387 3388 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux, 3389 DP_DECOMPRESSION_EN, enable) < 0) 3390 drm_dbg_kms(display->drm, 3391 "Failed to %s sink decompression state\n", 3392 str_enable_disable(enable)); 3393 } 3394 3395 static void 3396 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, 3397 bool enable) 3398 { 3399 struct intel_display *display = to_intel_display(connector); 3400 struct drm_dp_aux *aux = connector->mst.port ? 3401 connector->mst.port->passthrough_aux : NULL; 3402 3403 if (!aux) 3404 return; 3405 3406 if (write_dsc_decompression_flag(aux, 3407 DP_DSC_PASSTHROUGH_EN, enable) < 0) 3408 drm_dbg_kms(display->drm, 3409 "Failed to %s sink compression passthrough state\n", 3410 str_enable_disable(enable)); 3411 } 3412 3413 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, 3414 const struct intel_connector *connector, 3415 bool for_get_ref) 3416 { 3417 struct intel_display *display = to_intel_display(state); 3418 struct drm_connector *_connector_iter; 3419 struct drm_connector_state *old_conn_state; 3420 struct drm_connector_state *new_conn_state; 3421 int ref_count = 0; 3422 int i; 3423 3424 /* 3425 * On SST the decompression AUX device won't be shared, each connector 3426 * uses for this its own AUX targeting the sink device. 3427 */ 3428 if (!connector->mst.dp) 3429 return connector->dp.dsc_decompression_enabled ? 1 : 0; 3430 3431 for_each_oldnew_connector_in_state(&state->base, _connector_iter, 3432 old_conn_state, new_conn_state, i) { 3433 const struct intel_connector * 3434 connector_iter = to_intel_connector(_connector_iter); 3435 3436 if (connector_iter->mst.dp != connector->mst.dp) 3437 continue; 3438 3439 if (!connector_iter->dp.dsc_decompression_enabled) 3440 continue; 3441 3442 drm_WARN_ON(display->drm, 3443 (for_get_ref && !new_conn_state->crtc) || 3444 (!for_get_ref && !old_conn_state->crtc)); 3445 3446 if (connector_iter->dp.dsc_decompression_aux == 3447 connector->dp.dsc_decompression_aux) 3448 ref_count++; 3449 } 3450 3451 return ref_count; 3452 } 3453 3454 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state, 3455 struct intel_connector *connector) 3456 { 3457 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0; 3458 3459 connector->dp.dsc_decompression_enabled = true; 3460 3461 return ret; 3462 } 3463 3464 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state, 3465 struct intel_connector *connector) 3466 { 3467 connector->dp.dsc_decompression_enabled = false; 3468 3469 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0; 3470 } 3471 3472 /** 3473 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device 3474 * @state: atomic state 3475 * @connector: connector to enable the decompression for 3476 * @new_crtc_state: new state for the CRTC driving @connector 3477 * 3478 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3479 * register of the appropriate sink/branch device. On SST this is always the 3480 * sink device, whereas on MST based on each device's DSC capabilities it's 3481 * either the last branch device (enabling decompression in it) or both the 3482 * last branch device (enabling passthrough in it) and the sink device 3483 * (enabling decompression in it). 3484 */ 3485 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, 3486 struct intel_connector *connector, 3487 const struct intel_crtc_state *new_crtc_state) 3488 { 3489 struct intel_display *display = to_intel_display(state); 3490 3491 if (!new_crtc_state->dsc.compression_enable) 3492 return; 3493 3494 if (drm_WARN_ON(display->drm, 3495 !connector->dp.dsc_decompression_aux || 3496 connector->dp.dsc_decompression_enabled)) 3497 return; 3498 3499 if (!intel_dp_dsc_aux_get_ref(state, connector)) 3500 return; 3501 3502 intel_dp_sink_set_dsc_passthrough(connector, true); 3503 intel_dp_sink_set_dsc_decompression(connector, true); 3504 } 3505 3506 /** 3507 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device 3508 * @state: atomic state 3509 * @connector: connector to disable the decompression for 3510 * @old_crtc_state: old state for the CRTC driving @connector 3511 * 3512 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3513 * register of the appropriate sink/branch device, corresponding to the 3514 * sequence in intel_dp_sink_enable_decompression(). 3515 */ 3516 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, 3517 struct intel_connector *connector, 3518 const struct intel_crtc_state *old_crtc_state) 3519 { 3520 struct intel_display *display = to_intel_display(state); 3521 3522 if (!old_crtc_state->dsc.compression_enable) 3523 return; 3524 3525 if (drm_WARN_ON(display->drm, 3526 !connector->dp.dsc_decompression_aux || 3527 !connector->dp.dsc_decompression_enabled)) 3528 return; 3529 3530 if (!intel_dp_dsc_aux_put_ref(state, connector)) 3531 return; 3532 3533 intel_dp_sink_set_dsc_decompression(connector, false); 3534 intel_dp_sink_set_dsc_passthrough(connector, false); 3535 } 3536 3537 static void 3538 intel_dp_init_source_oui(struct intel_dp *intel_dp) 3539 { 3540 struct intel_display *display = to_intel_display(intel_dp); 3541 u8 oui[] = { 0x00, 0xaa, 0x01 }; 3542 u8 buf[3] = {}; 3543 3544 if (READ_ONCE(intel_dp->oui_valid)) 3545 return; 3546 3547 WRITE_ONCE(intel_dp->oui_valid, true); 3548 3549 /* 3550 * During driver init, we want to be careful and avoid changing the source OUI if it's 3551 * already set to what we want, so as to avoid clearing any state by accident 3552 */ 3553 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) 3554 drm_dbg_kms(display->drm, "Failed to read source OUI\n"); 3555 3556 if (memcmp(oui, buf, sizeof(oui)) == 0) { 3557 /* Assume the OUI was written now. */ 3558 intel_dp->last_oui_write = jiffies; 3559 return; 3560 } 3561 3562 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) { 3563 drm_dbg_kms(display->drm, "Failed to write source OUI\n"); 3564 WRITE_ONCE(intel_dp->oui_valid, false); 3565 } 3566 3567 intel_dp->last_oui_write = jiffies; 3568 } 3569 3570 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp) 3571 { 3572 WRITE_ONCE(intel_dp->oui_valid, false); 3573 } 3574 3575 void intel_dp_wait_source_oui(struct intel_dp *intel_dp) 3576 { 3577 struct intel_display *display = to_intel_display(intel_dp); 3578 struct intel_connector *connector = intel_dp->attached_connector; 3579 3580 drm_dbg_kms(display->drm, 3581 "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n", 3582 connector->base.base.id, connector->base.name, 3583 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3584 3585 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 3586 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3587 } 3588 3589 /* If the device supports it, try to set the power state appropriately */ 3590 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) 3591 { 3592 struct intel_display *display = to_intel_display(intel_dp); 3593 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3594 int ret, i; 3595 3596 /* Should have a valid DPCD by this point */ 3597 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 3598 return; 3599 3600 if (mode != DP_SET_POWER_D0) { 3601 if (downstream_hpd_needs_d0(intel_dp)) 3602 return; 3603 3604 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3605 } else { 3606 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3607 3608 intel_lspcon_resume(dig_port); 3609 3610 /* Write the source OUI as early as possible */ 3611 intel_dp_init_source_oui(intel_dp); 3612 3613 /* 3614 * When turning on, we need to retry for 1ms to give the sink 3615 * time to wake up. 3616 */ 3617 for (i = 0; i < 3; i++) { 3618 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3619 if (ret == 1) 3620 break; 3621 msleep(1); 3622 } 3623 3624 if (ret == 1 && intel_lspcon_active(dig_port)) 3625 intel_lspcon_wait_pcon_mode(dig_port); 3626 } 3627 3628 if (ret != 1) 3629 drm_dbg_kms(display->drm, 3630 "[ENCODER:%d:%s] Set power to %s failed\n", 3631 encoder->base.base.id, encoder->base.name, 3632 mode == DP_SET_POWER_D0 ? "D0" : "D3"); 3633 } 3634 3635 static bool 3636 intel_dp_get_dpcd(struct intel_dp *intel_dp); 3637 3638 /** 3639 * intel_dp_sync_state - sync the encoder state during init/resume 3640 * @encoder: intel encoder to sync 3641 * @crtc_state: state for the CRTC connected to the encoder 3642 * 3643 * Sync any state stored in the encoder wrt. HW state during driver init 3644 * and system resume. 3645 */ 3646 void intel_dp_sync_state(struct intel_encoder *encoder, 3647 const struct intel_crtc_state *crtc_state) 3648 { 3649 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3650 bool dpcd_updated = false; 3651 3652 /* 3653 * Don't clobber DPCD if it's been already read out during output 3654 * setup (eDP) or detect. 3655 */ 3656 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) { 3657 intel_dp_get_dpcd(intel_dp); 3658 dpcd_updated = true; 3659 } 3660 3661 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); 3662 3663 if (crtc_state) { 3664 intel_dp_reset_link_params(intel_dp); 3665 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 3666 intel_dp->link.active = true; 3667 } 3668 } 3669 3670 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 3671 struct intel_crtc_state *crtc_state) 3672 { 3673 struct intel_display *display = to_intel_display(encoder); 3674 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3675 bool fastset = true; 3676 3677 /* 3678 * If BIOS has set an unsupported or non-standard link rate for some 3679 * reason force an encoder recompute and full modeset. 3680 */ 3681 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, 3682 crtc_state->port_clock) < 0) { 3683 drm_dbg_kms(display->drm, 3684 "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n", 3685 encoder->base.base.id, encoder->base.name); 3686 crtc_state->uapi.connectors_changed = true; 3687 fastset = false; 3688 } 3689 3690 /* 3691 * FIXME hack to force full modeset when DSC is being used. 3692 * 3693 * As long as we do not have full state readout and config comparison 3694 * of crtc_state->dsc, we have no way to ensure reliable fastset. 3695 * Remove once we have readout for DSC. 3696 */ 3697 if (crtc_state->dsc.compression_enable) { 3698 drm_dbg_kms(display->drm, 3699 "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n", 3700 encoder->base.base.id, encoder->base.name); 3701 crtc_state->uapi.mode_changed = true; 3702 fastset = false; 3703 } 3704 3705 if (CAN_PANEL_REPLAY(intel_dp)) { 3706 drm_dbg_kms(display->drm, 3707 "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n", 3708 encoder->base.base.id, encoder->base.name); 3709 crtc_state->uapi.mode_changed = true; 3710 fastset = false; 3711 } 3712 3713 return fastset; 3714 } 3715 3716 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) 3717 { 3718 struct intel_display *display = to_intel_display(intel_dp); 3719 3720 /* Clear the cached register set to avoid using stale values */ 3721 3722 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); 3723 3724 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, 3725 intel_dp->pcon_dsc_dpcd, 3726 sizeof(intel_dp->pcon_dsc_dpcd)) < 0) 3727 drm_err(display->drm, "Failed to read DPCD register 0x%x\n", 3728 DP_PCON_DSC_ENCODER); 3729 3730 drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n", 3731 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); 3732 } 3733 3734 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) 3735 { 3736 static const int bw_gbps[] = {9, 18, 24, 32, 40, 48}; 3737 int i; 3738 3739 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { 3740 if (frl_bw_mask & (1 << i)) 3741 return bw_gbps[i]; 3742 } 3743 return 0; 3744 } 3745 3746 static int intel_dp_pcon_set_frl_mask(int max_frl) 3747 { 3748 switch (max_frl) { 3749 case 48: 3750 return DP_PCON_FRL_BW_MASK_48GBPS; 3751 case 40: 3752 return DP_PCON_FRL_BW_MASK_40GBPS; 3753 case 32: 3754 return DP_PCON_FRL_BW_MASK_32GBPS; 3755 case 24: 3756 return DP_PCON_FRL_BW_MASK_24GBPS; 3757 case 18: 3758 return DP_PCON_FRL_BW_MASK_18GBPS; 3759 case 9: 3760 return DP_PCON_FRL_BW_MASK_9GBPS; 3761 } 3762 3763 return 0; 3764 } 3765 3766 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) 3767 { 3768 struct intel_connector *connector = intel_dp->attached_connector; 3769 const struct drm_display_info *info = &connector->base.display_info; 3770 int max_frl_rate; 3771 int max_lanes, rate_per_lane; 3772 int max_dsc_lanes, dsc_rate_per_lane; 3773 3774 max_lanes = info->hdmi.max_lanes; 3775 rate_per_lane = info->hdmi.max_frl_rate_per_lane; 3776 max_frl_rate = max_lanes * rate_per_lane; 3777 3778 if (info->hdmi.dsc_cap.v_1p2) { 3779 max_dsc_lanes = info->hdmi.dsc_cap.max_lanes; 3780 dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane; 3781 if (max_dsc_lanes && dsc_rate_per_lane) 3782 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane); 3783 } 3784 3785 return max_frl_rate; 3786 } 3787 3788 static bool 3789 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp, 3790 u8 max_frl_bw_mask, u8 *frl_trained_mask) 3791 { 3792 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) && 3793 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL && 3794 *frl_trained_mask >= max_frl_bw_mask) 3795 return true; 3796 3797 return false; 3798 } 3799 3800 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) 3801 { 3802 struct intel_display *display = to_intel_display(intel_dp); 3803 #define TIMEOUT_FRL_READY_MS 500 3804 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 3805 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret; 3806 u8 max_frl_bw_mask = 0, frl_trained_mask; 3807 bool is_active; 3808 3809 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 3810 drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); 3811 3812 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp); 3813 drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n", 3814 max_edid_frl_bw); 3815 3816 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw); 3817 3818 if (max_frl_bw <= 0) 3819 return -EINVAL; 3820 3821 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); 3822 drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask); 3823 3824 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask)) 3825 goto frl_trained; 3826 3827 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); 3828 if (ret < 0) 3829 return ret; 3830 /* Wait for PCON to be FRL Ready */ 3831 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS); 3832 3833 if (!is_active) 3834 return -ETIMEDOUT; 3835 3836 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, 3837 DP_PCON_ENABLE_SEQUENTIAL_LINK); 3838 if (ret < 0) 3839 return ret; 3840 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, 3841 DP_PCON_FRL_LINK_TRAIN_NORMAL); 3842 if (ret < 0) 3843 return ret; 3844 ret = drm_dp_pcon_frl_enable(&intel_dp->aux); 3845 if (ret < 0) 3846 return ret; 3847 /* 3848 * Wait for FRL to be completed 3849 * Check if the HDMI Link is up and active. 3850 */ 3851 wait_for(is_active = 3852 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask), 3853 TIMEOUT_HDMI_LINK_ACTIVE_MS); 3854 3855 if (!is_active) 3856 return -ETIMEDOUT; 3857 3858 frl_trained: 3859 drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask); 3860 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); 3861 intel_dp->frl.is_trained = true; 3862 drm_dbg(display->drm, "FRL trained with : %d Gbps\n", 3863 intel_dp->frl.trained_rate_gbps); 3864 3865 return 0; 3866 } 3867 3868 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) 3869 { 3870 if (drm_dp_is_branch(intel_dp->dpcd) && 3871 intel_dp_has_hdmi_sink(intel_dp) && 3872 intel_dp_hdmi_sink_max_frl(intel_dp) > 0) 3873 return true; 3874 3875 return false; 3876 } 3877 3878 static 3879 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp) 3880 { 3881 int ret; 3882 u8 buf = 0; 3883 3884 /* Set PCON source control mode */ 3885 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE; 3886 3887 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3888 if (ret < 0) 3889 return ret; 3890 3891 /* Set HDMI LINK ENABLE */ 3892 buf |= DP_PCON_ENABLE_HDMI_LINK; 3893 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3894 if (ret < 0) 3895 return ret; 3896 3897 return 0; 3898 } 3899 3900 void intel_dp_check_frl_training(struct intel_dp *intel_dp) 3901 { 3902 struct intel_display *display = to_intel_display(intel_dp); 3903 3904 /* 3905 * Always go for FRL training if: 3906 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) 3907 * -sink is HDMI2.1 3908 */ 3909 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || 3910 !intel_dp_is_hdmi_2_1_sink(intel_dp) || 3911 intel_dp->frl.is_trained) 3912 return; 3913 3914 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) { 3915 int ret, mode; 3916 3917 drm_dbg(display->drm, 3918 "Couldn't set FRL mode, continuing with TMDS mode\n"); 3919 ret = intel_dp_pcon_set_tmds_mode(intel_dp); 3920 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); 3921 3922 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS) 3923 drm_dbg(display->drm, 3924 "Issue with PCON, cannot set TMDS mode\n"); 3925 } else { 3926 drm_dbg(display->drm, "FRL training Completed\n"); 3927 } 3928 } 3929 3930 static int 3931 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state) 3932 { 3933 int vactive = crtc_state->hw.adjusted_mode.vdisplay; 3934 3935 return intel_hdmi_dsc_get_slice_height(vactive); 3936 } 3937 3938 static int 3939 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, 3940 const struct intel_crtc_state *crtc_state) 3941 { 3942 struct intel_connector *connector = intel_dp->attached_connector; 3943 const struct drm_display_info *info = &connector->base.display_info; 3944 int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice; 3945 int hdmi_max_slices = info->hdmi.dsc_cap.max_slices; 3946 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); 3947 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); 3948 3949 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, 3950 pcon_max_slice_width, 3951 hdmi_max_slices, hdmi_throughput); 3952 } 3953 3954 static int 3955 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, 3956 const struct intel_crtc_state *crtc_state, 3957 int num_slices, int slice_width) 3958 { 3959 struct intel_connector *connector = intel_dp->attached_connector; 3960 const struct drm_display_info *info = &connector->base.display_info; 3961 int output_format = crtc_state->output_format; 3962 bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp; 3963 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); 3964 int hdmi_max_chunk_bytes = 3965 info->hdmi.dsc_cap.total_chunk_kbytes * 1024; 3966 3967 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, 3968 num_slices, output_format, hdmi_all_bpp, 3969 hdmi_max_chunk_bytes); 3970 } 3971 3972 void 3973 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 3974 const struct intel_crtc_state *crtc_state) 3975 { 3976 struct intel_display *display = to_intel_display(intel_dp); 3977 struct intel_connector *connector = intel_dp->attached_connector; 3978 const struct drm_display_info *info; 3979 u8 pps_param[6]; 3980 int slice_height; 3981 int slice_width; 3982 int num_slices; 3983 int bits_per_pixel; 3984 int ret; 3985 bool hdmi_is_dsc_1_2; 3986 3987 if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) 3988 return; 3989 3990 if (!connector) 3991 return; 3992 3993 info = &connector->base.display_info; 3994 3995 hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2; 3996 3997 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || 3998 !hdmi_is_dsc_1_2) 3999 return; 4000 4001 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); 4002 if (!slice_height) 4003 return; 4004 4005 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); 4006 if (!num_slices) 4007 return; 4008 4009 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, 4010 num_slices); 4011 4012 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, 4013 num_slices, slice_width); 4014 if (!bits_per_pixel) 4015 return; 4016 4017 pps_param[0] = slice_height & 0xFF; 4018 pps_param[1] = slice_height >> 8; 4019 pps_param[2] = slice_width & 0xFF; 4020 pps_param[3] = slice_width >> 8; 4021 pps_param[4] = bits_per_pixel & 0xFF; 4022 pps_param[5] = (bits_per_pixel >> 8) & 0x3; 4023 4024 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); 4025 if (ret < 0) 4026 drm_dbg_kms(display->drm, "Failed to set pcon DSC\n"); 4027 } 4028 4029 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 4030 const struct intel_crtc_state *crtc_state) 4031 { 4032 struct intel_display *display = to_intel_display(intel_dp); 4033 bool ycbcr444_to_420 = false; 4034 bool rgb_to_ycbcr = false; 4035 u8 tmp; 4036 4037 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) 4038 return; 4039 4040 if (!drm_dp_is_branch(intel_dp->dpcd)) 4041 return; 4042 4043 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0; 4044 4045 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4046 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) 4047 drm_dbg_kms(display->drm, 4048 "Failed to %s protocol converter HDMI mode\n", 4049 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp))); 4050 4051 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 4052 switch (crtc_state->output_format) { 4053 case INTEL_OUTPUT_FORMAT_YCBCR420: 4054 break; 4055 case INTEL_OUTPUT_FORMAT_YCBCR444: 4056 ycbcr444_to_420 = true; 4057 break; 4058 case INTEL_OUTPUT_FORMAT_RGB: 4059 rgb_to_ycbcr = true; 4060 ycbcr444_to_420 = true; 4061 break; 4062 default: 4063 MISSING_CASE(crtc_state->output_format); 4064 break; 4065 } 4066 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 4067 switch (crtc_state->output_format) { 4068 case INTEL_OUTPUT_FORMAT_YCBCR444: 4069 break; 4070 case INTEL_OUTPUT_FORMAT_RGB: 4071 rgb_to_ycbcr = true; 4072 break; 4073 default: 4074 MISSING_CASE(crtc_state->output_format); 4075 break; 4076 } 4077 } 4078 4079 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; 4080 4081 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4082 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) 4083 drm_dbg_kms(display->drm, 4084 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", 4085 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); 4086 4087 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; 4088 4089 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) 4090 drm_dbg_kms(display->drm, 4091 "Failed to %s protocol converter RGB->YCbCr conversion mode\n", 4092 str_enable_disable(tmp)); 4093 } 4094 4095 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) 4096 { 4097 u8 dprx = 0; 4098 4099 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 4100 &dprx) != 1) 4101 return false; 4102 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; 4103 } 4104 4105 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, 4106 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 4107 { 4108 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, 4109 DP_DSC_RECEIVER_CAP_SIZE) < 0) { 4110 drm_err(aux->drm_dev, 4111 "Failed to read DPCD register 0x%x\n", 4112 DP_DSC_SUPPORT); 4113 return; 4114 } 4115 4116 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", 4117 DP_DSC_RECEIVER_CAP_SIZE, 4118 dsc_dpcd); 4119 } 4120 4121 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector) 4122 { 4123 struct intel_display *display = to_intel_display(connector); 4124 4125 /* 4126 * Clear the cached register set to avoid using stale values 4127 * for the sinks that do not support DSC. 4128 */ 4129 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 4130 4131 /* Clear fec_capable to avoid using stale values */ 4132 connector->dp.fec_capability = 0; 4133 4134 if (dpcd_rev < DP_DPCD_REV_14) 4135 return; 4136 4137 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, 4138 connector->dp.dsc_dpcd); 4139 4140 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, 4141 &connector->dp.fec_capability) < 0) { 4142 drm_err(display->drm, "Failed to read FEC DPCD register\n"); 4143 return; 4144 } 4145 4146 drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n", 4147 connector->dp.fec_capability); 4148 } 4149 4150 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) 4151 { 4152 if (edp_dpcd_rev < DP_EDP_14) 4153 return; 4154 4155 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); 4156 } 4157 4158 static void 4159 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) 4160 { 4161 struct intel_display *display = to_intel_display(intel_dp); 4162 4163 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ 4164 if (!HAS_DSC(display)) 4165 return; 4166 4167 if (intel_dp_is_edp(intel_dp)) 4168 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], 4169 connector); 4170 else 4171 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], 4172 connector); 4173 } 4174 4175 static void intel_edp_mso_mode_fixup(struct intel_connector *connector, 4176 struct drm_display_mode *mode) 4177 { 4178 struct intel_display *display = to_intel_display(connector); 4179 struct intel_dp *intel_dp = intel_attached_dp(connector); 4180 int n = intel_dp->mso_link_count; 4181 int overlap = intel_dp->mso_pixel_overlap; 4182 4183 if (!mode || !n) 4184 return; 4185 4186 mode->hdisplay = (mode->hdisplay - overlap) * n; 4187 mode->hsync_start = (mode->hsync_start - overlap) * n; 4188 mode->hsync_end = (mode->hsync_end - overlap) * n; 4189 mode->htotal = (mode->htotal - overlap) * n; 4190 mode->clock *= n; 4191 4192 drm_mode_set_name(mode); 4193 4194 drm_dbg_kms(display->drm, 4195 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n", 4196 connector->base.base.id, connector->base.name, 4197 DRM_MODE_ARG(mode)); 4198 } 4199 4200 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) 4201 { 4202 struct intel_display *display = to_intel_display(encoder); 4203 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4204 struct intel_connector *connector = intel_dp->attached_connector; 4205 4206 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { 4207 /* 4208 * This is a big fat ugly hack. 4209 * 4210 * Some machines in UEFI boot mode provide us a VBT that has 18 4211 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4212 * unknown we fail to light up. Yet the same BIOS boots up with 4213 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4214 * max, not what it tells us to use. 4215 * 4216 * Note: This will still be broken if the eDP panel is not lit 4217 * up by the BIOS, and thus we can't get the mode at module 4218 * load. 4219 */ 4220 drm_dbg_kms(display->drm, 4221 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4222 pipe_bpp, connector->panel.vbt.edp.bpp); 4223 connector->panel.vbt.edp.bpp = pipe_bpp; 4224 } 4225 } 4226 4227 static void intel_edp_mso_init(struct intel_dp *intel_dp) 4228 { 4229 struct intel_display *display = to_intel_display(intel_dp); 4230 struct intel_connector *connector = intel_dp->attached_connector; 4231 struct drm_display_info *info = &connector->base.display_info; 4232 u8 mso; 4233 4234 if (intel_dp->edp_dpcd[0] < DP_EDP_14) 4235 return; 4236 4237 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { 4238 drm_err(display->drm, "Failed to read MSO cap\n"); 4239 return; 4240 } 4241 4242 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ 4243 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; 4244 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { 4245 drm_err(display->drm, "Invalid MSO link count cap %u\n", mso); 4246 mso = 0; 4247 } 4248 4249 if (mso) { 4250 drm_dbg_kms(display->drm, 4251 "Sink MSO %ux%u configuration, pixel overlap %u\n", 4252 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, 4253 info->mso_pixel_overlap); 4254 if (!HAS_MSO(display)) { 4255 drm_err(display->drm, 4256 "No source MSO support, disabling\n"); 4257 mso = 0; 4258 } 4259 } 4260 4261 intel_dp->mso_link_count = mso; 4262 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; 4263 } 4264 4265 static void 4266 intel_edp_set_sink_rates(struct intel_dp *intel_dp) 4267 { 4268 struct intel_display *display = to_intel_display(intel_dp); 4269 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4270 4271 intel_dp->num_sink_rates = 0; 4272 4273 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { 4274 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 4275 int i; 4276 4277 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 4278 sink_rates, sizeof(sink_rates)); 4279 4280 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 4281 int rate; 4282 4283 /* Value read multiplied by 200kHz gives the per-lane 4284 * link rate in kHz. The source rates are, however, 4285 * stored in terms of LS_Clk kHz. The full conversion 4286 * back to symbols is 4287 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) 4288 */ 4289 rate = le16_to_cpu(sink_rates[i]) * 200 / 10; 4290 4291 if (rate == 0) 4292 break; 4293 4294 /* 4295 * Some broken eDP sinks illegally declare support for 4296 * HBR3 without TPS4, and are unable to produce a stable 4297 * output. Reject HBR3 when TPS4 is not available. 4298 */ 4299 if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) { 4300 drm_dbg_kms(display->drm, 4301 "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n", 4302 encoder->base.base.id, encoder->base.name); 4303 break; 4304 } 4305 4306 intel_dp->sink_rates[i] = rate; 4307 } 4308 intel_dp->num_sink_rates = i; 4309 } 4310 4311 /* 4312 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, 4313 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. 4314 */ 4315 if (intel_dp->num_sink_rates) 4316 intel_dp->use_rate_select = true; 4317 else 4318 intel_dp_set_sink_rates(intel_dp); 4319 } 4320 4321 static bool 4322 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 4323 { 4324 struct intel_display *display = to_intel_display(intel_dp); 4325 4326 /* this function is meant to be called only once */ 4327 drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); 4328 4329 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) 4330 return false; 4331 4332 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4333 drm_dp_is_branch(intel_dp->dpcd)); 4334 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4335 4336 intel_dp->colorimetry_support = 4337 intel_dp_get_colorimetry_status(intel_dp); 4338 4339 /* 4340 * Read the eDP display control registers. 4341 * 4342 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in 4343 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it 4344 * set, but require eDP 1.4+ detection (e.g. for supported link rates 4345 * method). The display control registers should read zero if they're 4346 * not supported anyway. 4347 */ 4348 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 4349 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 4350 sizeof(intel_dp->edp_dpcd)) { 4351 drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n", 4352 (int)sizeof(intel_dp->edp_dpcd), 4353 intel_dp->edp_dpcd); 4354 4355 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; 4356 } 4357 4358 /* 4359 * If needed, program our source OUI so we can make various Intel-specific AUX services 4360 * available (such as HDR backlight controls) 4361 */ 4362 intel_dp_init_source_oui(intel_dp); 4363 4364 /* 4365 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 4366 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 4367 */ 4368 intel_psr_init_dpcd(intel_dp); 4369 4370 intel_edp_set_sink_rates(intel_dp); 4371 intel_dp_set_max_sink_lane_count(intel_dp); 4372 4373 /* Read the eDP DSC DPCD registers */ 4374 intel_dp_detect_dsc_caps(intel_dp, connector); 4375 4376 return true; 4377 } 4378 4379 static bool 4380 intel_dp_has_sink_count(struct intel_dp *intel_dp) 4381 { 4382 if (!intel_dp->attached_connector) 4383 return false; 4384 4385 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, 4386 intel_dp->dpcd, 4387 &intel_dp->desc); 4388 } 4389 4390 void intel_dp_update_sink_caps(struct intel_dp *intel_dp) 4391 { 4392 intel_dp_set_sink_rates(intel_dp); 4393 intel_dp_set_max_sink_lane_count(intel_dp); 4394 intel_dp_set_common_rates(intel_dp); 4395 } 4396 4397 static bool 4398 intel_dp_get_dpcd(struct intel_dp *intel_dp) 4399 { 4400 int ret; 4401 4402 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) 4403 return false; 4404 4405 /* 4406 * Don't clobber cached eDP rates. Also skip re-reading 4407 * the OUI/ID since we know it won't change. 4408 */ 4409 if (!intel_dp_is_edp(intel_dp)) { 4410 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4411 drm_dp_is_branch(intel_dp->dpcd)); 4412 4413 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4414 4415 intel_dp->colorimetry_support = 4416 intel_dp_get_colorimetry_status(intel_dp); 4417 4418 intel_dp_update_sink_caps(intel_dp); 4419 } 4420 4421 if (intel_dp_has_sink_count(intel_dp)) { 4422 ret = drm_dp_read_sink_count(&intel_dp->aux); 4423 if (ret < 0) 4424 return false; 4425 4426 /* 4427 * Sink count can change between short pulse hpd hence 4428 * a member variable in intel_dp will track any changes 4429 * between short pulse interrupts. 4430 */ 4431 intel_dp->sink_count = ret; 4432 4433 /* 4434 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 4435 * a dongle is present but no display. Unless we require to know 4436 * if a dongle is present or not, we don't need to update 4437 * downstream port information. So, an early return here saves 4438 * time from performing other operations which are not required. 4439 */ 4440 if (!intel_dp->sink_count) 4441 return false; 4442 } 4443 4444 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, 4445 intel_dp->downstream_ports) == 0; 4446 } 4447 4448 static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode) 4449 { 4450 if (mst_mode == DRM_DP_MST) 4451 return "MST"; 4452 else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG) 4453 return "SST w/ sideband messaging"; 4454 else 4455 return "SST"; 4456 } 4457 4458 static enum drm_dp_mst_mode 4459 intel_dp_mst_mode_choose(struct intel_dp *intel_dp, 4460 enum drm_dp_mst_mode sink_mst_mode) 4461 { 4462 struct intel_display *display = to_intel_display(intel_dp); 4463 4464 if (!display->params.enable_dp_mst) 4465 return DRM_DP_SST; 4466 4467 if (!intel_dp_mst_source_support(intel_dp)) 4468 return DRM_DP_SST; 4469 4470 if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG && 4471 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)) 4472 return DRM_DP_SST; 4473 4474 return sink_mst_mode; 4475 } 4476 4477 static enum drm_dp_mst_mode 4478 intel_dp_mst_detect(struct intel_dp *intel_dp) 4479 { 4480 struct intel_display *display = to_intel_display(intel_dp); 4481 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4482 enum drm_dp_mst_mode sink_mst_mode; 4483 enum drm_dp_mst_mode mst_detect; 4484 4485 sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 4486 4487 mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode); 4488 4489 drm_dbg_kms(display->drm, 4490 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n", 4491 encoder->base.base.id, encoder->base.name, 4492 str_yes_no(intel_dp_mst_source_support(intel_dp)), 4493 intel_dp_mst_mode_str(sink_mst_mode), 4494 str_yes_no(display->params.enable_dp_mst), 4495 intel_dp_mst_mode_str(mst_detect)); 4496 4497 return mst_detect; 4498 } 4499 4500 static void 4501 intel_dp_mst_configure(struct intel_dp *intel_dp) 4502 { 4503 if (!intel_dp_mst_source_support(intel_dp)) 4504 return; 4505 4506 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST; 4507 4508 if (intel_dp->is_mst) 4509 intel_dp_mst_prepare_probe(intel_dp); 4510 4511 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst); 4512 4513 /* Avoid stale info on the next detect cycle. */ 4514 intel_dp->mst_detect = DRM_DP_SST; 4515 } 4516 4517 static void 4518 intel_dp_mst_disconnect(struct intel_dp *intel_dp) 4519 { 4520 struct intel_display *display = to_intel_display(intel_dp); 4521 4522 if (!intel_dp->is_mst) 4523 return; 4524 4525 drm_dbg_kms(display->drm, 4526 "MST device may have disappeared %d vs %d\n", 4527 intel_dp->is_mst, intel_dp->mst.mgr.mst_state); 4528 intel_dp->is_mst = false; 4529 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst); 4530 } 4531 4532 static bool 4533 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi) 4534 { 4535 struct intel_display *display = to_intel_display(intel_dp); 4536 4537 /* 4538 * Display WA for HSD #13013007775: mtl/arl/lnl 4539 * Read the sink count and link service IRQ registers in separate 4540 * transactions to prevent disconnecting the sink on a TBT link 4541 * inadvertently. 4542 */ 4543 if (IS_DISPLAY_VER(display, 14, 20) && !display->platform.battlemage) { 4544 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 3) != 3) 4545 return false; 4546 4547 /* DP_SINK_COUNT_ESI + 3 == DP_LINK_SERVICE_IRQ_VECTOR_ESI0 */ 4548 return drm_dp_dpcd_readb(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, 4549 &esi[3]) == 1; 4550 } 4551 4552 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; 4553 } 4554 4555 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4]) 4556 { 4557 int retry; 4558 4559 for (retry = 0; retry < 3; retry++) { 4560 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1, 4561 &esi[1], 3) == 3) 4562 return true; 4563 } 4564 4565 return false; 4566 } 4567 4568 bool 4569 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 4570 const struct drm_connector_state *conn_state) 4571 { 4572 /* 4573 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 4574 * of Color Encoding Format and Content Color Gamut], in order to 4575 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. 4576 */ 4577 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 4578 return true; 4579 4580 switch (conn_state->colorspace) { 4581 case DRM_MODE_COLORIMETRY_SYCC_601: 4582 case DRM_MODE_COLORIMETRY_OPYCC_601: 4583 case DRM_MODE_COLORIMETRY_BT2020_YCC: 4584 case DRM_MODE_COLORIMETRY_BT2020_RGB: 4585 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 4586 return true; 4587 default: 4588 break; 4589 } 4590 4591 return false; 4592 } 4593 4594 static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, 4595 struct dp_sdp *sdp, size_t size) 4596 { 4597 size_t length = sizeof(struct dp_sdp); 4598 4599 if (size < length) 4600 return -ENOSPC; 4601 4602 memset(sdp, 0, size); 4603 4604 /* Prepare AS (Adaptive Sync) SDP Header */ 4605 sdp->sdp_header.HB0 = 0; 4606 sdp->sdp_header.HB1 = as_sdp->sdp_type; 4607 sdp->sdp_header.HB2 = 0x02; 4608 sdp->sdp_header.HB3 = as_sdp->length; 4609 4610 /* Fill AS (Adaptive Sync) SDP Payload */ 4611 sdp->db[0] = as_sdp->mode; 4612 sdp->db[1] = as_sdp->vtotal & 0xFF; 4613 sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF; 4614 sdp->db[3] = as_sdp->target_rr & 0xFF; 4615 sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; 4616 4617 if (as_sdp->target_rr_divider) 4618 sdp->db[4] |= 0x20; 4619 4620 return length; 4621 } 4622 4623 static ssize_t 4624 intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display, 4625 const struct hdmi_drm_infoframe *drm_infoframe, 4626 struct dp_sdp *sdp, 4627 size_t size) 4628 { 4629 size_t length = sizeof(struct dp_sdp); 4630 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; 4631 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; 4632 ssize_t len; 4633 4634 if (size < length) 4635 return -ENOSPC; 4636 4637 memset(sdp, 0, size); 4638 4639 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); 4640 if (len < 0) { 4641 drm_dbg_kms(display->drm, 4642 "buffer size is smaller than hdr metadata infoframe\n"); 4643 return -ENOSPC; 4644 } 4645 4646 if (len != infoframe_size) { 4647 drm_dbg_kms(display->drm, "wrong static hdr metadata size\n"); 4648 return -ENOSPC; 4649 } 4650 4651 /* 4652 * Set up the infoframe sdp packet for HDR static metadata. 4653 * Prepare VSC Header for SU as per DP 1.4a spec, 4654 * Table 2-100 and Table 2-101 4655 */ 4656 4657 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ 4658 sdp->sdp_header.HB0 = 0; 4659 /* 4660 * Packet Type 80h + Non-audio INFOFRAME Type value 4661 * HDMI_INFOFRAME_TYPE_DRM: 0x87 4662 * - 80h + Non-audio INFOFRAME Type value 4663 * - InfoFrame Type: 0x07 4664 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] 4665 */ 4666 sdp->sdp_header.HB1 = drm_infoframe->type; 4667 /* 4668 * Least Significant Eight Bits of (Data Byte Count – 1) 4669 * infoframe_size - 1 4670 */ 4671 sdp->sdp_header.HB2 = 0x1D; 4672 /* INFOFRAME SDP Version Number */ 4673 sdp->sdp_header.HB3 = (0x13 << 2); 4674 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4675 sdp->db[0] = drm_infoframe->version; 4676 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4677 sdp->db[1] = drm_infoframe->length; 4678 /* 4679 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after 4680 * HDMI_INFOFRAME_HEADER_SIZE 4681 */ 4682 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); 4683 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], 4684 HDMI_DRM_INFOFRAME_SIZE); 4685 4686 /* 4687 * Size of DP infoframe sdp packet for HDR static metadata consists of 4688 * - DP SDP Header(struct dp_sdp_header): 4 bytes 4689 * - Two Data Blocks: 2 bytes 4690 * CTA Header Byte2 (INFOFRAME Version Number) 4691 * CTA Header Byte3 (Length of INFOFRAME) 4692 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes 4693 * 4694 * Prior to GEN11's GMP register size is identical to DP HDR static metadata 4695 * infoframe size. But GEN11+ has larger than that size, write_infoframe 4696 * will pad rest of the size. 4697 */ 4698 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; 4699 } 4700 4701 static void intel_write_dp_sdp(struct intel_encoder *encoder, 4702 const struct intel_crtc_state *crtc_state, 4703 unsigned int type) 4704 { 4705 struct intel_display *display = to_intel_display(encoder); 4706 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4707 struct dp_sdp sdp = {}; 4708 ssize_t len; 4709 4710 if ((crtc_state->infoframes.enable & 4711 intel_hdmi_infoframe_enable(type)) == 0) 4712 return; 4713 4714 switch (type) { 4715 case DP_SDP_VSC: 4716 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp); 4717 break; 4718 case HDMI_PACKET_TYPE_GAMUT_METADATA: 4719 len = intel_dp_hdr_metadata_infoframe_sdp_pack(display, 4720 &crtc_state->infoframes.drm.drm, 4721 &sdp, sizeof(sdp)); 4722 break; 4723 case DP_SDP_ADAPTIVE_SYNC: 4724 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp, 4725 sizeof(sdp)); 4726 break; 4727 default: 4728 MISSING_CASE(type); 4729 return; 4730 } 4731 4732 if (drm_WARN_ON(display->drm, len < 0)) 4733 return; 4734 4735 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); 4736 } 4737 4738 void intel_dp_set_infoframes(struct intel_encoder *encoder, 4739 bool enable, 4740 const struct intel_crtc_state *crtc_state, 4741 const struct drm_connector_state *conn_state) 4742 { 4743 struct intel_display *display = to_intel_display(encoder); 4744 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); 4745 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 4746 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | 4747 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; 4748 4749 if (HAS_AS_SDP(display)) 4750 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL; 4751 4752 u32 val = intel_de_read(display, reg) & ~dip_enable; 4753 4754 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ 4755 if (!enable && HAS_DSC(display)) 4756 val &= ~VDIP_ENABLE_PPS; 4757 4758 /* 4759 * This routine disables VSC DIP if the function is called 4760 * to disable SDP or if it does not have PSR 4761 */ 4762 if (!enable || !crtc_state->has_psr) 4763 val &= ~VIDEO_DIP_ENABLE_VSC_HSW; 4764 4765 intel_de_write(display, reg, val); 4766 intel_de_posting_read(display, reg); 4767 4768 if (!enable) 4769 return; 4770 4771 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); 4772 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); 4773 4774 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); 4775 } 4776 4777 static 4778 int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, 4779 const void *buffer, size_t size) 4780 { 4781 const struct dp_sdp *sdp = buffer; 4782 4783 if (size < sizeof(struct dp_sdp)) 4784 return -EINVAL; 4785 4786 memset(as_sdp, 0, sizeof(*as_sdp)); 4787 4788 if (sdp->sdp_header.HB0 != 0) 4789 return -EINVAL; 4790 4791 if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC) 4792 return -EINVAL; 4793 4794 if (sdp->sdp_header.HB2 != 0x02) 4795 return -EINVAL; 4796 4797 if ((sdp->sdp_header.HB3 & 0x3F) != 9) 4798 return -EINVAL; 4799 4800 as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH; 4801 as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; 4802 as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; 4803 as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); 4804 as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; 4805 4806 return 0; 4807 } 4808 4809 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, 4810 const void *buffer, size_t size) 4811 { 4812 const struct dp_sdp *sdp = buffer; 4813 4814 if (size < sizeof(struct dp_sdp)) 4815 return -EINVAL; 4816 4817 memset(vsc, 0, sizeof(*vsc)); 4818 4819 if (sdp->sdp_header.HB0 != 0) 4820 return -EINVAL; 4821 4822 if (sdp->sdp_header.HB1 != DP_SDP_VSC) 4823 return -EINVAL; 4824 4825 vsc->sdp_type = sdp->sdp_header.HB1; 4826 vsc->revision = sdp->sdp_header.HB2; 4827 vsc->length = sdp->sdp_header.HB3; 4828 4829 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || 4830 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) || 4831 (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) { 4832 /* 4833 * - HB2 = 0x2, HB3 = 0x8 4834 * VSC SDP supporting 3D stereo + PSR 4835 * - HB2 = 0x4, HB3 = 0xe 4836 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of 4837 * first scan line of the SU region (applies to eDP v1.4b 4838 * and higher). 4839 * - HB2 = 0x6, HB3 = 0x10 4840 * VSC SDP supporting 3D stereo + Panel Replay. 4841 */ 4842 return 0; 4843 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { 4844 /* 4845 * - HB2 = 0x5, HB3 = 0x13 4846 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry 4847 * Format. 4848 */ 4849 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; 4850 vsc->colorimetry = sdp->db[16] & 0xf; 4851 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; 4852 4853 switch (sdp->db[17] & 0x7) { 4854 case 0x0: 4855 vsc->bpc = 6; 4856 break; 4857 case 0x1: 4858 vsc->bpc = 8; 4859 break; 4860 case 0x2: 4861 vsc->bpc = 10; 4862 break; 4863 case 0x3: 4864 vsc->bpc = 12; 4865 break; 4866 case 0x4: 4867 vsc->bpc = 16; 4868 break; 4869 default: 4870 MISSING_CASE(sdp->db[17] & 0x7); 4871 return -EINVAL; 4872 } 4873 4874 vsc->content_type = sdp->db[18] & 0x7; 4875 } else { 4876 return -EINVAL; 4877 } 4878 4879 return 0; 4880 } 4881 4882 static void 4883 intel_read_dp_as_sdp(struct intel_encoder *encoder, 4884 struct intel_crtc_state *crtc_state, 4885 struct drm_dp_as_sdp *as_sdp) 4886 { 4887 struct intel_display *display = to_intel_display(encoder); 4888 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4889 unsigned int type = DP_SDP_ADAPTIVE_SYNC; 4890 struct dp_sdp sdp = {}; 4891 int ret; 4892 4893 if ((crtc_state->infoframes.enable & 4894 intel_hdmi_infoframe_enable(type)) == 0) 4895 return; 4896 4897 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 4898 sizeof(sdp)); 4899 4900 ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp)); 4901 if (ret) 4902 drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n"); 4903 } 4904 4905 static int 4906 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, 4907 const void *buffer, size_t size) 4908 { 4909 int ret; 4910 4911 const struct dp_sdp *sdp = buffer; 4912 4913 if (size < sizeof(struct dp_sdp)) 4914 return -EINVAL; 4915 4916 if (sdp->sdp_header.HB0 != 0) 4917 return -EINVAL; 4918 4919 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) 4920 return -EINVAL; 4921 4922 /* 4923 * Least Significant Eight Bits of (Data Byte Count – 1) 4924 * 1Dh (i.e., Data Byte Count = 30 bytes). 4925 */ 4926 if (sdp->sdp_header.HB2 != 0x1D) 4927 return -EINVAL; 4928 4929 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ 4930 if ((sdp->sdp_header.HB3 & 0x3) != 0) 4931 return -EINVAL; 4932 4933 /* INFOFRAME SDP Version Number */ 4934 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) 4935 return -EINVAL; 4936 4937 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4938 if (sdp->db[0] != 1) 4939 return -EINVAL; 4940 4941 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4942 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) 4943 return -EINVAL; 4944 4945 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], 4946 HDMI_DRM_INFOFRAME_SIZE); 4947 4948 return ret; 4949 } 4950 4951 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, 4952 struct intel_crtc_state *crtc_state, 4953 struct drm_dp_vsc_sdp *vsc) 4954 { 4955 struct intel_display *display = to_intel_display(encoder); 4956 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4957 unsigned int type = DP_SDP_VSC; 4958 struct dp_sdp sdp = {}; 4959 int ret; 4960 4961 if ((crtc_state->infoframes.enable & 4962 intel_hdmi_infoframe_enable(type)) == 0) 4963 return; 4964 4965 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); 4966 4967 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); 4968 4969 if (ret) 4970 drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n"); 4971 } 4972 4973 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, 4974 struct intel_crtc_state *crtc_state, 4975 struct hdmi_drm_infoframe *drm_infoframe) 4976 { 4977 struct intel_display *display = to_intel_display(encoder); 4978 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4979 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; 4980 struct dp_sdp sdp = {}; 4981 int ret; 4982 4983 if ((crtc_state->infoframes.enable & 4984 intel_hdmi_infoframe_enable(type)) == 0) 4985 return; 4986 4987 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 4988 sizeof(sdp)); 4989 4990 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, 4991 sizeof(sdp)); 4992 4993 if (ret) 4994 drm_dbg_kms(display->drm, 4995 "Failed to unpack DP HDR Metadata Infoframe SDP\n"); 4996 } 4997 4998 void intel_read_dp_sdp(struct intel_encoder *encoder, 4999 struct intel_crtc_state *crtc_state, 5000 unsigned int type) 5001 { 5002 switch (type) { 5003 case DP_SDP_VSC: 5004 intel_read_dp_vsc_sdp(encoder, crtc_state, 5005 &crtc_state->infoframes.vsc); 5006 break; 5007 case HDMI_PACKET_TYPE_GAMUT_METADATA: 5008 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, 5009 &crtc_state->infoframes.drm.drm); 5010 break; 5011 case DP_SDP_ADAPTIVE_SYNC: 5012 intel_read_dp_as_sdp(encoder, crtc_state, 5013 &crtc_state->infoframes.as_sdp); 5014 break; 5015 default: 5016 MISSING_CASE(type); 5017 break; 5018 } 5019 } 5020 5021 static bool intel_dp_link_ok(struct intel_dp *intel_dp, 5022 u8 link_status[DP_LINK_STATUS_SIZE]) 5023 { 5024 struct intel_display *display = to_intel_display(intel_dp); 5025 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5026 bool uhbr = intel_dp->link_rate >= 1000000; 5027 bool ok; 5028 5029 if (uhbr) 5030 ok = drm_dp_128b132b_lane_channel_eq_done(link_status, 5031 intel_dp->lane_count); 5032 else 5033 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); 5034 5035 if (ok) 5036 return true; 5037 5038 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 5039 drm_dbg_kms(display->drm, 5040 "[ENCODER:%d:%s] %s link not ok, retraining\n", 5041 encoder->base.base.id, encoder->base.name, 5042 uhbr ? "128b/132b" : "8b/10b"); 5043 5044 return false; 5045 } 5046 5047 static void 5048 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) 5049 { 5050 bool handled = false; 5051 5052 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst.mgr, esi, ack, &handled); 5053 5054 if (esi[1] & DP_CP_IRQ) { 5055 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5056 ack[1] |= DP_CP_IRQ; 5057 } 5058 } 5059 5060 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp) 5061 { 5062 struct intel_display *display = to_intel_display(intel_dp); 5063 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5064 u8 link_status[DP_LINK_STATUS_SIZE] = {}; 5065 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2; 5066 5067 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status, 5068 esi_link_status_size) != esi_link_status_size) { 5069 drm_err(display->drm, 5070 "[ENCODER:%d:%s] Failed to read link status\n", 5071 encoder->base.base.id, encoder->base.name); 5072 return false; 5073 } 5074 5075 return intel_dp_link_ok(intel_dp, link_status); 5076 } 5077 5078 /** 5079 * intel_dp_check_mst_status - service any pending MST interrupts, check link status 5080 * @intel_dp: Intel DP struct 5081 * 5082 * Read any pending MST interrupts, call MST core to handle these and ack the 5083 * interrupts. Check if the main and AUX link state is ok. 5084 * 5085 * Returns: 5086 * - %true if pending interrupts were serviced (or no interrupts were 5087 * pending) w/o detecting an error condition. 5088 * - %false if an error condition - like AUX failure or a loss of link - is 5089 * detected, or another condition - like a DP tunnel BW state change - needs 5090 * servicing from the hotplug work. 5091 */ 5092 static bool 5093 intel_dp_check_mst_status(struct intel_dp *intel_dp) 5094 { 5095 struct intel_display *display = to_intel_display(intel_dp); 5096 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5097 struct intel_encoder *encoder = &dig_port->base; 5098 bool link_ok = true; 5099 bool reprobe_needed = false; 5100 5101 for (;;) { 5102 u8 esi[4] = {}; 5103 u8 ack[4] = {}; 5104 5105 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { 5106 drm_dbg_kms(display->drm, 5107 "failed to get ESI - device may have failed\n"); 5108 link_ok = false; 5109 5110 break; 5111 } 5112 5113 drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi); 5114 5115 if (intel_dp_mst_active_streams(intel_dp) > 0 && link_ok && 5116 esi[3] & LINK_STATUS_CHANGED) { 5117 if (!intel_dp_mst_link_status(intel_dp)) 5118 link_ok = false; 5119 ack[3] |= LINK_STATUS_CHANGED; 5120 } 5121 5122 intel_dp_mst_hpd_irq(intel_dp, esi, ack); 5123 5124 if (esi[3] & DP_TUNNELING_IRQ) { 5125 if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr, 5126 &intel_dp->aux)) 5127 reprobe_needed = true; 5128 ack[3] |= DP_TUNNELING_IRQ; 5129 } 5130 5131 if (mem_is_zero(ack, sizeof(ack))) 5132 break; 5133 5134 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack)) 5135 drm_dbg_kms(display->drm, "Failed to ack ESI\n"); 5136 5137 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY)) 5138 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst.mgr); 5139 } 5140 5141 if (!link_ok || intel_dp->link.force_retrain) 5142 intel_encoder_link_check_queue_work(encoder, 0); 5143 5144 return !reprobe_needed; 5145 } 5146 5147 static void 5148 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) 5149 { 5150 bool is_active; 5151 u8 buf = 0; 5152 5153 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); 5154 if (intel_dp->frl.is_trained && !is_active) { 5155 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) 5156 return; 5157 5158 buf &= ~DP_PCON_ENABLE_HDMI_LINK; 5159 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) 5160 return; 5161 5162 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); 5163 5164 intel_dp->frl.is_trained = false; 5165 5166 /* Restart FRL training or fall back to TMDS mode */ 5167 intel_dp_check_frl_training(intel_dp); 5168 } 5169 } 5170 5171 static bool 5172 intel_dp_needs_link_retrain(struct intel_dp *intel_dp) 5173 { 5174 u8 link_status[DP_LINK_STATUS_SIZE]; 5175 5176 if (!intel_dp->link.active) 5177 return false; 5178 5179 /* 5180 * While PSR source HW is enabled, it will control main-link sending 5181 * frames, enabling and disabling it so trying to do a retrain will fail 5182 * as the link would or not be on or it could mix training patterns 5183 * and frame data at the same time causing retrain to fail. 5184 * Also when exiting PSR, HW will retrain the link anyways fixing 5185 * any link status error. 5186 */ 5187 if (intel_psr_enabled(intel_dp)) 5188 return false; 5189 5190 if (intel_dp->link.force_retrain) 5191 return true; 5192 5193 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 5194 link_status) < 0) 5195 return false; 5196 5197 /* 5198 * Validate the cached values of intel_dp->link_rate and 5199 * intel_dp->lane_count before attempting to retrain. 5200 * 5201 * FIXME would be nice to user the crtc state here, but since 5202 * we need to call this from the short HPD handler that seems 5203 * a bit hard. 5204 */ 5205 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, 5206 intel_dp->lane_count)) 5207 return false; 5208 5209 if (intel_dp->link.retrain_disabled) 5210 return false; 5211 5212 if (intel_dp->link.seq_train_failures) 5213 return true; 5214 5215 /* Retrain if link not ok */ 5216 return !intel_dp_link_ok(intel_dp, link_status) && 5217 !intel_psr_link_ok(intel_dp); 5218 } 5219 5220 bool intel_dp_has_connector(struct intel_dp *intel_dp, 5221 const struct drm_connector_state *conn_state) 5222 { 5223 struct intel_display *display = to_intel_display(intel_dp); 5224 struct intel_encoder *encoder; 5225 enum pipe pipe; 5226 5227 if (!conn_state->best_encoder) 5228 return false; 5229 5230 /* SST */ 5231 encoder = &dp_to_dig_port(intel_dp)->base; 5232 if (conn_state->best_encoder == &encoder->base) 5233 return true; 5234 5235 /* MST */ 5236 for_each_pipe(display, pipe) { 5237 encoder = &intel_dp->mst.stream_encoders[pipe]->base; 5238 if (conn_state->best_encoder == &encoder->base) 5239 return true; 5240 } 5241 5242 return false; 5243 } 5244 5245 static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state) 5246 { 5247 struct intel_connector *connector = to_intel_connector(conn_state->connector); 5248 struct intel_display *display = to_intel_display(connector); 5249 5250 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); 5251 5252 if (!conn_state->commit) 5253 return; 5254 5255 drm_WARN_ON(display->drm, 5256 !wait_for_completion_timeout(&conn_state->commit->hw_done, 5257 msecs_to_jiffies(5000))); 5258 } 5259 5260 int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 5261 struct drm_modeset_acquire_ctx *ctx, 5262 u8 *pipe_mask) 5263 { 5264 struct intel_display *display = to_intel_display(intel_dp); 5265 struct drm_connector_list_iter conn_iter; 5266 struct intel_connector *connector; 5267 int ret = 0; 5268 5269 *pipe_mask = 0; 5270 5271 drm_connector_list_iter_begin(display->drm, &conn_iter); 5272 for_each_intel_connector_iter(connector, &conn_iter) { 5273 struct drm_connector_state *conn_state = 5274 connector->base.state; 5275 struct intel_crtc_state *crtc_state; 5276 struct intel_crtc *crtc; 5277 5278 if (!intel_dp_has_connector(intel_dp, conn_state)) 5279 continue; 5280 5281 crtc = to_intel_crtc(conn_state->crtc); 5282 if (!crtc) 5283 continue; 5284 5285 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 5286 if (ret) 5287 break; 5288 5289 crtc_state = to_intel_crtc_state(crtc->base.state); 5290 5291 drm_WARN_ON(display->drm, 5292 !intel_crtc_has_dp_encoder(crtc_state)); 5293 5294 if (!crtc_state->hw.active) 5295 continue; 5296 5297 wait_for_connector_hw_done(conn_state); 5298 5299 *pipe_mask |= BIT(crtc->pipe); 5300 } 5301 drm_connector_list_iter_end(&conn_iter); 5302 5303 return ret; 5304 } 5305 5306 void intel_dp_flush_connector_commits(struct intel_connector *connector) 5307 { 5308 wait_for_connector_hw_done(connector->base.state); 5309 } 5310 5311 static bool intel_dp_is_connected(struct intel_dp *intel_dp) 5312 { 5313 struct intel_connector *connector = intel_dp->attached_connector; 5314 5315 return connector->base.status == connector_status_connected || 5316 intel_dp->is_mst; 5317 } 5318 5319 static int intel_dp_retrain_link(struct intel_encoder *encoder, 5320 struct drm_modeset_acquire_ctx *ctx) 5321 { 5322 struct intel_display *display = to_intel_display(encoder); 5323 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5324 u8 pipe_mask; 5325 int ret; 5326 5327 if (!intel_dp_is_connected(intel_dp)) 5328 return 0; 5329 5330 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 5331 ctx); 5332 if (ret) 5333 return ret; 5334 5335 if (!intel_dp_needs_link_retrain(intel_dp)) 5336 return 0; 5337 5338 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); 5339 if (ret) 5340 return ret; 5341 5342 if (pipe_mask == 0) 5343 return 0; 5344 5345 if (!intel_dp_needs_link_retrain(intel_dp)) 5346 return 0; 5347 5348 drm_dbg_kms(display->drm, 5349 "[ENCODER:%d:%s] retraining link (forced %s)\n", 5350 encoder->base.base.id, encoder->base.name, 5351 str_yes_no(intel_dp->link.force_retrain)); 5352 5353 ret = intel_modeset_commit_pipes(display, pipe_mask, ctx); 5354 if (ret == -EDEADLK) 5355 return ret; 5356 5357 intel_dp->link.force_retrain = false; 5358 5359 if (ret) 5360 drm_dbg_kms(display->drm, 5361 "[ENCODER:%d:%s] link retraining failed: %pe\n", 5362 encoder->base.base.id, encoder->base.name, 5363 ERR_PTR(ret)); 5364 5365 return ret; 5366 } 5367 5368 void intel_dp_link_check(struct intel_encoder *encoder) 5369 { 5370 struct drm_modeset_acquire_ctx ctx; 5371 int ret; 5372 5373 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 5374 ret = intel_dp_retrain_link(encoder, &ctx); 5375 } 5376 5377 void intel_dp_check_link_state(struct intel_dp *intel_dp) 5378 { 5379 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5380 struct intel_encoder *encoder = &dig_port->base; 5381 5382 if (!intel_dp_is_connected(intel_dp)) 5383 return; 5384 5385 if (!intel_dp_needs_link_retrain(intel_dp)) 5386 return; 5387 5388 intel_encoder_link_check_queue_work(encoder, 0); 5389 } 5390 5391 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp) 5392 { 5393 struct intel_display *display = to_intel_display(intel_dp); 5394 u8 val; 5395 5396 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5397 return; 5398 5399 if (drm_dp_dpcd_readb(&intel_dp->aux, 5400 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) 5401 return; 5402 5403 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); 5404 5405 if (val & DP_AUTOMATED_TEST_REQUEST) 5406 intel_dp_test_request(intel_dp); 5407 5408 if (val & DP_CP_IRQ) 5409 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5410 5411 if (val & DP_SINK_SPECIFIC_IRQ) 5412 drm_dbg_kms(display->drm, "Sink specific irq unhandled\n"); 5413 } 5414 5415 static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp) 5416 { 5417 struct intel_display *display = to_intel_display(intel_dp); 5418 bool reprobe_needed = false; 5419 u8 val; 5420 5421 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5422 return false; 5423 5424 if (drm_dp_dpcd_readb(&intel_dp->aux, 5425 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) 5426 return false; 5427 5428 if ((val & DP_TUNNELING_IRQ) && 5429 drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr, 5430 &intel_dp->aux)) 5431 reprobe_needed = true; 5432 5433 if (drm_dp_dpcd_writeb(&intel_dp->aux, 5434 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) 5435 return reprobe_needed; 5436 5437 if (val & HDMI_LINK_STATUS_CHANGED) 5438 intel_dp_handle_hdmi_link_status_change(intel_dp); 5439 5440 return reprobe_needed; 5441 } 5442 5443 /* 5444 * According to DP spec 5445 * 5.1.2: 5446 * 1. Read DPCD 5447 * 2. Configure link according to Receiver Capabilities 5448 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 5449 * 4. Check link status on receipt of hot-plug interrupt 5450 * 5451 * intel_dp_short_pulse - handles short pulse interrupts 5452 * when full detection is not required. 5453 * Returns %true if short pulse is handled and full detection 5454 * is NOT required and %false otherwise. 5455 */ 5456 static bool 5457 intel_dp_short_pulse(struct intel_dp *intel_dp) 5458 { 5459 u8 old_sink_count = intel_dp->sink_count; 5460 bool reprobe_needed = false; 5461 bool ret; 5462 5463 intel_dp_test_reset(intel_dp); 5464 5465 /* 5466 * Now read the DPCD to see if it's actually running 5467 * If the current value of sink count doesn't match with 5468 * the value that was stored earlier or dpcd read failed 5469 * we need to do full detection 5470 */ 5471 ret = intel_dp_get_dpcd(intel_dp); 5472 5473 if ((old_sink_count != intel_dp->sink_count) || !ret) { 5474 /* No need to proceed if we are going to do full detect */ 5475 return false; 5476 } 5477 5478 intel_dp_check_device_service_irq(intel_dp); 5479 reprobe_needed = intel_dp_check_link_service_irq(intel_dp); 5480 5481 /* Handle CEC interrupts, if any */ 5482 drm_dp_cec_irq(&intel_dp->aux); 5483 5484 intel_dp_check_link_state(intel_dp); 5485 5486 intel_psr_short_pulse(intel_dp); 5487 5488 if (intel_alpm_get_error(intel_dp)) { 5489 intel_alpm_disable(intel_dp); 5490 intel_dp->alpm_parameters.sink_alpm_error = true; 5491 } 5492 5493 if (intel_dp_test_short_pulse(intel_dp)) 5494 reprobe_needed = true; 5495 5496 return !reprobe_needed; 5497 } 5498 5499 /* XXX this is probably wrong for multiple downstream ports */ 5500 static enum drm_connector_status 5501 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 5502 { 5503 struct intel_display *display = to_intel_display(intel_dp); 5504 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5505 u8 *dpcd = intel_dp->dpcd; 5506 u8 type; 5507 5508 if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp))) 5509 return connector_status_connected; 5510 5511 intel_lspcon_resume(dig_port); 5512 5513 if (!intel_dp_get_dpcd(intel_dp)) 5514 return connector_status_disconnected; 5515 5516 intel_dp->mst_detect = intel_dp_mst_detect(intel_dp); 5517 5518 /* if there's no downstream port, we're done */ 5519 if (!drm_dp_is_branch(dpcd)) 5520 return connector_status_connected; 5521 5522 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 5523 if (intel_dp_has_sink_count(intel_dp) && 5524 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 5525 return intel_dp->sink_count ? 5526 connector_status_connected : connector_status_disconnected; 5527 } 5528 5529 if (intel_dp->mst_detect == DRM_DP_MST) 5530 return connector_status_connected; 5531 5532 /* If no HPD, poke DDC gently */ 5533 if (drm_probe_ddc(&intel_dp->aux.ddc)) 5534 return connector_status_connected; 5535 5536 /* Well we tried, say unknown for unreliable port types */ 5537 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 5538 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 5539 if (type == DP_DS_PORT_TYPE_VGA || 5540 type == DP_DS_PORT_TYPE_NON_EDID) 5541 return connector_status_unknown; 5542 } else { 5543 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 5544 DP_DWN_STRM_PORT_TYPE_MASK; 5545 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 5546 type == DP_DWN_STRM_PORT_TYPE_OTHER) 5547 return connector_status_unknown; 5548 } 5549 5550 /* Anything else is out of spec, warn and ignore */ 5551 drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n"); 5552 return connector_status_disconnected; 5553 } 5554 5555 static enum drm_connector_status 5556 edp_detect(struct intel_dp *intel_dp) 5557 { 5558 return connector_status_connected; 5559 } 5560 5561 void intel_digital_port_lock(struct intel_encoder *encoder) 5562 { 5563 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5564 5565 if (dig_port->lock) 5566 dig_port->lock(dig_port); 5567 } 5568 5569 void intel_digital_port_unlock(struct intel_encoder *encoder) 5570 { 5571 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5572 5573 if (dig_port->unlock) 5574 dig_port->unlock(dig_port); 5575 } 5576 5577 /* 5578 * intel_digital_port_connected_locked - is the specified port connected? 5579 * @encoder: intel_encoder 5580 * 5581 * In cases where there's a connector physically connected but it can't be used 5582 * by our hardware we also return false, since the rest of the driver should 5583 * pretty much treat the port as disconnected. This is relevant for type-C 5584 * (starting on ICL) where there's ownership involved. 5585 * 5586 * The caller must hold the lock acquired by calling intel_digital_port_lock() 5587 * when calling this function. 5588 * 5589 * Return %true if port is connected, %false otherwise. 5590 */ 5591 bool intel_digital_port_connected_locked(struct intel_encoder *encoder) 5592 { 5593 struct intel_display *display = to_intel_display(encoder); 5594 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5595 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); 5596 bool is_connected = false; 5597 intel_wakeref_t wakeref; 5598 5599 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { 5600 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4); 5601 5602 do { 5603 is_connected = dig_port->connected(encoder); 5604 if (is_connected || is_glitch_free) 5605 break; 5606 usleep_range(10, 30); 5607 } while (time_before(jiffies, wait_expires)); 5608 } 5609 5610 return is_connected; 5611 } 5612 5613 bool intel_digital_port_connected(struct intel_encoder *encoder) 5614 { 5615 bool ret; 5616 5617 intel_digital_port_lock(encoder); 5618 ret = intel_digital_port_connected_locked(encoder); 5619 intel_digital_port_unlock(encoder); 5620 5621 return ret; 5622 } 5623 5624 static const struct drm_edid * 5625 intel_dp_get_edid(struct intel_dp *intel_dp) 5626 { 5627 struct intel_connector *connector = intel_dp->attached_connector; 5628 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 5629 5630 /* Use panel fixed edid if we have one */ 5631 if (fixed_edid) { 5632 /* invalid edid */ 5633 if (IS_ERR(fixed_edid)) 5634 return NULL; 5635 5636 return drm_edid_dup(fixed_edid); 5637 } 5638 5639 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc); 5640 } 5641 5642 static void 5643 intel_dp_update_dfp(struct intel_dp *intel_dp, 5644 const struct drm_edid *drm_edid) 5645 { 5646 struct intel_display *display = to_intel_display(intel_dp); 5647 struct intel_connector *connector = intel_dp->attached_connector; 5648 5649 intel_dp->dfp.max_bpc = 5650 drm_dp_downstream_max_bpc(intel_dp->dpcd, 5651 intel_dp->downstream_ports, drm_edid); 5652 5653 intel_dp->dfp.max_dotclock = 5654 drm_dp_downstream_max_dotclock(intel_dp->dpcd, 5655 intel_dp->downstream_ports); 5656 5657 intel_dp->dfp.min_tmds_clock = 5658 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, 5659 intel_dp->downstream_ports, 5660 drm_edid); 5661 intel_dp->dfp.max_tmds_clock = 5662 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, 5663 intel_dp->downstream_ports, 5664 drm_edid); 5665 5666 intel_dp->dfp.pcon_max_frl_bw = 5667 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, 5668 intel_dp->downstream_ports); 5669 5670 drm_dbg_kms(display->drm, 5671 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", 5672 connector->base.base.id, connector->base.name, 5673 intel_dp->dfp.max_bpc, 5674 intel_dp->dfp.max_dotclock, 5675 intel_dp->dfp.min_tmds_clock, 5676 intel_dp->dfp.max_tmds_clock, 5677 intel_dp->dfp.pcon_max_frl_bw); 5678 5679 intel_dp_get_pcon_dsc_cap(intel_dp); 5680 } 5681 5682 static bool 5683 intel_dp_can_ycbcr420(struct intel_dp *intel_dp) 5684 { 5685 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) && 5686 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough)) 5687 return true; 5688 5689 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) && 5690 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5691 return true; 5692 5693 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) && 5694 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5695 return true; 5696 5697 return false; 5698 } 5699 5700 static void 5701 intel_dp_update_420(struct intel_dp *intel_dp) 5702 { 5703 struct intel_display *display = to_intel_display(intel_dp); 5704 struct intel_connector *connector = intel_dp->attached_connector; 5705 5706 intel_dp->dfp.ycbcr420_passthrough = 5707 drm_dp_downstream_420_passthrough(intel_dp->dpcd, 5708 intel_dp->downstream_ports); 5709 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ 5710 intel_dp->dfp.ycbcr_444_to_420 = 5711 intel_lspcon_active(dp_to_dig_port(intel_dp)) || 5712 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, 5713 intel_dp->downstream_ports); 5714 intel_dp->dfp.rgb_to_ycbcr = 5715 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, 5716 intel_dp->downstream_ports, 5717 DP_DS_HDMI_BT709_RGB_YCBCR_CONV); 5718 5719 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp); 5720 5721 drm_dbg_kms(display->drm, 5722 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", 5723 connector->base.base.id, connector->base.name, 5724 str_yes_no(intel_dp->dfp.rgb_to_ycbcr), 5725 str_yes_no(connector->base.ycbcr_420_allowed), 5726 str_yes_no(intel_dp->dfp.ycbcr_444_to_420)); 5727 } 5728 5729 static void 5730 intel_dp_set_edid(struct intel_dp *intel_dp) 5731 { 5732 struct intel_display *display = to_intel_display(intel_dp); 5733 struct intel_connector *connector = intel_dp->attached_connector; 5734 const struct drm_edid *drm_edid; 5735 bool vrr_capable; 5736 5737 intel_dp_unset_edid(intel_dp); 5738 drm_edid = intel_dp_get_edid(intel_dp); 5739 connector->detect_edid = drm_edid; 5740 5741 /* Below we depend on display info having been updated */ 5742 drm_edid_connector_update(&connector->base, drm_edid); 5743 5744 vrr_capable = intel_vrr_is_capable(connector); 5745 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n", 5746 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable)); 5747 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable); 5748 5749 intel_dp_update_dfp(intel_dp, drm_edid); 5750 intel_dp_update_420(intel_dp); 5751 5752 drm_dp_cec_attach(&intel_dp->aux, 5753 connector->base.display_info.source_physical_address); 5754 } 5755 5756 static void 5757 intel_dp_unset_edid(struct intel_dp *intel_dp) 5758 { 5759 struct intel_connector *connector = intel_dp->attached_connector; 5760 5761 drm_dp_cec_unset_edid(&intel_dp->aux); 5762 drm_edid_free(connector->detect_edid); 5763 connector->detect_edid = NULL; 5764 5765 intel_dp->dfp.max_bpc = 0; 5766 intel_dp->dfp.max_dotclock = 0; 5767 intel_dp->dfp.min_tmds_clock = 0; 5768 intel_dp->dfp.max_tmds_clock = 0; 5769 5770 intel_dp->dfp.pcon_max_frl_bw = 0; 5771 5772 intel_dp->dfp.ycbcr_444_to_420 = false; 5773 connector->base.ycbcr_420_allowed = false; 5774 5775 drm_connector_set_vrr_capable_property(&connector->base, 5776 false); 5777 } 5778 5779 static void 5780 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) 5781 { 5782 struct intel_display *display = to_intel_display(intel_dp); 5783 5784 intel_dp->as_sdp_supported = HAS_AS_SDP(display) && 5785 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); 5786 } 5787 5788 static int 5789 intel_dp_detect(struct drm_connector *_connector, 5790 struct drm_modeset_acquire_ctx *ctx, 5791 bool force) 5792 { 5793 struct intel_display *display = to_intel_display(_connector->dev); 5794 struct intel_connector *connector = to_intel_connector(_connector); 5795 struct intel_dp *intel_dp = intel_attached_dp(connector); 5796 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5797 struct intel_encoder *encoder = &dig_port->base; 5798 enum drm_connector_status status; 5799 int ret; 5800 5801 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 5802 connector->base.base.id, connector->base.name); 5803 drm_WARN_ON(display->drm, 5804 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 5805 5806 if (!intel_display_device_enabled(display)) 5807 return connector_status_disconnected; 5808 5809 if (!intel_display_driver_check_access(display)) 5810 return connector->base.status; 5811 5812 intel_dp_flush_connector_commits(connector); 5813 5814 intel_pps_vdd_on(intel_dp); 5815 5816 /* Can't disconnect eDP */ 5817 if (intel_dp_is_edp(intel_dp)) 5818 status = edp_detect(intel_dp); 5819 else if (intel_digital_port_connected(encoder)) 5820 status = intel_dp_detect_dpcd(intel_dp); 5821 else 5822 status = connector_status_disconnected; 5823 5824 if (status != connector_status_disconnected && 5825 !intel_dp_mst_verify_dpcd_state(intel_dp)) 5826 /* 5827 * This requires retrying detection for instance to re-enable 5828 * the MST mode that got reset via a long HPD pulse. The retry 5829 * will happen either via the hotplug handler's retry logic, 5830 * ensured by setting the connector here to SST/disconnected, 5831 * or via a userspace connector probing in response to the 5832 * hotplug uevent sent when removing the MST connectors. 5833 */ 5834 status = connector_status_disconnected; 5835 5836 if (status == connector_status_disconnected) { 5837 intel_dp_test_reset(intel_dp); 5838 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 5839 intel_dp->psr.sink_panel_replay_support = false; 5840 intel_dp->psr.sink_panel_replay_su_support = false; 5841 5842 intel_dp_mst_disconnect(intel_dp); 5843 5844 intel_dp_tunnel_disconnect(intel_dp); 5845 5846 goto out_unset_edid; 5847 } 5848 5849 intel_dp_init_source_oui(intel_dp); 5850 5851 ret = intel_dp_tunnel_detect(intel_dp, ctx); 5852 if (ret == -EDEADLK) { 5853 status = ret; 5854 5855 goto out_vdd_off; 5856 } 5857 5858 if (ret == 1) 5859 connector->base.epoch_counter++; 5860 5861 if (!intel_dp_is_edp(intel_dp)) 5862 intel_psr_init_dpcd(intel_dp); 5863 5864 intel_dp_detect_dsc_caps(intel_dp, connector); 5865 5866 intel_dp_detect_sdp_caps(intel_dp); 5867 5868 if (intel_dp->reset_link_params) { 5869 intel_dp_reset_link_params(intel_dp); 5870 intel_dp->reset_link_params = false; 5871 } 5872 5873 intel_dp_mst_configure(intel_dp); 5874 5875 intel_dp_print_rates(intel_dp); 5876 5877 if (intel_dp->is_mst) { 5878 /* 5879 * If we are in MST mode then this connector 5880 * won't appear connected or have anything 5881 * with EDID on it 5882 */ 5883 status = connector_status_disconnected; 5884 goto out_unset_edid; 5885 } 5886 5887 /* 5888 * Some external monitors do not signal loss of link synchronization 5889 * with an IRQ_HPD, so force a link status check. 5890 * 5891 * TODO: this probably became redundant, so remove it: the link state 5892 * is rechecked/recovered now after modesets, where the loss of 5893 * synchronization tends to occur. 5894 */ 5895 if (!intel_dp_is_edp(intel_dp)) 5896 intel_dp_check_link_state(intel_dp); 5897 5898 /* 5899 * Clearing NACK and defer counts to get their exact values 5900 * while reading EDID which are required by Compliance tests 5901 * 4.2.2.4 and 4.2.2.5 5902 */ 5903 intel_dp->aux.i2c_nack_count = 0; 5904 intel_dp->aux.i2c_defer_count = 0; 5905 5906 intel_dp_set_edid(intel_dp); 5907 if (intel_dp_is_edp(intel_dp) || connector->detect_edid) 5908 status = connector_status_connected; 5909 5910 intel_dp_check_device_service_irq(intel_dp); 5911 5912 out_unset_edid: 5913 if (status != connector_status_connected && !intel_dp->is_mst) 5914 intel_dp_unset_edid(intel_dp); 5915 5916 if (!intel_dp_is_edp(intel_dp)) 5917 drm_dp_set_subconnector_property(&connector->base, 5918 status, 5919 intel_dp->dpcd, 5920 intel_dp->downstream_ports); 5921 out_vdd_off: 5922 intel_pps_vdd_off(intel_dp); 5923 5924 return status; 5925 } 5926 5927 static void 5928 intel_dp_force(struct drm_connector *_connector) 5929 { 5930 struct intel_connector *connector = to_intel_connector(_connector); 5931 struct intel_display *display = to_intel_display(connector); 5932 struct intel_dp *intel_dp = intel_attached_dp(connector); 5933 5934 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 5935 connector->base.base.id, connector->base.name); 5936 5937 if (!intel_display_driver_check_access(display)) 5938 return; 5939 5940 intel_dp_unset_edid(intel_dp); 5941 5942 if (connector->base.status != connector_status_connected) 5943 return; 5944 5945 intel_dp_set_edid(intel_dp); 5946 } 5947 5948 static int intel_dp_get_modes(struct drm_connector *_connector) 5949 { 5950 struct intel_display *display = to_intel_display(_connector->dev); 5951 struct intel_connector *connector = to_intel_connector(_connector); 5952 struct intel_dp *intel_dp = intel_attached_dp(connector); 5953 int num_modes; 5954 5955 /* drm_edid_connector_update() done in ->detect() or ->force() */ 5956 num_modes = drm_edid_connector_add_modes(&connector->base); 5957 5958 /* Also add fixed mode, which may or may not be present in EDID */ 5959 if (intel_dp_is_edp(intel_dp)) 5960 num_modes += intel_panel_get_modes(connector); 5961 5962 if (num_modes) 5963 return num_modes; 5964 5965 if (!connector->detect_edid) { 5966 struct drm_display_mode *mode; 5967 5968 mode = drm_dp_downstream_mode(display->drm, 5969 intel_dp->dpcd, 5970 intel_dp->downstream_ports); 5971 if (mode) { 5972 drm_mode_probed_add(&connector->base, mode); 5973 num_modes++; 5974 } 5975 } 5976 5977 return num_modes; 5978 } 5979 5980 static int 5981 intel_dp_connector_register(struct drm_connector *_connector) 5982 { 5983 struct intel_connector *connector = to_intel_connector(_connector); 5984 struct intel_display *display = to_intel_display(connector); 5985 struct intel_dp *intel_dp = intel_attached_dp(connector); 5986 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5987 int ret; 5988 5989 ret = intel_connector_register(&connector->base); 5990 if (ret) 5991 return ret; 5992 5993 drm_dbg_kms(display->drm, "registering %s bus for %s\n", 5994 intel_dp->aux.name, connector->base.kdev->kobj.name); 5995 5996 intel_dp->aux.dev = connector->base.kdev; 5997 ret = drm_dp_aux_register(&intel_dp->aux); 5998 if (!ret) 5999 drm_dp_cec_register_connector(&intel_dp->aux, &connector->base); 6000 6001 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) 6002 return ret; 6003 6004 /* 6005 * ToDo: Clean this up to handle lspcon init and resume more 6006 * efficiently and streamlined. 6007 */ 6008 if (intel_lspcon_init(dig_port)) { 6009 if (intel_lspcon_detect_hdr_capability(dig_port)) 6010 drm_connector_attach_hdr_output_metadata_property(&connector->base); 6011 } 6012 6013 return ret; 6014 } 6015 6016 static void 6017 intel_dp_connector_unregister(struct drm_connector *_connector) 6018 { 6019 struct intel_connector *connector = to_intel_connector(_connector); 6020 struct intel_dp *intel_dp = intel_attached_dp(connector); 6021 6022 drm_dp_cec_unregister_connector(&intel_dp->aux); 6023 drm_dp_aux_unregister(&intel_dp->aux); 6024 intel_connector_unregister(&connector->base); 6025 } 6026 6027 void intel_dp_connector_sync_state(struct intel_connector *connector, 6028 const struct intel_crtc_state *crtc_state) 6029 { 6030 struct intel_display *display = to_intel_display(connector); 6031 6032 if (crtc_state && crtc_state->dsc.compression_enable) { 6033 drm_WARN_ON(display->drm, 6034 !connector->dp.dsc_decompression_aux); 6035 connector->dp.dsc_decompression_enabled = true; 6036 } else { 6037 connector->dp.dsc_decompression_enabled = false; 6038 } 6039 } 6040 6041 void intel_dp_encoder_flush_work(struct drm_encoder *_encoder) 6042 { 6043 struct intel_encoder *encoder = to_intel_encoder(_encoder); 6044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 6045 struct intel_dp *intel_dp = &dig_port->dp; 6046 6047 intel_encoder_link_check_flush_work(encoder); 6048 6049 intel_dp_mst_encoder_cleanup(dig_port); 6050 6051 intel_dp_tunnel_destroy(intel_dp); 6052 6053 intel_pps_vdd_off_sync(intel_dp); 6054 6055 /* 6056 * Ensure power off delay is respected on module remove, so that we can 6057 * reduce delays at driver probe. See pps_init_timestamps(). 6058 */ 6059 intel_pps_wait_power_cycle(intel_dp); 6060 6061 intel_dp_aux_fini(intel_dp); 6062 } 6063 6064 void intel_dp_encoder_suspend(struct intel_encoder *encoder) 6065 { 6066 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 6067 6068 intel_pps_vdd_off_sync(intel_dp); 6069 6070 intel_dp_tunnel_suspend(intel_dp); 6071 } 6072 6073 void intel_dp_encoder_shutdown(struct intel_encoder *encoder) 6074 { 6075 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 6076 6077 intel_pps_wait_power_cycle(intel_dp); 6078 } 6079 6080 static int intel_modeset_tile_group(struct intel_atomic_state *state, 6081 int tile_group_id) 6082 { 6083 struct intel_display *display = to_intel_display(state); 6084 struct drm_connector_list_iter conn_iter; 6085 struct intel_connector *connector; 6086 int ret = 0; 6087 6088 drm_connector_list_iter_begin(display->drm, &conn_iter); 6089 for_each_intel_connector_iter(connector, &conn_iter) { 6090 struct drm_connector_state *conn_state; 6091 struct intel_crtc_state *crtc_state; 6092 struct intel_crtc *crtc; 6093 6094 if (!connector->base.has_tile || 6095 connector->base.tile_group->id != tile_group_id) 6096 continue; 6097 6098 conn_state = drm_atomic_get_connector_state(&state->base, 6099 &connector->base); 6100 if (IS_ERR(conn_state)) { 6101 ret = PTR_ERR(conn_state); 6102 break; 6103 } 6104 6105 crtc = to_intel_crtc(conn_state->crtc); 6106 6107 if (!crtc) 6108 continue; 6109 6110 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6111 crtc_state->uapi.mode_changed = true; 6112 6113 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6114 if (ret) 6115 break; 6116 } 6117 drm_connector_list_iter_end(&conn_iter); 6118 6119 return ret; 6120 } 6121 6122 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) 6123 { 6124 struct intel_display *display = to_intel_display(state); 6125 struct intel_crtc *crtc; 6126 6127 if (transcoders == 0) 6128 return 0; 6129 6130 for_each_intel_crtc(display->drm, crtc) { 6131 struct intel_crtc_state *crtc_state; 6132 int ret; 6133 6134 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6135 if (IS_ERR(crtc_state)) 6136 return PTR_ERR(crtc_state); 6137 6138 if (!crtc_state->hw.enable) 6139 continue; 6140 6141 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) 6142 continue; 6143 6144 crtc_state->uapi.mode_changed = true; 6145 6146 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6147 if (ret) 6148 return ret; 6149 6150 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6151 if (ret) 6152 return ret; 6153 6154 transcoders &= ~BIT(crtc_state->cpu_transcoder); 6155 } 6156 6157 drm_WARN_ON(display->drm, transcoders != 0); 6158 6159 return 0; 6160 } 6161 6162 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, 6163 struct drm_connector *_connector) 6164 { 6165 struct intel_connector *connector = to_intel_connector(_connector); 6166 const struct drm_connector_state *old_conn_state = 6167 drm_atomic_get_old_connector_state(&state->base, &connector->base); 6168 const struct intel_crtc_state *old_crtc_state; 6169 struct intel_crtc *crtc; 6170 u8 transcoders; 6171 6172 crtc = to_intel_crtc(old_conn_state->crtc); 6173 if (!crtc) 6174 return 0; 6175 6176 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6177 6178 if (!old_crtc_state->hw.active) 6179 return 0; 6180 6181 transcoders = old_crtc_state->sync_mode_slaves_mask; 6182 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) 6183 transcoders |= BIT(old_crtc_state->master_transcoder); 6184 6185 return intel_modeset_affected_transcoders(state, 6186 transcoders); 6187 } 6188 6189 static int intel_dp_connector_atomic_check(struct drm_connector *_connector, 6190 struct drm_atomic_state *_state) 6191 { 6192 struct intel_connector *connector = to_intel_connector(_connector); 6193 struct intel_display *display = to_intel_display(connector); 6194 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6195 struct drm_connector_state *conn_state = 6196 drm_atomic_get_new_connector_state(_state, &connector->base); 6197 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 6198 int ret; 6199 6200 ret = intel_digital_connector_atomic_check(&connector->base, &state->base); 6201 if (ret) 6202 return ret; 6203 6204 if (intel_dp_mst_source_support(intel_dp)) { 6205 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst.mgr); 6206 if (ret) 6207 return ret; 6208 } 6209 6210 if (!intel_connector_needs_modeset(state, &connector->base)) 6211 return 0; 6212 6213 ret = intel_dp_tunnel_atomic_check_state(state, 6214 intel_dp, 6215 connector); 6216 if (ret) 6217 return ret; 6218 6219 /* 6220 * We don't enable port sync on BDW due to missing w/as and 6221 * due to not having adjusted the modeset sequence appropriately. 6222 */ 6223 if (DISPLAY_VER(display) < 9) 6224 return 0; 6225 6226 if (connector->base.has_tile) { 6227 ret = intel_modeset_tile_group(state, connector->base.tile_group->id); 6228 if (ret) 6229 return ret; 6230 } 6231 6232 return intel_modeset_synced_crtcs(state, &connector->base); 6233 } 6234 6235 static void intel_dp_oob_hotplug_event(struct drm_connector *_connector, 6236 enum drm_connector_status hpd_state) 6237 { 6238 struct intel_connector *connector = to_intel_connector(_connector); 6239 struct intel_display *display = to_intel_display(connector); 6240 struct intel_encoder *encoder = intel_attached_encoder(connector); 6241 bool hpd_high = hpd_state == connector_status_connected; 6242 unsigned int hpd_pin = encoder->hpd_pin; 6243 bool need_work = false; 6244 6245 spin_lock_irq(&display->irq.lock); 6246 if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) { 6247 display->hotplug.event_bits |= BIT(hpd_pin); 6248 6249 __assign_bit(hpd_pin, 6250 &display->hotplug.oob_hotplug_last_state, 6251 hpd_high); 6252 need_work = true; 6253 } 6254 spin_unlock_irq(&display->irq.lock); 6255 6256 if (need_work) 6257 intel_hpd_schedule_detection(display); 6258 } 6259 6260 static const struct drm_connector_funcs intel_dp_connector_funcs = { 6261 .force = intel_dp_force, 6262 .fill_modes = drm_helper_probe_single_connector_modes, 6263 .atomic_get_property = intel_digital_connector_atomic_get_property, 6264 .atomic_set_property = intel_digital_connector_atomic_set_property, 6265 .late_register = intel_dp_connector_register, 6266 .early_unregister = intel_dp_connector_unregister, 6267 .destroy = intel_connector_destroy, 6268 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6269 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 6270 .oob_hotplug_event = intel_dp_oob_hotplug_event, 6271 }; 6272 6273 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 6274 .detect_ctx = intel_dp_detect, 6275 .get_modes = intel_dp_get_modes, 6276 .mode_valid = intel_dp_mode_valid, 6277 .atomic_check = intel_dp_connector_atomic_check, 6278 }; 6279 6280 enum irqreturn 6281 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) 6282 { 6283 struct intel_display *display = to_intel_display(dig_port); 6284 struct intel_dp *intel_dp = &dig_port->dp; 6285 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 6286 6287 if (dig_port->base.type == INTEL_OUTPUT_EDP && 6288 (long_hpd || 6289 intel_display_rpm_suspended(display) || 6290 !intel_pps_have_panel_power_or_vdd(intel_dp))) { 6291 /* 6292 * vdd off can generate a long/short pulse on eDP which 6293 * would require vdd on to handle it, and thus we 6294 * would end up in an endless cycle of 6295 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." 6296 */ 6297 drm_dbg_kms(display->drm, 6298 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", 6299 long_hpd ? "long" : "short", 6300 dig_port->base.base.base.id, 6301 dig_port->base.base.name); 6302 return IRQ_HANDLED; 6303 } 6304 6305 drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", 6306 dig_port->base.base.base.id, 6307 dig_port->base.base.name, 6308 long_hpd ? "long" : "short"); 6309 6310 /* 6311 * TBT DP tunnels require the GFX driver to read out the DPRX caps in 6312 * response to long HPD pulses. The DP hotplug handler does that, 6313 * however the hotplug handler may be blocked by another 6314 * connector's/encoder's hotplug handler. Since the TBT CM may not 6315 * complete the DP tunnel BW request for the latter connector/encoder 6316 * waiting for this encoder's DPRX read, perform a dummy read here. 6317 */ 6318 if (long_hpd) 6319 intel_dp_read_dprx_caps(intel_dp, dpcd); 6320 6321 if (long_hpd) { 6322 intel_dp->reset_link_params = true; 6323 intel_dp_invalidate_source_oui(intel_dp); 6324 6325 return IRQ_NONE; 6326 } 6327 6328 if (intel_dp->is_mst) { 6329 if (!intel_dp_check_mst_status(intel_dp)) 6330 return IRQ_NONE; 6331 } else if (!intel_dp_short_pulse(intel_dp)) { 6332 return IRQ_NONE; 6333 } 6334 6335 return IRQ_HANDLED; 6336 } 6337 6338 static bool _intel_dp_is_port_edp(struct intel_display *display, 6339 const struct intel_bios_encoder_data *devdata, 6340 enum port port) 6341 { 6342 /* 6343 * eDP not supported on g4x. so bail out early just 6344 * for a bit extra safety in case the VBT is bonkers. 6345 */ 6346 if (DISPLAY_VER(display) < 5) 6347 return false; 6348 6349 if (DISPLAY_VER(display) < 9 && port == PORT_A) 6350 return true; 6351 6352 return devdata && intel_bios_encoder_supports_edp(devdata); 6353 } 6354 6355 bool intel_dp_is_port_edp(struct intel_display *display, enum port port) 6356 { 6357 const struct intel_bios_encoder_data *devdata = 6358 intel_bios_encoder_data_lookup(display, port); 6359 6360 return _intel_dp_is_port_edp(display, devdata, port); 6361 } 6362 6363 bool 6364 intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder) 6365 { 6366 struct intel_display *display = to_intel_display(encoder); 6367 enum port port = encoder->port; 6368 6369 if (intel_bios_encoder_is_lspcon(encoder->devdata)) 6370 return false; 6371 6372 if (DISPLAY_VER(display) >= 11) 6373 return true; 6374 6375 if (port == PORT_A) 6376 return false; 6377 6378 if (display->platform.haswell || display->platform.broadwell || 6379 DISPLAY_VER(display) >= 9) 6380 return true; 6381 6382 return false; 6383 } 6384 6385 static void 6386 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *_connector) 6387 { 6388 struct intel_connector *connector = to_intel_connector(_connector); 6389 struct intel_display *display = to_intel_display(intel_dp); 6390 enum port port = dp_to_dig_port(intel_dp)->base.port; 6391 6392 if (!intel_dp_is_edp(intel_dp)) 6393 drm_connector_attach_dp_subconnector_property(&connector->base); 6394 6395 if (!display->platform.g4x && port != PORT_A) 6396 intel_attach_force_audio_property(&connector->base); 6397 6398 intel_attach_broadcast_rgb_property(&connector->base); 6399 if (HAS_GMCH(display)) 6400 drm_connector_attach_max_bpc_property(&connector->base, 6, 10); 6401 else if (DISPLAY_VER(display) >= 5) 6402 drm_connector_attach_max_bpc_property(&connector->base, 6, 12); 6403 6404 /* Register HDMI colorspace for case of lspcon */ 6405 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) { 6406 drm_connector_attach_content_type_property(&connector->base); 6407 intel_attach_hdmi_colorspace_property(&connector->base); 6408 } else { 6409 intel_attach_dp_colorspace_property(&connector->base); 6410 } 6411 6412 if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) 6413 drm_connector_attach_hdr_output_metadata_property(&connector->base); 6414 6415 if (HAS_VRR(display)) 6416 drm_connector_attach_vrr_capable_property(&connector->base); 6417 } 6418 6419 static void 6420 intel_edp_add_properties(struct intel_dp *intel_dp) 6421 { 6422 struct intel_display *display = to_intel_display(intel_dp); 6423 struct intel_connector *connector = intel_dp->attached_connector; 6424 const struct drm_display_mode *fixed_mode = 6425 intel_panel_preferred_fixed_mode(connector); 6426 6427 intel_attach_scaling_mode_property(&connector->base); 6428 6429 drm_connector_set_panel_orientation_with_quirk(&connector->base, 6430 display->vbt.orientation, 6431 fixed_mode->hdisplay, 6432 fixed_mode->vdisplay); 6433 } 6434 6435 static void intel_edp_backlight_setup(struct intel_dp *intel_dp, 6436 struct intel_connector *connector) 6437 { 6438 struct intel_display *display = to_intel_display(intel_dp); 6439 enum pipe pipe = INVALID_PIPE; 6440 6441 if (display->platform.valleyview || display->platform.cherryview) 6442 pipe = vlv_pps_backlight_initial_pipe(intel_dp); 6443 6444 intel_backlight_setup(connector, pipe); 6445 } 6446 6447 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 6448 struct intel_connector *connector) 6449 { 6450 struct intel_display *display = to_intel_display(intel_dp); 6451 struct drm_display_mode *fixed_mode; 6452 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 6453 bool has_dpcd; 6454 const struct drm_edid *drm_edid; 6455 6456 if (!intel_dp_is_edp(intel_dp)) 6457 return true; 6458 6459 /* 6460 * On IBX/CPT we may get here with LVDS already registered. Since the 6461 * driver uses the only internal power sequencer available for both 6462 * eDP and LVDS bail out early in this case to prevent interfering 6463 * with an already powered-on LVDS power sequencer. 6464 */ 6465 if (intel_get_lvds_encoder(display)) { 6466 drm_WARN_ON(display->drm, 6467 !(HAS_PCH_IBX(display) || HAS_PCH_CPT(display))); 6468 drm_info(display->drm, 6469 "LVDS was detected, not registering eDP\n"); 6470 6471 return false; 6472 } 6473 6474 intel_bios_init_panel_early(display, &connector->panel, 6475 encoder->devdata); 6476 6477 if (!intel_pps_init(intel_dp)) { 6478 drm_info(display->drm, 6479 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n", 6480 encoder->base.base.id, encoder->base.name); 6481 /* 6482 * The BIOS may have still enabled VDD on the PPS even 6483 * though it's unusable. Make sure we turn it back off 6484 * and to release the power domain references/etc. 6485 */ 6486 goto out_vdd_off; 6487 } 6488 6489 /* 6490 * Enable HPD sense for live status check. 6491 * intel_hpd_irq_setup() will turn it off again 6492 * if it's no longer needed later. 6493 * 6494 * The DPCD probe below will make sure VDD is on. 6495 */ 6496 intel_hpd_enable_detection(encoder); 6497 6498 intel_alpm_init(intel_dp); 6499 6500 /* Cache DPCD and EDID for edp. */ 6501 has_dpcd = intel_edp_init_dpcd(intel_dp, connector); 6502 6503 if (!has_dpcd) { 6504 /* if this fails, presume the device is a ghost */ 6505 drm_info(display->drm, 6506 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n", 6507 encoder->base.base.id, encoder->base.name); 6508 goto out_vdd_off; 6509 } 6510 6511 /* 6512 * VBT and straps are liars. Also check HPD as that seems 6513 * to be the most reliable piece of information available. 6514 * 6515 * ... expect on devices that forgot to hook HPD up for eDP 6516 * (eg. Acer Chromebook C710), so we'll check it only if multiple 6517 * ports are attempting to use the same AUX CH, according to VBT. 6518 */ 6519 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) { 6520 /* 6521 * If this fails, presume the DPCD answer came 6522 * from some other port using the same AUX CH. 6523 * 6524 * FIXME maybe cleaner to check this before the 6525 * DPCD read? Would need sort out the VDD handling... 6526 */ 6527 if (!intel_digital_port_connected(encoder)) { 6528 drm_info(display->drm, 6529 "[ENCODER:%d:%s] HPD is down, disabling eDP\n", 6530 encoder->base.base.id, encoder->base.name); 6531 goto out_vdd_off; 6532 } 6533 6534 /* 6535 * Unfortunately even the HPD based detection fails on 6536 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall 6537 * back to checking for a VGA branch device. Only do this 6538 * on known affected platforms to minimize false positives. 6539 */ 6540 if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) && 6541 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) == 6542 DP_DWN_STRM_PORT_TYPE_ANALOG) { 6543 drm_info(display->drm, 6544 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n", 6545 encoder->base.base.id, encoder->base.name); 6546 goto out_vdd_off; 6547 } 6548 } 6549 6550 mutex_lock(&display->drm->mode_config.mutex); 6551 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc); 6552 if (!drm_edid) { 6553 /* Fallback to EDID from ACPI OpRegion, if any */ 6554 drm_edid = intel_opregion_get_edid(connector); 6555 if (drm_edid) 6556 drm_dbg_kms(display->drm, 6557 "[CONNECTOR:%d:%s] Using OpRegion EDID\n", 6558 connector->base.base.id, connector->base.name); 6559 } 6560 if (drm_edid) { 6561 if (drm_edid_connector_update(&connector->base, drm_edid) || 6562 !drm_edid_connector_add_modes(&connector->base)) { 6563 drm_edid_connector_update(&connector->base, NULL); 6564 drm_edid_free(drm_edid); 6565 drm_edid = ERR_PTR(-EINVAL); 6566 } 6567 } else { 6568 drm_edid = ERR_PTR(-ENOENT); 6569 } 6570 6571 intel_bios_init_panel_late(display, &connector->panel, encoder->devdata, 6572 IS_ERR(drm_edid) ? NULL : drm_edid); 6573 6574 intel_panel_add_edid_fixed_modes(connector, true); 6575 6576 /* MSO requires information from the EDID */ 6577 intel_edp_mso_init(intel_dp); 6578 6579 /* multiply the mode clock and horizontal timings for MSO */ 6580 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) 6581 intel_edp_mso_mode_fixup(connector, fixed_mode); 6582 6583 /* fallback to VBT if available for eDP */ 6584 if (!intel_panel_preferred_fixed_mode(connector)) 6585 intel_panel_add_vbt_lfp_fixed_mode(connector); 6586 6587 mutex_unlock(&display->drm->mode_config.mutex); 6588 6589 if (!intel_panel_preferred_fixed_mode(connector)) { 6590 drm_info(display->drm, 6591 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n", 6592 encoder->base.base.id, encoder->base.name); 6593 goto out_vdd_off; 6594 } 6595 6596 intel_panel_init(connector, drm_edid); 6597 6598 intel_edp_backlight_setup(intel_dp, connector); 6599 6600 intel_edp_add_properties(intel_dp); 6601 6602 intel_pps_init_late(intel_dp); 6603 6604 return true; 6605 6606 out_vdd_off: 6607 intel_pps_vdd_off_sync(intel_dp); 6608 intel_bios_fini_panel(&connector->panel); 6609 6610 return false; 6611 } 6612 6613 bool 6614 intel_dp_init_connector(struct intel_digital_port *dig_port, 6615 struct intel_connector *connector) 6616 { 6617 struct intel_display *display = to_intel_display(dig_port); 6618 struct intel_dp *intel_dp = &dig_port->dp; 6619 struct intel_encoder *encoder = &dig_port->base; 6620 struct drm_device *dev = encoder->base.dev; 6621 enum port port = encoder->port; 6622 int type; 6623 6624 if (drm_WARN(dev, dig_port->max_lanes < 1, 6625 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", 6626 dig_port->max_lanes, encoder->base.base.id, 6627 encoder->base.name)) 6628 return false; 6629 6630 intel_dp->reset_link_params = true; 6631 6632 /* Preserve the current hw state. */ 6633 intel_dp->DP = intel_de_read(display, intel_dp->output_reg); 6634 intel_dp->attached_connector = connector; 6635 6636 if (_intel_dp_is_port_edp(display, encoder->devdata, port)) { 6637 /* 6638 * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30, 6639 * although in theory it could work on TypeC legacy ports. 6640 */ 6641 drm_WARN_ON(dev, intel_encoder_is_tc(encoder) && 6642 DISPLAY_VER(display) < 30); 6643 type = DRM_MODE_CONNECTOR_eDP; 6644 encoder->type = INTEL_OUTPUT_EDP; 6645 6646 /* eDP only on port B and/or C on vlv/chv */ 6647 if (drm_WARN_ON(dev, (display->platform.valleyview || 6648 display->platform.cherryview) && 6649 port != PORT_B && port != PORT_C)) 6650 return false; 6651 } else { 6652 type = DRM_MODE_CONNECTOR_DisplayPort; 6653 } 6654 6655 intel_dp_set_default_sink_rates(intel_dp); 6656 intel_dp_set_default_max_sink_lane_count(intel_dp); 6657 6658 if (display->platform.valleyview || display->platform.cherryview) 6659 vlv_pps_pipe_init(intel_dp); 6660 6661 intel_dp_aux_init(intel_dp); 6662 connector->dp.dsc_decompression_aux = &intel_dp->aux; 6663 6664 drm_dbg_kms(display->drm, 6665 "Adding %s connector on [ENCODER:%d:%s]\n", 6666 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 6667 encoder->base.base.id, encoder->base.name); 6668 6669 drm_connector_init_with_ddc(dev, &connector->base, &intel_dp_connector_funcs, 6670 type, &intel_dp->aux.ddc); 6671 drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs); 6672 6673 if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12) 6674 connector->base.interlace_allowed = true; 6675 6676 if (type != DRM_MODE_CONNECTOR_eDP) 6677 connector->polled = DRM_CONNECTOR_POLL_HPD; 6678 connector->base.polled = connector->polled; 6679 6680 intel_connector_attach_encoder(connector, encoder); 6681 6682 if (HAS_DDI(display)) 6683 connector->get_hw_state = intel_ddi_connector_get_hw_state; 6684 else 6685 connector->get_hw_state = intel_connector_get_hw_state; 6686 connector->sync_state = intel_dp_connector_sync_state; 6687 6688 if (!intel_edp_init_connector(intel_dp, connector)) { 6689 intel_dp_aux_fini(intel_dp); 6690 goto fail; 6691 } 6692 6693 intel_dp_set_source_rates(intel_dp); 6694 intel_dp_set_common_rates(intel_dp); 6695 intel_dp_reset_link_params(intel_dp); 6696 6697 /* init MST on ports that can support it */ 6698 intel_dp_mst_encoder_init(dig_port, connector->base.base.id); 6699 6700 intel_dp_add_properties(intel_dp, &connector->base); 6701 6702 if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) { 6703 int ret = intel_dp_hdcp_init(dig_port, connector); 6704 if (ret) 6705 drm_dbg_kms(display->drm, 6706 "HDCP init failed, skipping.\n"); 6707 } 6708 6709 intel_dp->frl.is_trained = false; 6710 intel_dp->frl.trained_rate_gbps = 0; 6711 6712 intel_psr_init(intel_dp); 6713 6714 return true; 6715 6716 fail: 6717 intel_display_power_flush_work(display); 6718 drm_connector_cleanup(&connector->base); 6719 6720 return false; 6721 } 6722 6723 void intel_dp_mst_suspend(struct intel_display *display) 6724 { 6725 struct intel_encoder *encoder; 6726 6727 if (!HAS_DISPLAY(display)) 6728 return; 6729 6730 for_each_intel_encoder(display->drm, encoder) { 6731 struct intel_dp *intel_dp; 6732 6733 if (encoder->type != INTEL_OUTPUT_DDI) 6734 continue; 6735 6736 intel_dp = enc_to_intel_dp(encoder); 6737 6738 if (!intel_dp_mst_source_support(intel_dp)) 6739 continue; 6740 6741 if (intel_dp->is_mst) 6742 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst.mgr); 6743 } 6744 } 6745 6746 void intel_dp_mst_resume(struct intel_display *display) 6747 { 6748 struct intel_encoder *encoder; 6749 6750 if (!HAS_DISPLAY(display)) 6751 return; 6752 6753 for_each_intel_encoder(display->drm, encoder) { 6754 struct intel_dp *intel_dp; 6755 int ret; 6756 6757 if (encoder->type != INTEL_OUTPUT_DDI) 6758 continue; 6759 6760 intel_dp = enc_to_intel_dp(encoder); 6761 6762 if (!intel_dp_mst_source_support(intel_dp)) 6763 continue; 6764 6765 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst.mgr, true); 6766 if (ret) { 6767 intel_dp->is_mst = false; 6768 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, false); 6769 } 6770 } 6771 } 6772