1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DMC_REGS_H__ 7 #define __INTEL_DMC_REGS_H__ 8 9 #include "i915_reg_defs.h" 10 11 #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4) 12 #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0 13 14 #define _PIPEDMC_CONTROL_A 0x45250 15 #define _PIPEDMC_CONTROL_B 0x45254 16 #define PIPEDMC_CONTROL(pipe) _MMIO_PIPE(pipe, \ 17 _PIPEDMC_CONTROL_A, \ 18 _PIPEDMC_CONTROL_B) 19 #define PIPEDMC_ENABLE REG_BIT(0) 20 21 #define MTL_PIPEDMC_CONTROL _MMIO(0x45250) 22 #define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4) 23 24 #define _MTL_PIPEDMC_EVT_CTL_4_A 0x5f044 25 #define _MTL_PIPEDMC_EVT_CTL_4_B 0x5f444 26 #define MTL_PIPEDMC_EVT_CTL_4(pipe) _MMIO_PIPE(pipe, \ 27 _MTL_PIPEDMC_EVT_CTL_4_A, \ 28 _MTL_PIPEDMC_EVT_CTL_4_B) 29 30 #define PIPEDMC_BLOCK_PKGC_SW_A 0x5f1d0 31 #define PIPEDMC_BLOCK_PKGC_SW_B 0x5F5d0 32 #define PIPEDMC_BLOCK_PKGC_SW(pipe) _MMIO_PIPE(pipe, \ 33 PIPEDMC_BLOCK_PKGC_SW_A, \ 34 PIPEDMC_BLOCK_PKGC_SW_B) 35 #define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS BIT(31) 36 #define PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_UNTIL_NEXT_FRAMESTART BIT(15) 37 38 #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000 39 #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000 40 41 #define __PIPEDMC_REG_MMIO_BASE(i915, dmc_id) \ 42 ((DISPLAY_VER(i915) >= 13 ? _ADLP_PIPEDMC_REG_MMIO_BASE_A : \ 43 _TGL_PIPEDMC_REG_MMIO_BASE_A) + \ 44 0x400 * ((dmc_id) - 1)) 45 46 #define __DMC_REG_MMIO_BASE 0x8f000 47 48 #define _DMC_REG_MMIO_BASE(i915, dmc_id) \ 49 ((dmc_id) == DMC_FW_MAIN ? __DMC_REG_MMIO_BASE : \ 50 __PIPEDMC_REG_MMIO_BASE(i915, dmc_id)) 51 52 #define _DMC_REG(i915, dmc_id, reg) \ 53 ((reg) - __DMC_REG_MMIO_BASE + _DMC_REG_MMIO_BASE(i915, dmc_id)) 54 55 #define DMC_EVENT_HANDLER_COUNT_GEN12 8 56 57 #define _DMC_EVT_HTP_0 0x8f004 58 59 #define DMC_EVT_HTP(i915, dmc_id, handler) \ 60 _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_HTP_0) + 4 * (handler)) 61 62 #define _DMC_EVT_CTL_0 0x8f034 63 64 #define DMC_EVT_CTL(i915, dmc_id, handler) \ 65 _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_CTL_0) + 4 * (handler)) 66 67 #define DMC_EVT_CTL_ENABLE REG_BIT(31) 68 #define DMC_EVT_CTL_RECURRING REG_BIT(30) 69 #define DMC_EVT_CTL_TYPE_MASK REG_GENMASK(17, 16) 70 #define DMC_EVT_CTL_TYPE_LEVEL_0 0 71 #define DMC_EVT_CTL_TYPE_LEVEL_1 1 72 #define DMC_EVT_CTL_TYPE_EDGE_1_0 2 73 #define DMC_EVT_CTL_TYPE_EDGE_0_1 3 74 75 #define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8) 76 #define DMC_EVT_CTL_EVENT_ID_FALSE 0x01 77 #define DMC_EVT_CTL_EVENT_ID_VBLANK_A 0x32 /* main DMC */ 78 /* An event handler scheduled to run at a 1 kHz frequency. */ 79 #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC 0xbf 80 81 #define DMC_HTP_ADDR_SKL 0x00500034 82 #define DMC_SSP_BASE _MMIO(0x8F074) 83 #define DMC_HTP_SKL _MMIO(0x8F004) 84 #define DMC_LAST_WRITE _MMIO(0x8F034) 85 #define DMC_LAST_WRITE_VALUE 0xc003b400 86 #define DMC_MMIO_START_RANGE 0x80000 87 #define DMC_MMIO_END_RANGE 0x8FFFF 88 #define DMC_V1_MMIO_START_RANGE 0x80000 89 #define TGL_MAIN_MMIO_START 0x8F000 90 #define TGL_MAIN_MMIO_END 0x8FFFF 91 #define _TGL_PIPEA_MMIO_START 0x92000 92 #define _TGL_PIPEA_MMIO_END 0x93FFF 93 #define _TGL_PIPEB_MMIO_START 0x96000 94 #define _TGL_PIPEB_MMIO_END 0x97FFF 95 #define ADLP_PIPE_MMIO_START 0x5F000 96 #define ADLP_PIPE_MMIO_END 0x5FFFF 97 98 #define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\ 99 _TGL_PIPEB_MMIO_START) 100 101 #define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\ 102 _TGL_PIPEB_MMIO_END) 103 104 #define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030) 105 #define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C) 106 #define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038) 107 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) 108 #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) 109 #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154) 110 111 #define TGL_DMC_DEBUG3 _MMIO(0x101090) 112 #define DG1_DMC_DEBUG3 _MMIO(0x13415c) 113 114 #define DMC_WAKELOCK_CFG _MMIO(0x8F1B0) 115 #define DMC_WAKELOCK_CFG_ENABLE REG_BIT(31) 116 #define DMC_WAKELOCK1_CTL _MMIO(0x8F140) 117 #define DMC_WAKELOCK_CTL_REQ REG_BIT(31) 118 #define DMC_WAKELOCK_CTL_ACK REG_BIT(15) 119 120 #endif /* __INTEL_DMC_REGS_H__ */ 121