1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_de.h" 30 #include "intel_dmc.h" 31 #include "intel_dmc_regs.h" 32 33 /** 34 * DOC: DMC Firmware Support 35 * 36 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 37 * engine to save and restore the state of display engine when it enter into 38 * low-power state and comes back to normal. 39 */ 40 41 enum intel_dmc_id { 42 DMC_FW_MAIN = 0, 43 DMC_FW_PIPEA, 44 DMC_FW_PIPEB, 45 DMC_FW_PIPEC, 46 DMC_FW_PIPED, 47 DMC_FW_MAX 48 }; 49 50 struct intel_dmc { 51 struct drm_i915_private *i915; 52 struct work_struct work; 53 const char *fw_path; 54 u32 max_fw_size; /* bytes */ 55 u32 version; 56 struct dmc_fw_info { 57 u32 mmio_count; 58 i915_reg_t mmioaddr[20]; 59 u32 mmiodata[20]; 60 u32 dmc_offset; 61 u32 start_mmioaddr; 62 u32 dmc_fw_size; /*dwords */ 63 u32 *payload; 64 bool present; 65 } dmc_info[DMC_FW_MAX]; 66 }; 67 68 /* Note: This may be NULL. */ 69 static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915) 70 { 71 return i915->display.dmc.dmc; 72 } 73 74 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 75 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 76 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 77 78 #define DMC_PATH(platform) \ 79 "i915/" __stringify(platform) "_dmc.bin" 80 81 /* 82 * New DMC additions should not use this. This is used solely to remain 83 * compatible with systems that have not yet updated DMC blobs to use 84 * unversioned file names. 85 */ 86 #define DMC_LEGACY_PATH(platform, major, minor) \ 87 "i915/" \ 88 __stringify(platform) "_dmc_ver" \ 89 __stringify(major) "_" \ 90 __stringify(minor) ".bin" 91 92 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 93 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 94 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 95 96 #define MTL_DMC_PATH DMC_PATH(mtl) 97 MODULE_FIRMWARE(MTL_DMC_PATH); 98 99 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 100 MODULE_FIRMWARE(DG2_DMC_PATH); 101 102 #define ADLP_DMC_PATH DMC_PATH(adlp) 103 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 104 MODULE_FIRMWARE(ADLP_DMC_PATH); 105 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 106 107 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 108 MODULE_FIRMWARE(ADLS_DMC_PATH); 109 110 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 111 MODULE_FIRMWARE(DG1_DMC_PATH); 112 113 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 114 MODULE_FIRMWARE(RKL_DMC_PATH); 115 116 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 117 MODULE_FIRMWARE(TGL_DMC_PATH); 118 119 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 120 #define ICL_DMC_MAX_FW_SIZE 0x6000 121 MODULE_FIRMWARE(ICL_DMC_PATH); 122 123 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 124 #define GLK_DMC_MAX_FW_SIZE 0x4000 125 MODULE_FIRMWARE(GLK_DMC_PATH); 126 127 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 128 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 129 MODULE_FIRMWARE(KBL_DMC_PATH); 130 131 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 132 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 133 MODULE_FIRMWARE(SKL_DMC_PATH); 134 135 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 136 #define BXT_DMC_MAX_FW_SIZE 0x3000 137 MODULE_FIRMWARE(BXT_DMC_PATH); 138 139 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 140 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 141 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 142 #define DMC_V1_MAX_MMIO_COUNT 8 143 #define DMC_V3_MAX_MMIO_COUNT 20 144 #define DMC_V1_MMIO_START_RANGE 0x80000 145 146 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 147 148 struct intel_css_header { 149 /* 0x09 for DMC */ 150 u32 module_type; 151 152 /* Includes the DMC specific header in dwords */ 153 u32 header_len; 154 155 /* always value would be 0x10000 */ 156 u32 header_ver; 157 158 /* Not used */ 159 u32 module_id; 160 161 /* Not used */ 162 u32 module_vendor; 163 164 /* in YYYYMMDD format */ 165 u32 date; 166 167 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 168 u32 size; 169 170 /* Not used */ 171 u32 key_size; 172 173 /* Not used */ 174 u32 modulus_size; 175 176 /* Not used */ 177 u32 exponent_size; 178 179 /* Not used */ 180 u32 reserved1[12]; 181 182 /* Major Minor */ 183 u32 version; 184 185 /* Not used */ 186 u32 reserved2[8]; 187 188 /* Not used */ 189 u32 kernel_header_info; 190 } __packed; 191 192 struct intel_fw_info { 193 u8 reserved1; 194 195 /* reserved on package_header version 1, must be 0 on version 2 */ 196 u8 dmc_id; 197 198 /* Stepping (A, B, C, ..., *). * is a wildcard */ 199 char stepping; 200 201 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 202 char substepping; 203 204 u32 offset; 205 u32 reserved2; 206 } __packed; 207 208 struct intel_package_header { 209 /* DMC container header length in dwords */ 210 u8 header_len; 211 212 /* 0x01, 0x02 */ 213 u8 header_ver; 214 215 u8 reserved[10]; 216 217 /* Number of valid entries in the FWInfo array below */ 218 u32 num_entries; 219 } __packed; 220 221 struct intel_dmc_header_base { 222 /* always value would be 0x40403E3E */ 223 u32 signature; 224 225 /* DMC binary header length */ 226 u8 header_len; 227 228 /* 0x01 */ 229 u8 header_ver; 230 231 /* Reserved */ 232 u16 dmcc_ver; 233 234 /* Major, Minor */ 235 u32 project; 236 237 /* Firmware program size (excluding header) in dwords */ 238 u32 fw_size; 239 240 /* Major Minor version */ 241 u32 fw_version; 242 } __packed; 243 244 struct intel_dmc_header_v1 { 245 struct intel_dmc_header_base base; 246 247 /* Number of valid MMIO cycles present. */ 248 u32 mmio_count; 249 250 /* MMIO address */ 251 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 252 253 /* MMIO data */ 254 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 255 256 /* FW filename */ 257 char dfile[32]; 258 259 u32 reserved1[2]; 260 } __packed; 261 262 struct intel_dmc_header_v3 { 263 struct intel_dmc_header_base base; 264 265 /* DMC RAM start MMIO address */ 266 u32 start_mmioaddr; 267 268 u32 reserved[9]; 269 270 /* FW filename */ 271 char dfile[32]; 272 273 /* Number of valid MMIO cycles present. */ 274 u32 mmio_count; 275 276 /* MMIO address */ 277 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 278 279 /* MMIO data */ 280 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 281 } __packed; 282 283 struct stepping_info { 284 char stepping; 285 char substepping; 286 }; 287 288 #define for_each_dmc_id(__dmc_id) \ 289 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 290 291 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 292 { 293 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 294 } 295 296 static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id dmc_id) 297 { 298 struct intel_dmc *dmc = i915_to_dmc(i915); 299 300 return dmc && dmc->dmc_info[dmc_id].payload; 301 } 302 303 bool intel_dmc_has_payload(struct drm_i915_private *i915) 304 { 305 return has_dmc_id_fw(i915, DMC_FW_MAIN); 306 } 307 308 static const struct stepping_info * 309 intel_get_stepping_info(struct drm_i915_private *i915, 310 struct stepping_info *si) 311 { 312 const char *step_name = intel_display_step_name(i915); 313 314 si->stepping = step_name[0]; 315 si->substepping = step_name[1]; 316 return si; 317 } 318 319 static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915) 320 { 321 /* The below bit doesn't need to be cleared ever afterwards */ 322 intel_de_rmw(i915, DC_STATE_DEBUG, 0, 323 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 324 intel_de_posting_read(i915, DC_STATE_DEBUG); 325 } 326 327 static void disable_event_handler(struct drm_i915_private *i915, 328 i915_reg_t ctl_reg, i915_reg_t htp_reg) 329 { 330 intel_de_write(i915, ctl_reg, 331 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 332 DMC_EVT_CTL_TYPE_EDGE_0_1) | 333 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 334 DMC_EVT_CTL_EVENT_ID_FALSE)); 335 intel_de_write(i915, htp_reg, 0); 336 } 337 338 static void 339 disable_flip_queue_event(struct drm_i915_private *i915, 340 i915_reg_t ctl_reg, i915_reg_t htp_reg) 341 { 342 u32 event_ctl; 343 u32 event_htp; 344 345 event_ctl = intel_de_read(i915, ctl_reg); 346 event_htp = intel_de_read(i915, htp_reg); 347 if (event_ctl != (DMC_EVT_CTL_ENABLE | 348 DMC_EVT_CTL_RECURRING | 349 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 350 DMC_EVT_CTL_TYPE_EDGE_0_1) | 351 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 352 DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) || 353 !event_htp) { 354 drm_dbg_kms(&i915->drm, 355 "Unexpected DMC event configuration (control %08x htp %08x)\n", 356 event_ctl, event_htp); 357 return; 358 } 359 360 disable_event_handler(i915, ctl_reg, htp_reg); 361 } 362 363 static bool 364 get_flip_queue_event_regs(struct drm_i915_private *i915, enum intel_dmc_id dmc_id, 365 i915_reg_t *ctl_reg, i915_reg_t *htp_reg) 366 { 367 if (dmc_id == DMC_FW_MAIN) { 368 if (DISPLAY_VER(i915) == 12) { 369 *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3); 370 *htp_reg = DMC_EVT_HTP(i915, dmc_id, 3); 371 372 return true; 373 } 374 } else if (dmc_id >= DMC_FW_PIPEA && dmc_id <= DMC_FW_PIPED) { 375 if (IS_DG2(i915)) { 376 *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2); 377 *htp_reg = DMC_EVT_HTP(i915, dmc_id, 2); 378 379 return true; 380 } 381 } 382 383 return false; 384 } 385 386 static void 387 disable_all_flip_queue_events(struct drm_i915_private *i915) 388 { 389 enum intel_dmc_id dmc_id; 390 391 /* TODO: check if the following applies to all D13+ platforms. */ 392 if (!IS_DG2(i915) && !IS_TIGERLAKE(i915)) 393 return; 394 395 for_each_dmc_id(dmc_id) { 396 i915_reg_t ctl_reg; 397 i915_reg_t htp_reg; 398 399 if (!has_dmc_id_fw(i915, dmc_id)) 400 continue; 401 402 if (!get_flip_queue_event_regs(i915, dmc_id, &ctl_reg, &htp_reg)) 403 continue; 404 405 disable_flip_queue_event(i915, ctl_reg, htp_reg); 406 } 407 } 408 409 static void disable_all_event_handlers(struct drm_i915_private *i915) 410 { 411 enum intel_dmc_id dmc_id; 412 413 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 414 if (DISPLAY_VER(i915) < 12) 415 return; 416 417 for_each_dmc_id(dmc_id) { 418 int handler; 419 420 if (!has_dmc_id_fw(i915, dmc_id)) 421 continue; 422 423 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 424 disable_event_handler(i915, 425 DMC_EVT_CTL(i915, dmc_id, handler), 426 DMC_EVT_HTP(i915, dmc_id, handler)); 427 } 428 } 429 430 static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 431 { 432 enum pipe pipe; 433 434 /* 435 * Wa_16015201720:adl-p,dg2 436 * The WA requires clock gating to be disabled all the time 437 * for pipe A and B. 438 * For pipe C and D clock gating needs to be disabled only 439 * during initializing the firmware. 440 */ 441 if (enable) 442 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 443 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 444 0, PIPEDMC_GATING_DIS); 445 else 446 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 447 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 448 PIPEDMC_GATING_DIS, 0); 449 } 450 451 static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915) 452 { 453 /* 454 * Wa_16015201720 455 * The WA requires clock gating to be disabled all the time 456 * for pipe A and B. 457 */ 458 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, 459 MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); 460 } 461 462 static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 463 { 464 if (DISPLAY_VER(i915) >= 14 && enable) 465 mtl_pipedmc_clock_gating_wa(i915); 466 else if (DISPLAY_VER(i915) == 13) 467 adlp_pipedmc_clock_gating_wa(i915, enable); 468 } 469 470 void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe) 471 { 472 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 473 474 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) 475 return; 476 477 if (DISPLAY_VER(i915) >= 14) 478 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 479 else 480 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 481 } 482 483 void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe) 484 { 485 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 486 487 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) 488 return; 489 490 if (DISPLAY_VER(i915) >= 14) 491 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 492 else 493 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 494 } 495 496 /** 497 * intel_dmc_load_program() - write the firmware from memory to register. 498 * @i915: i915 drm device. 499 * 500 * DMC firmware is read from a .bin file and kept in internal memory one time. 501 * Everytime display comes back from low power state this function is called to 502 * copy the firmware from internal memory to registers. 503 */ 504 void intel_dmc_load_program(struct drm_i915_private *i915) 505 { 506 struct i915_power_domains *power_domains = &i915->display.power.domains; 507 struct intel_dmc *dmc = i915_to_dmc(i915); 508 enum intel_dmc_id dmc_id; 509 u32 i; 510 511 if (!intel_dmc_has_payload(i915)) 512 return; 513 514 pipedmc_clock_gating_wa(i915, true); 515 516 disable_all_event_handlers(i915); 517 518 assert_rpm_wakelock_held(&i915->runtime_pm); 519 520 preempt_disable(); 521 522 for_each_dmc_id(dmc_id) { 523 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 524 intel_de_write_fw(i915, 525 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 526 dmc->dmc_info[dmc_id].payload[i]); 527 } 528 } 529 530 preempt_enable(); 531 532 for_each_dmc_id(dmc_id) { 533 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 534 intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i], 535 dmc->dmc_info[dmc_id].mmiodata[i]); 536 } 537 } 538 539 power_domains->dc_state = 0; 540 541 gen9_set_dc_state_debugmask(i915); 542 543 /* 544 * Flip queue events need to be disabled before enabling DC5/6. 545 * i915 doesn't use the flip queue feature, so disable it already 546 * here. 547 */ 548 disable_all_flip_queue_events(i915); 549 550 pipedmc_clock_gating_wa(i915, false); 551 } 552 553 /** 554 * intel_dmc_disable_program() - disable the firmware 555 * @i915: i915 drm device 556 * 557 * Disable all event handlers in the firmware, making sure the firmware is 558 * inactive after the display is uninitialized. 559 */ 560 void intel_dmc_disable_program(struct drm_i915_private *i915) 561 { 562 if (!intel_dmc_has_payload(i915)) 563 return; 564 565 pipedmc_clock_gating_wa(i915, true); 566 disable_all_event_handlers(i915); 567 pipedmc_clock_gating_wa(i915, false); 568 } 569 570 void assert_dmc_loaded(struct drm_i915_private *i915) 571 { 572 struct intel_dmc *dmc = i915_to_dmc(i915); 573 574 drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n"); 575 drm_WARN_ONCE(&i915->drm, dmc && 576 !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 577 "DMC program storage start is NULL\n"); 578 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), 579 "DMC SSP Base Not fine\n"); 580 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), 581 "DMC HTP Not fine\n"); 582 } 583 584 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 585 const struct stepping_info *si) 586 { 587 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 588 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 589 /* 590 * If we don't find a more specific one from above two checks, we 591 * then check for the generic one to be sure to work even with 592 * "broken firmware" 593 */ 594 (si->stepping == '*' && si->substepping == fw_info->substepping) || 595 (fw_info->stepping == '*' && fw_info->substepping == '*')) 596 return true; 597 598 return false; 599 } 600 601 /* 602 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 603 * already sanitized. 604 */ 605 static void dmc_set_fw_offset(struct intel_dmc *dmc, 606 const struct intel_fw_info *fw_info, 607 unsigned int num_entries, 608 const struct stepping_info *si, 609 u8 package_ver) 610 { 611 struct drm_i915_private *i915 = dmc->i915; 612 enum intel_dmc_id dmc_id; 613 unsigned int i; 614 615 for (i = 0; i < num_entries; i++) { 616 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 617 618 if (!is_valid_dmc_id(dmc_id)) { 619 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", dmc_id); 620 continue; 621 } 622 623 /* More specific versions come first, so we don't even have to 624 * check for the stepping since we already found a previous FW 625 * for this id. 626 */ 627 if (dmc->dmc_info[dmc_id].present) 628 continue; 629 630 if (fw_info_matches_stepping(&fw_info[i], si)) { 631 dmc->dmc_info[dmc_id].present = true; 632 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 633 } 634 } 635 } 636 637 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 638 const u32 *mmioaddr, u32 mmio_count, 639 int header_ver, enum intel_dmc_id dmc_id) 640 { 641 struct drm_i915_private *i915 = dmc->i915; 642 u32 start_range, end_range; 643 int i; 644 645 if (header_ver == 1) { 646 start_range = DMC_MMIO_START_RANGE; 647 end_range = DMC_MMIO_END_RANGE; 648 } else if (dmc_id == DMC_FW_MAIN) { 649 start_range = TGL_MAIN_MMIO_START; 650 end_range = TGL_MAIN_MMIO_END; 651 } else if (DISPLAY_VER(i915) >= 13) { 652 start_range = ADLP_PIPE_MMIO_START; 653 end_range = ADLP_PIPE_MMIO_END; 654 } else if (DISPLAY_VER(i915) >= 12) { 655 start_range = TGL_PIPE_MMIO_START(dmc_id); 656 end_range = TGL_PIPE_MMIO_END(dmc_id); 657 } else { 658 drm_warn(&i915->drm, "Unknown mmio range for sanity check"); 659 return false; 660 } 661 662 for (i = 0; i < mmio_count; i++) { 663 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 664 return false; 665 } 666 667 return true; 668 } 669 670 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 671 const struct intel_dmc_header_base *dmc_header, 672 size_t rem_size, enum intel_dmc_id dmc_id) 673 { 674 struct drm_i915_private *i915 = dmc->i915; 675 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 676 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 677 const u32 *mmioaddr, *mmiodata; 678 u32 mmio_count, mmio_count_max, start_mmioaddr; 679 u8 *payload; 680 681 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 682 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 683 684 /* 685 * Check if we can access common fields, we will checkc again below 686 * after we have read the version 687 */ 688 if (rem_size < sizeof(struct intel_dmc_header_base)) 689 goto error_truncated; 690 691 /* Cope with small differences between v1 and v3 */ 692 if (dmc_header->header_ver == 3) { 693 const struct intel_dmc_header_v3 *v3 = 694 (const struct intel_dmc_header_v3 *)dmc_header; 695 696 if (rem_size < sizeof(struct intel_dmc_header_v3)) 697 goto error_truncated; 698 699 mmioaddr = v3->mmioaddr; 700 mmiodata = v3->mmiodata; 701 mmio_count = v3->mmio_count; 702 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 703 /* header_len is in dwords */ 704 header_len_bytes = dmc_header->header_len * 4; 705 start_mmioaddr = v3->start_mmioaddr; 706 dmc_header_size = sizeof(*v3); 707 } else if (dmc_header->header_ver == 1) { 708 const struct intel_dmc_header_v1 *v1 = 709 (const struct intel_dmc_header_v1 *)dmc_header; 710 711 if (rem_size < sizeof(struct intel_dmc_header_v1)) 712 goto error_truncated; 713 714 mmioaddr = v1->mmioaddr; 715 mmiodata = v1->mmiodata; 716 mmio_count = v1->mmio_count; 717 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 718 header_len_bytes = dmc_header->header_len; 719 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 720 dmc_header_size = sizeof(*v1); 721 } else { 722 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 723 dmc_header->header_ver); 724 return 0; 725 } 726 727 if (header_len_bytes != dmc_header_size) { 728 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 729 "(%u bytes)\n", header_len_bytes); 730 return 0; 731 } 732 733 /* Cache the dmc header info. */ 734 if (mmio_count > mmio_count_max) { 735 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 736 return 0; 737 } 738 739 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 740 dmc_header->header_ver, dmc_id)) { 741 drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); 742 return 0; 743 } 744 745 for (i = 0; i < mmio_count; i++) { 746 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 747 dmc_info->mmiodata[i] = mmiodata[i]; 748 } 749 dmc_info->mmio_count = mmio_count; 750 dmc_info->start_mmioaddr = start_mmioaddr; 751 752 rem_size -= header_len_bytes; 753 754 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 755 payload_size = dmc_header->fw_size * 4; 756 if (rem_size < payload_size) 757 goto error_truncated; 758 759 if (payload_size > dmc->max_fw_size) { 760 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 761 return 0; 762 } 763 dmc_info->dmc_fw_size = dmc_header->fw_size; 764 765 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 766 if (!dmc_info->payload) 767 return 0; 768 769 payload = (u8 *)(dmc_header) + header_len_bytes; 770 memcpy(dmc_info->payload, payload, payload_size); 771 772 return header_len_bytes + payload_size; 773 774 error_truncated: 775 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 776 return 0; 777 } 778 779 static u32 780 parse_dmc_fw_package(struct intel_dmc *dmc, 781 const struct intel_package_header *package_header, 782 const struct stepping_info *si, 783 size_t rem_size) 784 { 785 struct drm_i915_private *i915 = dmc->i915; 786 u32 package_size = sizeof(struct intel_package_header); 787 u32 num_entries, max_entries; 788 const struct intel_fw_info *fw_info; 789 790 if (rem_size < package_size) 791 goto error_truncated; 792 793 if (package_header->header_ver == 1) { 794 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 795 } else if (package_header->header_ver == 2) { 796 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 797 } else { 798 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 799 package_header->header_ver); 800 return 0; 801 } 802 803 /* 804 * We should always have space for max_entries, 805 * even if not all are used 806 */ 807 package_size += max_entries * sizeof(struct intel_fw_info); 808 if (rem_size < package_size) 809 goto error_truncated; 810 811 if (package_header->header_len * 4 != package_size) { 812 drm_err(&i915->drm, "DMC firmware has wrong package header length " 813 "(%u bytes)\n", package_size); 814 return 0; 815 } 816 817 num_entries = package_header->num_entries; 818 if (WARN_ON(package_header->num_entries > max_entries)) 819 num_entries = max_entries; 820 821 fw_info = (const struct intel_fw_info *) 822 ((u8 *)package_header + sizeof(*package_header)); 823 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 824 package_header->header_ver); 825 826 /* dmc_offset is in dwords */ 827 return package_size; 828 829 error_truncated: 830 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 831 return 0; 832 } 833 834 /* Return number of bytes parsed or 0 on error */ 835 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 836 struct intel_css_header *css_header, 837 size_t rem_size) 838 { 839 struct drm_i915_private *i915 = dmc->i915; 840 841 if (rem_size < sizeof(struct intel_css_header)) { 842 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 843 return 0; 844 } 845 846 if (sizeof(struct intel_css_header) != 847 (css_header->header_len * 4)) { 848 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 849 "(%u bytes)\n", 850 (css_header->header_len * 4)); 851 return 0; 852 } 853 854 dmc->version = css_header->version; 855 856 return sizeof(struct intel_css_header); 857 } 858 859 static void parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 860 { 861 struct drm_i915_private *i915 = dmc->i915; 862 struct intel_css_header *css_header; 863 struct intel_package_header *package_header; 864 struct intel_dmc_header_base *dmc_header; 865 struct stepping_info display_info = { '*', '*'}; 866 const struct stepping_info *si = intel_get_stepping_info(i915, &display_info); 867 enum intel_dmc_id dmc_id; 868 u32 readcount = 0; 869 u32 r, offset; 870 871 if (!fw) 872 return; 873 874 /* Extract CSS Header information */ 875 css_header = (struct intel_css_header *)fw->data; 876 r = parse_dmc_fw_css(dmc, css_header, fw->size); 877 if (!r) 878 return; 879 880 readcount += r; 881 882 /* Extract Package Header information */ 883 package_header = (struct intel_package_header *)&fw->data[readcount]; 884 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 885 if (!r) 886 return; 887 888 readcount += r; 889 890 for_each_dmc_id(dmc_id) { 891 if (!dmc->dmc_info[dmc_id].present) 892 continue; 893 894 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 895 if (offset > fw->size) { 896 drm_err(&i915->drm, "Reading beyond the fw_size\n"); 897 continue; 898 } 899 900 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 901 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 902 } 903 } 904 905 static void intel_dmc_runtime_pm_get(struct drm_i915_private *i915) 906 { 907 drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); 908 i915->display.dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 909 } 910 911 static void intel_dmc_runtime_pm_put(struct drm_i915_private *i915) 912 { 913 intel_wakeref_t wakeref __maybe_unused = 914 fetch_and_zero(&i915->display.dmc.wakeref); 915 916 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 917 } 918 919 static const char *dmc_fallback_path(struct drm_i915_private *i915) 920 { 921 if (IS_ALDERLAKE_P(i915)) 922 return ADLP_DMC_FALLBACK_PATH; 923 924 return NULL; 925 } 926 927 static void dmc_load_work_fn(struct work_struct *work) 928 { 929 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 930 struct drm_i915_private *i915 = dmc->i915; 931 const struct firmware *fw = NULL; 932 const char *fallback_path; 933 int err; 934 935 err = request_firmware(&fw, dmc->fw_path, i915->drm.dev); 936 937 if (err == -ENOENT && !i915->params.dmc_firmware_path) { 938 fallback_path = dmc_fallback_path(i915); 939 if (fallback_path) { 940 drm_dbg_kms(&i915->drm, "%s not found, falling back to %s\n", 941 dmc->fw_path, fallback_path); 942 err = request_firmware(&fw, fallback_path, i915->drm.dev); 943 if (err == 0) 944 dmc->fw_path = fallback_path; 945 } 946 } 947 948 parse_dmc_fw(dmc, fw); 949 950 if (intel_dmc_has_payload(i915)) { 951 intel_dmc_load_program(i915); 952 intel_dmc_runtime_pm_put(i915); 953 954 drm_info(&i915->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 955 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 956 DMC_VERSION_MINOR(dmc->version)); 957 } else { 958 drm_notice(&i915->drm, 959 "Failed to load DMC firmware %s." 960 " Disabling runtime power management.\n", 961 dmc->fw_path); 962 drm_notice(&i915->drm, "DMC firmware homepage: %s", 963 INTEL_UC_FIRMWARE_URL); 964 } 965 966 release_firmware(fw); 967 } 968 969 /** 970 * intel_dmc_init() - initialize the firmware loading. 971 * @i915: i915 drm device. 972 * 973 * This function is called at the time of loading the display driver to read 974 * firmware from a .bin file and copied into a internal memory. 975 */ 976 void intel_dmc_init(struct drm_i915_private *i915) 977 { 978 struct intel_dmc *dmc; 979 980 if (!HAS_DMC(i915)) 981 return; 982 983 /* 984 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 985 * runtime-suspend. 986 * 987 * On error, we return with the rpm wakeref held to prevent runtime 988 * suspend as runtime suspend *requires* a working DMC for whatever 989 * reason. 990 */ 991 intel_dmc_runtime_pm_get(i915); 992 993 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); 994 if (!dmc) 995 return; 996 997 dmc->i915 = i915; 998 999 INIT_WORK(&dmc->work, dmc_load_work_fn); 1000 1001 if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) { 1002 dmc->fw_path = MTL_DMC_PATH; 1003 dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 1004 } else if (IS_DG2(i915)) { 1005 dmc->fw_path = DG2_DMC_PATH; 1006 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 1007 } else if (IS_ALDERLAKE_P(i915)) { 1008 dmc->fw_path = ADLP_DMC_PATH; 1009 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 1010 } else if (IS_ALDERLAKE_S(i915)) { 1011 dmc->fw_path = ADLS_DMC_PATH; 1012 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 1013 } else if (IS_DG1(i915)) { 1014 dmc->fw_path = DG1_DMC_PATH; 1015 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 1016 } else if (IS_ROCKETLAKE(i915)) { 1017 dmc->fw_path = RKL_DMC_PATH; 1018 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 1019 } else if (IS_TIGERLAKE(i915)) { 1020 dmc->fw_path = TGL_DMC_PATH; 1021 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 1022 } else if (DISPLAY_VER(i915) == 11) { 1023 dmc->fw_path = ICL_DMC_PATH; 1024 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE; 1025 } else if (IS_GEMINILAKE(i915)) { 1026 dmc->fw_path = GLK_DMC_PATH; 1027 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE; 1028 } else if (IS_KABYLAKE(i915) || 1029 IS_COFFEELAKE(i915) || 1030 IS_COMETLAKE(i915)) { 1031 dmc->fw_path = KBL_DMC_PATH; 1032 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE; 1033 } else if (IS_SKYLAKE(i915)) { 1034 dmc->fw_path = SKL_DMC_PATH; 1035 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE; 1036 } else if (IS_BROXTON(i915)) { 1037 dmc->fw_path = BXT_DMC_PATH; 1038 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE; 1039 } 1040 1041 if (i915->params.dmc_firmware_path) { 1042 if (strlen(i915->params.dmc_firmware_path) == 0) { 1043 drm_info(&i915->drm, 1044 "Disabling DMC firmware and runtime PM\n"); 1045 goto out; 1046 } 1047 1048 dmc->fw_path = i915->params.dmc_firmware_path; 1049 } 1050 1051 if (!dmc->fw_path) { 1052 drm_dbg_kms(&i915->drm, 1053 "No known DMC firmware for platform, disabling runtime PM\n"); 1054 goto out; 1055 } 1056 1057 i915->display.dmc.dmc = dmc; 1058 1059 drm_dbg_kms(&i915->drm, "Loading %s\n", dmc->fw_path); 1060 queue_work(i915->unordered_wq, &dmc->work); 1061 1062 return; 1063 1064 out: 1065 kfree(dmc); 1066 } 1067 1068 /** 1069 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1070 * @i915: i915 drm device 1071 * 1072 * Prepare the DMC firmware before entering system suspend. This includes 1073 * flushing pending work items and releasing any resources acquired during 1074 * init. 1075 */ 1076 void intel_dmc_suspend(struct drm_i915_private *i915) 1077 { 1078 struct intel_dmc *dmc = i915_to_dmc(i915); 1079 1080 if (!HAS_DMC(i915)) 1081 return; 1082 1083 if (dmc) 1084 flush_work(&dmc->work); 1085 1086 /* Drop the reference held in case DMC isn't loaded. */ 1087 if (!intel_dmc_has_payload(i915)) 1088 intel_dmc_runtime_pm_put(i915); 1089 } 1090 1091 /** 1092 * intel_dmc_resume() - init DMC firmware during system resume 1093 * @i915: i915 drm device 1094 * 1095 * Reinitialize the DMC firmware during system resume, reacquiring any 1096 * resources released in intel_dmc_suspend(). 1097 */ 1098 void intel_dmc_resume(struct drm_i915_private *i915) 1099 { 1100 if (!HAS_DMC(i915)) 1101 return; 1102 1103 /* 1104 * Reacquire the reference to keep RPM disabled in case DMC isn't 1105 * loaded. 1106 */ 1107 if (!intel_dmc_has_payload(i915)) 1108 intel_dmc_runtime_pm_get(i915); 1109 } 1110 1111 /** 1112 * intel_dmc_fini() - unload the DMC firmware. 1113 * @i915: i915 drm device. 1114 * 1115 * Firmmware unloading includes freeing the internal memory and reset the 1116 * firmware loading status. 1117 */ 1118 void intel_dmc_fini(struct drm_i915_private *i915) 1119 { 1120 struct intel_dmc *dmc = i915_to_dmc(i915); 1121 enum intel_dmc_id dmc_id; 1122 1123 if (!HAS_DMC(i915)) 1124 return; 1125 1126 intel_dmc_suspend(i915); 1127 drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); 1128 1129 if (dmc) { 1130 for_each_dmc_id(dmc_id) 1131 kfree(dmc->dmc_info[dmc_id].payload); 1132 1133 kfree(dmc); 1134 i915->display.dmc.dmc = NULL; 1135 } 1136 } 1137 1138 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, 1139 struct drm_i915_private *i915) 1140 { 1141 struct intel_dmc *dmc = i915_to_dmc(i915); 1142 1143 if (!HAS_DMC(i915)) 1144 return; 1145 1146 i915_error_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1147 i915_error_printf(m, "DMC loaded: %s\n", 1148 str_yes_no(intel_dmc_has_payload(i915))); 1149 if (dmc) 1150 i915_error_printf(m, "DMC fw version: %d.%d\n", 1151 DMC_VERSION_MAJOR(dmc->version), 1152 DMC_VERSION_MINOR(dmc->version)); 1153 } 1154 1155 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1156 { 1157 struct drm_i915_private *i915 = m->private; 1158 struct intel_dmc *dmc = i915_to_dmc(i915); 1159 intel_wakeref_t wakeref; 1160 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1161 1162 if (!HAS_DMC(i915)) 1163 return -ENODEV; 1164 1165 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1166 1167 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1168 seq_printf(m, "fw loaded: %s\n", 1169 str_yes_no(intel_dmc_has_payload(i915))); 1170 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1171 seq_printf(m, "Pipe A fw needed: %s\n", 1172 str_yes_no(GRAPHICS_VER(i915) >= 12)); 1173 seq_printf(m, "Pipe A fw loaded: %s\n", 1174 str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEA))); 1175 seq_printf(m, "Pipe B fw needed: %s\n", 1176 str_yes_no(IS_ALDERLAKE_P(i915) || 1177 DISPLAY_VER(i915) >= 14)); 1178 seq_printf(m, "Pipe B fw loaded: %s\n", 1179 str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEB))); 1180 1181 if (!intel_dmc_has_payload(i915)) 1182 goto out; 1183 1184 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1185 DMC_VERSION_MINOR(dmc->version)); 1186 1187 if (DISPLAY_VER(i915) >= 12) { 1188 i915_reg_t dc3co_reg; 1189 1190 if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) { 1191 dc3co_reg = DG1_DMC_DEBUG3; 1192 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1193 } else { 1194 dc3co_reg = TGL_DMC_DEBUG3; 1195 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1196 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1197 } 1198 1199 seq_printf(m, "DC3CO count: %d\n", 1200 intel_de_read(i915, dc3co_reg)); 1201 } else { 1202 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : 1203 SKL_DMC_DC3_DC5_COUNT; 1204 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) 1205 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1206 } 1207 1208 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); 1209 if (i915_mmio_reg_valid(dc6_reg)) 1210 seq_printf(m, "DC5 -> DC6 count: %d\n", 1211 intel_de_read(i915, dc6_reg)); 1212 1213 seq_printf(m, "program base: 0x%08x\n", 1214 intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1215 1216 out: 1217 seq_printf(m, "ssp base: 0x%08x\n", 1218 intel_de_read(i915, DMC_SSP_BASE)); 1219 seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL)); 1220 1221 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1222 1223 return 0; 1224 } 1225 1226 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1227 1228 void intel_dmc_debugfs_register(struct drm_i915_private *i915) 1229 { 1230 struct drm_minor *minor = i915->drm.primary; 1231 1232 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 1233 i915, &intel_dmc_debugfs_status_fops); 1234 } 1235