1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 28 #include "i915_drv.h" 29 #include "i915_reg.h" 30 #include "intel_de.h" 31 #include "intel_display_rpm.h" 32 #include "intel_display_power_well.h" 33 #include "intel_dmc.h" 34 #include "intel_dmc_regs.h" 35 #include "intel_step.h" 36 37 /** 38 * DOC: DMC Firmware Support 39 * 40 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 41 * engine to save and restore the state of display engine when it enter into 42 * low-power state and comes back to normal. 43 */ 44 45 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 46 47 enum intel_dmc_id { 48 DMC_FW_MAIN = 0, 49 DMC_FW_PIPEA, 50 DMC_FW_PIPEB, 51 DMC_FW_PIPEC, 52 DMC_FW_PIPED, 53 DMC_FW_MAX 54 }; 55 56 struct intel_dmc { 57 struct intel_display *display; 58 struct work_struct work; 59 const char *fw_path; 60 u32 max_fw_size; /* bytes */ 61 u32 version; 62 struct { 63 u32 dc5_start; 64 u32 count; 65 } dc6_allowed; 66 struct dmc_fw_info { 67 u32 mmio_count; 68 i915_reg_t mmioaddr[20]; 69 u32 mmiodata[20]; 70 u32 dmc_offset; 71 u32 start_mmioaddr; 72 u32 dmc_fw_size; /*dwords */ 73 u32 *payload; 74 bool present; 75 } dmc_info[DMC_FW_MAX]; 76 }; 77 78 /* Note: This may be NULL. */ 79 static struct intel_dmc *display_to_dmc(struct intel_display *display) 80 { 81 return display->dmc.dmc; 82 } 83 84 static const char *dmc_firmware_param(struct intel_display *display) 85 { 86 const char *p = display->params.dmc_firmware_path; 87 88 return p && *p ? p : NULL; 89 } 90 91 static bool dmc_firmware_param_disabled(struct intel_display *display) 92 { 93 const char *p = dmc_firmware_param(display); 94 95 /* Magic path to indicate disabled */ 96 return p && !strcmp(p, "/dev/null"); 97 } 98 99 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 100 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 101 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 102 103 #define DMC_PATH(platform) \ 104 "i915/" __stringify(platform) "_dmc.bin" 105 106 /* 107 * New DMC additions should not use this. This is used solely to remain 108 * compatible with systems that have not yet updated DMC blobs to use 109 * unversioned file names. 110 */ 111 #define DMC_LEGACY_PATH(platform, major, minor) \ 112 "i915/" \ 113 __stringify(platform) "_dmc_ver" \ 114 __stringify(major) "_" \ 115 __stringify(minor) ".bin" 116 117 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 118 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 119 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 120 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 121 122 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd) 123 MODULE_FIRMWARE(XE3LPD_DMC_PATH); 124 125 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 126 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 127 128 #define BMG_DMC_PATH DMC_PATH(bmg) 129 MODULE_FIRMWARE(BMG_DMC_PATH); 130 131 #define MTL_DMC_PATH DMC_PATH(mtl) 132 MODULE_FIRMWARE(MTL_DMC_PATH); 133 134 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 135 MODULE_FIRMWARE(DG2_DMC_PATH); 136 137 #define ADLP_DMC_PATH DMC_PATH(adlp) 138 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 139 MODULE_FIRMWARE(ADLP_DMC_PATH); 140 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 141 142 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 143 MODULE_FIRMWARE(ADLS_DMC_PATH); 144 145 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 146 MODULE_FIRMWARE(DG1_DMC_PATH); 147 148 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 149 MODULE_FIRMWARE(RKL_DMC_PATH); 150 151 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 152 MODULE_FIRMWARE(TGL_DMC_PATH); 153 154 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 155 #define ICL_DMC_MAX_FW_SIZE 0x6000 156 MODULE_FIRMWARE(ICL_DMC_PATH); 157 158 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 159 #define GLK_DMC_MAX_FW_SIZE 0x4000 160 MODULE_FIRMWARE(GLK_DMC_PATH); 161 162 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 163 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 164 MODULE_FIRMWARE(KBL_DMC_PATH); 165 166 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 167 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 168 MODULE_FIRMWARE(SKL_DMC_PATH); 169 170 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 171 #define BXT_DMC_MAX_FW_SIZE 0x3000 172 MODULE_FIRMWARE(BXT_DMC_PATH); 173 174 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) 175 { 176 const char *fw_path = NULL; 177 u32 max_fw_size = 0; 178 179 if (DISPLAY_VERx100(display) == 3000) { 180 fw_path = XE3LPD_DMC_PATH; 181 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 182 } else if (DISPLAY_VERx100(display) == 2000) { 183 fw_path = XE2LPD_DMC_PATH; 184 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 185 } else if (DISPLAY_VERx100(display) == 1401) { 186 fw_path = BMG_DMC_PATH; 187 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 188 } else if (DISPLAY_VERx100(display) == 1400) { 189 fw_path = MTL_DMC_PATH; 190 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 191 } else if (display->platform.dg2) { 192 fw_path = DG2_DMC_PATH; 193 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 194 } else if (display->platform.alderlake_p) { 195 fw_path = ADLP_DMC_PATH; 196 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 197 } else if (display->platform.alderlake_s) { 198 fw_path = ADLS_DMC_PATH; 199 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 200 } else if (display->platform.dg1) { 201 fw_path = DG1_DMC_PATH; 202 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 203 } else if (display->platform.rocketlake) { 204 fw_path = RKL_DMC_PATH; 205 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 206 } else if (display->platform.tigerlake) { 207 fw_path = TGL_DMC_PATH; 208 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 209 } else if (DISPLAY_VER(display) == 11) { 210 fw_path = ICL_DMC_PATH; 211 max_fw_size = ICL_DMC_MAX_FW_SIZE; 212 } else if (display->platform.geminilake) { 213 fw_path = GLK_DMC_PATH; 214 max_fw_size = GLK_DMC_MAX_FW_SIZE; 215 } else if (display->platform.kabylake || 216 display->platform.coffeelake || 217 display->platform.cometlake) { 218 fw_path = KBL_DMC_PATH; 219 max_fw_size = KBL_DMC_MAX_FW_SIZE; 220 } else if (display->platform.skylake) { 221 fw_path = SKL_DMC_PATH; 222 max_fw_size = SKL_DMC_MAX_FW_SIZE; 223 } else if (display->platform.broxton) { 224 fw_path = BXT_DMC_PATH; 225 max_fw_size = BXT_DMC_MAX_FW_SIZE; 226 } 227 228 *size = max_fw_size; 229 230 return fw_path; 231 } 232 233 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 234 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 235 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 236 #define DMC_V1_MAX_MMIO_COUNT 8 237 #define DMC_V3_MAX_MMIO_COUNT 20 238 #define DMC_V1_MMIO_START_RANGE 0x80000 239 240 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 241 242 struct intel_css_header { 243 /* 0x09 for DMC */ 244 u32 module_type; 245 246 /* Includes the DMC specific header in dwords */ 247 u32 header_len; 248 249 /* always value would be 0x10000 */ 250 u32 header_ver; 251 252 /* Not used */ 253 u32 module_id; 254 255 /* Not used */ 256 u32 module_vendor; 257 258 /* in YYYYMMDD format */ 259 u32 date; 260 261 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 262 u32 size; 263 264 /* Not used */ 265 u32 key_size; 266 267 /* Not used */ 268 u32 modulus_size; 269 270 /* Not used */ 271 u32 exponent_size; 272 273 /* Not used */ 274 u32 reserved1[12]; 275 276 /* Major Minor */ 277 u32 version; 278 279 /* Not used */ 280 u32 reserved2[8]; 281 282 /* Not used */ 283 u32 kernel_header_info; 284 } __packed; 285 286 struct intel_fw_info { 287 u8 reserved1; 288 289 /* reserved on package_header version 1, must be 0 on version 2 */ 290 u8 dmc_id; 291 292 /* Stepping (A, B, C, ..., *). * is a wildcard */ 293 char stepping; 294 295 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 296 char substepping; 297 298 u32 offset; 299 u32 reserved2; 300 } __packed; 301 302 struct intel_package_header { 303 /* DMC container header length in dwords */ 304 u8 header_len; 305 306 /* 0x01, 0x02 */ 307 u8 header_ver; 308 309 u8 reserved[10]; 310 311 /* Number of valid entries in the FWInfo array below */ 312 u32 num_entries; 313 } __packed; 314 315 struct intel_dmc_header_base { 316 /* always value would be 0x40403E3E */ 317 u32 signature; 318 319 /* DMC binary header length */ 320 u8 header_len; 321 322 /* 0x01 */ 323 u8 header_ver; 324 325 /* Reserved */ 326 u16 dmcc_ver; 327 328 /* Major, Minor */ 329 u32 project; 330 331 /* Firmware program size (excluding header) in dwords */ 332 u32 fw_size; 333 334 /* Major Minor version */ 335 u32 fw_version; 336 } __packed; 337 338 struct intel_dmc_header_v1 { 339 struct intel_dmc_header_base base; 340 341 /* Number of valid MMIO cycles present. */ 342 u32 mmio_count; 343 344 /* MMIO address */ 345 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 346 347 /* MMIO data */ 348 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 349 350 /* FW filename */ 351 char dfile[32]; 352 353 u32 reserved1[2]; 354 } __packed; 355 356 struct intel_dmc_header_v3 { 357 struct intel_dmc_header_base base; 358 359 /* DMC RAM start MMIO address */ 360 u32 start_mmioaddr; 361 362 u32 reserved[9]; 363 364 /* FW filename */ 365 char dfile[32]; 366 367 /* Number of valid MMIO cycles present. */ 368 u32 mmio_count; 369 370 /* MMIO address */ 371 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 372 373 /* MMIO data */ 374 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 375 } __packed; 376 377 struct stepping_info { 378 char stepping; 379 char substepping; 380 }; 381 382 #define for_each_dmc_id(__dmc_id) \ 383 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 384 385 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 386 { 387 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 388 } 389 390 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) 391 { 392 struct intel_dmc *dmc = display_to_dmc(display); 393 394 return dmc && dmc->dmc_info[dmc_id].payload; 395 } 396 397 bool intel_dmc_has_payload(struct intel_display *display) 398 { 399 return has_dmc_id_fw(display, DMC_FW_MAIN); 400 } 401 402 static const struct stepping_info * 403 intel_get_stepping_info(struct intel_display *display, 404 struct stepping_info *si) 405 { 406 const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display)); 407 408 si->stepping = step_name[0]; 409 si->substepping = step_name[1]; 410 return si; 411 } 412 413 static void gen9_set_dc_state_debugmask(struct intel_display *display) 414 { 415 /* The below bit doesn't need to be cleared ever afterwards */ 416 intel_de_rmw(display, DC_STATE_DEBUG, 0, 417 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 418 intel_de_posting_read(display, DC_STATE_DEBUG); 419 } 420 421 static void disable_event_handler(struct intel_display *display, 422 i915_reg_t ctl_reg, i915_reg_t htp_reg) 423 { 424 intel_de_write(display, ctl_reg, 425 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 426 DMC_EVT_CTL_TYPE_EDGE_0_1) | 427 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 428 DMC_EVT_CTL_EVENT_ID_FALSE)); 429 intel_de_write(display, htp_reg, 0); 430 } 431 432 static void disable_all_event_handlers(struct intel_display *display) 433 { 434 enum intel_dmc_id dmc_id; 435 436 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 437 if (DISPLAY_VER(display) < 12) 438 return; 439 440 for_each_dmc_id(dmc_id) { 441 int handler; 442 443 if (!has_dmc_id_fw(display, dmc_id)) 444 continue; 445 446 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 447 disable_event_handler(display, 448 DMC_EVT_CTL(display, dmc_id, handler), 449 DMC_EVT_HTP(display, dmc_id, handler)); 450 } 451 } 452 453 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 454 { 455 enum pipe pipe; 456 457 /* 458 * Wa_16015201720:adl-p,dg2 459 * The WA requires clock gating to be disabled all the time 460 * for pipe A and B. 461 * For pipe C and D clock gating needs to be disabled only 462 * during initializing the firmware. 463 */ 464 if (enable) 465 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 466 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 467 0, PIPEDMC_GATING_DIS); 468 else 469 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 470 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 471 PIPEDMC_GATING_DIS, 0); 472 } 473 474 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) 475 { 476 /* 477 * Wa_16015201720 478 * The WA requires clock gating to be disabled all the time 479 * for pipe A and B. 480 */ 481 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, 482 MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); 483 } 484 485 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 486 { 487 if (DISPLAY_VER(display) >= 14 && enable) 488 mtl_pipedmc_clock_gating_wa(display); 489 else if (DISPLAY_VER(display) == 13) 490 adlp_pipedmc_clock_gating_wa(display, enable); 491 } 492 493 void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe) 494 { 495 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 496 497 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 498 return; 499 500 if (DISPLAY_VER(display) >= 14) 501 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 502 else 503 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 504 } 505 506 void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe) 507 { 508 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 509 510 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 511 return; 512 513 if (DISPLAY_VER(display) >= 14) 514 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 515 else 516 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 517 } 518 519 /** 520 * intel_dmc_block_pkgc() - block PKG C-state 521 * @display: display instance 522 * @pipe: pipe which register use to block 523 * @block: block/unblock 524 * 525 * This interface is target for Wa_16025596647 usage. I.e. to set/clear 526 * PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register. 527 */ 528 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, 529 bool block) 530 { 531 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), 532 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, block ? 533 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0); 534 } 535 536 /** 537 * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG 538 * C-state exit 539 * @display: display instance 540 * @pipe: pipe which register use to block 541 * @enable: enable/disable 542 * 543 * This interface is target for Wa_16025596647 usage. I.e. start the package C 544 * exit at the start of the undelayed vblank 545 */ 546 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, 547 enum pipe pipe, bool enable) 548 { 549 u32 val; 550 551 if (enable) 552 val = DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING | 553 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 554 DMC_EVT_CTL_TYPE_EDGE_0_1) | 555 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 556 DMC_EVT_CTL_EVENT_ID_VBLANK_A); 557 else 558 val = REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 559 DMC_EVT_CTL_EVENT_ID_FALSE) | 560 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 561 DMC_EVT_CTL_TYPE_EDGE_0_1); 562 563 intel_de_write(display, MTL_PIPEDMC_EVT_CTL_4(pipe), 564 val); 565 } 566 567 static bool is_dmc_evt_ctl_reg(struct intel_display *display, 568 enum intel_dmc_id dmc_id, i915_reg_t reg) 569 { 570 u32 offset = i915_mmio_reg_offset(reg); 571 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); 572 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 573 574 return offset >= start && offset < end; 575 } 576 577 static bool is_dmc_evt_htp_reg(struct intel_display *display, 578 enum intel_dmc_id dmc_id, i915_reg_t reg) 579 { 580 u32 offset = i915_mmio_reg_offset(reg); 581 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); 582 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 583 584 return offset >= start && offset < end; 585 } 586 587 static bool disable_dmc_evt(struct intel_display *display, 588 enum intel_dmc_id dmc_id, 589 i915_reg_t reg, u32 data) 590 { 591 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) 592 return false; 593 594 /* keep all pipe DMC events disabled by default */ 595 if (dmc_id != DMC_FW_MAIN) 596 return true; 597 598 /* also disable the flip queue event on the main DMC on TGL */ 599 if (display->platform.tigerlake && 600 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC) 601 return true; 602 603 /* also disable the HRR event on the main DMC on TGL/ADLS */ 604 if ((display->platform.tigerlake || display->platform.alderlake_s) && 605 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A) 606 return true; 607 608 return false; 609 } 610 611 static u32 dmc_mmiodata(struct intel_display *display, 612 struct intel_dmc *dmc, 613 enum intel_dmc_id dmc_id, int i) 614 { 615 if (disable_dmc_evt(display, dmc_id, 616 dmc->dmc_info[dmc_id].mmioaddr[i], 617 dmc->dmc_info[dmc_id].mmiodata[i])) 618 return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 619 DMC_EVT_CTL_TYPE_EDGE_0_1) | 620 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 621 DMC_EVT_CTL_EVENT_ID_FALSE); 622 else 623 return dmc->dmc_info[dmc_id].mmiodata[i]; 624 } 625 626 /** 627 * intel_dmc_load_program() - write the firmware from memory to register. 628 * @display: display instance 629 * 630 * DMC firmware is read from a .bin file and kept in internal memory one time. 631 * Everytime display comes back from low power state this function is called to 632 * copy the firmware from internal memory to registers. 633 */ 634 void intel_dmc_load_program(struct intel_display *display) 635 { 636 struct i915_power_domains *power_domains = &display->power.domains; 637 struct intel_dmc *dmc = display_to_dmc(display); 638 enum intel_dmc_id dmc_id; 639 u32 i; 640 641 if (!intel_dmc_has_payload(display)) 642 return; 643 644 pipedmc_clock_gating_wa(display, true); 645 646 disable_all_event_handlers(display); 647 648 assert_display_rpm_held(display); 649 650 preempt_disable(); 651 652 for_each_dmc_id(dmc_id) { 653 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 654 intel_de_write_fw(display, 655 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 656 dmc->dmc_info[dmc_id].payload[i]); 657 } 658 } 659 660 preempt_enable(); 661 662 for_each_dmc_id(dmc_id) { 663 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 664 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], 665 dmc_mmiodata(display, dmc, dmc_id, i)); 666 } 667 } 668 669 power_domains->dc_state = 0; 670 671 gen9_set_dc_state_debugmask(display); 672 673 pipedmc_clock_gating_wa(display, false); 674 } 675 676 /** 677 * intel_dmc_disable_program() - disable the firmware 678 * @display: display instance 679 * 680 * Disable all event handlers in the firmware, making sure the firmware is 681 * inactive after the display is uninitialized. 682 */ 683 void intel_dmc_disable_program(struct intel_display *display) 684 { 685 if (!intel_dmc_has_payload(display)) 686 return; 687 688 pipedmc_clock_gating_wa(display, true); 689 disable_all_event_handlers(display); 690 pipedmc_clock_gating_wa(display, false); 691 } 692 693 void assert_dmc_loaded(struct intel_display *display) 694 { 695 struct intel_dmc *dmc = display_to_dmc(display); 696 697 drm_WARN_ONCE(display->drm, !dmc, "DMC not initialized\n"); 698 drm_WARN_ONCE(display->drm, dmc && 699 !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 700 "DMC program storage start is NULL\n"); 701 drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_SSP_BASE), 702 "DMC SSP Base Not fine\n"); 703 drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_HTP_SKL), 704 "DMC HTP Not fine\n"); 705 } 706 707 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 708 const struct stepping_info *si) 709 { 710 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 711 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 712 /* 713 * If we don't find a more specific one from above two checks, we 714 * then check for the generic one to be sure to work even with 715 * "broken firmware" 716 */ 717 (si->stepping == '*' && si->substepping == fw_info->substepping) || 718 (fw_info->stepping == '*' && fw_info->substepping == '*')) 719 return true; 720 721 return false; 722 } 723 724 /* 725 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 726 * already sanitized. 727 */ 728 static void dmc_set_fw_offset(struct intel_dmc *dmc, 729 const struct intel_fw_info *fw_info, 730 unsigned int num_entries, 731 const struct stepping_info *si, 732 u8 package_ver) 733 { 734 struct intel_display *display = dmc->display; 735 enum intel_dmc_id dmc_id; 736 unsigned int i; 737 738 for (i = 0; i < num_entries; i++) { 739 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 740 741 if (!is_valid_dmc_id(dmc_id)) { 742 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); 743 continue; 744 } 745 746 /* More specific versions come first, so we don't even have to 747 * check for the stepping since we already found a previous FW 748 * for this id. 749 */ 750 if (dmc->dmc_info[dmc_id].present) 751 continue; 752 753 if (fw_info_matches_stepping(&fw_info[i], si)) { 754 dmc->dmc_info[dmc_id].present = true; 755 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 756 } 757 } 758 } 759 760 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 761 const u32 *mmioaddr, u32 mmio_count, 762 int header_ver, enum intel_dmc_id dmc_id) 763 { 764 struct intel_display *display = dmc->display; 765 u32 start_range, end_range; 766 int i; 767 768 if (header_ver == 1) { 769 start_range = DMC_MMIO_START_RANGE; 770 end_range = DMC_MMIO_END_RANGE; 771 } else if (dmc_id == DMC_FW_MAIN) { 772 start_range = TGL_MAIN_MMIO_START; 773 end_range = TGL_MAIN_MMIO_END; 774 } else if (DISPLAY_VER(display) >= 13) { 775 start_range = ADLP_PIPE_MMIO_START; 776 end_range = ADLP_PIPE_MMIO_END; 777 } else if (DISPLAY_VER(display) >= 12) { 778 start_range = TGL_PIPE_MMIO_START(dmc_id); 779 end_range = TGL_PIPE_MMIO_END(dmc_id); 780 } else { 781 drm_warn(display->drm, "Unknown mmio range for sanity check"); 782 return false; 783 } 784 785 for (i = 0; i < mmio_count; i++) { 786 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 787 return false; 788 } 789 790 return true; 791 } 792 793 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 794 const struct intel_dmc_header_base *dmc_header, 795 size_t rem_size, enum intel_dmc_id dmc_id) 796 { 797 struct intel_display *display = dmc->display; 798 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 799 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 800 const u32 *mmioaddr, *mmiodata; 801 u32 mmio_count, mmio_count_max, start_mmioaddr; 802 u8 *payload; 803 804 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 805 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 806 807 /* 808 * Check if we can access common fields, we will checkc again below 809 * after we have read the version 810 */ 811 if (rem_size < sizeof(struct intel_dmc_header_base)) 812 goto error_truncated; 813 814 /* Cope with small differences between v1 and v3 */ 815 if (dmc_header->header_ver == 3) { 816 const struct intel_dmc_header_v3 *v3 = 817 (const struct intel_dmc_header_v3 *)dmc_header; 818 819 if (rem_size < sizeof(struct intel_dmc_header_v3)) 820 goto error_truncated; 821 822 mmioaddr = v3->mmioaddr; 823 mmiodata = v3->mmiodata; 824 mmio_count = v3->mmio_count; 825 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 826 /* header_len is in dwords */ 827 header_len_bytes = dmc_header->header_len * 4; 828 start_mmioaddr = v3->start_mmioaddr; 829 dmc_header_size = sizeof(*v3); 830 } else if (dmc_header->header_ver == 1) { 831 const struct intel_dmc_header_v1 *v1 = 832 (const struct intel_dmc_header_v1 *)dmc_header; 833 834 if (rem_size < sizeof(struct intel_dmc_header_v1)) 835 goto error_truncated; 836 837 mmioaddr = v1->mmioaddr; 838 mmiodata = v1->mmiodata; 839 mmio_count = v1->mmio_count; 840 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 841 header_len_bytes = dmc_header->header_len; 842 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 843 dmc_header_size = sizeof(*v1); 844 } else { 845 drm_err(display->drm, "Unknown DMC fw header version: %u\n", 846 dmc_header->header_ver); 847 return 0; 848 } 849 850 if (header_len_bytes != dmc_header_size) { 851 drm_err(display->drm, "DMC firmware has wrong dmc header length " 852 "(%u bytes)\n", header_len_bytes); 853 return 0; 854 } 855 856 /* Cache the dmc header info. */ 857 if (mmio_count > mmio_count_max) { 858 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 859 return 0; 860 } 861 862 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 863 dmc_header->header_ver, dmc_id)) { 864 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); 865 return 0; 866 } 867 868 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); 869 for (i = 0; i < mmio_count; i++) { 870 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 871 dmc_info->mmiodata[i] = mmiodata[i]; 872 873 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 874 i, mmioaddr[i], mmiodata[i], 875 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 876 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 877 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], 878 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 879 } 880 dmc_info->mmio_count = mmio_count; 881 dmc_info->start_mmioaddr = start_mmioaddr; 882 883 rem_size -= header_len_bytes; 884 885 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 886 payload_size = dmc_header->fw_size * 4; 887 if (rem_size < payload_size) 888 goto error_truncated; 889 890 if (payload_size > dmc->max_fw_size) { 891 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); 892 return 0; 893 } 894 dmc_info->dmc_fw_size = dmc_header->fw_size; 895 896 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 897 if (!dmc_info->payload) 898 return 0; 899 900 payload = (u8 *)(dmc_header) + header_len_bytes; 901 memcpy(dmc_info->payload, payload, payload_size); 902 903 return header_len_bytes + payload_size; 904 905 error_truncated: 906 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 907 return 0; 908 } 909 910 static u32 911 parse_dmc_fw_package(struct intel_dmc *dmc, 912 const struct intel_package_header *package_header, 913 const struct stepping_info *si, 914 size_t rem_size) 915 { 916 struct intel_display *display = dmc->display; 917 u32 package_size = sizeof(struct intel_package_header); 918 u32 num_entries, max_entries; 919 const struct intel_fw_info *fw_info; 920 921 if (rem_size < package_size) 922 goto error_truncated; 923 924 if (package_header->header_ver == 1) { 925 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 926 } else if (package_header->header_ver == 2) { 927 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 928 } else { 929 drm_err(display->drm, "DMC firmware has unknown header version %u\n", 930 package_header->header_ver); 931 return 0; 932 } 933 934 /* 935 * We should always have space for max_entries, 936 * even if not all are used 937 */ 938 package_size += max_entries * sizeof(struct intel_fw_info); 939 if (rem_size < package_size) 940 goto error_truncated; 941 942 if (package_header->header_len * 4 != package_size) { 943 drm_err(display->drm, "DMC firmware has wrong package header length " 944 "(%u bytes)\n", package_size); 945 return 0; 946 } 947 948 num_entries = package_header->num_entries; 949 if (WARN_ON(package_header->num_entries > max_entries)) 950 num_entries = max_entries; 951 952 fw_info = (const struct intel_fw_info *) 953 ((u8 *)package_header + sizeof(*package_header)); 954 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 955 package_header->header_ver); 956 957 /* dmc_offset is in dwords */ 958 return package_size; 959 960 error_truncated: 961 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 962 return 0; 963 } 964 965 /* Return number of bytes parsed or 0 on error */ 966 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 967 struct intel_css_header *css_header, 968 size_t rem_size) 969 { 970 struct intel_display *display = dmc->display; 971 972 if (rem_size < sizeof(struct intel_css_header)) { 973 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 974 return 0; 975 } 976 977 if (sizeof(struct intel_css_header) != 978 (css_header->header_len * 4)) { 979 drm_err(display->drm, "DMC firmware has wrong CSS header length " 980 "(%u bytes)\n", 981 (css_header->header_len * 4)); 982 return 0; 983 } 984 985 dmc->version = css_header->version; 986 987 return sizeof(struct intel_css_header); 988 } 989 990 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 991 { 992 struct intel_display *display = dmc->display; 993 struct intel_css_header *css_header; 994 struct intel_package_header *package_header; 995 struct intel_dmc_header_base *dmc_header; 996 struct stepping_info display_info = { '*', '*'}; 997 const struct stepping_info *si = intel_get_stepping_info(display, &display_info); 998 enum intel_dmc_id dmc_id; 999 u32 readcount = 0; 1000 u32 r, offset; 1001 1002 if (!fw) 1003 return -EINVAL; 1004 1005 /* Extract CSS Header information */ 1006 css_header = (struct intel_css_header *)fw->data; 1007 r = parse_dmc_fw_css(dmc, css_header, fw->size); 1008 if (!r) 1009 return -EINVAL; 1010 1011 readcount += r; 1012 1013 /* Extract Package Header information */ 1014 package_header = (struct intel_package_header *)&fw->data[readcount]; 1015 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 1016 if (!r) 1017 return -EINVAL; 1018 1019 readcount += r; 1020 1021 for_each_dmc_id(dmc_id) { 1022 if (!dmc->dmc_info[dmc_id].present) 1023 continue; 1024 1025 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 1026 if (offset > fw->size) { 1027 drm_err(display->drm, "Reading beyond the fw_size\n"); 1028 continue; 1029 } 1030 1031 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 1032 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 1033 } 1034 1035 if (!intel_dmc_has_payload(display)) { 1036 drm_err(display->drm, "DMC firmware main program not found\n"); 1037 return -ENOENT; 1038 } 1039 1040 return 0; 1041 } 1042 1043 static void intel_dmc_runtime_pm_get(struct intel_display *display) 1044 { 1045 drm_WARN_ON(display->drm, display->dmc.wakeref); 1046 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); 1047 } 1048 1049 static void intel_dmc_runtime_pm_put(struct intel_display *display) 1050 { 1051 intel_wakeref_t wakeref __maybe_unused = 1052 fetch_and_zero(&display->dmc.wakeref); 1053 1054 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 1055 } 1056 1057 static const char *dmc_fallback_path(struct intel_display *display) 1058 { 1059 if (display->platform.alderlake_p) 1060 return ADLP_DMC_FALLBACK_PATH; 1061 1062 return NULL; 1063 } 1064 1065 static void dmc_load_work_fn(struct work_struct *work) 1066 { 1067 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1068 struct intel_display *display = dmc->display; 1069 const struct firmware *fw = NULL; 1070 const char *fallback_path; 1071 int err; 1072 1073 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); 1074 1075 if (err == -ENOENT && !dmc_firmware_param(display)) { 1076 fallback_path = dmc_fallback_path(display); 1077 if (fallback_path) { 1078 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", 1079 dmc->fw_path, fallback_path); 1080 err = request_firmware(&fw, fallback_path, display->drm->dev); 1081 if (err == 0) 1082 dmc->fw_path = fallback_path; 1083 } 1084 } 1085 1086 if (err) { 1087 drm_notice(display->drm, 1088 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1089 dmc->fw_path, ERR_PTR(err)); 1090 drm_notice(display->drm, "DMC firmware homepage: %s", 1091 INTEL_DMC_FIRMWARE_URL); 1092 return; 1093 } 1094 1095 err = parse_dmc_fw(dmc, fw); 1096 if (err) { 1097 drm_notice(display->drm, 1098 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1099 dmc->fw_path, ERR_PTR(err)); 1100 goto out; 1101 } 1102 1103 intel_dmc_load_program(display); 1104 intel_dmc_runtime_pm_put(display); 1105 1106 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1107 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1108 DMC_VERSION_MINOR(dmc->version)); 1109 1110 out: 1111 release_firmware(fw); 1112 } 1113 1114 /** 1115 * intel_dmc_init() - initialize the firmware loading. 1116 * @display: display instance 1117 * 1118 * This function is called at the time of loading the display driver to read 1119 * firmware from a .bin file and copied into a internal memory. 1120 */ 1121 void intel_dmc_init(struct intel_display *display) 1122 { 1123 struct drm_i915_private *i915 = to_i915(display->drm); 1124 struct intel_dmc *dmc; 1125 1126 if (!HAS_DMC(display)) 1127 return; 1128 1129 /* 1130 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1131 * runtime-suspend. 1132 * 1133 * On error, we return with the rpm wakeref held to prevent runtime 1134 * suspend as runtime suspend *requires* a working DMC for whatever 1135 * reason. 1136 */ 1137 intel_dmc_runtime_pm_get(display); 1138 1139 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); 1140 if (!dmc) 1141 return; 1142 1143 dmc->display = display; 1144 1145 INIT_WORK(&dmc->work, dmc_load_work_fn); 1146 1147 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); 1148 1149 if (dmc_firmware_param_disabled(display)) { 1150 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); 1151 goto out; 1152 } 1153 1154 if (dmc_firmware_param(display)) 1155 dmc->fw_path = dmc_firmware_param(display); 1156 1157 if (!dmc->fw_path) { 1158 drm_dbg_kms(display->drm, 1159 "No known DMC firmware for platform, disabling runtime PM\n"); 1160 goto out; 1161 } 1162 1163 display->dmc.dmc = dmc; 1164 1165 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); 1166 queue_work(i915->unordered_wq, &dmc->work); 1167 1168 return; 1169 1170 out: 1171 kfree(dmc); 1172 } 1173 1174 /** 1175 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1176 * @display: display instance 1177 * 1178 * Prepare the DMC firmware before entering system suspend. This includes 1179 * flushing pending work items and releasing any resources acquired during 1180 * init. 1181 */ 1182 void intel_dmc_suspend(struct intel_display *display) 1183 { 1184 struct intel_dmc *dmc = display_to_dmc(display); 1185 1186 if (!HAS_DMC(display)) 1187 return; 1188 1189 if (dmc) 1190 flush_work(&dmc->work); 1191 1192 /* Drop the reference held in case DMC isn't loaded. */ 1193 if (!intel_dmc_has_payload(display)) 1194 intel_dmc_runtime_pm_put(display); 1195 } 1196 1197 /** 1198 * intel_dmc_resume() - init DMC firmware during system resume 1199 * @display: display instance 1200 * 1201 * Reinitialize the DMC firmware during system resume, reacquiring any 1202 * resources released in intel_dmc_suspend(). 1203 */ 1204 void intel_dmc_resume(struct intel_display *display) 1205 { 1206 if (!HAS_DMC(display)) 1207 return; 1208 1209 /* 1210 * Reacquire the reference to keep RPM disabled in case DMC isn't 1211 * loaded. 1212 */ 1213 if (!intel_dmc_has_payload(display)) 1214 intel_dmc_runtime_pm_get(display); 1215 } 1216 1217 /** 1218 * intel_dmc_fini() - unload the DMC firmware. 1219 * @display: display instance 1220 * 1221 * Firmmware unloading includes freeing the internal memory and reset the 1222 * firmware loading status. 1223 */ 1224 void intel_dmc_fini(struct intel_display *display) 1225 { 1226 struct intel_dmc *dmc = display_to_dmc(display); 1227 enum intel_dmc_id dmc_id; 1228 1229 if (!HAS_DMC(display)) 1230 return; 1231 1232 intel_dmc_suspend(display); 1233 drm_WARN_ON(display->drm, display->dmc.wakeref); 1234 1235 if (dmc) { 1236 for_each_dmc_id(dmc_id) 1237 kfree(dmc->dmc_info[dmc_id].payload); 1238 1239 kfree(dmc); 1240 display->dmc.dmc = NULL; 1241 } 1242 } 1243 1244 struct intel_dmc_snapshot { 1245 bool initialized; 1246 bool loaded; 1247 u32 version; 1248 }; 1249 1250 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) 1251 { 1252 struct intel_dmc *dmc = display_to_dmc(display); 1253 struct intel_dmc_snapshot *snapshot; 1254 1255 if (!HAS_DMC(display)) 1256 return NULL; 1257 1258 snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); 1259 if (!snapshot) 1260 return NULL; 1261 1262 snapshot->initialized = dmc; 1263 snapshot->loaded = intel_dmc_has_payload(display); 1264 if (dmc) 1265 snapshot->version = dmc->version; 1266 1267 return snapshot; 1268 } 1269 1270 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p) 1271 { 1272 if (!snapshot) 1273 return; 1274 1275 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized)); 1276 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded)); 1277 if (snapshot->initialized) 1278 drm_printf(p, "DMC fw version: %d.%d\n", 1279 DMC_VERSION_MAJOR(snapshot->version), 1280 DMC_VERSION_MINOR(snapshot->version)); 1281 } 1282 1283 void intel_dmc_update_dc6_allowed_count(struct intel_display *display, 1284 bool start_tracking) 1285 { 1286 struct intel_dmc *dmc = display_to_dmc(display); 1287 u32 dc5_cur_count; 1288 1289 if (DISPLAY_VER(dmc->display) < 14) 1290 return; 1291 1292 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT); 1293 1294 if (!start_tracking) 1295 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start; 1296 1297 dmc->dc6_allowed.dc5_start = dc5_cur_count; 1298 } 1299 1300 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count) 1301 { 1302 struct i915_power_domains *power_domains = &display->power.domains; 1303 struct intel_dmc *dmc = display_to_dmc(display); 1304 bool dc6_enabled; 1305 1306 if (DISPLAY_VER(display) < 14) 1307 return false; 1308 1309 mutex_lock(&power_domains->lock); 1310 dc6_enabled = intel_de_read(display, DC_STATE_EN) & 1311 DC_STATE_EN_UPTO_DC6; 1312 if (dc6_enabled) 1313 intel_dmc_update_dc6_allowed_count(display, false); 1314 1315 *count = dmc->dc6_allowed.count; 1316 mutex_unlock(&power_domains->lock); 1317 1318 return true; 1319 } 1320 1321 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1322 { 1323 struct intel_display *display = m->private; 1324 struct intel_dmc *dmc = display_to_dmc(display); 1325 struct ref_tracker *wakeref; 1326 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1327 u32 dc6_allowed_count; 1328 1329 if (!HAS_DMC(display)) 1330 return -ENODEV; 1331 1332 wakeref = intel_display_rpm_get(display); 1333 1334 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1335 seq_printf(m, "fw loaded: %s\n", 1336 str_yes_no(intel_dmc_has_payload(display))); 1337 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1338 seq_printf(m, "Pipe A fw needed: %s\n", 1339 str_yes_no(DISPLAY_VER(display) >= 12)); 1340 seq_printf(m, "Pipe A fw loaded: %s\n", 1341 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); 1342 seq_printf(m, "Pipe B fw needed: %s\n", 1343 str_yes_no(display->platform.alderlake_p || 1344 DISPLAY_VER(display) >= 14)); 1345 seq_printf(m, "Pipe B fw loaded: %s\n", 1346 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); 1347 1348 if (!intel_dmc_has_payload(display)) 1349 goto out; 1350 1351 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1352 DMC_VERSION_MINOR(dmc->version)); 1353 1354 if (DISPLAY_VER(display) >= 12) { 1355 i915_reg_t dc3co_reg; 1356 1357 if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { 1358 dc3co_reg = DG1_DMC_DEBUG3; 1359 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1360 } else { 1361 dc3co_reg = TGL_DMC_DEBUG3; 1362 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1363 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1364 } 1365 1366 seq_printf(m, "DC3CO count: %d\n", 1367 intel_de_read(display, dc3co_reg)); 1368 } else { 1369 dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT : 1370 SKL_DMC_DC3_DC5_COUNT; 1371 if (!display->platform.geminilake && !display->platform.broxton) 1372 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1373 } 1374 1375 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); 1376 1377 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) 1378 seq_printf(m, "DC5 -> DC6 allowed count: %d\n", 1379 dc6_allowed_count); 1380 else if (i915_mmio_reg_valid(dc6_reg)) 1381 seq_printf(m, "DC5 -> DC6 count: %d\n", 1382 intel_de_read(display, dc6_reg)); 1383 1384 seq_printf(m, "program base: 0x%08x\n", 1385 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1386 1387 out: 1388 seq_printf(m, "ssp base: 0x%08x\n", 1389 intel_de_read(display, DMC_SSP_BASE)); 1390 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); 1391 1392 intel_display_rpm_put(display, wakeref); 1393 1394 return 0; 1395 } 1396 1397 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1398 1399 void intel_dmc_debugfs_register(struct intel_display *display) 1400 { 1401 struct drm_minor *minor = display->drm->primary; 1402 1403 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 1404 display, &intel_dmc_debugfs_status_fops); 1405 } 1406