1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 28 #include "i915_drv.h" 29 #include "i915_reg.h" 30 #include "intel_crtc.h" 31 #include "intel_de.h" 32 #include "intel_display_power_well.h" 33 #include "intel_display_regs.h" 34 #include "intel_display_rpm.h" 35 #include "intel_display_types.h" 36 #include "intel_dmc.h" 37 #include "intel_dmc_regs.h" 38 #include "intel_step.h" 39 40 /** 41 * DOC: DMC Firmware Support 42 * 43 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 44 * engine to save and restore the state of display engine when it enter into 45 * low-power state and comes back to normal. 46 */ 47 48 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 49 50 enum intel_dmc_id { 51 DMC_FW_MAIN = 0, 52 DMC_FW_PIPEA, 53 DMC_FW_PIPEB, 54 DMC_FW_PIPEC, 55 DMC_FW_PIPED, 56 DMC_FW_MAX 57 }; 58 59 struct intel_dmc { 60 struct intel_display *display; 61 struct work_struct work; 62 const char *fw_path; 63 u32 max_fw_size; /* bytes */ 64 u32 version; 65 struct { 66 u32 dc5_start; 67 u32 count; 68 } dc6_allowed; 69 struct dmc_fw_info { 70 u32 mmio_count; 71 i915_reg_t mmioaddr[20]; 72 u32 mmiodata[20]; 73 u32 dmc_offset; 74 u32 start_mmioaddr; 75 u32 dmc_fw_size; /*dwords */ 76 u32 *payload; 77 bool present; 78 } dmc_info[DMC_FW_MAX]; 79 }; 80 81 /* Note: This may be NULL. */ 82 static struct intel_dmc *display_to_dmc(struct intel_display *display) 83 { 84 return display->dmc.dmc; 85 } 86 87 static const char *dmc_firmware_param(struct intel_display *display) 88 { 89 const char *p = display->params.dmc_firmware_path; 90 91 return p && *p ? p : NULL; 92 } 93 94 static bool dmc_firmware_param_disabled(struct intel_display *display) 95 { 96 const char *p = dmc_firmware_param(display); 97 98 /* Magic path to indicate disabled */ 99 return p && !strcmp(p, "/dev/null"); 100 } 101 102 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 103 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 104 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 105 106 #define DMC_PATH(platform) \ 107 "i915/" __stringify(platform) "_dmc.bin" 108 109 /* 110 * New DMC additions should not use this. This is used solely to remain 111 * compatible with systems that have not yet updated DMC blobs to use 112 * unversioned file names. 113 */ 114 #define DMC_LEGACY_PATH(platform, major, minor) \ 115 "i915/" \ 116 __stringify(platform) "_dmc_ver" \ 117 __stringify(major) "_" \ 118 __stringify(minor) ".bin" 119 120 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 121 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 122 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 123 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 124 125 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd) 126 MODULE_FIRMWARE(XE3LPD_DMC_PATH); 127 128 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 129 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 130 131 #define BMG_DMC_PATH DMC_PATH(bmg) 132 MODULE_FIRMWARE(BMG_DMC_PATH); 133 134 #define MTL_DMC_PATH DMC_PATH(mtl) 135 MODULE_FIRMWARE(MTL_DMC_PATH); 136 137 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 138 MODULE_FIRMWARE(DG2_DMC_PATH); 139 140 #define ADLP_DMC_PATH DMC_PATH(adlp) 141 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 142 MODULE_FIRMWARE(ADLP_DMC_PATH); 143 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 144 145 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 146 MODULE_FIRMWARE(ADLS_DMC_PATH); 147 148 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 149 MODULE_FIRMWARE(DG1_DMC_PATH); 150 151 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 152 MODULE_FIRMWARE(RKL_DMC_PATH); 153 154 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 155 MODULE_FIRMWARE(TGL_DMC_PATH); 156 157 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 158 #define ICL_DMC_MAX_FW_SIZE 0x6000 159 MODULE_FIRMWARE(ICL_DMC_PATH); 160 161 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 162 #define GLK_DMC_MAX_FW_SIZE 0x4000 163 MODULE_FIRMWARE(GLK_DMC_PATH); 164 165 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 166 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 167 MODULE_FIRMWARE(KBL_DMC_PATH); 168 169 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 170 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 171 MODULE_FIRMWARE(SKL_DMC_PATH); 172 173 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 174 #define BXT_DMC_MAX_FW_SIZE 0x3000 175 MODULE_FIRMWARE(BXT_DMC_PATH); 176 177 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) 178 { 179 const char *fw_path = NULL; 180 u32 max_fw_size = 0; 181 182 if (DISPLAY_VERx100(display) == 3000) { 183 fw_path = XE3LPD_DMC_PATH; 184 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 185 } else if (DISPLAY_VERx100(display) == 2000) { 186 fw_path = XE2LPD_DMC_PATH; 187 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 188 } else if (DISPLAY_VERx100(display) == 1401) { 189 fw_path = BMG_DMC_PATH; 190 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 191 } else if (DISPLAY_VERx100(display) == 1400) { 192 fw_path = MTL_DMC_PATH; 193 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 194 } else if (display->platform.dg2) { 195 fw_path = DG2_DMC_PATH; 196 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 197 } else if (display->platform.alderlake_p) { 198 fw_path = ADLP_DMC_PATH; 199 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 200 } else if (display->platform.alderlake_s) { 201 fw_path = ADLS_DMC_PATH; 202 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 203 } else if (display->platform.dg1) { 204 fw_path = DG1_DMC_PATH; 205 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 206 } else if (display->platform.rocketlake) { 207 fw_path = RKL_DMC_PATH; 208 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 209 } else if (display->platform.tigerlake) { 210 fw_path = TGL_DMC_PATH; 211 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 212 } else if (DISPLAY_VER(display) == 11) { 213 fw_path = ICL_DMC_PATH; 214 max_fw_size = ICL_DMC_MAX_FW_SIZE; 215 } else if (display->platform.geminilake) { 216 fw_path = GLK_DMC_PATH; 217 max_fw_size = GLK_DMC_MAX_FW_SIZE; 218 } else if (display->platform.kabylake || 219 display->platform.coffeelake || 220 display->platform.cometlake) { 221 fw_path = KBL_DMC_PATH; 222 max_fw_size = KBL_DMC_MAX_FW_SIZE; 223 } else if (display->platform.skylake) { 224 fw_path = SKL_DMC_PATH; 225 max_fw_size = SKL_DMC_MAX_FW_SIZE; 226 } else if (display->platform.broxton) { 227 fw_path = BXT_DMC_PATH; 228 max_fw_size = BXT_DMC_MAX_FW_SIZE; 229 } 230 231 *size = max_fw_size; 232 233 return fw_path; 234 } 235 236 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 237 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 238 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 239 #define DMC_V1_MAX_MMIO_COUNT 8 240 #define DMC_V3_MAX_MMIO_COUNT 20 241 #define DMC_V1_MMIO_START_RANGE 0x80000 242 243 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 244 245 struct intel_css_header { 246 /* 0x09 for DMC */ 247 u32 module_type; 248 249 /* Includes the DMC specific header in dwords */ 250 u32 header_len; 251 252 /* always value would be 0x10000 */ 253 u32 header_ver; 254 255 /* Not used */ 256 u32 module_id; 257 258 /* Not used */ 259 u32 module_vendor; 260 261 /* in YYYYMMDD format */ 262 u32 date; 263 264 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 265 u32 size; 266 267 /* Not used */ 268 u32 key_size; 269 270 /* Not used */ 271 u32 modulus_size; 272 273 /* Not used */ 274 u32 exponent_size; 275 276 /* Not used */ 277 u32 reserved1[12]; 278 279 /* Major Minor */ 280 u32 version; 281 282 /* Not used */ 283 u32 reserved2[8]; 284 285 /* Not used */ 286 u32 kernel_header_info; 287 } __packed; 288 289 struct intel_fw_info { 290 u8 reserved1; 291 292 /* reserved on package_header version 1, must be 0 on version 2 */ 293 u8 dmc_id; 294 295 /* Stepping (A, B, C, ..., *). * is a wildcard */ 296 char stepping; 297 298 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 299 char substepping; 300 301 u32 offset; 302 u32 reserved2; 303 } __packed; 304 305 struct intel_package_header { 306 /* DMC container header length in dwords */ 307 u8 header_len; 308 309 /* 0x01, 0x02 */ 310 u8 header_ver; 311 312 u8 reserved[10]; 313 314 /* Number of valid entries in the FWInfo array below */ 315 u32 num_entries; 316 } __packed; 317 318 struct intel_dmc_header_base { 319 /* always value would be 0x40403E3E */ 320 u32 signature; 321 322 /* DMC binary header length */ 323 u8 header_len; 324 325 /* 0x01 */ 326 u8 header_ver; 327 328 /* Reserved */ 329 u16 dmcc_ver; 330 331 /* Major, Minor */ 332 u32 project; 333 334 /* Firmware program size (excluding header) in dwords */ 335 u32 fw_size; 336 337 /* Major Minor version */ 338 u32 fw_version; 339 } __packed; 340 341 struct intel_dmc_header_v1 { 342 struct intel_dmc_header_base base; 343 344 /* Number of valid MMIO cycles present. */ 345 u32 mmio_count; 346 347 /* MMIO address */ 348 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 349 350 /* MMIO data */ 351 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 352 353 /* FW filename */ 354 char dfile[32]; 355 356 u32 reserved1[2]; 357 } __packed; 358 359 struct intel_dmc_header_v3 { 360 struct intel_dmc_header_base base; 361 362 /* DMC RAM start MMIO address */ 363 u32 start_mmioaddr; 364 365 u32 reserved[9]; 366 367 /* FW filename */ 368 char dfile[32]; 369 370 /* Number of valid MMIO cycles present. */ 371 u32 mmio_count; 372 373 /* MMIO address */ 374 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 375 376 /* MMIO data */ 377 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 378 } __packed; 379 380 struct stepping_info { 381 char stepping; 382 char substepping; 383 }; 384 385 #define for_each_dmc_id(__dmc_id) \ 386 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 387 388 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 389 { 390 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 391 } 392 393 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) 394 { 395 struct intel_dmc *dmc = display_to_dmc(display); 396 397 return dmc && dmc->dmc_info[dmc_id].payload; 398 } 399 400 bool intel_dmc_has_payload(struct intel_display *display) 401 { 402 return has_dmc_id_fw(display, DMC_FW_MAIN); 403 } 404 405 static const struct stepping_info * 406 intel_get_stepping_info(struct intel_display *display, 407 struct stepping_info *si) 408 { 409 const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display)); 410 411 si->stepping = step_name[0]; 412 si->substepping = step_name[1]; 413 return si; 414 } 415 416 static void gen9_set_dc_state_debugmask(struct intel_display *display) 417 { 418 /* The below bit doesn't need to be cleared ever afterwards */ 419 intel_de_rmw(display, DC_STATE_DEBUG, 0, 420 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 421 intel_de_posting_read(display, DC_STATE_DEBUG); 422 } 423 424 static void disable_event_handler(struct intel_display *display, 425 i915_reg_t ctl_reg, i915_reg_t htp_reg) 426 { 427 intel_de_write(display, ctl_reg, 428 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 429 DMC_EVT_CTL_TYPE_EDGE_0_1) | 430 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 431 DMC_EVENT_FALSE)); 432 intel_de_write(display, htp_reg, 0); 433 } 434 435 static void disable_all_event_handlers(struct intel_display *display) 436 { 437 enum intel_dmc_id dmc_id; 438 439 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 440 if (DISPLAY_VER(display) < 12) 441 return; 442 443 for_each_dmc_id(dmc_id) { 444 int handler; 445 446 if (!has_dmc_id_fw(display, dmc_id)) 447 continue; 448 449 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 450 disable_event_handler(display, 451 DMC_EVT_CTL(display, dmc_id, handler), 452 DMC_EVT_HTP(display, dmc_id, handler)); 453 } 454 } 455 456 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 457 { 458 enum pipe pipe; 459 460 /* 461 * Wa_16015201720:adl-p,dg2 462 * The WA requires clock gating to be disabled all the time 463 * for pipe A and B. 464 * For pipe C and D clock gating needs to be disabled only 465 * during initializing the firmware. 466 */ 467 if (enable) 468 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 469 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 470 0, PIPEDMC_GATING_DIS); 471 else 472 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 473 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 474 PIPEDMC_GATING_DIS, 0); 475 } 476 477 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) 478 { 479 /* 480 * Wa_16015201720 481 * The WA requires clock gating to be disabled all the time 482 * for pipe A and B. 483 */ 484 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, 485 MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); 486 } 487 488 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 489 { 490 if (DISPLAY_VER(display) >= 14 && enable) 491 mtl_pipedmc_clock_gating_wa(display); 492 else if (DISPLAY_VER(display) == 13) 493 adlp_pipedmc_clock_gating_wa(display, enable); 494 } 495 496 static u32 pipedmc_interrupt_mask(struct intel_display *display) 497 { 498 /* 499 * FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B 500 * triggering it during the first DC state transition. Figure 501 * out what is going on... 502 */ 503 return PIPEDMC_GTT_FAULT | 504 PIPEDMC_ATS_FAULT; 505 } 506 507 void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe) 508 { 509 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 510 511 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 512 return; 513 514 if (DISPLAY_VER(display) >= 20) { 515 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 516 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display)); 517 } 518 519 if (DISPLAY_VER(display) >= 14) 520 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 521 else 522 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 523 } 524 525 void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe) 526 { 527 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 528 529 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 530 return; 531 532 if (DISPLAY_VER(display) >= 14) 533 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 534 else 535 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 536 537 if (DISPLAY_VER(display) >= 20) { 538 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0); 539 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 540 } 541 } 542 543 static u32 dmc_evt_ctl_disable(void) 544 { 545 return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 546 DMC_EVT_CTL_TYPE_EDGE_0_1) | 547 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 548 DMC_EVENT_FALSE); 549 } 550 551 static bool is_dmc_evt_ctl_reg(struct intel_display *display, 552 enum intel_dmc_id dmc_id, i915_reg_t reg) 553 { 554 u32 offset = i915_mmio_reg_offset(reg); 555 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); 556 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 557 558 return offset >= start && offset < end; 559 } 560 561 static bool is_dmc_evt_htp_reg(struct intel_display *display, 562 enum intel_dmc_id dmc_id, i915_reg_t reg) 563 { 564 u32 offset = i915_mmio_reg_offset(reg); 565 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); 566 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 567 568 return offset >= start && offset < end; 569 } 570 571 static bool is_event_handler(struct intel_display *display, 572 enum intel_dmc_id dmc_id, 573 unsigned int event_id, 574 i915_reg_t reg, u32 data) 575 { 576 return is_dmc_evt_ctl_reg(display, dmc_id, reg) && 577 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id; 578 } 579 580 static void dmc_configure_event(struct intel_display *display, 581 enum intel_dmc_id dmc_id, 582 unsigned int event_id, 583 bool enable) 584 { 585 struct intel_dmc *dmc = display_to_dmc(display); 586 int num_handlers = 0; 587 int i; 588 589 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 590 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 591 u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; 592 593 if (!is_event_handler(display, dmc_id, event_id, reg, data)) 594 continue; 595 596 intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable()); 597 num_handlers++; 598 } 599 600 drm_WARN_ONCE(display->drm, num_handlers != 1, 601 "DMC %d has %d handlers for event 0x%x\n", 602 dmc_id, num_handlers, event_id); 603 } 604 605 /** 606 * intel_dmc_block_pkgc() - block PKG C-state 607 * @display: display instance 608 * @pipe: pipe which register use to block 609 * @block: block/unblock 610 * 611 * This interface is target for Wa_16025596647 usage. I.e. to set/clear 612 * PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register. 613 */ 614 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, 615 bool block) 616 { 617 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), 618 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, block ? 619 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0); 620 } 621 622 /** 623 * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG 624 * C-state exit 625 * @display: display instance 626 * @pipe: pipe which register use to block 627 * @enable: enable/disable 628 * 629 * This interface is target for Wa_16025596647 usage. I.e. start the package C 630 * exit at the start of the undelayed vblank 631 */ 632 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, 633 enum pipe pipe, bool enable) 634 { 635 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 636 637 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable); 638 } 639 640 static bool disable_dmc_evt(struct intel_display *display, 641 enum intel_dmc_id dmc_id, 642 i915_reg_t reg, u32 data) 643 { 644 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) 645 return false; 646 647 /* keep all pipe DMC events disabled by default */ 648 if (dmc_id != DMC_FW_MAIN) 649 return true; 650 651 /* also disable the flip queue event on the main DMC on TGL */ 652 if (display->platform.tigerlake && 653 is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data)) 654 return true; 655 656 /* also disable the HRR event on the main DMC on TGL/ADLS */ 657 if ((display->platform.tigerlake || display->platform.alderlake_s) && 658 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg, data)) 659 return true; 660 661 return false; 662 } 663 664 static u32 dmc_mmiodata(struct intel_display *display, 665 struct intel_dmc *dmc, 666 enum intel_dmc_id dmc_id, int i) 667 { 668 if (disable_dmc_evt(display, dmc_id, 669 dmc->dmc_info[dmc_id].mmioaddr[i], 670 dmc->dmc_info[dmc_id].mmiodata[i])) 671 return dmc_evt_ctl_disable(); 672 else 673 return dmc->dmc_info[dmc_id].mmiodata[i]; 674 } 675 676 /** 677 * intel_dmc_load_program() - write the firmware from memory to register. 678 * @display: display instance 679 * 680 * DMC firmware is read from a .bin file and kept in internal memory one time. 681 * Everytime display comes back from low power state this function is called to 682 * copy the firmware from internal memory to registers. 683 */ 684 void intel_dmc_load_program(struct intel_display *display) 685 { 686 struct i915_power_domains *power_domains = &display->power.domains; 687 struct intel_dmc *dmc = display_to_dmc(display); 688 enum intel_dmc_id dmc_id; 689 u32 i; 690 691 if (!intel_dmc_has_payload(display)) 692 return; 693 694 pipedmc_clock_gating_wa(display, true); 695 696 disable_all_event_handlers(display); 697 698 assert_display_rpm_held(display); 699 700 preempt_disable(); 701 702 for_each_dmc_id(dmc_id) { 703 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 704 intel_de_write_fw(display, 705 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 706 dmc->dmc_info[dmc_id].payload[i]); 707 } 708 } 709 710 preempt_enable(); 711 712 for_each_dmc_id(dmc_id) { 713 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 714 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], 715 dmc_mmiodata(display, dmc, dmc_id, i)); 716 } 717 } 718 719 power_domains->dc_state = 0; 720 721 gen9_set_dc_state_debugmask(display); 722 723 pipedmc_clock_gating_wa(display, false); 724 } 725 726 /** 727 * intel_dmc_disable_program() - disable the firmware 728 * @display: display instance 729 * 730 * Disable all event handlers in the firmware, making sure the firmware is 731 * inactive after the display is uninitialized. 732 */ 733 void intel_dmc_disable_program(struct intel_display *display) 734 { 735 if (!intel_dmc_has_payload(display)) 736 return; 737 738 pipedmc_clock_gating_wa(display, true); 739 disable_all_event_handlers(display); 740 pipedmc_clock_gating_wa(display, false); 741 } 742 743 void assert_dmc_loaded(struct intel_display *display) 744 { 745 struct intel_dmc *dmc = display_to_dmc(display); 746 747 drm_WARN_ONCE(display->drm, !dmc, "DMC not initialized\n"); 748 drm_WARN_ONCE(display->drm, dmc && 749 !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 750 "DMC program storage start is NULL\n"); 751 drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_SSP_BASE), 752 "DMC SSP Base Not fine\n"); 753 drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_HTP_SKL), 754 "DMC HTP Not fine\n"); 755 } 756 757 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 758 const struct stepping_info *si) 759 { 760 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 761 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 762 /* 763 * If we don't find a more specific one from above two checks, we 764 * then check for the generic one to be sure to work even with 765 * "broken firmware" 766 */ 767 (si->stepping == '*' && si->substepping == fw_info->substepping) || 768 (fw_info->stepping == '*' && fw_info->substepping == '*')) 769 return true; 770 771 return false; 772 } 773 774 /* 775 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 776 * already sanitized. 777 */ 778 static void dmc_set_fw_offset(struct intel_dmc *dmc, 779 const struct intel_fw_info *fw_info, 780 unsigned int num_entries, 781 const struct stepping_info *si, 782 u8 package_ver) 783 { 784 struct intel_display *display = dmc->display; 785 enum intel_dmc_id dmc_id; 786 unsigned int i; 787 788 for (i = 0; i < num_entries; i++) { 789 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 790 791 if (!is_valid_dmc_id(dmc_id)) { 792 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); 793 continue; 794 } 795 796 /* More specific versions come first, so we don't even have to 797 * check for the stepping since we already found a previous FW 798 * for this id. 799 */ 800 if (dmc->dmc_info[dmc_id].present) 801 continue; 802 803 if (fw_info_matches_stepping(&fw_info[i], si)) { 804 dmc->dmc_info[dmc_id].present = true; 805 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 806 } 807 } 808 } 809 810 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 811 const u32 *mmioaddr, u32 mmio_count, 812 int header_ver, enum intel_dmc_id dmc_id) 813 { 814 struct intel_display *display = dmc->display; 815 u32 start_range, end_range; 816 int i; 817 818 if (header_ver == 1) { 819 start_range = DMC_MMIO_START_RANGE; 820 end_range = DMC_MMIO_END_RANGE; 821 } else if (dmc_id == DMC_FW_MAIN) { 822 start_range = TGL_MAIN_MMIO_START; 823 end_range = TGL_MAIN_MMIO_END; 824 } else if (DISPLAY_VER(display) >= 13) { 825 start_range = ADLP_PIPE_MMIO_START; 826 end_range = ADLP_PIPE_MMIO_END; 827 } else if (DISPLAY_VER(display) >= 12) { 828 start_range = TGL_PIPE_MMIO_START(dmc_id); 829 end_range = TGL_PIPE_MMIO_END(dmc_id); 830 } else { 831 drm_warn(display->drm, "Unknown mmio range for sanity check"); 832 return false; 833 } 834 835 for (i = 0; i < mmio_count; i++) { 836 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 837 return false; 838 } 839 840 return true; 841 } 842 843 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 844 const struct intel_dmc_header_base *dmc_header, 845 size_t rem_size, enum intel_dmc_id dmc_id) 846 { 847 struct intel_display *display = dmc->display; 848 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 849 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 850 const u32 *mmioaddr, *mmiodata; 851 u32 mmio_count, mmio_count_max, start_mmioaddr; 852 u8 *payload; 853 854 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 855 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 856 857 /* 858 * Check if we can access common fields, we will checkc again below 859 * after we have read the version 860 */ 861 if (rem_size < sizeof(struct intel_dmc_header_base)) 862 goto error_truncated; 863 864 /* Cope with small differences between v1 and v3 */ 865 if (dmc_header->header_ver == 3) { 866 const struct intel_dmc_header_v3 *v3 = 867 (const struct intel_dmc_header_v3 *)dmc_header; 868 869 if (rem_size < sizeof(struct intel_dmc_header_v3)) 870 goto error_truncated; 871 872 mmioaddr = v3->mmioaddr; 873 mmiodata = v3->mmiodata; 874 mmio_count = v3->mmio_count; 875 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 876 /* header_len is in dwords */ 877 header_len_bytes = dmc_header->header_len * 4; 878 start_mmioaddr = v3->start_mmioaddr; 879 dmc_header_size = sizeof(*v3); 880 } else if (dmc_header->header_ver == 1) { 881 const struct intel_dmc_header_v1 *v1 = 882 (const struct intel_dmc_header_v1 *)dmc_header; 883 884 if (rem_size < sizeof(struct intel_dmc_header_v1)) 885 goto error_truncated; 886 887 mmioaddr = v1->mmioaddr; 888 mmiodata = v1->mmiodata; 889 mmio_count = v1->mmio_count; 890 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 891 header_len_bytes = dmc_header->header_len; 892 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 893 dmc_header_size = sizeof(*v1); 894 } else { 895 drm_err(display->drm, "Unknown DMC fw header version: %u\n", 896 dmc_header->header_ver); 897 return 0; 898 } 899 900 if (header_len_bytes != dmc_header_size) { 901 drm_err(display->drm, "DMC firmware has wrong dmc header length " 902 "(%u bytes)\n", header_len_bytes); 903 return 0; 904 } 905 906 /* Cache the dmc header info. */ 907 if (mmio_count > mmio_count_max) { 908 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 909 return 0; 910 } 911 912 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 913 dmc_header->header_ver, dmc_id)) { 914 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); 915 return 0; 916 } 917 918 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); 919 for (i = 0; i < mmio_count; i++) { 920 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 921 dmc_info->mmiodata[i] = mmiodata[i]; 922 923 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 924 i, mmioaddr[i], mmiodata[i], 925 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 926 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 927 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], 928 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 929 } 930 dmc_info->mmio_count = mmio_count; 931 dmc_info->start_mmioaddr = start_mmioaddr; 932 933 rem_size -= header_len_bytes; 934 935 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 936 payload_size = dmc_header->fw_size * 4; 937 if (rem_size < payload_size) 938 goto error_truncated; 939 940 if (payload_size > dmc->max_fw_size) { 941 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); 942 return 0; 943 } 944 dmc_info->dmc_fw_size = dmc_header->fw_size; 945 946 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 947 if (!dmc_info->payload) 948 return 0; 949 950 payload = (u8 *)(dmc_header) + header_len_bytes; 951 memcpy(dmc_info->payload, payload, payload_size); 952 953 return header_len_bytes + payload_size; 954 955 error_truncated: 956 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 957 return 0; 958 } 959 960 static u32 961 parse_dmc_fw_package(struct intel_dmc *dmc, 962 const struct intel_package_header *package_header, 963 const struct stepping_info *si, 964 size_t rem_size) 965 { 966 struct intel_display *display = dmc->display; 967 u32 package_size = sizeof(struct intel_package_header); 968 u32 num_entries, max_entries; 969 const struct intel_fw_info *fw_info; 970 971 if (rem_size < package_size) 972 goto error_truncated; 973 974 if (package_header->header_ver == 1) { 975 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 976 } else if (package_header->header_ver == 2) { 977 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 978 } else { 979 drm_err(display->drm, "DMC firmware has unknown header version %u\n", 980 package_header->header_ver); 981 return 0; 982 } 983 984 /* 985 * We should always have space for max_entries, 986 * even if not all are used 987 */ 988 package_size += max_entries * sizeof(struct intel_fw_info); 989 if (rem_size < package_size) 990 goto error_truncated; 991 992 if (package_header->header_len * 4 != package_size) { 993 drm_err(display->drm, "DMC firmware has wrong package header length " 994 "(%u bytes)\n", package_size); 995 return 0; 996 } 997 998 num_entries = package_header->num_entries; 999 if (WARN_ON(package_header->num_entries > max_entries)) 1000 num_entries = max_entries; 1001 1002 fw_info = (const struct intel_fw_info *) 1003 ((u8 *)package_header + sizeof(*package_header)); 1004 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 1005 package_header->header_ver); 1006 1007 /* dmc_offset is in dwords */ 1008 return package_size; 1009 1010 error_truncated: 1011 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1012 return 0; 1013 } 1014 1015 /* Return number of bytes parsed or 0 on error */ 1016 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 1017 struct intel_css_header *css_header, 1018 size_t rem_size) 1019 { 1020 struct intel_display *display = dmc->display; 1021 1022 if (rem_size < sizeof(struct intel_css_header)) { 1023 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1024 return 0; 1025 } 1026 1027 if (sizeof(struct intel_css_header) != 1028 (css_header->header_len * 4)) { 1029 drm_err(display->drm, "DMC firmware has wrong CSS header length " 1030 "(%u bytes)\n", 1031 (css_header->header_len * 4)); 1032 return 0; 1033 } 1034 1035 dmc->version = css_header->version; 1036 1037 return sizeof(struct intel_css_header); 1038 } 1039 1040 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 1041 { 1042 struct intel_display *display = dmc->display; 1043 struct intel_css_header *css_header; 1044 struct intel_package_header *package_header; 1045 struct intel_dmc_header_base *dmc_header; 1046 struct stepping_info display_info = { '*', '*'}; 1047 const struct stepping_info *si = intel_get_stepping_info(display, &display_info); 1048 enum intel_dmc_id dmc_id; 1049 u32 readcount = 0; 1050 u32 r, offset; 1051 1052 if (!fw) 1053 return -EINVAL; 1054 1055 /* Extract CSS Header information */ 1056 css_header = (struct intel_css_header *)fw->data; 1057 r = parse_dmc_fw_css(dmc, css_header, fw->size); 1058 if (!r) 1059 return -EINVAL; 1060 1061 readcount += r; 1062 1063 /* Extract Package Header information */ 1064 package_header = (struct intel_package_header *)&fw->data[readcount]; 1065 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 1066 if (!r) 1067 return -EINVAL; 1068 1069 readcount += r; 1070 1071 for_each_dmc_id(dmc_id) { 1072 if (!dmc->dmc_info[dmc_id].present) 1073 continue; 1074 1075 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 1076 if (offset > fw->size) { 1077 drm_err(display->drm, "Reading beyond the fw_size\n"); 1078 continue; 1079 } 1080 1081 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 1082 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 1083 } 1084 1085 if (!intel_dmc_has_payload(display)) { 1086 drm_err(display->drm, "DMC firmware main program not found\n"); 1087 return -ENOENT; 1088 } 1089 1090 return 0; 1091 } 1092 1093 static void intel_dmc_runtime_pm_get(struct intel_display *display) 1094 { 1095 drm_WARN_ON(display->drm, display->dmc.wakeref); 1096 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); 1097 } 1098 1099 static void intel_dmc_runtime_pm_put(struct intel_display *display) 1100 { 1101 intel_wakeref_t wakeref __maybe_unused = 1102 fetch_and_zero(&display->dmc.wakeref); 1103 1104 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 1105 } 1106 1107 static const char *dmc_fallback_path(struct intel_display *display) 1108 { 1109 if (display->platform.alderlake_p) 1110 return ADLP_DMC_FALLBACK_PATH; 1111 1112 return NULL; 1113 } 1114 1115 static void dmc_load_work_fn(struct work_struct *work) 1116 { 1117 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1118 struct intel_display *display = dmc->display; 1119 const struct firmware *fw = NULL; 1120 const char *fallback_path; 1121 int err; 1122 1123 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); 1124 1125 if (err == -ENOENT && !dmc_firmware_param(display)) { 1126 fallback_path = dmc_fallback_path(display); 1127 if (fallback_path) { 1128 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", 1129 dmc->fw_path, fallback_path); 1130 err = request_firmware(&fw, fallback_path, display->drm->dev); 1131 if (err == 0) 1132 dmc->fw_path = fallback_path; 1133 } 1134 } 1135 1136 if (err) { 1137 drm_notice(display->drm, 1138 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1139 dmc->fw_path, ERR_PTR(err)); 1140 drm_notice(display->drm, "DMC firmware homepage: %s", 1141 INTEL_DMC_FIRMWARE_URL); 1142 return; 1143 } 1144 1145 err = parse_dmc_fw(dmc, fw); 1146 if (err) { 1147 drm_notice(display->drm, 1148 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1149 dmc->fw_path, ERR_PTR(err)); 1150 goto out; 1151 } 1152 1153 intel_dmc_load_program(display); 1154 intel_dmc_runtime_pm_put(display); 1155 1156 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1157 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1158 DMC_VERSION_MINOR(dmc->version)); 1159 1160 out: 1161 release_firmware(fw); 1162 } 1163 1164 /** 1165 * intel_dmc_init() - initialize the firmware loading. 1166 * @display: display instance 1167 * 1168 * This function is called at the time of loading the display driver to read 1169 * firmware from a .bin file and copied into a internal memory. 1170 */ 1171 void intel_dmc_init(struct intel_display *display) 1172 { 1173 struct drm_i915_private *i915 = to_i915(display->drm); 1174 struct intel_dmc *dmc; 1175 1176 if (!HAS_DMC(display)) 1177 return; 1178 1179 /* 1180 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1181 * runtime-suspend. 1182 * 1183 * On error, we return with the rpm wakeref held to prevent runtime 1184 * suspend as runtime suspend *requires* a working DMC for whatever 1185 * reason. 1186 */ 1187 intel_dmc_runtime_pm_get(display); 1188 1189 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); 1190 if (!dmc) 1191 return; 1192 1193 dmc->display = display; 1194 1195 INIT_WORK(&dmc->work, dmc_load_work_fn); 1196 1197 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); 1198 1199 if (dmc_firmware_param_disabled(display)) { 1200 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); 1201 goto out; 1202 } 1203 1204 if (dmc_firmware_param(display)) 1205 dmc->fw_path = dmc_firmware_param(display); 1206 1207 if (!dmc->fw_path) { 1208 drm_dbg_kms(display->drm, 1209 "No known DMC firmware for platform, disabling runtime PM\n"); 1210 goto out; 1211 } 1212 1213 display->dmc.dmc = dmc; 1214 1215 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); 1216 queue_work(i915->unordered_wq, &dmc->work); 1217 1218 return; 1219 1220 out: 1221 kfree(dmc); 1222 } 1223 1224 /** 1225 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1226 * @display: display instance 1227 * 1228 * Prepare the DMC firmware before entering system suspend. This includes 1229 * flushing pending work items and releasing any resources acquired during 1230 * init. 1231 */ 1232 void intel_dmc_suspend(struct intel_display *display) 1233 { 1234 struct intel_dmc *dmc = display_to_dmc(display); 1235 1236 if (!HAS_DMC(display)) 1237 return; 1238 1239 if (dmc) 1240 flush_work(&dmc->work); 1241 1242 /* Drop the reference held in case DMC isn't loaded. */ 1243 if (!intel_dmc_has_payload(display)) 1244 intel_dmc_runtime_pm_put(display); 1245 } 1246 1247 /** 1248 * intel_dmc_resume() - init DMC firmware during system resume 1249 * @display: display instance 1250 * 1251 * Reinitialize the DMC firmware during system resume, reacquiring any 1252 * resources released in intel_dmc_suspend(). 1253 */ 1254 void intel_dmc_resume(struct intel_display *display) 1255 { 1256 if (!HAS_DMC(display)) 1257 return; 1258 1259 /* 1260 * Reacquire the reference to keep RPM disabled in case DMC isn't 1261 * loaded. 1262 */ 1263 if (!intel_dmc_has_payload(display)) 1264 intel_dmc_runtime_pm_get(display); 1265 } 1266 1267 /** 1268 * intel_dmc_fini() - unload the DMC firmware. 1269 * @display: display instance 1270 * 1271 * Firmmware unloading includes freeing the internal memory and reset the 1272 * firmware loading status. 1273 */ 1274 void intel_dmc_fini(struct intel_display *display) 1275 { 1276 struct intel_dmc *dmc = display_to_dmc(display); 1277 enum intel_dmc_id dmc_id; 1278 1279 if (!HAS_DMC(display)) 1280 return; 1281 1282 intel_dmc_suspend(display); 1283 drm_WARN_ON(display->drm, display->dmc.wakeref); 1284 1285 if (dmc) { 1286 for_each_dmc_id(dmc_id) 1287 kfree(dmc->dmc_info[dmc_id].payload); 1288 1289 kfree(dmc); 1290 display->dmc.dmc = NULL; 1291 } 1292 } 1293 1294 struct intel_dmc_snapshot { 1295 bool initialized; 1296 bool loaded; 1297 u32 version; 1298 }; 1299 1300 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) 1301 { 1302 struct intel_dmc *dmc = display_to_dmc(display); 1303 struct intel_dmc_snapshot *snapshot; 1304 1305 if (!HAS_DMC(display)) 1306 return NULL; 1307 1308 snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); 1309 if (!snapshot) 1310 return NULL; 1311 1312 snapshot->initialized = dmc; 1313 snapshot->loaded = intel_dmc_has_payload(display); 1314 if (dmc) 1315 snapshot->version = dmc->version; 1316 1317 return snapshot; 1318 } 1319 1320 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p) 1321 { 1322 if (!snapshot) 1323 return; 1324 1325 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized)); 1326 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded)); 1327 if (snapshot->initialized) 1328 drm_printf(p, "DMC fw version: %d.%d\n", 1329 DMC_VERSION_MAJOR(snapshot->version), 1330 DMC_VERSION_MINOR(snapshot->version)); 1331 } 1332 1333 void intel_dmc_update_dc6_allowed_count(struct intel_display *display, 1334 bool start_tracking) 1335 { 1336 struct intel_dmc *dmc = display_to_dmc(display); 1337 u32 dc5_cur_count; 1338 1339 if (DISPLAY_VER(dmc->display) < 14) 1340 return; 1341 1342 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT); 1343 1344 if (!start_tracking) 1345 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start; 1346 1347 dmc->dc6_allowed.dc5_start = dc5_cur_count; 1348 } 1349 1350 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count) 1351 { 1352 struct i915_power_domains *power_domains = &display->power.domains; 1353 struct intel_dmc *dmc = display_to_dmc(display); 1354 bool dc6_enabled; 1355 1356 if (DISPLAY_VER(display) < 14) 1357 return false; 1358 1359 mutex_lock(&power_domains->lock); 1360 dc6_enabled = intel_de_read(display, DC_STATE_EN) & 1361 DC_STATE_EN_UPTO_DC6; 1362 if (dc6_enabled) 1363 intel_dmc_update_dc6_allowed_count(display, false); 1364 1365 *count = dmc->dc6_allowed.count; 1366 mutex_unlock(&power_domains->lock); 1367 1368 return true; 1369 } 1370 1371 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1372 { 1373 struct intel_display *display = m->private; 1374 struct intel_dmc *dmc = display_to_dmc(display); 1375 struct ref_tracker *wakeref; 1376 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1377 u32 dc6_allowed_count; 1378 1379 if (!HAS_DMC(display)) 1380 return -ENODEV; 1381 1382 wakeref = intel_display_rpm_get(display); 1383 1384 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1385 seq_printf(m, "fw loaded: %s\n", 1386 str_yes_no(intel_dmc_has_payload(display))); 1387 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1388 seq_printf(m, "Pipe A fw needed: %s\n", 1389 str_yes_no(DISPLAY_VER(display) >= 12)); 1390 seq_printf(m, "Pipe A fw loaded: %s\n", 1391 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); 1392 seq_printf(m, "Pipe B fw needed: %s\n", 1393 str_yes_no(display->platform.alderlake_p || 1394 DISPLAY_VER(display) >= 14)); 1395 seq_printf(m, "Pipe B fw loaded: %s\n", 1396 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); 1397 1398 if (!intel_dmc_has_payload(display)) 1399 goto out; 1400 1401 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1402 DMC_VERSION_MINOR(dmc->version)); 1403 1404 if (DISPLAY_VER(display) >= 12) { 1405 i915_reg_t dc3co_reg; 1406 1407 if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { 1408 dc3co_reg = DG1_DMC_DEBUG3; 1409 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1410 } else { 1411 dc3co_reg = TGL_DMC_DEBUG3; 1412 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1413 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1414 } 1415 1416 seq_printf(m, "DC3CO count: %d\n", 1417 intel_de_read(display, dc3co_reg)); 1418 } else { 1419 dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT : 1420 SKL_DMC_DC3_DC5_COUNT; 1421 if (!display->platform.geminilake && !display->platform.broxton) 1422 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1423 } 1424 1425 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); 1426 1427 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) 1428 seq_printf(m, "DC5 -> DC6 allowed count: %d\n", 1429 dc6_allowed_count); 1430 else if (i915_mmio_reg_valid(dc6_reg)) 1431 seq_printf(m, "DC5 -> DC6 count: %d\n", 1432 intel_de_read(display, dc6_reg)); 1433 1434 seq_printf(m, "program base: 0x%08x\n", 1435 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1436 1437 out: 1438 seq_printf(m, "ssp base: 0x%08x\n", 1439 intel_de_read(display, DMC_SSP_BASE)); 1440 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); 1441 1442 intel_display_rpm_put(display, wakeref); 1443 1444 return 0; 1445 } 1446 1447 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1448 1449 void intel_dmc_debugfs_register(struct intel_display *display) 1450 { 1451 struct drm_minor *minor = display->drm->primary; 1452 1453 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 1454 display, &intel_dmc_debugfs_status_fops); 1455 } 1456 1457 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe) 1458 { 1459 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 1460 u32 tmp; 1461 1462 if (DISPLAY_VER(display) >= 20) { 1463 tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe)); 1464 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp); 1465 1466 if (tmp & PIPEDMC_ATS_FAULT) 1467 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n", 1468 crtc->base.base.id, crtc->base.name); 1469 if (tmp & PIPEDMC_GTT_FAULT) 1470 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n", 1471 crtc->base.base.id, crtc->base.name); 1472 if (tmp & PIPEDMC_ERROR) 1473 drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC error\n", 1474 crtc->base.base.id, crtc->base.name); 1475 } 1476 1477 tmp = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK; 1478 if (tmp) 1479 drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n", 1480 crtc->base.base.id, crtc->base.name, tmp); 1481 } 1482