1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 #include <drm/drm_vblank.h> 28 29 #include <drm/drm_file.h> 30 #include <drm/drm_print.h> 31 32 #include "intel_crtc.h" 33 #include "intel_de.h" 34 #include "intel_display_power_well.h" 35 #include "intel_display_regs.h" 36 #include "intel_display_rpm.h" 37 #include "intel_display_types.h" 38 #include "intel_display_utils.h" 39 #include "intel_dmc.h" 40 #include "intel_dmc_regs.h" 41 #include "intel_flipq.h" 42 43 /** 44 * DOC: DMC Firmware Support 45 * 46 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 47 * engine to save and restore the state of display engine when it enter into 48 * low-power state and comes back to normal. 49 */ 50 51 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 52 53 enum intel_dmc_id { 54 DMC_FW_MAIN = 0, 55 DMC_FW_PIPEA, 56 DMC_FW_PIPEB, 57 DMC_FW_PIPEC, 58 DMC_FW_PIPED, 59 DMC_FW_MAX 60 }; 61 62 struct intel_dmc { 63 struct intel_display *display; 64 struct work_struct work; 65 const char *fw_path; 66 u32 max_fw_size; /* bytes */ 67 u32 version; 68 struct { 69 u32 dc5_start; 70 u32 count; 71 } dc6_allowed; 72 struct dmc_fw_info { 73 u32 mmio_count; 74 intel_reg_t mmioaddr[20]; 75 u32 mmiodata[20]; 76 u32 dmc_offset; 77 u32 start_mmioaddr; 78 u32 dmc_fw_size; /*dwords */ 79 u32 *payload; 80 bool present; 81 } dmc_info[DMC_FW_MAX]; 82 }; 83 84 /* Note: This may be NULL. */ 85 static struct intel_dmc *display_to_dmc(struct intel_display *display) 86 { 87 return display->dmc.dmc; 88 } 89 90 static const char *dmc_firmware_param(struct intel_display *display) 91 { 92 const char *p = display->params.dmc_firmware_path; 93 94 return p && *p ? p : NULL; 95 } 96 97 static bool dmc_firmware_param_disabled(struct intel_display *display) 98 { 99 const char *p = dmc_firmware_param(display); 100 101 /* Magic path to indicate disabled */ 102 return p && !strcmp(p, "/dev/null"); 103 } 104 105 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 106 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 107 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 108 109 #define DMC_PATH(platform) \ 110 "i915/" __stringify(platform) "_dmc.bin" 111 112 /* 113 * New DMC additions should not use this. This is used solely to remain 114 * compatible with systems that have not yet updated DMC blobs to use 115 * unversioned file names. 116 */ 117 #define DMC_LEGACY_PATH(platform, major, minor) \ 118 "i915/" \ 119 __stringify(platform) "_dmc_ver" \ 120 __stringify(major) "_" \ 121 __stringify(minor) ".bin" 122 123 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 124 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 125 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 126 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 127 128 #define XE3P_LPD_DMC_PATH DMC_PATH(xe3p_lpd) 129 MODULE_FIRMWARE(XE3P_LPD_DMC_PATH); 130 131 #define XE3LPD_3002_DMC_PATH DMC_PATH(xe3lpd_3002) 132 MODULE_FIRMWARE(XE3LPD_3002_DMC_PATH); 133 134 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd) 135 MODULE_FIRMWARE(XE3LPD_DMC_PATH); 136 137 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 138 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 139 140 #define BMG_DMC_PATH DMC_PATH(bmg) 141 MODULE_FIRMWARE(BMG_DMC_PATH); 142 143 #define MTL_DMC_PATH DMC_PATH(mtl) 144 MODULE_FIRMWARE(MTL_DMC_PATH); 145 146 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 147 MODULE_FIRMWARE(DG2_DMC_PATH); 148 149 #define ADLP_DMC_PATH DMC_PATH(adlp) 150 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 151 MODULE_FIRMWARE(ADLP_DMC_PATH); 152 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 153 154 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 155 MODULE_FIRMWARE(ADLS_DMC_PATH); 156 157 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 158 MODULE_FIRMWARE(DG1_DMC_PATH); 159 160 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 161 MODULE_FIRMWARE(RKL_DMC_PATH); 162 163 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 164 MODULE_FIRMWARE(TGL_DMC_PATH); 165 166 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 167 #define ICL_DMC_MAX_FW_SIZE 0x6000 168 MODULE_FIRMWARE(ICL_DMC_PATH); 169 170 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 171 #define GLK_DMC_MAX_FW_SIZE 0x4000 172 MODULE_FIRMWARE(GLK_DMC_PATH); 173 174 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 175 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 176 MODULE_FIRMWARE(KBL_DMC_PATH); 177 178 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 179 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 180 MODULE_FIRMWARE(SKL_DMC_PATH); 181 182 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 183 #define BXT_DMC_MAX_FW_SIZE 0x3000 184 MODULE_FIRMWARE(BXT_DMC_PATH); 185 186 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) 187 { 188 const char *fw_path = NULL; 189 u32 max_fw_size = 0; 190 191 if (DISPLAY_VERx100(display) == 3500) { 192 fw_path = XE3P_LPD_DMC_PATH; 193 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 194 } else if (DISPLAY_VERx100(display) == 3002) { 195 fw_path = XE3LPD_3002_DMC_PATH; 196 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 197 } else if (DISPLAY_VERx100(display) == 3000) { 198 fw_path = XE3LPD_DMC_PATH; 199 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 200 } else if (DISPLAY_VERx100(display) == 2000) { 201 fw_path = XE2LPD_DMC_PATH; 202 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 203 } else if (DISPLAY_VERx100(display) == 1401) { 204 fw_path = BMG_DMC_PATH; 205 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 206 } else if (DISPLAY_VERx100(display) == 1400) { 207 fw_path = MTL_DMC_PATH; 208 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 209 } else if (display->platform.dg2) { 210 fw_path = DG2_DMC_PATH; 211 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 212 } else if (display->platform.alderlake_p) { 213 fw_path = ADLP_DMC_PATH; 214 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 215 } else if (display->platform.alderlake_s) { 216 fw_path = ADLS_DMC_PATH; 217 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 218 } else if (display->platform.dg1) { 219 fw_path = DG1_DMC_PATH; 220 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 221 } else if (display->platform.rocketlake) { 222 fw_path = RKL_DMC_PATH; 223 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 224 } else if (display->platform.tigerlake) { 225 fw_path = TGL_DMC_PATH; 226 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 227 } else if (DISPLAY_VER(display) == 11) { 228 fw_path = ICL_DMC_PATH; 229 max_fw_size = ICL_DMC_MAX_FW_SIZE; 230 } else if (display->platform.geminilake) { 231 fw_path = GLK_DMC_PATH; 232 max_fw_size = GLK_DMC_MAX_FW_SIZE; 233 } else if (display->platform.kabylake || 234 display->platform.coffeelake || 235 display->platform.cometlake) { 236 fw_path = KBL_DMC_PATH; 237 max_fw_size = KBL_DMC_MAX_FW_SIZE; 238 } else if (display->platform.skylake) { 239 fw_path = SKL_DMC_PATH; 240 max_fw_size = SKL_DMC_MAX_FW_SIZE; 241 } else if (display->platform.broxton) { 242 fw_path = BXT_DMC_PATH; 243 max_fw_size = BXT_DMC_MAX_FW_SIZE; 244 } 245 246 *size = max_fw_size; 247 248 return fw_path; 249 } 250 251 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 252 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 253 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 254 #define DMC_V1_MAX_MMIO_COUNT 8 255 #define DMC_V3_MAX_MMIO_COUNT 20 256 #define DMC_V1_MMIO_START_RANGE 0x80000 257 258 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 259 260 struct intel_css_header { 261 /* 0x09 for DMC */ 262 u32 module_type; 263 264 /* Includes the DMC specific header in dwords */ 265 u32 header_len; 266 267 /* always value would be 0x10000 */ 268 u32 header_ver; 269 270 /* Not used */ 271 u32 module_id; 272 273 /* Not used */ 274 u32 module_vendor; 275 276 /* in YYYYMMDD format */ 277 u32 date; 278 279 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 280 u32 size; 281 282 /* Not used */ 283 u32 key_size; 284 285 /* Not used */ 286 u32 modulus_size; 287 288 /* Not used */ 289 u32 exponent_size; 290 291 /* Not used */ 292 u32 reserved1[12]; 293 294 /* Major Minor */ 295 u32 version; 296 297 /* Not used */ 298 u32 reserved2[8]; 299 300 /* Not used */ 301 u32 kernel_header_info; 302 } __packed; 303 304 struct intel_fw_info { 305 u8 reserved1; 306 307 /* reserved on package_header version 1, must be 0 on version 2 */ 308 u8 dmc_id; 309 310 /* Stepping (A, B, C, ..., *). * is a wildcard */ 311 char stepping; 312 313 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 314 char substepping; 315 316 u32 offset; 317 u32 reserved2; 318 } __packed; 319 320 struct intel_package_header { 321 /* DMC container header length in dwords */ 322 u8 header_len; 323 324 /* 0x01, 0x02 */ 325 u8 header_ver; 326 327 u8 reserved[10]; 328 329 /* Number of valid entries in the FWInfo array below */ 330 u32 num_entries; 331 } __packed; 332 333 struct intel_dmc_header_base { 334 /* always value would be 0x40403E3E */ 335 u32 signature; 336 337 /* DMC binary header length */ 338 u8 header_len; 339 340 /* 0x01 */ 341 u8 header_ver; 342 343 /* Reserved */ 344 u16 dmcc_ver; 345 346 /* Major, Minor */ 347 u32 project; 348 349 /* Firmware program size (excluding header) in dwords */ 350 u32 fw_size; 351 352 /* Major Minor version */ 353 u32 fw_version; 354 } __packed; 355 356 struct intel_dmc_header_v1 { 357 struct intel_dmc_header_base base; 358 359 /* Number of valid MMIO cycles present. */ 360 u32 mmio_count; 361 362 /* MMIO address */ 363 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 364 365 /* MMIO data */ 366 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 367 368 /* FW filename */ 369 char dfile[32]; 370 371 u32 reserved1[2]; 372 } __packed; 373 374 struct intel_dmc_header_v3 { 375 struct intel_dmc_header_base base; 376 377 /* DMC RAM start MMIO address */ 378 u32 start_mmioaddr; 379 380 u32 reserved[9]; 381 382 /* FW filename */ 383 char dfile[32]; 384 385 /* Number of valid MMIO cycles present. */ 386 u32 mmio_count; 387 388 /* MMIO address */ 389 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 390 391 /* MMIO data */ 392 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 393 } __packed; 394 395 struct stepping_info { 396 char stepping; 397 char substepping; 398 }; 399 400 #define for_each_dmc_id(__dmc_id) \ 401 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 402 403 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 404 { 405 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 406 } 407 408 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) 409 { 410 struct intel_dmc *dmc = display_to_dmc(display); 411 412 return dmc && dmc->dmc_info[dmc_id].payload; 413 } 414 415 bool intel_dmc_has_payload(struct intel_display *display) 416 { 417 return has_dmc_id_fw(display, DMC_FW_MAIN); 418 } 419 420 static void initialize_stepping_info(struct intel_display *display, struct stepping_info *si) 421 { 422 const char *step_name = DISPLAY_RUNTIME_INFO(display)->step_name; 423 424 si->stepping = step_name[0] ?: '*'; 425 si->substepping = step_name[1] ?: '*'; 426 } 427 428 static void gen9_set_dc_state_debugmask(struct intel_display *display) 429 { 430 /* The below bit doesn't need to be cleared ever afterwards */ 431 intel_de_rmw(display, DC_STATE_DEBUG, 0, 432 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 433 intel_de_posting_read(display, DC_STATE_DEBUG); 434 } 435 436 static void disable_event_handler(struct intel_display *display, 437 intel_reg_t ctl_reg, intel_reg_t htp_reg) 438 { 439 intel_de_write(display, ctl_reg, 440 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 441 DMC_EVT_CTL_TYPE_EDGE_0_1) | 442 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 443 DMC_EVENT_FALSE)); 444 intel_de_write(display, htp_reg, 0); 445 } 446 447 static void disable_all_event_handlers(struct intel_display *display, 448 enum intel_dmc_id dmc_id) 449 { 450 int handler; 451 452 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 453 if (DISPLAY_VER(display) < 12) 454 return; 455 456 if (!has_dmc_id_fw(display, dmc_id)) 457 return; 458 459 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 460 disable_event_handler(display, 461 DMC_EVT_CTL(display, dmc_id, handler), 462 DMC_EVT_HTP(display, dmc_id, handler)); 463 } 464 465 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 466 { 467 enum pipe pipe; 468 469 /* 470 * Wa_16015201720:adl-p,dg2 471 * The WA requires clock gating to be disabled all the time 472 * for pipe A and B. 473 * For pipe C and D clock gating needs to be disabled only 474 * during initializing the firmware. 475 */ 476 if (enable) 477 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 478 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 479 0, PIPEDMC_GATING_DIS); 480 else 481 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 482 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 483 PIPEDMC_GATING_DIS, 0); 484 } 485 486 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) 487 { 488 /* 489 * Wa_16015201720 490 * The WA requires clock gating to be disabled all the time 491 * for pipe A and B. 492 */ 493 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, 494 MTL_PIPEDMC_GATING_DIS(PIPE_A) | 495 MTL_PIPEDMC_GATING_DIS(PIPE_B)); 496 } 497 498 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 499 { 500 if (display->platform.meteorlake && enable) 501 mtl_pipedmc_clock_gating_wa(display); 502 else if (DISPLAY_VER(display) == 13) 503 adlp_pipedmc_clock_gating_wa(display, enable); 504 } 505 506 static u32 pipedmc_interrupt_mask(struct intel_display *display) 507 { 508 if (DISPLAY_VER(display) >= 35) 509 return PIPEDMC_FLIPQ_PROG_DONE | 510 PIPEDMC_ERROR; 511 512 if (DISPLAY_VER(display) >= 30) 513 return PIPEDMC_FLIPQ_PROG_DONE | 514 PIPEDMC_GTT_FAULT | 515 PIPEDMC_ATS_FAULT | 516 PIPEDMC_ERROR; 517 518 /* 519 * FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B 520 * triggering it during the first DC state transition. Figure 521 * out what is going on... 522 */ 523 return PIPEDMC_FLIPQ_PROG_DONE | 524 PIPEDMC_GTT_FAULT | 525 PIPEDMC_ATS_FAULT; 526 } 527 528 static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl) 529 { 530 /* 531 * DMC_EVT_CTL_ENABLE cannot be cleared once set. Always 532 * configure it based on the original event definition to 533 * avoid mismatches in assert_dmc_loaded(). 534 */ 535 return (dmc_evt_ctl & DMC_EVT_CTL_ENABLE) | 536 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 537 DMC_EVT_CTL_TYPE_EDGE_0_1) | 538 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 539 DMC_EVENT_FALSE); 540 } 541 542 static bool is_dmc_evt_ctl_reg(struct intel_display *display, 543 enum intel_dmc_id dmc_id, intel_reg_t reg) 544 { 545 u32 offset = intel_reg_offset(reg); 546 u32 start = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); 547 u32 end = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 548 549 return offset >= start && offset < end; 550 } 551 552 static bool is_dmc_evt_htp_reg(struct intel_display *display, 553 enum intel_dmc_id dmc_id, intel_reg_t reg) 554 { 555 u32 offset = intel_reg_offset(reg); 556 u32 start = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); 557 u32 end = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 558 559 return offset >= start && offset < end; 560 } 561 562 static bool is_event_handler(struct intel_display *display, 563 enum intel_dmc_id dmc_id, 564 unsigned int event_id, 565 intel_reg_t reg, u32 data) 566 { 567 return is_dmc_evt_ctl_reg(display, dmc_id, reg) && 568 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id; 569 } 570 571 static bool fixup_dmc_evt(struct intel_display *display, 572 enum intel_dmc_id dmc_id, 573 intel_reg_t reg_ctl, u32 *data_ctl, 574 intel_reg_t reg_htp, u32 *data_htp) 575 { 576 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl)) 577 return false; 578 579 if (!is_dmc_evt_htp_reg(display, dmc_id, reg_htp)) 580 return false; 581 582 /* make sure reg_ctl and reg_htp are for the same event */ 583 if (intel_reg_offset(reg_ctl) - intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != 584 intel_reg_offset(reg_htp) - intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0))) 585 return false; 586 587 /* 588 * On ADL-S the HRR event handler is not restored after DC6. 589 * Clear it to zero from the beginning to avoid mismatches later. 590 */ 591 if (display->platform.alderlake_s && dmc_id == DMC_FW_MAIN && 592 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { 593 *data_ctl = 0; 594 *data_htp = 0; 595 return true; 596 } 597 598 /* 599 * TGL/ADL-S DMC firmware incorrectly uses the undelayed vblank 600 * event for the HRR handler, when it should be using the delayed 601 * vblank event instead. Fixed firmware was never released 602 * so the Windows driver just hacks around it by overriding 603 * the event ID. Do the same. 604 */ 605 if ((display->platform.tigerlake || display->platform.alderlake_s) && 606 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { 607 *data_ctl &= ~DMC_EVT_CTL_EVENT_ID_MASK; 608 *data_ctl |= REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 609 MAINDMC_EVENT_VBLANK_DELAYED_A); 610 return true; 611 } 612 613 return false; 614 } 615 616 static bool disable_dmc_evt(struct intel_display *display, 617 enum intel_dmc_id dmc_id, 618 intel_reg_t reg, u32 data) 619 { 620 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) 621 return false; 622 623 /* keep all pipe DMC events disabled by default */ 624 if (dmc_id != DMC_FW_MAIN) 625 return true; 626 627 /* also disable the flip queue event on the main DMC on TGL */ 628 if (display->platform.tigerlake && 629 is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data)) 630 return true; 631 632 /* also disable the HRR event on the main DMC on TGL/ADLS */ 633 if ((display->platform.tigerlake || display->platform.alderlake_s) && 634 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_DELAYED_A, reg, data)) 635 return true; 636 637 return false; 638 } 639 640 static u32 dmc_mmiodata(struct intel_display *display, 641 struct intel_dmc *dmc, 642 enum intel_dmc_id dmc_id, int i) 643 { 644 if (disable_dmc_evt(display, dmc_id, 645 dmc->dmc_info[dmc_id].mmioaddr[i], 646 dmc->dmc_info[dmc_id].mmiodata[i])) 647 return dmc_evt_ctl_disable(dmc->dmc_info[dmc_id].mmiodata[i]); 648 else 649 return dmc->dmc_info[dmc_id].mmiodata[i]; 650 } 651 652 static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id) 653 { 654 struct intel_dmc *dmc = display_to_dmc(display); 655 int i; 656 657 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 658 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], 659 dmc_mmiodata(display, dmc, dmc_id, i)); 660 } 661 } 662 663 static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id) 664 { 665 struct intel_dmc *dmc = display_to_dmc(display); 666 int i; 667 668 disable_all_event_handlers(display, dmc_id); 669 670 preempt_disable(); 671 672 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 673 intel_de_write_fw(display, 674 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 675 dmc->dmc_info[dmc_id].payload[i]); 676 } 677 678 preempt_enable(); 679 680 dmc_load_mmio(display, dmc_id); 681 } 682 683 static void assert_dmc_loaded(struct intel_display *display, 684 enum intel_dmc_id dmc_id) 685 { 686 struct intel_dmc *dmc = display_to_dmc(display); 687 u32 expected, found; 688 int i; 689 690 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 691 return; 692 693 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); 694 expected = dmc->dmc_info[dmc_id].payload[0]; 695 696 drm_WARN(display->drm, found != expected, 697 "DMC %d program storage start incorrect (expected 0x%x, current 0x%x)\n", 698 dmc_id, expected, found); 699 700 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 701 intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 702 703 found = intel_de_read(display, reg); 704 expected = dmc_mmiodata(display, dmc, dmc_id, i); 705 706 drm_WARN(display->drm, found != expected, 707 "DMC %d mmio[%d]/0x%x incorrect (expected 0x%x, current 0x%x)\n", 708 dmc_id, i, intel_reg_offset(reg), expected, found); 709 } 710 } 711 712 void assert_main_dmc_loaded(struct intel_display *display) 713 { 714 assert_dmc_loaded(display, DMC_FW_MAIN); 715 } 716 717 static bool need_pipedmc_load_program(struct intel_display *display) 718 { 719 /* On TGL/derivatives pipe DMC state is lost when PG1 is disabled */ 720 return DISPLAY_VER(display) == 12; 721 } 722 723 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe) 724 { 725 /* 726 * Xe3_LPD/Xe3p_LPD: 727 * - pipe A/B DMC doesn't need save/restore 728 * - pipe C/D DMC is in PG0, needs manual save/restore 729 */ 730 if (IS_DISPLAY_VER(display, 30, 35)) 731 return pipe >= PIPE_C; 732 733 /* 734 * FIXME LNL unclear, main DMC firmware has the pipe DMC A/B PG0 735 * save/restore, but so far unable to see the loss of pipe DMC state 736 * in action. Are we just failing to turn off PG0 due to some other 737 * SoC level stuff? 738 */ 739 if (DISPLAY_VER(display) == 20) 740 return false; 741 742 /* 743 * FIXME BMG untested, main DMC firmware has the 744 * pipe DMC A/B PG0 save/restore... 745 */ 746 if (display->platform.battlemage) 747 return false; 748 749 /* 750 * DG2: 751 * - Pipe DMCs presumably in PG0? 752 * - No DC6, and even DC9 doesn't seem to result 753 * in loss of DMC state for whatever reason 754 */ 755 if (display->platform.dg2) 756 return false; 757 758 /* 759 * ADL/MTL: 760 * - pipe A/B DMC is in PG0, saved/restored by the main DMC 761 * - pipe C/D DMC is in PG0, needs manual save/restore 762 */ 763 if (IS_DISPLAY_VER(display, 13, 14)) 764 return pipe >= PIPE_C; 765 766 return false; 767 } 768 769 static bool can_enable_pipedmc(const struct intel_crtc_state *crtc_state) 770 { 771 struct intel_display *display = to_intel_display(crtc_state); 772 773 /* 774 * On TGL/derivatives pipe DMC state is lost when PG1 is disabled. 775 * Do not even enable the pipe DMC when that can happen outside 776 * of driver control (PSR+DC5/6). 777 */ 778 if (DISPLAY_VER(display) == 12 && crtc_state->has_psr) 779 return false; 780 781 return true; 782 } 783 784 void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state) 785 { 786 struct intel_display *display = to_intel_display(crtc_state); 787 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 788 enum pipe pipe = crtc->pipe; 789 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 790 791 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 792 return; 793 794 if (!can_enable_pipedmc(crtc_state)) { 795 intel_dmc_disable_pipe(crtc_state); 796 return; 797 } 798 799 if (need_pipedmc_load_program(display)) 800 dmc_load_program(display, dmc_id); 801 else if (need_pipedmc_load_mmio(display, pipe)) 802 dmc_load_mmio(display, dmc_id); 803 804 assert_dmc_loaded(display, dmc_id); 805 806 if (DISPLAY_VER(display) >= 20) { 807 intel_flipq_reset(display, pipe); 808 809 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 810 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display)); 811 } 812 813 if (DISPLAY_VER(display) >= 14) 814 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 815 else 816 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 817 } 818 819 void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state) 820 { 821 struct intel_display *display = to_intel_display(crtc_state); 822 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 823 enum pipe pipe = crtc->pipe; 824 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 825 826 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 827 return; 828 829 if (DISPLAY_VER(display) >= 14) 830 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 831 else 832 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 833 834 if (DISPLAY_VER(display) >= 20) { 835 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0); 836 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 837 838 intel_flipq_reset(display, pipe); 839 } 840 } 841 842 static void dmc_configure_event(struct intel_display *display, 843 enum intel_dmc_id dmc_id, 844 unsigned int event_id, 845 bool enable) 846 { 847 struct intel_dmc *dmc = display_to_dmc(display); 848 int num_handlers = 0; 849 int i; 850 851 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 852 intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 853 u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; 854 855 if (!is_event_handler(display, dmc_id, event_id, reg, data)) 856 continue; 857 858 intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable(data)); 859 num_handlers++; 860 } 861 862 drm_WARN_ONCE(display->drm, num_handlers != 1, 863 "DMC %d has %d handlers for event 0x%x\n", 864 dmc_id, num_handlers, event_id); 865 } 866 867 void intel_dmc_configure_dc_balance_event(struct intel_display *display, 868 enum pipe pipe, bool enable) 869 { 870 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 871 872 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable); 873 } 874 875 /** 876 * intel_dmc_block_pkgc() - block PKG C-state 877 * @display: display instance 878 * @pipe: pipe which register use to block 879 * @block: block/unblock 880 * 881 * This interface is target for Wa_16025596647 usage. I.e. to set/clear 882 * PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register. 883 */ 884 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, 885 bool block) 886 { 887 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), 888 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, block ? 889 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0); 890 } 891 892 /** 893 * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG 894 * C-state exit 895 * @display: display instance 896 * @pipe: pipe which register use to block 897 * @enable: enable/disable 898 * 899 * This interface is target for Wa_16025596647 usage. I.e. start the package C 900 * exit at the start of the undelayed vblank 901 */ 902 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, 903 enum pipe pipe, bool enable) 904 { 905 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 906 907 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable); 908 } 909 910 /** 911 * intel_dmc_load_program() - write the firmware from memory to register. 912 * @display: display instance 913 * 914 * DMC firmware is read from a .bin file and kept in internal memory one time. 915 * Everytime display comes back from low power state this function is called to 916 * copy the firmware from internal memory to registers. 917 */ 918 void intel_dmc_load_program(struct intel_display *display) 919 { 920 struct i915_power_domains *power_domains = &display->power.domains; 921 enum intel_dmc_id dmc_id; 922 923 if (!intel_dmc_has_payload(display)) 924 return; 925 926 assert_display_rpm_held(display); 927 928 pipedmc_clock_gating_wa(display, true); 929 930 for_each_dmc_id(dmc_id) { 931 dmc_load_program(display, dmc_id); 932 assert_dmc_loaded(display, dmc_id); 933 } 934 935 if (DISPLAY_VER(display) >= 20) 936 intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL, 937 PIPE_D_DMC_W2_PTS_CONFIG_SELECT(PIPE_D) | 938 PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) | 939 PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) | 940 PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A)); 941 942 power_domains->dc_state = 0; 943 944 gen9_set_dc_state_debugmask(display); 945 946 xe3lpd_enable_dc_count(display); 947 948 pipedmc_clock_gating_wa(display, false); 949 } 950 951 /** 952 * intel_dmc_disable_program() - disable the firmware 953 * @display: display instance 954 * 955 * Disable all event handlers in the firmware, making sure the firmware is 956 * inactive after the display is uninitialized. 957 */ 958 void intel_dmc_disable_program(struct intel_display *display) 959 { 960 enum intel_dmc_id dmc_id; 961 962 if (!intel_dmc_has_payload(display)) 963 return; 964 965 pipedmc_clock_gating_wa(display, true); 966 967 for_each_dmc_id(dmc_id) 968 disable_all_event_handlers(display, dmc_id); 969 970 pipedmc_clock_gating_wa(display, false); 971 } 972 973 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 974 const struct stepping_info *si) 975 { 976 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 977 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 978 /* 979 * If we don't find a more specific one from above two checks, we 980 * then check for the generic one to be sure to work even with 981 * "broken firmware" 982 */ 983 (si->stepping == '*' && si->substepping == fw_info->substepping) || 984 (fw_info->stepping == '*' && fw_info->substepping == '*')) 985 return true; 986 987 return false; 988 } 989 990 /* 991 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 992 * already sanitized. 993 */ 994 static void dmc_set_fw_offset(struct intel_dmc *dmc, 995 const struct intel_fw_info *fw_info, 996 unsigned int num_entries, 997 const struct stepping_info *si, 998 u8 package_ver) 999 { 1000 struct intel_display *display = dmc->display; 1001 enum intel_dmc_id dmc_id; 1002 unsigned int i; 1003 1004 for (i = 0; i < num_entries; i++) { 1005 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 1006 1007 if (!is_valid_dmc_id(dmc_id)) { 1008 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); 1009 continue; 1010 } 1011 1012 /* More specific versions come first, so we don't even have to 1013 * check for the stepping since we already found a previous FW 1014 * for this id. 1015 */ 1016 if (dmc->dmc_info[dmc_id].present) 1017 continue; 1018 1019 if (fw_info_matches_stepping(&fw_info[i], si)) { 1020 dmc->dmc_info[dmc_id].present = true; 1021 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 1022 } 1023 } 1024 } 1025 1026 /* 1027 * Check if the load address is within the valid range for the given DMC ID. 1028 */ 1029 static bool dmc_load_addr_sanity_check(struct intel_dmc *dmc, 1030 u32 start_addr, u32 payload_size, 1031 int header_ver, enum intel_dmc_id dmc_id) 1032 { 1033 u32 start_range, end_range, end_addr; 1034 1035 if (header_ver != 3) 1036 return true; 1037 1038 switch (dmc_id) { 1039 case DMC_FW_MAIN: 1040 start_range = DMC_MAIN_PROGRAM_BASE_START; 1041 end_range = DMC_MAIN_PROGRAM_BASE_END; 1042 break; 1043 case DMC_FW_PIPEA: 1044 start_range = DMC_PIPEA_PROGRAM_BASE_START; 1045 end_range = DMC_PIPEA_PROGRAM_BASE_END; 1046 break; 1047 case DMC_FW_PIPEB: 1048 start_range = DMC_PIPEB_PROGRAM_BASE_START; 1049 end_range = DMC_PIPEB_PROGRAM_BASE_END; 1050 break; 1051 case DMC_FW_PIPEC: 1052 start_range = DMC_PIPEC_PROGRAM_BASE_START; 1053 end_range = DMC_PIPEC_PROGRAM_BASE_END; 1054 break; 1055 case DMC_FW_PIPED: 1056 start_range = DMC_PIPED_PROGRAM_BASE_START; 1057 end_range = DMC_PIPED_PROGRAM_BASE_END; 1058 break; 1059 default: 1060 MISSING_CASE(dmc_id); 1061 return false; 1062 } 1063 1064 if (payload_size == 0) 1065 end_addr = start_addr; 1066 else if (check_add_overflow(start_addr, payload_size - 1, &end_addr)) 1067 return false; 1068 1069 if (start_addr < start_range || end_addr > end_range) 1070 return false; 1071 1072 return true; 1073 } 1074 1075 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 1076 const u32 *mmioaddr, u32 mmio_count, 1077 int header_ver, enum intel_dmc_id dmc_id) 1078 { 1079 struct intel_display *display = dmc->display; 1080 u32 start_range, end_range; 1081 int i; 1082 1083 if (header_ver == 1) { 1084 start_range = DMC_MMIO_START_RANGE; 1085 end_range = DMC_MMIO_END_RANGE; 1086 } else if (dmc_id == DMC_FW_MAIN) { 1087 start_range = TGL_MAIN_MMIO_START; 1088 end_range = TGL_MAIN_MMIO_END; 1089 } else if (DISPLAY_VER(display) >= 13) { 1090 start_range = ADLP_PIPE_MMIO_START; 1091 end_range = ADLP_PIPE_MMIO_END; 1092 } else if (DISPLAY_VER(display) >= 12) { 1093 start_range = TGL_PIPE_MMIO_START(dmc_id); 1094 end_range = TGL_PIPE_MMIO_END(dmc_id); 1095 } else { 1096 drm_warn(display->drm, "Unknown mmio range for sanity check"); 1097 return false; 1098 } 1099 1100 for (i = 0; i < mmio_count; i++) { 1101 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 1102 return false; 1103 } 1104 1105 return true; 1106 } 1107 1108 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 1109 const struct intel_dmc_header_base *dmc_header, 1110 size_t rem_size, enum intel_dmc_id dmc_id) 1111 { 1112 struct intel_display *display = dmc->display; 1113 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 1114 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 1115 const u32 *mmioaddr, *mmiodata; 1116 u32 mmio_count, mmio_count_max, start_mmioaddr; 1117 u8 *payload; 1118 1119 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 1120 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 1121 1122 /* 1123 * Check if we can access common fields, we will checkc again below 1124 * after we have read the version 1125 */ 1126 if (rem_size < sizeof(struct intel_dmc_header_base)) 1127 goto error_truncated; 1128 1129 /* Cope with small differences between v1 and v3 */ 1130 if (dmc_header->header_ver == 3) { 1131 const struct intel_dmc_header_v3 *v3 = 1132 (const struct intel_dmc_header_v3 *)dmc_header; 1133 1134 if (rem_size < sizeof(struct intel_dmc_header_v3)) 1135 goto error_truncated; 1136 1137 mmioaddr = v3->mmioaddr; 1138 mmiodata = v3->mmiodata; 1139 mmio_count = v3->mmio_count; 1140 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 1141 /* header_len is in dwords */ 1142 header_len_bytes = dmc_header->header_len * 4; 1143 start_mmioaddr = v3->start_mmioaddr; 1144 dmc_header_size = sizeof(*v3); 1145 } else if (dmc_header->header_ver == 1) { 1146 const struct intel_dmc_header_v1 *v1 = 1147 (const struct intel_dmc_header_v1 *)dmc_header; 1148 1149 if (rem_size < sizeof(struct intel_dmc_header_v1)) 1150 goto error_truncated; 1151 1152 mmioaddr = v1->mmioaddr; 1153 mmiodata = v1->mmiodata; 1154 mmio_count = v1->mmio_count; 1155 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 1156 header_len_bytes = dmc_header->header_len; 1157 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 1158 dmc_header_size = sizeof(*v1); 1159 } else { 1160 drm_err(display->drm, "Unknown DMC fw header version: %u\n", 1161 dmc_header->header_ver); 1162 return 0; 1163 } 1164 1165 if (header_len_bytes != dmc_header_size) { 1166 drm_err(display->drm, "DMC firmware has wrong dmc header length " 1167 "(%u bytes)\n", header_len_bytes); 1168 return 0; 1169 } 1170 1171 /* Cache the dmc header info. */ 1172 if (!mmio_count || mmio_count > mmio_count_max) { 1173 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 1174 return 0; 1175 } 1176 1177 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 1178 dmc_header->header_ver, dmc_id)) { 1179 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); 1180 return 0; 1181 } 1182 1183 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); 1184 for (i = 0; i < mmio_count; i++) { 1185 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 1186 dmc_info->mmiodata[i] = mmiodata[i]; 1187 } 1188 1189 for (i = 0; i < mmio_count - 1; i++) { 1190 u32 orig_mmiodata[2] = { 1191 dmc_info->mmiodata[i], 1192 dmc_info->mmiodata[i+1], 1193 }; 1194 1195 if (!fixup_dmc_evt(display, dmc_id, 1196 dmc_info->mmioaddr[i], &dmc_info->mmiodata[i], 1197 dmc_info->mmioaddr[i+1], &dmc_info->mmiodata[i+1])) 1198 continue; 1199 1200 drm_dbg_kms(display->drm, 1201 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_CTL)\n", 1202 i, intel_reg_offset(dmc_info->mmioaddr[i]), 1203 orig_mmiodata[0], dmc_info->mmiodata[i]); 1204 drm_dbg_kms(display->drm, 1205 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_HTP)\n", 1206 i+1, intel_reg_offset(dmc_info->mmioaddr[i+1]), 1207 orig_mmiodata[1], dmc_info->mmiodata[i+1]); 1208 } 1209 1210 for (i = 0; i < mmio_count; i++) { 1211 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 1212 i, intel_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i], 1213 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 1214 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 1215 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], 1216 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 1217 } 1218 1219 rem_size -= header_len_bytes; 1220 1221 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 1222 if (check_mul_overflow(dmc_header->fw_size, 4u, &payload_size)) { 1223 drm_err(display->drm, "DMC fw_size too large (%u dwords)\n", 1224 dmc_header->fw_size); 1225 return 0; 1226 } 1227 1228 if (!payload_size) { 1229 drm_err(display->drm, "DMC firmware has empty payload\n"); 1230 return 0; 1231 } 1232 1233 if (rem_size < payload_size) 1234 goto error_truncated; 1235 1236 if (payload_size > dmc->max_fw_size) { 1237 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); 1238 return 0; 1239 } 1240 1241 if (!dmc_load_addr_sanity_check(dmc, start_mmioaddr, payload_size, 1242 dmc_header->header_ver, dmc_id)) { 1243 drm_err(display->drm, "DMC %d: firmware has wrong load address\n", dmc_id); 1244 return 0; 1245 } 1246 1247 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 1248 if (!dmc_info->payload) 1249 return 0; 1250 1251 dmc_info->mmio_count = mmio_count; 1252 dmc_info->start_mmioaddr = start_mmioaddr; 1253 dmc_info->dmc_fw_size = dmc_header->fw_size; 1254 1255 payload = (u8 *)(dmc_header) + header_len_bytes; 1256 memcpy(dmc_info->payload, payload, payload_size); 1257 1258 return header_len_bytes + payload_size; 1259 1260 error_truncated: 1261 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1262 return 0; 1263 } 1264 1265 static u32 1266 parse_dmc_fw_package(struct intel_dmc *dmc, 1267 const struct intel_package_header *package_header, 1268 const struct stepping_info *si, 1269 size_t rem_size) 1270 { 1271 struct intel_display *display = dmc->display; 1272 u32 package_size = sizeof(struct intel_package_header); 1273 u32 num_entries, max_entries; 1274 const struct intel_fw_info *fw_info; 1275 1276 if (rem_size < package_size) 1277 goto error_truncated; 1278 1279 if (package_header->header_ver == 1) { 1280 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 1281 } else if (package_header->header_ver == 2) { 1282 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 1283 } else { 1284 drm_err(display->drm, "DMC firmware has unknown header version %u\n", 1285 package_header->header_ver); 1286 return 0; 1287 } 1288 1289 /* 1290 * We should always have space for max_entries, 1291 * even if not all are used 1292 */ 1293 package_size += max_entries * sizeof(struct intel_fw_info); 1294 if (rem_size < package_size) 1295 goto error_truncated; 1296 1297 if (package_header->header_len * 4 != package_size) { 1298 drm_err(display->drm, "DMC firmware has wrong package header length " 1299 "(%u bytes)\n", package_size); 1300 return 0; 1301 } 1302 1303 num_entries = package_header->num_entries; 1304 if (WARN_ON(num_entries > max_entries)) 1305 num_entries = max_entries; 1306 1307 fw_info = (const struct intel_fw_info *) 1308 ((u8 *)package_header + sizeof(*package_header)); 1309 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 1310 package_header->header_ver); 1311 1312 /* dmc_offset is in dwords */ 1313 return package_size; 1314 1315 error_truncated: 1316 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1317 return 0; 1318 } 1319 1320 /* Return number of bytes parsed or 0 on error */ 1321 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 1322 struct intel_css_header *css_header, 1323 size_t rem_size) 1324 { 1325 struct intel_display *display = dmc->display; 1326 1327 if (rem_size < sizeof(struct intel_css_header)) { 1328 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1329 return 0; 1330 } 1331 1332 if (sizeof(struct intel_css_header) != 1333 (css_header->header_len * 4)) { 1334 drm_err(display->drm, "DMC firmware has wrong CSS header length " 1335 "(%u bytes)\n", 1336 (css_header->header_len * 4)); 1337 return 0; 1338 } 1339 1340 dmc->version = css_header->version; 1341 1342 return sizeof(struct intel_css_header); 1343 } 1344 1345 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 1346 { 1347 struct intel_display *display = dmc->display; 1348 struct intel_css_header *css_header; 1349 struct intel_package_header *package_header; 1350 struct intel_dmc_header_base *dmc_header; 1351 struct stepping_info si = {}; 1352 enum intel_dmc_id dmc_id; 1353 u32 readcount = 0; 1354 u32 r, offset; 1355 1356 if (!fw) 1357 return -EINVAL; 1358 1359 initialize_stepping_info(display, &si); 1360 1361 /* Extract CSS Header information */ 1362 css_header = (struct intel_css_header *)fw->data; 1363 r = parse_dmc_fw_css(dmc, css_header, fw->size); 1364 if (!r) 1365 return -EINVAL; 1366 1367 readcount += r; 1368 1369 /* Extract Package Header information */ 1370 package_header = (struct intel_package_header *)&fw->data[readcount]; 1371 r = parse_dmc_fw_package(dmc, package_header, &si, fw->size - readcount); 1372 if (!r) 1373 return -EINVAL; 1374 1375 readcount += r; 1376 1377 for_each_dmc_id(dmc_id) { 1378 if (!dmc->dmc_info[dmc_id].present) 1379 continue; 1380 1381 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 1382 if (offset > fw->size) { 1383 drm_err(display->drm, "Reading beyond the fw_size\n"); 1384 continue; 1385 } 1386 1387 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 1388 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 1389 } 1390 1391 if (!intel_dmc_has_payload(display)) { 1392 drm_err(display->drm, "DMC firmware main program not found\n"); 1393 return -ENOENT; 1394 } 1395 1396 return 0; 1397 } 1398 1399 static void intel_dmc_runtime_pm_get(struct intel_display *display) 1400 { 1401 drm_WARN_ON(display->drm, display->dmc.wakeref); 1402 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); 1403 } 1404 1405 static void intel_dmc_runtime_pm_put(struct intel_display *display) 1406 { 1407 struct ref_tracker *wakeref __maybe_unused = 1408 fetch_and_zero(&display->dmc.wakeref); 1409 1410 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 1411 } 1412 1413 static const char *dmc_fallback_path(struct intel_display *display) 1414 { 1415 if (display->platform.alderlake_p) 1416 return ADLP_DMC_FALLBACK_PATH; 1417 1418 return NULL; 1419 } 1420 1421 static void dmc_load_work_fn(struct work_struct *work) 1422 { 1423 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1424 struct intel_display *display = dmc->display; 1425 const struct firmware *fw = NULL; 1426 const char *fallback_path; 1427 int err; 1428 1429 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); 1430 1431 if (err == -ENOENT && !dmc_firmware_param(display)) { 1432 fallback_path = dmc_fallback_path(display); 1433 if (fallback_path) { 1434 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", 1435 dmc->fw_path, fallback_path); 1436 err = request_firmware(&fw, fallback_path, display->drm->dev); 1437 if (err == 0) 1438 dmc->fw_path = fallback_path; 1439 } 1440 } 1441 1442 if (err) { 1443 drm_notice(display->drm, 1444 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1445 dmc->fw_path, ERR_PTR(err)); 1446 drm_notice(display->drm, "DMC firmware homepage: %s", 1447 INTEL_DMC_FIRMWARE_URL); 1448 return; 1449 } 1450 1451 err = parse_dmc_fw(dmc, fw); 1452 if (err) { 1453 drm_notice(display->drm, 1454 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1455 dmc->fw_path, ERR_PTR(err)); 1456 goto out; 1457 } 1458 1459 intel_dmc_load_program(display); 1460 intel_dmc_runtime_pm_put(display); 1461 1462 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1463 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1464 DMC_VERSION_MINOR(dmc->version)); 1465 1466 out: 1467 release_firmware(fw); 1468 } 1469 1470 /** 1471 * intel_dmc_init() - initialize the firmware loading. 1472 * @display: display instance 1473 * 1474 * This function is called at the time of loading the display driver to read 1475 * firmware from a .bin file and copied into a internal memory. 1476 */ 1477 void intel_dmc_init(struct intel_display *display) 1478 { 1479 struct intel_dmc *dmc; 1480 1481 if (!HAS_DMC(display)) 1482 return; 1483 1484 /* 1485 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1486 * runtime-suspend. 1487 * 1488 * On error, we return with the rpm wakeref held to prevent runtime 1489 * suspend as runtime suspend *requires* a working DMC for whatever 1490 * reason. 1491 */ 1492 intel_dmc_runtime_pm_get(display); 1493 1494 dmc = kzalloc_obj(*dmc); 1495 if (!dmc) 1496 return; 1497 1498 dmc->display = display; 1499 1500 INIT_WORK(&dmc->work, dmc_load_work_fn); 1501 1502 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); 1503 1504 if (dmc_firmware_param_disabled(display)) { 1505 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); 1506 goto out; 1507 } 1508 1509 if (dmc_firmware_param(display)) 1510 dmc->fw_path = dmc_firmware_param(display); 1511 1512 if (!dmc->fw_path) { 1513 drm_dbg_kms(display->drm, 1514 "No known DMC firmware for platform, disabling runtime PM\n"); 1515 goto out; 1516 } 1517 1518 display->dmc.dmc = dmc; 1519 1520 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); 1521 queue_work(display->wq.unordered, &dmc->work); 1522 1523 return; 1524 1525 out: 1526 kfree(dmc); 1527 } 1528 1529 /** 1530 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1531 * @display: display instance 1532 * 1533 * Prepare the DMC firmware before entering system suspend. This includes 1534 * flushing pending work items and releasing any resources acquired during 1535 * init. 1536 */ 1537 void intel_dmc_suspend(struct intel_display *display) 1538 { 1539 struct intel_dmc *dmc = display_to_dmc(display); 1540 1541 if (!HAS_DMC(display)) 1542 return; 1543 1544 if (dmc) 1545 flush_work(&dmc->work); 1546 1547 /* Drop the reference held in case DMC isn't loaded. */ 1548 if (!intel_dmc_has_payload(display)) 1549 intel_dmc_runtime_pm_put(display); 1550 } 1551 1552 void intel_dmc_wait_fw_load(struct intel_display *display) 1553 { 1554 struct intel_dmc *dmc = display_to_dmc(display); 1555 1556 if (!HAS_DMC(display)) 1557 return; 1558 1559 if (dmc) 1560 flush_work(&dmc->work); 1561 } 1562 1563 /** 1564 * intel_dmc_resume() - init DMC firmware during system resume 1565 * @display: display instance 1566 * 1567 * Reinitialize the DMC firmware during system resume, reacquiring any 1568 * resources released in intel_dmc_suspend(). 1569 */ 1570 void intel_dmc_resume(struct intel_display *display) 1571 { 1572 if (!HAS_DMC(display)) 1573 return; 1574 1575 /* 1576 * Reacquire the reference to keep RPM disabled in case DMC isn't 1577 * loaded. 1578 */ 1579 if (!intel_dmc_has_payload(display)) 1580 intel_dmc_runtime_pm_get(display); 1581 } 1582 1583 /** 1584 * intel_dmc_fini() - unload the DMC firmware. 1585 * @display: display instance 1586 * 1587 * Firmmware unloading includes freeing the internal memory and reset the 1588 * firmware loading status. 1589 */ 1590 void intel_dmc_fini(struct intel_display *display) 1591 { 1592 struct intel_dmc *dmc = display_to_dmc(display); 1593 enum intel_dmc_id dmc_id; 1594 1595 if (!HAS_DMC(display)) 1596 return; 1597 1598 intel_dmc_suspend(display); 1599 drm_WARN_ON(display->drm, display->dmc.wakeref); 1600 1601 if (dmc) { 1602 for_each_dmc_id(dmc_id) 1603 kfree(dmc->dmc_info[dmc_id].payload); 1604 1605 kfree(dmc); 1606 display->dmc.dmc = NULL; 1607 } 1608 } 1609 1610 struct intel_dmc_snapshot { 1611 bool initialized; 1612 bool loaded; 1613 u32 version; 1614 }; 1615 1616 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) 1617 { 1618 struct intel_dmc *dmc = display_to_dmc(display); 1619 struct intel_dmc_snapshot *snapshot; 1620 1621 if (!HAS_DMC(display)) 1622 return NULL; 1623 1624 snapshot = kzalloc_obj(*snapshot, GFP_ATOMIC); 1625 if (!snapshot) 1626 return NULL; 1627 1628 snapshot->initialized = dmc; 1629 snapshot->loaded = intel_dmc_has_payload(display); 1630 if (dmc) 1631 snapshot->version = dmc->version; 1632 1633 return snapshot; 1634 } 1635 1636 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p) 1637 { 1638 if (!snapshot) 1639 return; 1640 1641 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized)); 1642 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded)); 1643 if (snapshot->initialized) 1644 drm_printf(p, "DMC fw version: %d.%d\n", 1645 DMC_VERSION_MAJOR(snapshot->version), 1646 DMC_VERSION_MINOR(snapshot->version)); 1647 } 1648 1649 void intel_dmc_update_dc6_allowed_count(struct intel_display *display, 1650 bool start_tracking) 1651 { 1652 struct intel_dmc *dmc = display_to_dmc(display); 1653 u32 dc5_cur_count; 1654 1655 if (DISPLAY_VER(display) < 14) 1656 return; 1657 1658 dc5_cur_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT); 1659 1660 if (!start_tracking) 1661 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start; 1662 1663 dmc->dc6_allowed.dc5_start = dc5_cur_count; 1664 } 1665 1666 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count) 1667 { 1668 struct i915_power_domains *power_domains = &display->power.domains; 1669 struct intel_dmc *dmc = display_to_dmc(display); 1670 bool dc6_enabled; 1671 1672 if (DISPLAY_VER(display) < 14) 1673 return false; 1674 1675 mutex_lock(&power_domains->lock); 1676 dc6_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6; 1677 if (dc6_enabled) 1678 intel_dmc_update_dc6_allowed_count(display, false); 1679 1680 *count = dmc->dc6_allowed.count; 1681 mutex_unlock(&power_domains->lock); 1682 1683 return true; 1684 } 1685 1686 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1687 { 1688 struct intel_display *display = m->private; 1689 struct intel_dmc *dmc = display_to_dmc(display); 1690 struct ref_tracker *wakeref; 1691 intel_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1692 u32 dc6_allowed_count; 1693 1694 if (!HAS_DMC(display)) 1695 return -ENODEV; 1696 1697 wakeref = intel_display_rpm_get(display); 1698 1699 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1700 seq_printf(m, "fw loaded: %s\n", 1701 str_yes_no(intel_dmc_has_payload(display))); 1702 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1703 seq_printf(m, "Pipe A fw needed: %s\n", 1704 str_yes_no(DISPLAY_VER(display) >= 12)); 1705 seq_printf(m, "Pipe A fw loaded: %s\n", 1706 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); 1707 seq_printf(m, "Pipe B fw needed: %s\n", 1708 str_yes_no(display->platform.alderlake_p || 1709 DISPLAY_VER(display) >= 14)); 1710 seq_printf(m, "Pipe B fw loaded: %s\n", 1711 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); 1712 1713 if (!intel_dmc_has_payload(display)) 1714 goto out; 1715 1716 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1717 DMC_VERSION_MINOR(dmc->version)); 1718 1719 if (DISPLAY_VER(display) >= 12) { 1720 if (DISPLAY_VER(display) >= 35) { 1721 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1722 seq_printf(m, "DC3CO count: %d\n", 1723 intel_de_read(display, XE3P_DMC_DC3CO_COUNT)); 1724 1725 seq_printf(m, "DC3CO residency: %d\n", 1726 intel_de_read(display, DC_STATE_DC3CO_RESIDENCY)); 1727 } else if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { 1728 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1729 } else { 1730 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1731 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1732 } 1733 1734 } else { 1735 dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT : 1736 SKL_DMC_DC3_DC5_COUNT; 1737 if (!display->platform.geminilake && !display->platform.broxton) 1738 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1739 } 1740 1741 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); 1742 1743 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) 1744 seq_printf(m, "DC5 -> DC6 allowed count: %d\n", 1745 dc6_allowed_count); 1746 else if (intel_reg_valid(dc6_reg)) 1747 seq_printf(m, "DC5 -> DC6 count: %d\n", 1748 intel_de_read(display, dc6_reg)); 1749 1750 seq_printf(m, "program base: 0x%08x\n", 1751 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1752 1753 out: 1754 seq_printf(m, "ssp base: 0x%08x\n", 1755 intel_de_read(display, DMC_SSP_BASE)); 1756 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); 1757 1758 intel_display_rpm_put(display, wakeref); 1759 1760 return 0; 1761 } 1762 1763 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1764 1765 void intel_dmc_debugfs_register(struct intel_display *display) 1766 { 1767 debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root, 1768 display, &intel_dmc_debugfs_status_fops); 1769 } 1770 1771 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe) 1772 { 1773 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 1774 u32 tmp = 0, int_vector; 1775 1776 if (DISPLAY_VER(display) >= 20) { 1777 tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe)); 1778 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp); 1779 1780 if (tmp & PIPEDMC_FLIPQ_PROG_DONE) { 1781 spin_lock(&display->drm->event_lock); 1782 1783 if (crtc->flipq_event) { 1784 /* 1785 * Update vblank counter/timestamp in case it 1786 * hasn't been done yet for this frame. 1787 */ 1788 drm_crtc_accurate_vblank_count(&crtc->base); 1789 1790 drm_crtc_send_vblank_event(&crtc->base, crtc->flipq_event); 1791 crtc->flipq_event = NULL; 1792 } 1793 1794 spin_unlock(&display->drm->event_lock); 1795 } 1796 1797 if (tmp & PIPEDMC_ATS_FAULT) 1798 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n", 1799 crtc->base.base.id, crtc->base.name); 1800 if (tmp & PIPEDMC_GTT_FAULT) 1801 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n", 1802 crtc->base.base.id, crtc->base.name); 1803 if (tmp & PIPEDMC_ERROR) 1804 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC error\n", 1805 crtc->base.base.id, crtc->base.name); 1806 } 1807 1808 int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK; 1809 if (tmp == 0 && int_vector != 0) 1810 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC interrupt vector 0x%x\n", 1811 crtc->base.base.id, crtc->base.name, int_vector); 1812 } 1813 1814 void intel_pipedmc_enable_event(struct intel_crtc *crtc, 1815 enum pipedmc_event_id event) 1816 { 1817 struct intel_display *display = to_intel_display(crtc); 1818 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1819 1820 dmc_configure_event(display, dmc_id, event, true); 1821 } 1822 1823 void intel_pipedmc_disable_event(struct intel_crtc *crtc, 1824 enum pipedmc_event_id event) 1825 { 1826 struct intel_display *display = to_intel_display(crtc); 1827 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1828 1829 dmc_configure_event(display, dmc_id, event, false); 1830 } 1831 1832 u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc) 1833 { 1834 struct intel_display *display = to_intel_display(crtc); 1835 struct intel_dmc *dmc = display_to_dmc(display); 1836 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1837 1838 return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0; 1839 } 1840 1841 void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc) 1842 { 1843 struct intel_display *display = to_intel_display(crtc); 1844 enum pipe pipe = crtc->pipe; 1845 1846 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 1847 PIPEDMC_ADAPTIVE_DCB_ENABLE); 1848 } 1849 1850 void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc) 1851 { 1852 struct intel_display *display = to_intel_display(crtc); 1853 enum pipe pipe = crtc->pipe; 1854 1855 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0); 1856 } 1857