1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 28 #include "i915_drv.h" 29 #include "i915_reg.h" 30 #include "intel_de.h" 31 #include "intel_dmc.h" 32 #include "intel_dmc_regs.h" 33 #include "intel_step.h" 34 35 /** 36 * DOC: DMC Firmware Support 37 * 38 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 39 * engine to save and restore the state of display engine when it enter into 40 * low-power state and comes back to normal. 41 */ 42 43 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 44 45 enum intel_dmc_id { 46 DMC_FW_MAIN = 0, 47 DMC_FW_PIPEA, 48 DMC_FW_PIPEB, 49 DMC_FW_PIPEC, 50 DMC_FW_PIPED, 51 DMC_FW_MAX 52 }; 53 54 struct intel_dmc { 55 struct intel_display *display; 56 struct work_struct work; 57 const char *fw_path; 58 u32 max_fw_size; /* bytes */ 59 u32 version; 60 struct dmc_fw_info { 61 u32 mmio_count; 62 i915_reg_t mmioaddr[20]; 63 u32 mmiodata[20]; 64 u32 dmc_offset; 65 u32 start_mmioaddr; 66 u32 dmc_fw_size; /*dwords */ 67 u32 *payload; 68 bool present; 69 } dmc_info[DMC_FW_MAX]; 70 }; 71 72 /* Note: This may be NULL. */ 73 static struct intel_dmc *display_to_dmc(struct intel_display *display) 74 { 75 return display->dmc.dmc; 76 } 77 78 static const char *dmc_firmware_param(struct intel_display *display) 79 { 80 const char *p = display->params.dmc_firmware_path; 81 82 return p && *p ? p : NULL; 83 } 84 85 static bool dmc_firmware_param_disabled(struct intel_display *display) 86 { 87 const char *p = dmc_firmware_param(display); 88 89 /* Magic path to indicate disabled */ 90 return p && !strcmp(p, "/dev/null"); 91 } 92 93 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 94 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 95 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 96 97 #define DMC_PATH(platform) \ 98 "i915/" __stringify(platform) "_dmc.bin" 99 100 /* 101 * New DMC additions should not use this. This is used solely to remain 102 * compatible with systems that have not yet updated DMC blobs to use 103 * unversioned file names. 104 */ 105 #define DMC_LEGACY_PATH(platform, major, minor) \ 106 "i915/" \ 107 __stringify(platform) "_dmc_ver" \ 108 __stringify(major) "_" \ 109 __stringify(minor) ".bin" 110 111 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 112 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 113 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 114 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 115 116 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 117 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 118 119 #define BMG_DMC_PATH DMC_PATH(bmg) 120 MODULE_FIRMWARE(BMG_DMC_PATH); 121 122 #define MTL_DMC_PATH DMC_PATH(mtl) 123 MODULE_FIRMWARE(MTL_DMC_PATH); 124 125 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 126 MODULE_FIRMWARE(DG2_DMC_PATH); 127 128 #define ADLP_DMC_PATH DMC_PATH(adlp) 129 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 130 MODULE_FIRMWARE(ADLP_DMC_PATH); 131 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 132 133 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 134 MODULE_FIRMWARE(ADLS_DMC_PATH); 135 136 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 137 MODULE_FIRMWARE(DG1_DMC_PATH); 138 139 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 140 MODULE_FIRMWARE(RKL_DMC_PATH); 141 142 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 143 MODULE_FIRMWARE(TGL_DMC_PATH); 144 145 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 146 #define ICL_DMC_MAX_FW_SIZE 0x6000 147 MODULE_FIRMWARE(ICL_DMC_PATH); 148 149 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 150 #define GLK_DMC_MAX_FW_SIZE 0x4000 151 MODULE_FIRMWARE(GLK_DMC_PATH); 152 153 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 154 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 155 MODULE_FIRMWARE(KBL_DMC_PATH); 156 157 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 158 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 159 MODULE_FIRMWARE(SKL_DMC_PATH); 160 161 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 162 #define BXT_DMC_MAX_FW_SIZE 0x3000 163 MODULE_FIRMWARE(BXT_DMC_PATH); 164 165 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) 166 { 167 struct drm_i915_private *i915 = to_i915(display->drm); 168 const char *fw_path = NULL; 169 u32 max_fw_size = 0; 170 171 if (DISPLAY_VER_FULL(display) == IP_VER(20, 0)) { 172 fw_path = XE2LPD_DMC_PATH; 173 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 174 } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 1)) { 175 fw_path = BMG_DMC_PATH; 176 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 177 } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 0)) { 178 fw_path = MTL_DMC_PATH; 179 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 180 } else if (IS_DG2(i915)) { 181 fw_path = DG2_DMC_PATH; 182 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 183 } else if (IS_ALDERLAKE_P(i915)) { 184 fw_path = ADLP_DMC_PATH; 185 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 186 } else if (IS_ALDERLAKE_S(i915)) { 187 fw_path = ADLS_DMC_PATH; 188 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 189 } else if (IS_DG1(i915)) { 190 fw_path = DG1_DMC_PATH; 191 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 192 } else if (IS_ROCKETLAKE(i915)) { 193 fw_path = RKL_DMC_PATH; 194 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 195 } else if (IS_TIGERLAKE(i915)) { 196 fw_path = TGL_DMC_PATH; 197 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 198 } else if (DISPLAY_VER(display) == 11) { 199 fw_path = ICL_DMC_PATH; 200 max_fw_size = ICL_DMC_MAX_FW_SIZE; 201 } else if (IS_GEMINILAKE(i915)) { 202 fw_path = GLK_DMC_PATH; 203 max_fw_size = GLK_DMC_MAX_FW_SIZE; 204 } else if (IS_KABYLAKE(i915) || 205 IS_COFFEELAKE(i915) || 206 IS_COMETLAKE(i915)) { 207 fw_path = KBL_DMC_PATH; 208 max_fw_size = KBL_DMC_MAX_FW_SIZE; 209 } else if (IS_SKYLAKE(i915)) { 210 fw_path = SKL_DMC_PATH; 211 max_fw_size = SKL_DMC_MAX_FW_SIZE; 212 } else if (IS_BROXTON(i915)) { 213 fw_path = BXT_DMC_PATH; 214 max_fw_size = BXT_DMC_MAX_FW_SIZE; 215 } 216 217 *size = max_fw_size; 218 219 return fw_path; 220 } 221 222 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 223 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 224 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 225 #define DMC_V1_MAX_MMIO_COUNT 8 226 #define DMC_V3_MAX_MMIO_COUNT 20 227 #define DMC_V1_MMIO_START_RANGE 0x80000 228 229 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 230 231 struct intel_css_header { 232 /* 0x09 for DMC */ 233 u32 module_type; 234 235 /* Includes the DMC specific header in dwords */ 236 u32 header_len; 237 238 /* always value would be 0x10000 */ 239 u32 header_ver; 240 241 /* Not used */ 242 u32 module_id; 243 244 /* Not used */ 245 u32 module_vendor; 246 247 /* in YYYYMMDD format */ 248 u32 date; 249 250 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 251 u32 size; 252 253 /* Not used */ 254 u32 key_size; 255 256 /* Not used */ 257 u32 modulus_size; 258 259 /* Not used */ 260 u32 exponent_size; 261 262 /* Not used */ 263 u32 reserved1[12]; 264 265 /* Major Minor */ 266 u32 version; 267 268 /* Not used */ 269 u32 reserved2[8]; 270 271 /* Not used */ 272 u32 kernel_header_info; 273 } __packed; 274 275 struct intel_fw_info { 276 u8 reserved1; 277 278 /* reserved on package_header version 1, must be 0 on version 2 */ 279 u8 dmc_id; 280 281 /* Stepping (A, B, C, ..., *). * is a wildcard */ 282 char stepping; 283 284 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 285 char substepping; 286 287 u32 offset; 288 u32 reserved2; 289 } __packed; 290 291 struct intel_package_header { 292 /* DMC container header length in dwords */ 293 u8 header_len; 294 295 /* 0x01, 0x02 */ 296 u8 header_ver; 297 298 u8 reserved[10]; 299 300 /* Number of valid entries in the FWInfo array below */ 301 u32 num_entries; 302 } __packed; 303 304 struct intel_dmc_header_base { 305 /* always value would be 0x40403E3E */ 306 u32 signature; 307 308 /* DMC binary header length */ 309 u8 header_len; 310 311 /* 0x01 */ 312 u8 header_ver; 313 314 /* Reserved */ 315 u16 dmcc_ver; 316 317 /* Major, Minor */ 318 u32 project; 319 320 /* Firmware program size (excluding header) in dwords */ 321 u32 fw_size; 322 323 /* Major Minor version */ 324 u32 fw_version; 325 } __packed; 326 327 struct intel_dmc_header_v1 { 328 struct intel_dmc_header_base base; 329 330 /* Number of valid MMIO cycles present. */ 331 u32 mmio_count; 332 333 /* MMIO address */ 334 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 335 336 /* MMIO data */ 337 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 338 339 /* FW filename */ 340 char dfile[32]; 341 342 u32 reserved1[2]; 343 } __packed; 344 345 struct intel_dmc_header_v3 { 346 struct intel_dmc_header_base base; 347 348 /* DMC RAM start MMIO address */ 349 u32 start_mmioaddr; 350 351 u32 reserved[9]; 352 353 /* FW filename */ 354 char dfile[32]; 355 356 /* Number of valid MMIO cycles present. */ 357 u32 mmio_count; 358 359 /* MMIO address */ 360 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 361 362 /* MMIO data */ 363 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 364 } __packed; 365 366 struct stepping_info { 367 char stepping; 368 char substepping; 369 }; 370 371 #define for_each_dmc_id(__dmc_id) \ 372 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 373 374 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 375 { 376 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 377 } 378 379 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) 380 { 381 struct intel_dmc *dmc = display_to_dmc(display); 382 383 return dmc && dmc->dmc_info[dmc_id].payload; 384 } 385 386 bool intel_dmc_has_payload(struct intel_display *display) 387 { 388 return has_dmc_id_fw(display, DMC_FW_MAIN); 389 } 390 391 static const struct stepping_info * 392 intel_get_stepping_info(struct intel_display *display, 393 struct stepping_info *si) 394 { 395 const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display)); 396 397 si->stepping = step_name[0]; 398 si->substepping = step_name[1]; 399 return si; 400 } 401 402 static void gen9_set_dc_state_debugmask(struct intel_display *display) 403 { 404 /* The below bit doesn't need to be cleared ever afterwards */ 405 intel_de_rmw(display, DC_STATE_DEBUG, 0, 406 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 407 intel_de_posting_read(display, DC_STATE_DEBUG); 408 } 409 410 static void disable_event_handler(struct intel_display *display, 411 i915_reg_t ctl_reg, i915_reg_t htp_reg) 412 { 413 intel_de_write(display, ctl_reg, 414 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 415 DMC_EVT_CTL_TYPE_EDGE_0_1) | 416 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 417 DMC_EVT_CTL_EVENT_ID_FALSE)); 418 intel_de_write(display, htp_reg, 0); 419 } 420 421 static void disable_all_event_handlers(struct intel_display *display) 422 { 423 enum intel_dmc_id dmc_id; 424 425 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 426 if (DISPLAY_VER(display) < 12) 427 return; 428 429 for_each_dmc_id(dmc_id) { 430 int handler; 431 432 if (!has_dmc_id_fw(display, dmc_id)) 433 continue; 434 435 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 436 disable_event_handler(display, 437 DMC_EVT_CTL(display, dmc_id, handler), 438 DMC_EVT_HTP(display, dmc_id, handler)); 439 } 440 } 441 442 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 443 { 444 enum pipe pipe; 445 446 /* 447 * Wa_16015201720:adl-p,dg2 448 * The WA requires clock gating to be disabled all the time 449 * for pipe A and B. 450 * For pipe C and D clock gating needs to be disabled only 451 * during initializing the firmware. 452 */ 453 if (enable) 454 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 455 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 456 0, PIPEDMC_GATING_DIS); 457 else 458 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 459 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 460 PIPEDMC_GATING_DIS, 0); 461 } 462 463 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) 464 { 465 /* 466 * Wa_16015201720 467 * The WA requires clock gating to be disabled all the time 468 * for pipe A and B. 469 */ 470 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, 471 MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); 472 } 473 474 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 475 { 476 if (DISPLAY_VER(display) >= 14 && enable) 477 mtl_pipedmc_clock_gating_wa(display); 478 else if (DISPLAY_VER(display) == 13) 479 adlp_pipedmc_clock_gating_wa(display, enable); 480 } 481 482 void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe) 483 { 484 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 485 486 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 487 return; 488 489 if (DISPLAY_VER(display) >= 14) 490 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 491 else 492 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 493 } 494 495 void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe) 496 { 497 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 498 499 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 500 return; 501 502 if (DISPLAY_VER(display) >= 14) 503 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 504 else 505 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 506 } 507 508 static bool is_dmc_evt_ctl_reg(struct intel_display *display, 509 enum intel_dmc_id dmc_id, i915_reg_t reg) 510 { 511 u32 offset = i915_mmio_reg_offset(reg); 512 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); 513 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 514 515 return offset >= start && offset < end; 516 } 517 518 static bool is_dmc_evt_htp_reg(struct intel_display *display, 519 enum intel_dmc_id dmc_id, i915_reg_t reg) 520 { 521 u32 offset = i915_mmio_reg_offset(reg); 522 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); 523 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 524 525 return offset >= start && offset < end; 526 } 527 528 static bool disable_dmc_evt(struct intel_display *display, 529 enum intel_dmc_id dmc_id, 530 i915_reg_t reg, u32 data) 531 { 532 struct drm_i915_private *i915 = to_i915(display->drm); 533 534 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) 535 return false; 536 537 /* keep all pipe DMC events disabled by default */ 538 if (dmc_id != DMC_FW_MAIN) 539 return true; 540 541 /* also disable the flip queue event on the main DMC on TGL */ 542 if (IS_TIGERLAKE(i915) && 543 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC) 544 return true; 545 546 /* also disable the HRR event on the main DMC on TGL/ADLS */ 547 if ((IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915)) && 548 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A) 549 return true; 550 551 return false; 552 } 553 554 static u32 dmc_mmiodata(struct intel_display *display, 555 struct intel_dmc *dmc, 556 enum intel_dmc_id dmc_id, int i) 557 { 558 if (disable_dmc_evt(display, dmc_id, 559 dmc->dmc_info[dmc_id].mmioaddr[i], 560 dmc->dmc_info[dmc_id].mmiodata[i])) 561 return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 562 DMC_EVT_CTL_TYPE_EDGE_0_1) | 563 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 564 DMC_EVT_CTL_EVENT_ID_FALSE); 565 else 566 return dmc->dmc_info[dmc_id].mmiodata[i]; 567 } 568 569 /** 570 * intel_dmc_load_program() - write the firmware from memory to register. 571 * @display: display instance 572 * 573 * DMC firmware is read from a .bin file and kept in internal memory one time. 574 * Everytime display comes back from low power state this function is called to 575 * copy the firmware from internal memory to registers. 576 */ 577 void intel_dmc_load_program(struct intel_display *display) 578 { 579 struct drm_i915_private *i915 __maybe_unused = to_i915(display->drm); 580 struct i915_power_domains *power_domains = &display->power.domains; 581 struct intel_dmc *dmc = display_to_dmc(display); 582 enum intel_dmc_id dmc_id; 583 u32 i; 584 585 if (!intel_dmc_has_payload(display)) 586 return; 587 588 pipedmc_clock_gating_wa(display, true); 589 590 disable_all_event_handlers(display); 591 592 assert_rpm_wakelock_held(&i915->runtime_pm); 593 594 preempt_disable(); 595 596 for_each_dmc_id(dmc_id) { 597 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 598 intel_de_write_fw(display, 599 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 600 dmc->dmc_info[dmc_id].payload[i]); 601 } 602 } 603 604 preempt_enable(); 605 606 for_each_dmc_id(dmc_id) { 607 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 608 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], 609 dmc_mmiodata(display, dmc, dmc_id, i)); 610 } 611 } 612 613 power_domains->dc_state = 0; 614 615 gen9_set_dc_state_debugmask(display); 616 617 pipedmc_clock_gating_wa(display, false); 618 } 619 620 /** 621 * intel_dmc_disable_program() - disable the firmware 622 * @display: display instance 623 * 624 * Disable all event handlers in the firmware, making sure the firmware is 625 * inactive after the display is uninitialized. 626 */ 627 void intel_dmc_disable_program(struct intel_display *display) 628 { 629 if (!intel_dmc_has_payload(display)) 630 return; 631 632 pipedmc_clock_gating_wa(display, true); 633 disable_all_event_handlers(display); 634 pipedmc_clock_gating_wa(display, false); 635 636 intel_dmc_wl_disable(display); 637 } 638 639 void assert_dmc_loaded(struct intel_display *display) 640 { 641 struct intel_dmc *dmc = display_to_dmc(display); 642 643 drm_WARN_ONCE(display->drm, !dmc, "DMC not initialized\n"); 644 drm_WARN_ONCE(display->drm, dmc && 645 !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 646 "DMC program storage start is NULL\n"); 647 drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_SSP_BASE), 648 "DMC SSP Base Not fine\n"); 649 drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_HTP_SKL), 650 "DMC HTP Not fine\n"); 651 } 652 653 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 654 const struct stepping_info *si) 655 { 656 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 657 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 658 /* 659 * If we don't find a more specific one from above two checks, we 660 * then check for the generic one to be sure to work even with 661 * "broken firmware" 662 */ 663 (si->stepping == '*' && si->substepping == fw_info->substepping) || 664 (fw_info->stepping == '*' && fw_info->substepping == '*')) 665 return true; 666 667 return false; 668 } 669 670 /* 671 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 672 * already sanitized. 673 */ 674 static void dmc_set_fw_offset(struct intel_dmc *dmc, 675 const struct intel_fw_info *fw_info, 676 unsigned int num_entries, 677 const struct stepping_info *si, 678 u8 package_ver) 679 { 680 struct intel_display *display = dmc->display; 681 enum intel_dmc_id dmc_id; 682 unsigned int i; 683 684 for (i = 0; i < num_entries; i++) { 685 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 686 687 if (!is_valid_dmc_id(dmc_id)) { 688 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); 689 continue; 690 } 691 692 /* More specific versions come first, so we don't even have to 693 * check for the stepping since we already found a previous FW 694 * for this id. 695 */ 696 if (dmc->dmc_info[dmc_id].present) 697 continue; 698 699 if (fw_info_matches_stepping(&fw_info[i], si)) { 700 dmc->dmc_info[dmc_id].present = true; 701 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 702 } 703 } 704 } 705 706 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 707 const u32 *mmioaddr, u32 mmio_count, 708 int header_ver, enum intel_dmc_id dmc_id) 709 { 710 struct intel_display *display = dmc->display; 711 u32 start_range, end_range; 712 int i; 713 714 if (header_ver == 1) { 715 start_range = DMC_MMIO_START_RANGE; 716 end_range = DMC_MMIO_END_RANGE; 717 } else if (dmc_id == DMC_FW_MAIN) { 718 start_range = TGL_MAIN_MMIO_START; 719 end_range = TGL_MAIN_MMIO_END; 720 } else if (DISPLAY_VER(display) >= 13) { 721 start_range = ADLP_PIPE_MMIO_START; 722 end_range = ADLP_PIPE_MMIO_END; 723 } else if (DISPLAY_VER(display) >= 12) { 724 start_range = TGL_PIPE_MMIO_START(dmc_id); 725 end_range = TGL_PIPE_MMIO_END(dmc_id); 726 } else { 727 drm_warn(display->drm, "Unknown mmio range for sanity check"); 728 return false; 729 } 730 731 for (i = 0; i < mmio_count; i++) { 732 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 733 return false; 734 } 735 736 return true; 737 } 738 739 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 740 const struct intel_dmc_header_base *dmc_header, 741 size_t rem_size, enum intel_dmc_id dmc_id) 742 { 743 struct intel_display *display = dmc->display; 744 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 745 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 746 const u32 *mmioaddr, *mmiodata; 747 u32 mmio_count, mmio_count_max, start_mmioaddr; 748 u8 *payload; 749 750 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 751 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 752 753 /* 754 * Check if we can access common fields, we will checkc again below 755 * after we have read the version 756 */ 757 if (rem_size < sizeof(struct intel_dmc_header_base)) 758 goto error_truncated; 759 760 /* Cope with small differences between v1 and v3 */ 761 if (dmc_header->header_ver == 3) { 762 const struct intel_dmc_header_v3 *v3 = 763 (const struct intel_dmc_header_v3 *)dmc_header; 764 765 if (rem_size < sizeof(struct intel_dmc_header_v3)) 766 goto error_truncated; 767 768 mmioaddr = v3->mmioaddr; 769 mmiodata = v3->mmiodata; 770 mmio_count = v3->mmio_count; 771 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 772 /* header_len is in dwords */ 773 header_len_bytes = dmc_header->header_len * 4; 774 start_mmioaddr = v3->start_mmioaddr; 775 dmc_header_size = sizeof(*v3); 776 } else if (dmc_header->header_ver == 1) { 777 const struct intel_dmc_header_v1 *v1 = 778 (const struct intel_dmc_header_v1 *)dmc_header; 779 780 if (rem_size < sizeof(struct intel_dmc_header_v1)) 781 goto error_truncated; 782 783 mmioaddr = v1->mmioaddr; 784 mmiodata = v1->mmiodata; 785 mmio_count = v1->mmio_count; 786 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 787 header_len_bytes = dmc_header->header_len; 788 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 789 dmc_header_size = sizeof(*v1); 790 } else { 791 drm_err(display->drm, "Unknown DMC fw header version: %u\n", 792 dmc_header->header_ver); 793 return 0; 794 } 795 796 if (header_len_bytes != dmc_header_size) { 797 drm_err(display->drm, "DMC firmware has wrong dmc header length " 798 "(%u bytes)\n", header_len_bytes); 799 return 0; 800 } 801 802 /* Cache the dmc header info. */ 803 if (mmio_count > mmio_count_max) { 804 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 805 return 0; 806 } 807 808 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 809 dmc_header->header_ver, dmc_id)) { 810 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); 811 return 0; 812 } 813 814 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); 815 for (i = 0; i < mmio_count; i++) { 816 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 817 dmc_info->mmiodata[i] = mmiodata[i]; 818 819 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 820 i, mmioaddr[i], mmiodata[i], 821 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 822 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 823 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], 824 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 825 } 826 dmc_info->mmio_count = mmio_count; 827 dmc_info->start_mmioaddr = start_mmioaddr; 828 829 rem_size -= header_len_bytes; 830 831 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 832 payload_size = dmc_header->fw_size * 4; 833 if (rem_size < payload_size) 834 goto error_truncated; 835 836 if (payload_size > dmc->max_fw_size) { 837 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); 838 return 0; 839 } 840 dmc_info->dmc_fw_size = dmc_header->fw_size; 841 842 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 843 if (!dmc_info->payload) 844 return 0; 845 846 payload = (u8 *)(dmc_header) + header_len_bytes; 847 memcpy(dmc_info->payload, payload, payload_size); 848 849 return header_len_bytes + payload_size; 850 851 error_truncated: 852 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 853 return 0; 854 } 855 856 static u32 857 parse_dmc_fw_package(struct intel_dmc *dmc, 858 const struct intel_package_header *package_header, 859 const struct stepping_info *si, 860 size_t rem_size) 861 { 862 struct intel_display *display = dmc->display; 863 u32 package_size = sizeof(struct intel_package_header); 864 u32 num_entries, max_entries; 865 const struct intel_fw_info *fw_info; 866 867 if (rem_size < package_size) 868 goto error_truncated; 869 870 if (package_header->header_ver == 1) { 871 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 872 } else if (package_header->header_ver == 2) { 873 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 874 } else { 875 drm_err(display->drm, "DMC firmware has unknown header version %u\n", 876 package_header->header_ver); 877 return 0; 878 } 879 880 /* 881 * We should always have space for max_entries, 882 * even if not all are used 883 */ 884 package_size += max_entries * sizeof(struct intel_fw_info); 885 if (rem_size < package_size) 886 goto error_truncated; 887 888 if (package_header->header_len * 4 != package_size) { 889 drm_err(display->drm, "DMC firmware has wrong package header length " 890 "(%u bytes)\n", package_size); 891 return 0; 892 } 893 894 num_entries = package_header->num_entries; 895 if (WARN_ON(package_header->num_entries > max_entries)) 896 num_entries = max_entries; 897 898 fw_info = (const struct intel_fw_info *) 899 ((u8 *)package_header + sizeof(*package_header)); 900 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 901 package_header->header_ver); 902 903 /* dmc_offset is in dwords */ 904 return package_size; 905 906 error_truncated: 907 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 908 return 0; 909 } 910 911 /* Return number of bytes parsed or 0 on error */ 912 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 913 struct intel_css_header *css_header, 914 size_t rem_size) 915 { 916 struct intel_display *display = dmc->display; 917 918 if (rem_size < sizeof(struct intel_css_header)) { 919 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 920 return 0; 921 } 922 923 if (sizeof(struct intel_css_header) != 924 (css_header->header_len * 4)) { 925 drm_err(display->drm, "DMC firmware has wrong CSS header length " 926 "(%u bytes)\n", 927 (css_header->header_len * 4)); 928 return 0; 929 } 930 931 dmc->version = css_header->version; 932 933 return sizeof(struct intel_css_header); 934 } 935 936 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 937 { 938 struct intel_display *display = dmc->display; 939 struct intel_css_header *css_header; 940 struct intel_package_header *package_header; 941 struct intel_dmc_header_base *dmc_header; 942 struct stepping_info display_info = { '*', '*'}; 943 const struct stepping_info *si = intel_get_stepping_info(display, &display_info); 944 enum intel_dmc_id dmc_id; 945 u32 readcount = 0; 946 u32 r, offset; 947 948 if (!fw) 949 return -EINVAL; 950 951 /* Extract CSS Header information */ 952 css_header = (struct intel_css_header *)fw->data; 953 r = parse_dmc_fw_css(dmc, css_header, fw->size); 954 if (!r) 955 return -EINVAL; 956 957 readcount += r; 958 959 /* Extract Package Header information */ 960 package_header = (struct intel_package_header *)&fw->data[readcount]; 961 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 962 if (!r) 963 return -EINVAL; 964 965 readcount += r; 966 967 for_each_dmc_id(dmc_id) { 968 if (!dmc->dmc_info[dmc_id].present) 969 continue; 970 971 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 972 if (offset > fw->size) { 973 drm_err(display->drm, "Reading beyond the fw_size\n"); 974 continue; 975 } 976 977 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 978 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 979 } 980 981 if (!intel_dmc_has_payload(display)) { 982 drm_err(display->drm, "DMC firmware main program not found\n"); 983 return -ENOENT; 984 } 985 986 return 0; 987 } 988 989 static void intel_dmc_runtime_pm_get(struct intel_display *display) 990 { 991 struct drm_i915_private *i915 = to_i915(display->drm); 992 993 drm_WARN_ON(display->drm, display->dmc.wakeref); 994 display->dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 995 } 996 997 static void intel_dmc_runtime_pm_put(struct intel_display *display) 998 { 999 struct drm_i915_private *i915 = to_i915(display->drm); 1000 intel_wakeref_t wakeref __maybe_unused = 1001 fetch_and_zero(&display->dmc.wakeref); 1002 1003 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 1004 } 1005 1006 static const char *dmc_fallback_path(struct intel_display *display) 1007 { 1008 struct drm_i915_private *i915 = to_i915(display->drm); 1009 1010 if (IS_ALDERLAKE_P(i915)) 1011 return ADLP_DMC_FALLBACK_PATH; 1012 1013 return NULL; 1014 } 1015 1016 static void dmc_load_work_fn(struct work_struct *work) 1017 { 1018 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1019 struct intel_display *display = dmc->display; 1020 const struct firmware *fw = NULL; 1021 const char *fallback_path; 1022 int err; 1023 1024 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); 1025 1026 if (err == -ENOENT && !dmc_firmware_param(display)) { 1027 fallback_path = dmc_fallback_path(display); 1028 if (fallback_path) { 1029 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", 1030 dmc->fw_path, fallback_path); 1031 err = request_firmware(&fw, fallback_path, display->drm->dev); 1032 if (err == 0) 1033 dmc->fw_path = fallback_path; 1034 } 1035 } 1036 1037 if (err) { 1038 drm_notice(display->drm, 1039 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1040 dmc->fw_path, ERR_PTR(err)); 1041 drm_notice(display->drm, "DMC firmware homepage: %s", 1042 INTEL_DMC_FIRMWARE_URL); 1043 return; 1044 } 1045 1046 err = parse_dmc_fw(dmc, fw); 1047 if (err) { 1048 drm_notice(display->drm, 1049 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1050 dmc->fw_path, ERR_PTR(err)); 1051 goto out; 1052 } 1053 1054 intel_dmc_load_program(display); 1055 intel_dmc_runtime_pm_put(display); 1056 1057 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1058 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1059 DMC_VERSION_MINOR(dmc->version)); 1060 1061 out: 1062 release_firmware(fw); 1063 } 1064 1065 /** 1066 * intel_dmc_init() - initialize the firmware loading. 1067 * @display: display instance 1068 * 1069 * This function is called at the time of loading the display driver to read 1070 * firmware from a .bin file and copied into a internal memory. 1071 */ 1072 void intel_dmc_init(struct intel_display *display) 1073 { 1074 struct drm_i915_private *i915 = to_i915(display->drm); 1075 struct intel_dmc *dmc; 1076 1077 if (!HAS_DMC(display)) 1078 return; 1079 1080 /* 1081 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1082 * runtime-suspend. 1083 * 1084 * On error, we return with the rpm wakeref held to prevent runtime 1085 * suspend as runtime suspend *requires* a working DMC for whatever 1086 * reason. 1087 */ 1088 intel_dmc_runtime_pm_get(display); 1089 1090 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); 1091 if (!dmc) 1092 return; 1093 1094 dmc->display = display; 1095 1096 INIT_WORK(&dmc->work, dmc_load_work_fn); 1097 1098 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); 1099 1100 if (dmc_firmware_param_disabled(display)) { 1101 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); 1102 goto out; 1103 } 1104 1105 if (dmc_firmware_param(display)) 1106 dmc->fw_path = dmc_firmware_param(display); 1107 1108 if (!dmc->fw_path) { 1109 drm_dbg_kms(display->drm, 1110 "No known DMC firmware for platform, disabling runtime PM\n"); 1111 goto out; 1112 } 1113 1114 display->dmc.dmc = dmc; 1115 1116 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); 1117 queue_work(i915->unordered_wq, &dmc->work); 1118 1119 return; 1120 1121 out: 1122 kfree(dmc); 1123 } 1124 1125 /** 1126 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1127 * @display: display instance 1128 * 1129 * Prepare the DMC firmware before entering system suspend. This includes 1130 * flushing pending work items and releasing any resources acquired during 1131 * init. 1132 */ 1133 void intel_dmc_suspend(struct intel_display *display) 1134 { 1135 struct intel_dmc *dmc = display_to_dmc(display); 1136 1137 if (!HAS_DMC(display)) 1138 return; 1139 1140 if (dmc) 1141 flush_work(&dmc->work); 1142 1143 intel_dmc_wl_disable(display); 1144 1145 /* Drop the reference held in case DMC isn't loaded. */ 1146 if (!intel_dmc_has_payload(display)) 1147 intel_dmc_runtime_pm_put(display); 1148 } 1149 1150 /** 1151 * intel_dmc_resume() - init DMC firmware during system resume 1152 * @display: display instance 1153 * 1154 * Reinitialize the DMC firmware during system resume, reacquiring any 1155 * resources released in intel_dmc_suspend(). 1156 */ 1157 void intel_dmc_resume(struct intel_display *display) 1158 { 1159 if (!HAS_DMC(display)) 1160 return; 1161 1162 /* 1163 * Reacquire the reference to keep RPM disabled in case DMC isn't 1164 * loaded. 1165 */ 1166 if (!intel_dmc_has_payload(display)) 1167 intel_dmc_runtime_pm_get(display); 1168 } 1169 1170 /** 1171 * intel_dmc_fini() - unload the DMC firmware. 1172 * @display: display instance 1173 * 1174 * Firmmware unloading includes freeing the internal memory and reset the 1175 * firmware loading status. 1176 */ 1177 void intel_dmc_fini(struct intel_display *display) 1178 { 1179 struct intel_dmc *dmc = display_to_dmc(display); 1180 enum intel_dmc_id dmc_id; 1181 1182 if (!HAS_DMC(display)) 1183 return; 1184 1185 intel_dmc_suspend(display); 1186 drm_WARN_ON(display->drm, display->dmc.wakeref); 1187 1188 if (dmc) { 1189 for_each_dmc_id(dmc_id) 1190 kfree(dmc->dmc_info[dmc_id].payload); 1191 1192 kfree(dmc); 1193 display->dmc.dmc = NULL; 1194 } 1195 } 1196 1197 struct intel_dmc_snapshot { 1198 bool initialized; 1199 bool loaded; 1200 u32 version; 1201 }; 1202 1203 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) 1204 { 1205 struct intel_dmc *dmc = display_to_dmc(display); 1206 struct intel_dmc_snapshot *snapshot; 1207 1208 if (!HAS_DMC(display)) 1209 return NULL; 1210 1211 snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); 1212 if (!snapshot) 1213 return NULL; 1214 1215 snapshot->initialized = dmc; 1216 snapshot->loaded = intel_dmc_has_payload(display); 1217 if (dmc) 1218 snapshot->version = dmc->version; 1219 1220 return snapshot; 1221 } 1222 1223 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p) 1224 { 1225 if (!snapshot) 1226 return; 1227 1228 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized)); 1229 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded)); 1230 if (snapshot->initialized) 1231 drm_printf(p, "DMC fw version: %d.%d\n", 1232 DMC_VERSION_MAJOR(snapshot->version), 1233 DMC_VERSION_MINOR(snapshot->version)); 1234 } 1235 1236 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1237 { 1238 struct intel_display *display = m->private; 1239 struct drm_i915_private *i915 = to_i915(display->drm); 1240 struct intel_dmc *dmc = display_to_dmc(display); 1241 intel_wakeref_t wakeref; 1242 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1243 1244 if (!HAS_DMC(display)) 1245 return -ENODEV; 1246 1247 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1248 1249 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1250 seq_printf(m, "fw loaded: %s\n", 1251 str_yes_no(intel_dmc_has_payload(display))); 1252 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1253 seq_printf(m, "Pipe A fw needed: %s\n", 1254 str_yes_no(DISPLAY_VER(display) >= 12)); 1255 seq_printf(m, "Pipe A fw loaded: %s\n", 1256 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); 1257 seq_printf(m, "Pipe B fw needed: %s\n", 1258 str_yes_no(IS_ALDERLAKE_P(i915) || 1259 DISPLAY_VER(display) >= 14)); 1260 seq_printf(m, "Pipe B fw loaded: %s\n", 1261 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); 1262 1263 if (!intel_dmc_has_payload(display)) 1264 goto out; 1265 1266 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1267 DMC_VERSION_MINOR(dmc->version)); 1268 1269 if (DISPLAY_VER(display) >= 12) { 1270 i915_reg_t dc3co_reg; 1271 1272 if (IS_DGFX(i915) || DISPLAY_VER(display) >= 14) { 1273 dc3co_reg = DG1_DMC_DEBUG3; 1274 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1275 } else { 1276 dc3co_reg = TGL_DMC_DEBUG3; 1277 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1278 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1279 } 1280 1281 seq_printf(m, "DC3CO count: %d\n", 1282 intel_de_read(display, dc3co_reg)); 1283 } else { 1284 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : 1285 SKL_DMC_DC3_DC5_COUNT; 1286 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) 1287 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1288 } 1289 1290 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); 1291 if (i915_mmio_reg_valid(dc6_reg)) 1292 seq_printf(m, "DC5 -> DC6 count: %d\n", 1293 intel_de_read(display, dc6_reg)); 1294 1295 seq_printf(m, "program base: 0x%08x\n", 1296 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1297 1298 out: 1299 seq_printf(m, "ssp base: 0x%08x\n", 1300 intel_de_read(display, DMC_SSP_BASE)); 1301 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); 1302 1303 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1304 1305 return 0; 1306 } 1307 1308 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1309 1310 void intel_dmc_debugfs_register(struct intel_display *display) 1311 { 1312 struct drm_minor *minor = display->drm->primary; 1313 1314 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 1315 display, &intel_dmc_debugfs_status_fops); 1316 } 1317