1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 #include <drm/drm_vblank.h> 28 29 #include <drm/drm_file.h> 30 #include <drm/drm_print.h> 31 32 #include "intel_crtc.h" 33 #include "intel_de.h" 34 #include "intel_display_power_well.h" 35 #include "intel_display_regs.h" 36 #include "intel_display_rpm.h" 37 #include "intel_display_types.h" 38 #include "intel_display_utils.h" 39 #include "intel_dmc.h" 40 #include "intel_dmc_regs.h" 41 #include "intel_flipq.h" 42 43 /** 44 * DOC: DMC Firmware Support 45 * 46 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 47 * engine to save and restore the state of display engine when it enter into 48 * low-power state and comes back to normal. 49 */ 50 51 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 52 53 enum intel_dmc_id { 54 DMC_FW_MAIN = 0, 55 DMC_FW_PIPEA, 56 DMC_FW_PIPEB, 57 DMC_FW_PIPEC, 58 DMC_FW_PIPED, 59 DMC_FW_MAX 60 }; 61 62 struct intel_dmc { 63 struct intel_display *display; 64 struct work_struct work; 65 const char *fw_path; 66 u32 max_fw_size; /* bytes */ 67 u32 version; 68 struct { 69 u32 dc5_start; 70 u32 count; 71 } dc6_allowed; 72 struct dmc_fw_info { 73 u32 mmio_count; 74 intel_reg_t mmioaddr[20]; 75 u32 mmiodata[20]; 76 u32 dmc_offset; 77 u32 start_mmioaddr; 78 u32 dmc_fw_size; /*dwords */ 79 u32 *payload; 80 bool present; 81 } dmc_info[DMC_FW_MAX]; 82 }; 83 84 /* Note: This may be NULL. */ 85 static struct intel_dmc *display_to_dmc(struct intel_display *display) 86 { 87 return display->dmc.dmc; 88 } 89 90 static const char *dmc_firmware_param(struct intel_display *display) 91 { 92 const char *p = display->params.dmc_firmware_path; 93 94 return p && *p ? p : NULL; 95 } 96 97 static bool dmc_firmware_param_disabled(struct intel_display *display) 98 { 99 const char *p = dmc_firmware_param(display); 100 101 /* Magic path to indicate disabled */ 102 return p && !strcmp(p, "/dev/null"); 103 } 104 105 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 106 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 107 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 108 109 #define DMC_PATH(platform) \ 110 "i915/" __stringify(platform) "_dmc.bin" 111 112 /* 113 * New DMC additions should not use this. This is used solely to remain 114 * compatible with systems that have not yet updated DMC blobs to use 115 * unversioned file names. 116 */ 117 #define DMC_LEGACY_PATH(platform, major, minor) \ 118 "i915/" \ 119 __stringify(platform) "_dmc_ver" \ 120 __stringify(major) "_" \ 121 __stringify(minor) ".bin" 122 123 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 124 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 125 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 126 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 127 128 #define XE3P_LPD_DMC_PATH DMC_PATH(xe3p_lpd) 129 MODULE_FIRMWARE(XE3P_LPD_DMC_PATH); 130 131 #define XE3LPD_3002_DMC_PATH DMC_PATH(xe3lpd_3002) 132 MODULE_FIRMWARE(XE3LPD_3002_DMC_PATH); 133 134 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd) 135 MODULE_FIRMWARE(XE3LPD_DMC_PATH); 136 137 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 138 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 139 140 #define BMG_DMC_PATH DMC_PATH(bmg) 141 MODULE_FIRMWARE(BMG_DMC_PATH); 142 143 #define MTL_DMC_PATH DMC_PATH(mtl) 144 MODULE_FIRMWARE(MTL_DMC_PATH); 145 146 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 147 MODULE_FIRMWARE(DG2_DMC_PATH); 148 149 #define ADLP_DMC_PATH DMC_PATH(adlp) 150 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 151 MODULE_FIRMWARE(ADLP_DMC_PATH); 152 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 153 154 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 155 MODULE_FIRMWARE(ADLS_DMC_PATH); 156 157 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 158 MODULE_FIRMWARE(DG1_DMC_PATH); 159 160 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 161 MODULE_FIRMWARE(RKL_DMC_PATH); 162 163 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 164 MODULE_FIRMWARE(TGL_DMC_PATH); 165 166 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 167 #define ICL_DMC_MAX_FW_SIZE 0x6000 168 MODULE_FIRMWARE(ICL_DMC_PATH); 169 170 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 171 #define GLK_DMC_MAX_FW_SIZE 0x4000 172 MODULE_FIRMWARE(GLK_DMC_PATH); 173 174 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 175 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 176 MODULE_FIRMWARE(KBL_DMC_PATH); 177 178 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 179 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 180 MODULE_FIRMWARE(SKL_DMC_PATH); 181 182 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 183 #define BXT_DMC_MAX_FW_SIZE 0x3000 184 MODULE_FIRMWARE(BXT_DMC_PATH); 185 186 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) 187 { 188 const char *fw_path = NULL; 189 u32 max_fw_size = 0; 190 191 if (DISPLAY_VERx100(display) == 3500) { 192 fw_path = XE3P_LPD_DMC_PATH; 193 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 194 } else if (DISPLAY_VERx100(display) == 3002) { 195 fw_path = XE3LPD_3002_DMC_PATH; 196 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 197 } else if (DISPLAY_VERx100(display) == 3000) { 198 fw_path = XE3LPD_DMC_PATH; 199 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 200 } else if (DISPLAY_VERx100(display) == 2000) { 201 fw_path = XE2LPD_DMC_PATH; 202 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 203 } else if (DISPLAY_VERx100(display) == 1401) { 204 fw_path = BMG_DMC_PATH; 205 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 206 } else if (DISPLAY_VERx100(display) == 1400) { 207 fw_path = MTL_DMC_PATH; 208 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 209 } else if (display->platform.dg2) { 210 fw_path = DG2_DMC_PATH; 211 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 212 } else if (display->platform.alderlake_p) { 213 fw_path = ADLP_DMC_PATH; 214 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 215 } else if (display->platform.alderlake_s) { 216 fw_path = ADLS_DMC_PATH; 217 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 218 } else if (display->platform.dg1) { 219 fw_path = DG1_DMC_PATH; 220 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 221 } else if (display->platform.rocketlake) { 222 fw_path = RKL_DMC_PATH; 223 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 224 } else if (display->platform.tigerlake) { 225 fw_path = TGL_DMC_PATH; 226 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 227 } else if (DISPLAY_VER(display) == 11) { 228 fw_path = ICL_DMC_PATH; 229 max_fw_size = ICL_DMC_MAX_FW_SIZE; 230 } else if (display->platform.geminilake) { 231 fw_path = GLK_DMC_PATH; 232 max_fw_size = GLK_DMC_MAX_FW_SIZE; 233 } else if (display->platform.kabylake || 234 display->platform.coffeelake || 235 display->platform.cometlake) { 236 fw_path = KBL_DMC_PATH; 237 max_fw_size = KBL_DMC_MAX_FW_SIZE; 238 } else if (display->platform.skylake) { 239 fw_path = SKL_DMC_PATH; 240 max_fw_size = SKL_DMC_MAX_FW_SIZE; 241 } else if (display->platform.broxton) { 242 fw_path = BXT_DMC_PATH; 243 max_fw_size = BXT_DMC_MAX_FW_SIZE; 244 } 245 246 *size = max_fw_size; 247 248 return fw_path; 249 } 250 251 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 252 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 253 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 254 #define DMC_V1_MAX_MMIO_COUNT 8 255 #define DMC_V3_MAX_MMIO_COUNT 20 256 #define DMC_V1_MMIO_START_RANGE 0x80000 257 258 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 259 260 struct intel_css_header { 261 /* 0x09 for DMC */ 262 u32 module_type; 263 264 /* Includes the DMC specific header in dwords */ 265 u32 header_len; 266 267 /* always value would be 0x10000 */ 268 u32 header_ver; 269 270 /* Not used */ 271 u32 module_id; 272 273 /* Not used */ 274 u32 module_vendor; 275 276 /* in YYYYMMDD format */ 277 u32 date; 278 279 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 280 u32 size; 281 282 /* Not used */ 283 u32 key_size; 284 285 /* Not used */ 286 u32 modulus_size; 287 288 /* Not used */ 289 u32 exponent_size; 290 291 /* Not used */ 292 u32 reserved1[12]; 293 294 /* Major Minor */ 295 u32 version; 296 297 /* Not used */ 298 u32 reserved2[8]; 299 300 /* Not used */ 301 u32 kernel_header_info; 302 } __packed; 303 304 struct intel_fw_info { 305 u8 reserved1; 306 307 /* reserved on package_header version 1, must be 0 on version 2 */ 308 u8 dmc_id; 309 310 /* Stepping (A, B, C, ..., *). * is a wildcard */ 311 char stepping; 312 313 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 314 char substepping; 315 316 u32 offset; 317 u32 reserved2; 318 } __packed; 319 320 struct intel_package_header { 321 /* DMC container header length in dwords */ 322 u8 header_len; 323 324 /* 0x01, 0x02 */ 325 u8 header_ver; 326 327 u8 reserved[10]; 328 329 /* Number of valid entries in the FWInfo array below */ 330 u32 num_entries; 331 } __packed; 332 333 struct intel_dmc_header_base { 334 /* always value would be 0x40403E3E */ 335 u32 signature; 336 337 /* DMC binary header length */ 338 u8 header_len; 339 340 /* 0x01 */ 341 u8 header_ver; 342 343 /* Reserved */ 344 u16 dmcc_ver; 345 346 /* Major, Minor */ 347 u32 project; 348 349 /* Firmware program size (excluding header) in dwords */ 350 u32 fw_size; 351 352 /* Major Minor version */ 353 u32 fw_version; 354 } __packed; 355 356 struct intel_dmc_header_v1 { 357 struct intel_dmc_header_base base; 358 359 /* Number of valid MMIO cycles present. */ 360 u32 mmio_count; 361 362 /* MMIO address */ 363 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 364 365 /* MMIO data */ 366 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 367 368 /* FW filename */ 369 char dfile[32]; 370 371 u32 reserved1[2]; 372 } __packed; 373 374 struct intel_dmc_header_v3 { 375 struct intel_dmc_header_base base; 376 377 /* DMC RAM start MMIO address */ 378 u32 start_mmioaddr; 379 380 u32 reserved[9]; 381 382 /* FW filename */ 383 char dfile[32]; 384 385 /* Number of valid MMIO cycles present. */ 386 u32 mmio_count; 387 388 /* MMIO address */ 389 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 390 391 /* MMIO data */ 392 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 393 } __packed; 394 395 struct stepping_info { 396 char stepping; 397 char substepping; 398 }; 399 400 #define for_each_dmc_id(__dmc_id) \ 401 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 402 403 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 404 { 405 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 406 } 407 408 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) 409 { 410 struct intel_dmc *dmc = display_to_dmc(display); 411 412 return dmc && dmc->dmc_info[dmc_id].payload; 413 } 414 415 bool intel_dmc_has_payload(struct intel_display *display) 416 { 417 return has_dmc_id_fw(display, DMC_FW_MAIN); 418 } 419 420 static void initialize_stepping_info(struct intel_display *display, struct stepping_info *si) 421 { 422 const char *step_name = DISPLAY_RUNTIME_INFO(display)->step_name; 423 424 si->stepping = step_name[0] ?: '*'; 425 si->substepping = step_name[1] ?: '*'; 426 } 427 428 static void gen9_set_dc_state_debugmask(struct intel_display *display) 429 { 430 /* The below bit doesn't need to be cleared ever afterwards */ 431 intel_de_rmw(display, DC_STATE_DEBUG, 0, 432 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 433 intel_de_posting_read(display, DC_STATE_DEBUG); 434 } 435 436 static void disable_event_handler(struct intel_display *display, 437 intel_reg_t ctl_reg, intel_reg_t htp_reg) 438 { 439 intel_de_write(display, ctl_reg, 440 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 441 DMC_EVT_CTL_TYPE_EDGE_0_1) | 442 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 443 DMC_EVENT_FALSE)); 444 intel_de_write(display, htp_reg, 0); 445 } 446 447 static void disable_all_event_handlers(struct intel_display *display, 448 enum intel_dmc_id dmc_id) 449 { 450 int handler; 451 452 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 453 if (DISPLAY_VER(display) < 12) 454 return; 455 456 if (!has_dmc_id_fw(display, dmc_id)) 457 return; 458 459 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 460 disable_event_handler(display, 461 DMC_EVT_CTL(display, dmc_id, handler), 462 DMC_EVT_HTP(display, dmc_id, handler)); 463 } 464 465 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 466 { 467 enum pipe pipe; 468 469 /* 470 * Wa_16015201720:adl-p,dg2 471 * The WA requires clock gating to be disabled all the time 472 * for pipe A and B. 473 * For pipe C and D clock gating needs to be disabled only 474 * during initializing the firmware. 475 */ 476 if (enable) 477 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 478 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 479 0, PIPEDMC_GATING_DIS); 480 else 481 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 482 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 483 PIPEDMC_GATING_DIS, 0); 484 } 485 486 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) 487 { 488 /* 489 * Wa_16015201720 490 * The WA requires clock gating to be disabled all the time 491 * for pipe A and B. 492 */ 493 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, 494 MTL_PIPEDMC_GATING_DIS(PIPE_A) | 495 MTL_PIPEDMC_GATING_DIS(PIPE_B)); 496 } 497 498 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 499 { 500 if (display->platform.meteorlake && enable) 501 mtl_pipedmc_clock_gating_wa(display); 502 else if (DISPLAY_VER(display) == 13) 503 adlp_pipedmc_clock_gating_wa(display, enable); 504 } 505 506 static u32 pipedmc_interrupt_mask(struct intel_display *display) 507 { 508 if (DISPLAY_VER(display) >= 35) 509 return PIPEDMC_FLIPQ_PROG_DONE | 510 PIPEDMC_ERROR; 511 512 if (DISPLAY_VER(display) >= 30) 513 return PIPEDMC_FLIPQ_PROG_DONE | 514 PIPEDMC_GTT_FAULT | 515 PIPEDMC_ATS_FAULT | 516 PIPEDMC_ERROR; 517 518 /* 519 * FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B 520 * triggering it during the first DC state transition. Figure 521 * out what is going on... 522 */ 523 return PIPEDMC_FLIPQ_PROG_DONE | 524 PIPEDMC_GTT_FAULT | 525 PIPEDMC_ATS_FAULT; 526 } 527 528 static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl) 529 { 530 /* 531 * DMC_EVT_CTL_ENABLE cannot be cleared once set. Always 532 * configure it based on the original event definition to 533 * avoid mismatches in assert_dmc_loaded(). 534 */ 535 return (dmc_evt_ctl & DMC_EVT_CTL_ENABLE) | 536 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 537 DMC_EVT_CTL_TYPE_EDGE_0_1) | 538 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 539 DMC_EVENT_FALSE); 540 } 541 542 static bool is_dmc_evt_ctl_reg(struct intel_display *display, 543 enum intel_dmc_id dmc_id, intel_reg_t reg) 544 { 545 u32 offset = intel_reg_offset(reg); 546 u32 start = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); 547 u32 end = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 548 549 return offset >= start && offset < end; 550 } 551 552 static bool is_dmc_evt_htp_reg(struct intel_display *display, 553 enum intel_dmc_id dmc_id, intel_reg_t reg) 554 { 555 u32 offset = intel_reg_offset(reg); 556 u32 start = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); 557 u32 end = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 558 559 return offset >= start && offset < end; 560 } 561 562 static bool is_event_handler(struct intel_display *display, 563 enum intel_dmc_id dmc_id, 564 unsigned int event_id, 565 intel_reg_t reg, u32 data) 566 { 567 return is_dmc_evt_ctl_reg(display, dmc_id, reg) && 568 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id; 569 } 570 571 static bool fixup_dmc_evt(struct intel_display *display, 572 enum intel_dmc_id dmc_id, 573 intel_reg_t reg_ctl, u32 *data_ctl, 574 intel_reg_t reg_htp, u32 *data_htp) 575 { 576 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl)) 577 return false; 578 579 if (!is_dmc_evt_htp_reg(display, dmc_id, reg_htp)) 580 return false; 581 582 /* make sure reg_ctl and reg_htp are for the same event */ 583 if (intel_reg_offset(reg_ctl) - intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != 584 intel_reg_offset(reg_htp) - intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0))) 585 return false; 586 587 /* 588 * On ADL-S the HRR event handler is not restored after DC6. 589 * Clear it to zero from the beginning to avoid mismatches later. 590 */ 591 if (display->platform.alderlake_s && dmc_id == DMC_FW_MAIN && 592 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { 593 *data_ctl = 0; 594 *data_htp = 0; 595 return true; 596 } 597 598 /* 599 * TGL/ADL-S DMC firmware incorrectly uses the undelayed vblank 600 * event for the HRR handler, when it should be using the delayed 601 * vblank event instead. Fixed firmware was never released 602 * so the Windows driver just hacks around it by overriding 603 * the event ID. Do the same. 604 */ 605 if ((display->platform.tigerlake || display->platform.alderlake_s) && 606 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { 607 *data_ctl &= ~DMC_EVT_CTL_EVENT_ID_MASK; 608 *data_ctl |= REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 609 MAINDMC_EVENT_VBLANK_DELAYED_A); 610 return true; 611 } 612 613 return false; 614 } 615 616 static bool disable_dmc_evt(struct intel_display *display, 617 enum intel_dmc_id dmc_id, 618 intel_reg_t reg, u32 data) 619 { 620 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) 621 return false; 622 623 /* keep all pipe DMC events disabled by default */ 624 if (dmc_id != DMC_FW_MAIN) 625 return true; 626 627 /* also disable the flip queue event on the main DMC on TGL */ 628 if (display->platform.tigerlake && 629 is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data)) 630 return true; 631 632 /* also disable the HRR event on the main DMC on TGL/ADLS */ 633 if ((display->platform.tigerlake || display->platform.alderlake_s) && 634 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_DELAYED_A, reg, data)) 635 return true; 636 637 return false; 638 } 639 640 static u32 dmc_mmiodata(struct intel_display *display, 641 struct intel_dmc *dmc, 642 enum intel_dmc_id dmc_id, int i) 643 { 644 if (disable_dmc_evt(display, dmc_id, 645 dmc->dmc_info[dmc_id].mmioaddr[i], 646 dmc->dmc_info[dmc_id].mmiodata[i])) 647 return dmc_evt_ctl_disable(dmc->dmc_info[dmc_id].mmiodata[i]); 648 else 649 return dmc->dmc_info[dmc_id].mmiodata[i]; 650 } 651 652 static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id) 653 { 654 struct intel_dmc *dmc = display_to_dmc(display); 655 int i; 656 657 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 658 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], 659 dmc_mmiodata(display, dmc, dmc_id, i)); 660 } 661 } 662 663 static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id) 664 { 665 struct intel_dmc *dmc = display_to_dmc(display); 666 int i; 667 668 disable_all_event_handlers(display, dmc_id); 669 670 preempt_disable(); 671 672 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 673 intel_de_write_fw(display, 674 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 675 dmc->dmc_info[dmc_id].payload[i]); 676 } 677 678 preempt_enable(); 679 680 dmc_load_mmio(display, dmc_id); 681 } 682 683 static void assert_dmc_loaded(struct intel_display *display, 684 enum intel_dmc_id dmc_id) 685 { 686 struct intel_dmc *dmc = display_to_dmc(display); 687 u32 expected, found; 688 int i; 689 690 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 691 return; 692 693 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); 694 expected = dmc->dmc_info[dmc_id].payload[0]; 695 696 drm_WARN(display->drm, found != expected, 697 "DMC %d program storage start incorrect (expected 0x%x, current 0x%x)\n", 698 dmc_id, expected, found); 699 700 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 701 intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 702 703 found = intel_de_read(display, reg); 704 expected = dmc_mmiodata(display, dmc, dmc_id, i); 705 706 drm_WARN(display->drm, found != expected, 707 "DMC %d mmio[%d]/0x%x incorrect (expected 0x%x, current 0x%x)\n", 708 dmc_id, i, intel_reg_offset(reg), expected, found); 709 } 710 } 711 712 void assert_main_dmc_loaded(struct intel_display *display) 713 { 714 assert_dmc_loaded(display, DMC_FW_MAIN); 715 } 716 717 static bool need_pipedmc_load_program(struct intel_display *display) 718 { 719 /* On TGL/derivatives pipe DMC state is lost when PG1 is disabled */ 720 return DISPLAY_VER(display) == 12; 721 } 722 723 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe) 724 { 725 /* 726 * Xe3_LPD/Xe3p_LPD: 727 * - pipe A/B DMC doesn't need save/restore 728 * - pipe C/D DMC is in PG0, needs manual save/restore 729 */ 730 if (IS_DISPLAY_VER(display, 30, 35)) 731 return pipe >= PIPE_C; 732 733 /* 734 * FIXME LNL unclear, main DMC firmware has the pipe DMC A/B PG0 735 * save/restore, but so far unable to see the loss of pipe DMC state 736 * in action. Are we just failing to turn off PG0 due to some other 737 * SoC level stuff? 738 */ 739 if (DISPLAY_VER(display) == 20) 740 return false; 741 742 /* 743 * FIXME BMG untested, main DMC firmware has the 744 * pipe DMC A/B PG0 save/restore... 745 */ 746 if (display->platform.battlemage) 747 return false; 748 749 /* 750 * DG2: 751 * - Pipe DMCs presumably in PG0? 752 * - No DC6, and even DC9 doesn't seem to result 753 * in loss of DMC state for whatever reason 754 */ 755 if (display->platform.dg2) 756 return false; 757 758 /* 759 * ADL/MTL: 760 * - pipe A/B DMC is in PG0, saved/restored by the main DMC 761 * - pipe C/D DMC is in PG0, needs manual save/restore 762 */ 763 if (IS_DISPLAY_VER(display, 13, 14)) 764 return pipe >= PIPE_C; 765 766 return false; 767 } 768 769 static bool can_enable_pipedmc(const struct intel_crtc_state *crtc_state) 770 { 771 struct intel_display *display = to_intel_display(crtc_state); 772 773 /* 774 * On TGL/derivatives pipe DMC state is lost when PG1 is disabled. 775 * Do not even enable the pipe DMC when that can happen outside 776 * of driver control (PSR+DC5/6). 777 */ 778 if (DISPLAY_VER(display) == 12 && crtc_state->has_psr) 779 return false; 780 781 return true; 782 } 783 784 void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state) 785 { 786 struct intel_display *display = to_intel_display(crtc_state); 787 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 788 enum pipe pipe = crtc->pipe; 789 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 790 791 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 792 return; 793 794 if (!can_enable_pipedmc(crtc_state)) { 795 intel_dmc_disable_pipe(crtc_state); 796 return; 797 } 798 799 if (need_pipedmc_load_program(display)) 800 dmc_load_program(display, dmc_id); 801 else if (need_pipedmc_load_mmio(display, pipe)) 802 dmc_load_mmio(display, dmc_id); 803 804 assert_dmc_loaded(display, dmc_id); 805 806 if (DISPLAY_VER(display) >= 20) { 807 intel_flipq_reset(display, pipe); 808 809 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 810 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display)); 811 } 812 813 if (DISPLAY_VER(display) >= 14) 814 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 815 else 816 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 817 } 818 819 void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state) 820 { 821 struct intel_display *display = to_intel_display(crtc_state); 822 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 823 enum pipe pipe = crtc->pipe; 824 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 825 826 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 827 return; 828 829 if (DISPLAY_VER(display) >= 14) 830 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 831 else 832 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 833 834 if (DISPLAY_VER(display) >= 20) { 835 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0); 836 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 837 838 intel_flipq_reset(display, pipe); 839 } 840 } 841 842 static void dmc_configure_event(struct intel_display *display, 843 enum intel_dmc_id dmc_id, 844 unsigned int event_id, 845 bool enable) 846 { 847 struct intel_dmc *dmc = display_to_dmc(display); 848 int num_handlers = 0; 849 int i; 850 851 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 852 intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 853 u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; 854 855 if (!is_event_handler(display, dmc_id, event_id, reg, data)) 856 continue; 857 858 intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable(data)); 859 num_handlers++; 860 } 861 862 drm_WARN_ONCE(display->drm, num_handlers != 1, 863 "DMC %d has %d handlers for event 0x%x\n", 864 dmc_id, num_handlers, event_id); 865 } 866 867 void intel_dmc_configure_dc_balance_event(struct intel_display *display, 868 enum pipe pipe, bool enable) 869 { 870 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 871 872 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable); 873 } 874 875 /** 876 * intel_dmc_block_pkgc() - block PKG C-state 877 * @display: display instance 878 * @pipe: pipe which register use to block 879 * @block: block/unblock 880 * 881 * This interface is target for Wa_16025596647 usage. I.e. to set/clear 882 * PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register. 883 */ 884 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, 885 bool block) 886 { 887 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), 888 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, block ? 889 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0); 890 } 891 892 /** 893 * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG 894 * C-state exit 895 * @display: display instance 896 * @pipe: pipe which register use to block 897 * @enable: enable/disable 898 * 899 * This interface is target for Wa_16025596647 usage. I.e. start the package C 900 * exit at the start of the undelayed vblank 901 */ 902 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, 903 enum pipe pipe, bool enable) 904 { 905 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 906 907 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable); 908 } 909 910 /** 911 * intel_dmc_load_program() - write the firmware from memory to register. 912 * @display: display instance 913 * 914 * DMC firmware is read from a .bin file and kept in internal memory one time. 915 * Everytime display comes back from low power state this function is called to 916 * copy the firmware from internal memory to registers. 917 */ 918 void intel_dmc_load_program(struct intel_display *display) 919 { 920 struct i915_power_domains *power_domains = &display->power.domains; 921 enum intel_dmc_id dmc_id; 922 923 if (!intel_dmc_has_payload(display)) 924 return; 925 926 assert_display_rpm_held(display); 927 928 pipedmc_clock_gating_wa(display, true); 929 930 for_each_dmc_id(dmc_id) { 931 dmc_load_program(display, dmc_id); 932 assert_dmc_loaded(display, dmc_id); 933 } 934 935 if (DISPLAY_VER(display) >= 20) 936 intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL, 937 PIPE_D_DMC_W2_PTS_CONFIG_SELECT(PIPE_D) | 938 PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) | 939 PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) | 940 PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A)); 941 942 power_domains->dc_state = 0; 943 944 gen9_set_dc_state_debugmask(display); 945 946 xe3lpd_enable_dc_count(display); 947 948 pipedmc_clock_gating_wa(display, false); 949 } 950 951 /** 952 * intel_dmc_disable_program() - disable the firmware 953 * @display: display instance 954 * 955 * Disable all event handlers in the firmware, making sure the firmware is 956 * inactive after the display is uninitialized. 957 */ 958 void intel_dmc_disable_program(struct intel_display *display) 959 { 960 enum intel_dmc_id dmc_id; 961 962 if (!intel_dmc_has_payload(display)) 963 return; 964 965 pipedmc_clock_gating_wa(display, true); 966 967 for_each_dmc_id(dmc_id) 968 disable_all_event_handlers(display, dmc_id); 969 970 pipedmc_clock_gating_wa(display, false); 971 } 972 973 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 974 const struct stepping_info *si) 975 { 976 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 977 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 978 /* 979 * If we don't find a more specific one from above two checks, we 980 * then check for the generic one to be sure to work even with 981 * "broken firmware" 982 */ 983 (si->stepping == '*' && si->substepping == fw_info->substepping) || 984 (fw_info->stepping == '*' && fw_info->substepping == '*')) 985 return true; 986 987 return false; 988 } 989 990 /* 991 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 992 * already sanitized. 993 */ 994 static void dmc_set_fw_offset(struct intel_dmc *dmc, 995 const struct intel_fw_info *fw_info, 996 unsigned int num_entries, 997 const struct stepping_info *si, 998 u8 package_ver) 999 { 1000 struct intel_display *display = dmc->display; 1001 enum intel_dmc_id dmc_id; 1002 unsigned int i; 1003 1004 for (i = 0; i < num_entries; i++) { 1005 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 1006 1007 if (!is_valid_dmc_id(dmc_id)) { 1008 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); 1009 continue; 1010 } 1011 1012 /* More specific versions come first, so we don't even have to 1013 * check for the stepping since we already found a previous FW 1014 * for this id. 1015 */ 1016 if (dmc->dmc_info[dmc_id].present) 1017 continue; 1018 1019 if (fw_info_matches_stepping(&fw_info[i], si)) { 1020 dmc->dmc_info[dmc_id].present = true; 1021 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 1022 } 1023 } 1024 } 1025 1026 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 1027 const u32 *mmioaddr, u32 mmio_count, 1028 int header_ver, enum intel_dmc_id dmc_id) 1029 { 1030 struct intel_display *display = dmc->display; 1031 u32 start_range, end_range; 1032 int i; 1033 1034 if (header_ver == 1) { 1035 start_range = DMC_MMIO_START_RANGE; 1036 end_range = DMC_MMIO_END_RANGE; 1037 } else if (dmc_id == DMC_FW_MAIN) { 1038 start_range = TGL_MAIN_MMIO_START; 1039 end_range = TGL_MAIN_MMIO_END; 1040 } else if (DISPLAY_VER(display) >= 13) { 1041 start_range = ADLP_PIPE_MMIO_START; 1042 end_range = ADLP_PIPE_MMIO_END; 1043 } else if (DISPLAY_VER(display) >= 12) { 1044 start_range = TGL_PIPE_MMIO_START(dmc_id); 1045 end_range = TGL_PIPE_MMIO_END(dmc_id); 1046 } else { 1047 drm_warn(display->drm, "Unknown mmio range for sanity check"); 1048 return false; 1049 } 1050 1051 for (i = 0; i < mmio_count; i++) { 1052 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 1053 return false; 1054 } 1055 1056 return true; 1057 } 1058 1059 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 1060 const struct intel_dmc_header_base *dmc_header, 1061 size_t rem_size, enum intel_dmc_id dmc_id) 1062 { 1063 struct intel_display *display = dmc->display; 1064 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 1065 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 1066 const u32 *mmioaddr, *mmiodata; 1067 u32 mmio_count, mmio_count_max, start_mmioaddr; 1068 u8 *payload; 1069 1070 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 1071 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 1072 1073 /* 1074 * Check if we can access common fields, we will checkc again below 1075 * after we have read the version 1076 */ 1077 if (rem_size < sizeof(struct intel_dmc_header_base)) 1078 goto error_truncated; 1079 1080 /* Cope with small differences between v1 and v3 */ 1081 if (dmc_header->header_ver == 3) { 1082 const struct intel_dmc_header_v3 *v3 = 1083 (const struct intel_dmc_header_v3 *)dmc_header; 1084 1085 if (rem_size < sizeof(struct intel_dmc_header_v3)) 1086 goto error_truncated; 1087 1088 mmioaddr = v3->mmioaddr; 1089 mmiodata = v3->mmiodata; 1090 mmio_count = v3->mmio_count; 1091 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 1092 /* header_len is in dwords */ 1093 header_len_bytes = dmc_header->header_len * 4; 1094 start_mmioaddr = v3->start_mmioaddr; 1095 dmc_header_size = sizeof(*v3); 1096 } else if (dmc_header->header_ver == 1) { 1097 const struct intel_dmc_header_v1 *v1 = 1098 (const struct intel_dmc_header_v1 *)dmc_header; 1099 1100 if (rem_size < sizeof(struct intel_dmc_header_v1)) 1101 goto error_truncated; 1102 1103 mmioaddr = v1->mmioaddr; 1104 mmiodata = v1->mmiodata; 1105 mmio_count = v1->mmio_count; 1106 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 1107 header_len_bytes = dmc_header->header_len; 1108 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 1109 dmc_header_size = sizeof(*v1); 1110 } else { 1111 drm_err(display->drm, "Unknown DMC fw header version: %u\n", 1112 dmc_header->header_ver); 1113 return 0; 1114 } 1115 1116 if (header_len_bytes != dmc_header_size) { 1117 drm_err(display->drm, "DMC firmware has wrong dmc header length " 1118 "(%u bytes)\n", header_len_bytes); 1119 return 0; 1120 } 1121 1122 /* Cache the dmc header info. */ 1123 if (mmio_count > mmio_count_max) { 1124 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 1125 return 0; 1126 } 1127 1128 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 1129 dmc_header->header_ver, dmc_id)) { 1130 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); 1131 return 0; 1132 } 1133 1134 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); 1135 for (i = 0; i < mmio_count; i++) { 1136 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 1137 dmc_info->mmiodata[i] = mmiodata[i]; 1138 } 1139 1140 for (i = 0; i < mmio_count - 1; i++) { 1141 u32 orig_mmiodata[2] = { 1142 dmc_info->mmiodata[i], 1143 dmc_info->mmiodata[i+1], 1144 }; 1145 1146 if (!fixup_dmc_evt(display, dmc_id, 1147 dmc_info->mmioaddr[i], &dmc_info->mmiodata[i], 1148 dmc_info->mmioaddr[i+1], &dmc_info->mmiodata[i+1])) 1149 continue; 1150 1151 drm_dbg_kms(display->drm, 1152 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_CTL)\n", 1153 i, intel_reg_offset(dmc_info->mmioaddr[i]), 1154 orig_mmiodata[0], dmc_info->mmiodata[i]); 1155 drm_dbg_kms(display->drm, 1156 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_HTP)\n", 1157 i+1, intel_reg_offset(dmc_info->mmioaddr[i+1]), 1158 orig_mmiodata[1], dmc_info->mmiodata[i+1]); 1159 } 1160 1161 for (i = 0; i < mmio_count; i++) { 1162 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 1163 i, intel_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i], 1164 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 1165 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 1166 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], 1167 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 1168 } 1169 dmc_info->mmio_count = mmio_count; 1170 dmc_info->start_mmioaddr = start_mmioaddr; 1171 1172 rem_size -= header_len_bytes; 1173 1174 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 1175 payload_size = dmc_header->fw_size * 4; 1176 if (rem_size < payload_size) 1177 goto error_truncated; 1178 1179 if (payload_size > dmc->max_fw_size) { 1180 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); 1181 return 0; 1182 } 1183 dmc_info->dmc_fw_size = dmc_header->fw_size; 1184 1185 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 1186 if (!dmc_info->payload) 1187 return 0; 1188 1189 payload = (u8 *)(dmc_header) + header_len_bytes; 1190 memcpy(dmc_info->payload, payload, payload_size); 1191 1192 return header_len_bytes + payload_size; 1193 1194 error_truncated: 1195 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1196 return 0; 1197 } 1198 1199 static u32 1200 parse_dmc_fw_package(struct intel_dmc *dmc, 1201 const struct intel_package_header *package_header, 1202 const struct stepping_info *si, 1203 size_t rem_size) 1204 { 1205 struct intel_display *display = dmc->display; 1206 u32 package_size = sizeof(struct intel_package_header); 1207 u32 num_entries, max_entries; 1208 const struct intel_fw_info *fw_info; 1209 1210 if (rem_size < package_size) 1211 goto error_truncated; 1212 1213 if (package_header->header_ver == 1) { 1214 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 1215 } else if (package_header->header_ver == 2) { 1216 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 1217 } else { 1218 drm_err(display->drm, "DMC firmware has unknown header version %u\n", 1219 package_header->header_ver); 1220 return 0; 1221 } 1222 1223 /* 1224 * We should always have space for max_entries, 1225 * even if not all are used 1226 */ 1227 package_size += max_entries * sizeof(struct intel_fw_info); 1228 if (rem_size < package_size) 1229 goto error_truncated; 1230 1231 if (package_header->header_len * 4 != package_size) { 1232 drm_err(display->drm, "DMC firmware has wrong package header length " 1233 "(%u bytes)\n", package_size); 1234 return 0; 1235 } 1236 1237 num_entries = package_header->num_entries; 1238 if (WARN_ON(num_entries > max_entries)) 1239 num_entries = max_entries; 1240 1241 fw_info = (const struct intel_fw_info *) 1242 ((u8 *)package_header + sizeof(*package_header)); 1243 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 1244 package_header->header_ver); 1245 1246 /* dmc_offset is in dwords */ 1247 return package_size; 1248 1249 error_truncated: 1250 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1251 return 0; 1252 } 1253 1254 /* Return number of bytes parsed or 0 on error */ 1255 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 1256 struct intel_css_header *css_header, 1257 size_t rem_size) 1258 { 1259 struct intel_display *display = dmc->display; 1260 1261 if (rem_size < sizeof(struct intel_css_header)) { 1262 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1263 return 0; 1264 } 1265 1266 if (sizeof(struct intel_css_header) != 1267 (css_header->header_len * 4)) { 1268 drm_err(display->drm, "DMC firmware has wrong CSS header length " 1269 "(%u bytes)\n", 1270 (css_header->header_len * 4)); 1271 return 0; 1272 } 1273 1274 dmc->version = css_header->version; 1275 1276 return sizeof(struct intel_css_header); 1277 } 1278 1279 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 1280 { 1281 struct intel_display *display = dmc->display; 1282 struct intel_css_header *css_header; 1283 struct intel_package_header *package_header; 1284 struct intel_dmc_header_base *dmc_header; 1285 struct stepping_info si = {}; 1286 enum intel_dmc_id dmc_id; 1287 u32 readcount = 0; 1288 u32 r, offset; 1289 1290 if (!fw) 1291 return -EINVAL; 1292 1293 initialize_stepping_info(display, &si); 1294 1295 /* Extract CSS Header information */ 1296 css_header = (struct intel_css_header *)fw->data; 1297 r = parse_dmc_fw_css(dmc, css_header, fw->size); 1298 if (!r) 1299 return -EINVAL; 1300 1301 readcount += r; 1302 1303 /* Extract Package Header information */ 1304 package_header = (struct intel_package_header *)&fw->data[readcount]; 1305 r = parse_dmc_fw_package(dmc, package_header, &si, fw->size - readcount); 1306 if (!r) 1307 return -EINVAL; 1308 1309 readcount += r; 1310 1311 for_each_dmc_id(dmc_id) { 1312 if (!dmc->dmc_info[dmc_id].present) 1313 continue; 1314 1315 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 1316 if (offset > fw->size) { 1317 drm_err(display->drm, "Reading beyond the fw_size\n"); 1318 continue; 1319 } 1320 1321 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 1322 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 1323 } 1324 1325 if (!intel_dmc_has_payload(display)) { 1326 drm_err(display->drm, "DMC firmware main program not found\n"); 1327 return -ENOENT; 1328 } 1329 1330 return 0; 1331 } 1332 1333 static void intel_dmc_runtime_pm_get(struct intel_display *display) 1334 { 1335 drm_WARN_ON(display->drm, display->dmc.wakeref); 1336 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); 1337 } 1338 1339 static void intel_dmc_runtime_pm_put(struct intel_display *display) 1340 { 1341 struct ref_tracker *wakeref __maybe_unused = 1342 fetch_and_zero(&display->dmc.wakeref); 1343 1344 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 1345 } 1346 1347 static const char *dmc_fallback_path(struct intel_display *display) 1348 { 1349 if (display->platform.alderlake_p) 1350 return ADLP_DMC_FALLBACK_PATH; 1351 1352 return NULL; 1353 } 1354 1355 static void dmc_load_work_fn(struct work_struct *work) 1356 { 1357 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1358 struct intel_display *display = dmc->display; 1359 const struct firmware *fw = NULL; 1360 const char *fallback_path; 1361 int err; 1362 1363 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); 1364 1365 if (err == -ENOENT && !dmc_firmware_param(display)) { 1366 fallback_path = dmc_fallback_path(display); 1367 if (fallback_path) { 1368 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", 1369 dmc->fw_path, fallback_path); 1370 err = request_firmware(&fw, fallback_path, display->drm->dev); 1371 if (err == 0) 1372 dmc->fw_path = fallback_path; 1373 } 1374 } 1375 1376 if (err) { 1377 drm_notice(display->drm, 1378 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1379 dmc->fw_path, ERR_PTR(err)); 1380 drm_notice(display->drm, "DMC firmware homepage: %s", 1381 INTEL_DMC_FIRMWARE_URL); 1382 return; 1383 } 1384 1385 err = parse_dmc_fw(dmc, fw); 1386 if (err) { 1387 drm_notice(display->drm, 1388 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1389 dmc->fw_path, ERR_PTR(err)); 1390 goto out; 1391 } 1392 1393 intel_dmc_load_program(display); 1394 intel_dmc_runtime_pm_put(display); 1395 1396 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1397 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1398 DMC_VERSION_MINOR(dmc->version)); 1399 1400 out: 1401 release_firmware(fw); 1402 } 1403 1404 /** 1405 * intel_dmc_init() - initialize the firmware loading. 1406 * @display: display instance 1407 * 1408 * This function is called at the time of loading the display driver to read 1409 * firmware from a .bin file and copied into a internal memory. 1410 */ 1411 void intel_dmc_init(struct intel_display *display) 1412 { 1413 struct intel_dmc *dmc; 1414 1415 if (!HAS_DMC(display)) 1416 return; 1417 1418 /* 1419 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1420 * runtime-suspend. 1421 * 1422 * On error, we return with the rpm wakeref held to prevent runtime 1423 * suspend as runtime suspend *requires* a working DMC for whatever 1424 * reason. 1425 */ 1426 intel_dmc_runtime_pm_get(display); 1427 1428 dmc = kzalloc_obj(*dmc); 1429 if (!dmc) 1430 return; 1431 1432 dmc->display = display; 1433 1434 INIT_WORK(&dmc->work, dmc_load_work_fn); 1435 1436 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); 1437 1438 if (dmc_firmware_param_disabled(display)) { 1439 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); 1440 goto out; 1441 } 1442 1443 if (dmc_firmware_param(display)) 1444 dmc->fw_path = dmc_firmware_param(display); 1445 1446 if (!dmc->fw_path) { 1447 drm_dbg_kms(display->drm, 1448 "No known DMC firmware for platform, disabling runtime PM\n"); 1449 goto out; 1450 } 1451 1452 display->dmc.dmc = dmc; 1453 1454 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); 1455 queue_work(display->wq.unordered, &dmc->work); 1456 1457 return; 1458 1459 out: 1460 kfree(dmc); 1461 } 1462 1463 /** 1464 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1465 * @display: display instance 1466 * 1467 * Prepare the DMC firmware before entering system suspend. This includes 1468 * flushing pending work items and releasing any resources acquired during 1469 * init. 1470 */ 1471 void intel_dmc_suspend(struct intel_display *display) 1472 { 1473 struct intel_dmc *dmc = display_to_dmc(display); 1474 1475 if (!HAS_DMC(display)) 1476 return; 1477 1478 if (dmc) 1479 flush_work(&dmc->work); 1480 1481 /* Drop the reference held in case DMC isn't loaded. */ 1482 if (!intel_dmc_has_payload(display)) 1483 intel_dmc_runtime_pm_put(display); 1484 } 1485 1486 void intel_dmc_wait_fw_load(struct intel_display *display) 1487 { 1488 struct intel_dmc *dmc = display_to_dmc(display); 1489 1490 if (!HAS_DMC(display)) 1491 return; 1492 1493 if (dmc) 1494 flush_work(&dmc->work); 1495 } 1496 1497 /** 1498 * intel_dmc_resume() - init DMC firmware during system resume 1499 * @display: display instance 1500 * 1501 * Reinitialize the DMC firmware during system resume, reacquiring any 1502 * resources released in intel_dmc_suspend(). 1503 */ 1504 void intel_dmc_resume(struct intel_display *display) 1505 { 1506 if (!HAS_DMC(display)) 1507 return; 1508 1509 /* 1510 * Reacquire the reference to keep RPM disabled in case DMC isn't 1511 * loaded. 1512 */ 1513 if (!intel_dmc_has_payload(display)) 1514 intel_dmc_runtime_pm_get(display); 1515 } 1516 1517 /** 1518 * intel_dmc_fini() - unload the DMC firmware. 1519 * @display: display instance 1520 * 1521 * Firmmware unloading includes freeing the internal memory and reset the 1522 * firmware loading status. 1523 */ 1524 void intel_dmc_fini(struct intel_display *display) 1525 { 1526 struct intel_dmc *dmc = display_to_dmc(display); 1527 enum intel_dmc_id dmc_id; 1528 1529 if (!HAS_DMC(display)) 1530 return; 1531 1532 intel_dmc_suspend(display); 1533 drm_WARN_ON(display->drm, display->dmc.wakeref); 1534 1535 if (dmc) { 1536 for_each_dmc_id(dmc_id) 1537 kfree(dmc->dmc_info[dmc_id].payload); 1538 1539 kfree(dmc); 1540 display->dmc.dmc = NULL; 1541 } 1542 } 1543 1544 struct intel_dmc_snapshot { 1545 bool initialized; 1546 bool loaded; 1547 u32 version; 1548 }; 1549 1550 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) 1551 { 1552 struct intel_dmc *dmc = display_to_dmc(display); 1553 struct intel_dmc_snapshot *snapshot; 1554 1555 if (!HAS_DMC(display)) 1556 return NULL; 1557 1558 snapshot = kzalloc_obj(*snapshot, GFP_ATOMIC); 1559 if (!snapshot) 1560 return NULL; 1561 1562 snapshot->initialized = dmc; 1563 snapshot->loaded = intel_dmc_has_payload(display); 1564 if (dmc) 1565 snapshot->version = dmc->version; 1566 1567 return snapshot; 1568 } 1569 1570 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p) 1571 { 1572 if (!snapshot) 1573 return; 1574 1575 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized)); 1576 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded)); 1577 if (snapshot->initialized) 1578 drm_printf(p, "DMC fw version: %d.%d\n", 1579 DMC_VERSION_MAJOR(snapshot->version), 1580 DMC_VERSION_MINOR(snapshot->version)); 1581 } 1582 1583 void intel_dmc_update_dc6_allowed_count(struct intel_display *display, 1584 bool start_tracking) 1585 { 1586 struct intel_dmc *dmc = display_to_dmc(display); 1587 u32 dc5_cur_count; 1588 1589 if (DISPLAY_VER(display) < 14) 1590 return; 1591 1592 dc5_cur_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT); 1593 1594 if (!start_tracking) 1595 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start; 1596 1597 dmc->dc6_allowed.dc5_start = dc5_cur_count; 1598 } 1599 1600 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count) 1601 { 1602 struct i915_power_domains *power_domains = &display->power.domains; 1603 struct intel_dmc *dmc = display_to_dmc(display); 1604 bool dc6_enabled; 1605 1606 if (DISPLAY_VER(display) < 14) 1607 return false; 1608 1609 mutex_lock(&power_domains->lock); 1610 dc6_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6; 1611 if (dc6_enabled) 1612 intel_dmc_update_dc6_allowed_count(display, false); 1613 1614 *count = dmc->dc6_allowed.count; 1615 mutex_unlock(&power_domains->lock); 1616 1617 return true; 1618 } 1619 1620 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1621 { 1622 struct intel_display *display = m->private; 1623 struct intel_dmc *dmc = display_to_dmc(display); 1624 struct ref_tracker *wakeref; 1625 intel_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1626 u32 dc6_allowed_count; 1627 1628 if (!HAS_DMC(display)) 1629 return -ENODEV; 1630 1631 wakeref = intel_display_rpm_get(display); 1632 1633 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1634 seq_printf(m, "fw loaded: %s\n", 1635 str_yes_no(intel_dmc_has_payload(display))); 1636 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1637 seq_printf(m, "Pipe A fw needed: %s\n", 1638 str_yes_no(DISPLAY_VER(display) >= 12)); 1639 seq_printf(m, "Pipe A fw loaded: %s\n", 1640 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); 1641 seq_printf(m, "Pipe B fw needed: %s\n", 1642 str_yes_no(display->platform.alderlake_p || 1643 DISPLAY_VER(display) >= 14)); 1644 seq_printf(m, "Pipe B fw loaded: %s\n", 1645 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); 1646 1647 if (!intel_dmc_has_payload(display)) 1648 goto out; 1649 1650 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1651 DMC_VERSION_MINOR(dmc->version)); 1652 1653 if (DISPLAY_VER(display) >= 12) { 1654 if (DISPLAY_VER(display) >= 35) { 1655 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1656 seq_printf(m, "DC3CO count: %d\n", 1657 intel_de_read(display, XE3P_DMC_DC3CO_COUNT)); 1658 1659 seq_printf(m, "DC3CO residency: %d\n", 1660 intel_de_read(display, DC_STATE_DC3CO_RESIDENCY)); 1661 } else if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { 1662 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1663 } else { 1664 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1665 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1666 } 1667 1668 } else { 1669 dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT : 1670 SKL_DMC_DC3_DC5_COUNT; 1671 if (!display->platform.geminilake && !display->platform.broxton) 1672 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1673 } 1674 1675 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); 1676 1677 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) 1678 seq_printf(m, "DC5 -> DC6 allowed count: %d\n", 1679 dc6_allowed_count); 1680 else if (intel_reg_valid(dc6_reg)) 1681 seq_printf(m, "DC5 -> DC6 count: %d\n", 1682 intel_de_read(display, dc6_reg)); 1683 1684 seq_printf(m, "program base: 0x%08x\n", 1685 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1686 1687 out: 1688 seq_printf(m, "ssp base: 0x%08x\n", 1689 intel_de_read(display, DMC_SSP_BASE)); 1690 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); 1691 1692 intel_display_rpm_put(display, wakeref); 1693 1694 return 0; 1695 } 1696 1697 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1698 1699 void intel_dmc_debugfs_register(struct intel_display *display) 1700 { 1701 debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root, 1702 display, &intel_dmc_debugfs_status_fops); 1703 } 1704 1705 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe) 1706 { 1707 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 1708 u32 tmp = 0, int_vector; 1709 1710 if (DISPLAY_VER(display) >= 20) { 1711 tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe)); 1712 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp); 1713 1714 if (tmp & PIPEDMC_FLIPQ_PROG_DONE) { 1715 spin_lock(&display->drm->event_lock); 1716 1717 if (crtc->flipq_event) { 1718 /* 1719 * Update vblank counter/timestamp in case it 1720 * hasn't been done yet for this frame. 1721 */ 1722 drm_crtc_accurate_vblank_count(&crtc->base); 1723 1724 drm_crtc_send_vblank_event(&crtc->base, crtc->flipq_event); 1725 crtc->flipq_event = NULL; 1726 } 1727 1728 spin_unlock(&display->drm->event_lock); 1729 } 1730 1731 if (tmp & PIPEDMC_ATS_FAULT) 1732 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n", 1733 crtc->base.base.id, crtc->base.name); 1734 if (tmp & PIPEDMC_GTT_FAULT) 1735 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n", 1736 crtc->base.base.id, crtc->base.name); 1737 if (tmp & PIPEDMC_ERROR) 1738 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC error\n", 1739 crtc->base.base.id, crtc->base.name); 1740 } 1741 1742 int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK; 1743 if (tmp == 0 && int_vector != 0) 1744 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC interrupt vector 0x%x\n", 1745 crtc->base.base.id, crtc->base.name, int_vector); 1746 } 1747 1748 void intel_pipedmc_enable_event(struct intel_crtc *crtc, 1749 enum pipedmc_event_id event) 1750 { 1751 struct intel_display *display = to_intel_display(crtc); 1752 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1753 1754 dmc_configure_event(display, dmc_id, event, true); 1755 } 1756 1757 void intel_pipedmc_disable_event(struct intel_crtc *crtc, 1758 enum pipedmc_event_id event) 1759 { 1760 struct intel_display *display = to_intel_display(crtc); 1761 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1762 1763 dmc_configure_event(display, dmc_id, event, false); 1764 } 1765 1766 u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc) 1767 { 1768 struct intel_display *display = to_intel_display(crtc); 1769 struct intel_dmc *dmc = display_to_dmc(display); 1770 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1771 1772 return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0; 1773 } 1774 1775 void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc) 1776 { 1777 struct intel_display *display = to_intel_display(crtc); 1778 enum pipe pipe = crtc->pipe; 1779 1780 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 1781 PIPEDMC_ADAPTIVE_DCB_ENABLE); 1782 } 1783 1784 void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc) 1785 { 1786 struct intel_display *display = to_intel_display(crtc); 1787 enum pipe pipe = crtc->pipe; 1788 1789 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0); 1790 } 1791