1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_de.h" 30 #include "intel_dmc.h" 31 32 /** 33 * DOC: DMC Firmware Support 34 * 35 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 36 * engine to save and restore the state of display engine when it enter into 37 * low-power state and comes back to normal. 38 */ 39 40 #define DMC_PATH(platform, major, minor) \ 41 "i915/" \ 42 __stringify(platform) "_dmc_ver" \ 43 __stringify(major) "_" \ 44 __stringify(minor) ".bin" 45 46 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 47 48 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 49 50 #define ADLP_DMC_PATH DMC_PATH(adlp, 2, 14) 51 #define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 14) 52 MODULE_FIRMWARE(ADLP_DMC_PATH); 53 54 #define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) 55 #define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1) 56 MODULE_FIRMWARE(ADLS_DMC_PATH); 57 58 #define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) 59 #define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) 60 MODULE_FIRMWARE(DG1_DMC_PATH); 61 62 #define RKL_DMC_PATH DMC_PATH(rkl, 2, 03) 63 #define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 3) 64 MODULE_FIRMWARE(RKL_DMC_PATH); 65 66 #define TGL_DMC_PATH DMC_PATH(tgl, 2, 12) 67 #define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 12) 68 MODULE_FIRMWARE(TGL_DMC_PATH); 69 70 #define ICL_DMC_PATH DMC_PATH(icl, 1, 09) 71 #define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) 72 #define ICL_DMC_MAX_FW_SIZE 0x6000 73 MODULE_FIRMWARE(ICL_DMC_PATH); 74 75 #define GLK_DMC_PATH DMC_PATH(glk, 1, 04) 76 #define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 77 #define GLK_DMC_MAX_FW_SIZE 0x4000 78 MODULE_FIRMWARE(GLK_DMC_PATH); 79 80 #define KBL_DMC_PATH DMC_PATH(kbl, 1, 04) 81 #define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 82 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 83 MODULE_FIRMWARE(KBL_DMC_PATH); 84 85 #define SKL_DMC_PATH DMC_PATH(skl, 1, 27) 86 #define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27) 87 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 88 MODULE_FIRMWARE(SKL_DMC_PATH); 89 90 #define BXT_DMC_PATH DMC_PATH(bxt, 1, 07) 91 #define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) 92 #define BXT_DMC_MAX_FW_SIZE 0x3000 93 MODULE_FIRMWARE(BXT_DMC_PATH); 94 95 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 96 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 97 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 98 #define DMC_V1_MAX_MMIO_COUNT 8 99 #define DMC_V3_MAX_MMIO_COUNT 20 100 #define DMC_V1_MMIO_START_RANGE 0x80000 101 102 struct intel_css_header { 103 /* 0x09 for DMC */ 104 u32 module_type; 105 106 /* Includes the DMC specific header in dwords */ 107 u32 header_len; 108 109 /* always value would be 0x10000 */ 110 u32 header_ver; 111 112 /* Not used */ 113 u32 module_id; 114 115 /* Not used */ 116 u32 module_vendor; 117 118 /* in YYYYMMDD format */ 119 u32 date; 120 121 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 122 u32 size; 123 124 /* Not used */ 125 u32 key_size; 126 127 /* Not used */ 128 u32 modulus_size; 129 130 /* Not used */ 131 u32 exponent_size; 132 133 /* Not used */ 134 u32 reserved1[12]; 135 136 /* Major Minor */ 137 u32 version; 138 139 /* Not used */ 140 u32 reserved2[8]; 141 142 /* Not used */ 143 u32 kernel_header_info; 144 } __packed; 145 146 struct intel_fw_info { 147 u8 reserved1; 148 149 /* reserved on package_header version 1, must be 0 on version 2 */ 150 u8 dmc_id; 151 152 /* Stepping (A, B, C, ..., *). * is a wildcard */ 153 char stepping; 154 155 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 156 char substepping; 157 158 u32 offset; 159 u32 reserved2; 160 } __packed; 161 162 struct intel_package_header { 163 /* DMC container header length in dwords */ 164 u8 header_len; 165 166 /* 0x01, 0x02 */ 167 u8 header_ver; 168 169 u8 reserved[10]; 170 171 /* Number of valid entries in the FWInfo array below */ 172 u32 num_entries; 173 } __packed; 174 175 struct intel_dmc_header_base { 176 /* always value would be 0x40403E3E */ 177 u32 signature; 178 179 /* DMC binary header length */ 180 u8 header_len; 181 182 /* 0x01 */ 183 u8 header_ver; 184 185 /* Reserved */ 186 u16 dmcc_ver; 187 188 /* Major, Minor */ 189 u32 project; 190 191 /* Firmware program size (excluding header) in dwords */ 192 u32 fw_size; 193 194 /* Major Minor version */ 195 u32 fw_version; 196 } __packed; 197 198 struct intel_dmc_header_v1 { 199 struct intel_dmc_header_base base; 200 201 /* Number of valid MMIO cycles present. */ 202 u32 mmio_count; 203 204 /* MMIO address */ 205 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 206 207 /* MMIO data */ 208 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 209 210 /* FW filename */ 211 char dfile[32]; 212 213 u32 reserved1[2]; 214 } __packed; 215 216 struct intel_dmc_header_v3 { 217 struct intel_dmc_header_base base; 218 219 /* DMC RAM start MMIO address */ 220 u32 start_mmioaddr; 221 222 u32 reserved[9]; 223 224 /* FW filename */ 225 char dfile[32]; 226 227 /* Number of valid MMIO cycles present. */ 228 u32 mmio_count; 229 230 /* MMIO address */ 231 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 232 233 /* MMIO data */ 234 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 235 } __packed; 236 237 struct stepping_info { 238 char stepping; 239 char substepping; 240 }; 241 242 bool intel_dmc_has_payload(struct drm_i915_private *i915) 243 { 244 return i915->dmc.dmc_info[DMC_FW_MAIN].payload; 245 } 246 247 static const struct stepping_info * 248 intel_get_stepping_info(struct drm_i915_private *i915, 249 struct stepping_info *si) 250 { 251 const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step); 252 253 si->stepping = step_name[0]; 254 si->substepping = step_name[1]; 255 return si; 256 } 257 258 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 259 { 260 /* The below bit doesn't need to be cleared ever afterwards */ 261 intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0, 262 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 263 intel_de_posting_read(dev_priv, DC_STATE_DEBUG); 264 } 265 266 /** 267 * intel_dmc_load_program() - write the firmware from memory to register. 268 * @dev_priv: i915 drm device. 269 * 270 * DMC firmware is read from a .bin file and kept in internal memory one time. 271 * Everytime display comes back from low power state this function is called to 272 * copy the firmware from internal memory to registers. 273 */ 274 void intel_dmc_load_program(struct drm_i915_private *dev_priv) 275 { 276 struct intel_dmc *dmc = &dev_priv->dmc; 277 u32 id, i; 278 279 if (!HAS_DMC(dev_priv)) { 280 drm_err(&dev_priv->drm, 281 "No DMC support available for this platform\n"); 282 return; 283 } 284 285 if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) { 286 drm_err(&dev_priv->drm, 287 "Tried to program CSR with empty payload\n"); 288 return; 289 } 290 291 assert_rpm_wakelock_held(&dev_priv->runtime_pm); 292 293 preempt_disable(); 294 295 for (id = 0; id < DMC_FW_MAX; id++) { 296 for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) { 297 intel_uncore_write_fw(&dev_priv->uncore, 298 DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i), 299 dmc->dmc_info[id].payload[i]); 300 } 301 } 302 303 preempt_enable(); 304 305 for (id = 0; id < DMC_FW_MAX; id++) { 306 for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) { 307 intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i], 308 dmc->dmc_info[id].mmiodata[i]); 309 } 310 } 311 312 dev_priv->dmc.dc_state = 0; 313 314 gen9_set_dc_state_debugmask(dev_priv); 315 } 316 317 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 318 const struct stepping_info *si) 319 { 320 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 321 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 322 /* 323 * If we don't find a more specific one from above two checks, we 324 * then check for the generic one to be sure to work even with 325 * "broken firmware" 326 */ 327 (si->stepping == '*' && si->substepping == fw_info->substepping) || 328 (fw_info->stepping == '*' && fw_info->substepping == '*')) 329 return true; 330 331 return false; 332 } 333 334 /* 335 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 336 * already sanitized. 337 */ 338 static void dmc_set_fw_offset(struct intel_dmc *dmc, 339 const struct intel_fw_info *fw_info, 340 unsigned int num_entries, 341 const struct stepping_info *si, 342 u8 package_ver) 343 { 344 unsigned int i, id; 345 346 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 347 348 for (i = 0; i < num_entries; i++) { 349 id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 350 351 if (id >= DMC_FW_MAX) { 352 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id); 353 continue; 354 } 355 356 /* More specific versions come first, so we don't even have to 357 * check for the stepping since we already found a previous FW 358 * for this id. 359 */ 360 if (dmc->dmc_info[id].present) 361 continue; 362 363 if (fw_info_matches_stepping(&fw_info[i], si)) { 364 dmc->dmc_info[id].present = true; 365 dmc->dmc_info[id].dmc_offset = fw_info[i].offset; 366 } 367 } 368 } 369 370 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 371 const struct intel_dmc_header_base *dmc_header, 372 size_t rem_size, u8 dmc_id) 373 { 374 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 375 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 376 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 377 const u32 *mmioaddr, *mmiodata; 378 u32 mmio_count, mmio_count_max, start_mmioaddr; 379 u8 *payload; 380 381 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 382 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 383 384 /* 385 * Check if we can access common fields, we will checkc again below 386 * after we have read the version 387 */ 388 if (rem_size < sizeof(struct intel_dmc_header_base)) 389 goto error_truncated; 390 391 /* Cope with small differences between v1 and v3 */ 392 if (dmc_header->header_ver == 3) { 393 const struct intel_dmc_header_v3 *v3 = 394 (const struct intel_dmc_header_v3 *)dmc_header; 395 396 if (rem_size < sizeof(struct intel_dmc_header_v3)) 397 goto error_truncated; 398 399 mmioaddr = v3->mmioaddr; 400 mmiodata = v3->mmiodata; 401 mmio_count = v3->mmio_count; 402 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 403 /* header_len is in dwords */ 404 header_len_bytes = dmc_header->header_len * 4; 405 start_mmioaddr = v3->start_mmioaddr; 406 dmc_header_size = sizeof(*v3); 407 } else if (dmc_header->header_ver == 1) { 408 const struct intel_dmc_header_v1 *v1 = 409 (const struct intel_dmc_header_v1 *)dmc_header; 410 411 if (rem_size < sizeof(struct intel_dmc_header_v1)) 412 goto error_truncated; 413 414 mmioaddr = v1->mmioaddr; 415 mmiodata = v1->mmiodata; 416 mmio_count = v1->mmio_count; 417 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 418 header_len_bytes = dmc_header->header_len; 419 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 420 dmc_header_size = sizeof(*v1); 421 } else { 422 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 423 dmc_header->header_ver); 424 return 0; 425 } 426 427 if (header_len_bytes != dmc_header_size) { 428 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 429 "(%u bytes)\n", header_len_bytes); 430 return 0; 431 } 432 433 /* Cache the dmc header info. */ 434 if (mmio_count > mmio_count_max) { 435 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 436 return 0; 437 } 438 439 for (i = 0; i < mmio_count; i++) { 440 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 441 dmc_info->mmiodata[i] = mmiodata[i]; 442 } 443 dmc_info->mmio_count = mmio_count; 444 dmc_info->start_mmioaddr = start_mmioaddr; 445 446 rem_size -= header_len_bytes; 447 448 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 449 payload_size = dmc_header->fw_size * 4; 450 if (rem_size < payload_size) 451 goto error_truncated; 452 453 if (payload_size > dmc->max_fw_size) { 454 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 455 return 0; 456 } 457 dmc_info->dmc_fw_size = dmc_header->fw_size; 458 459 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 460 if (!dmc_info->payload) 461 return 0; 462 463 payload = (u8 *)(dmc_header) + header_len_bytes; 464 memcpy(dmc_info->payload, payload, payload_size); 465 466 return header_len_bytes + payload_size; 467 468 error_truncated: 469 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 470 return 0; 471 } 472 473 static u32 474 parse_dmc_fw_package(struct intel_dmc *dmc, 475 const struct intel_package_header *package_header, 476 const struct stepping_info *si, 477 size_t rem_size) 478 { 479 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 480 u32 package_size = sizeof(struct intel_package_header); 481 u32 num_entries, max_entries; 482 const struct intel_fw_info *fw_info; 483 484 if (rem_size < package_size) 485 goto error_truncated; 486 487 if (package_header->header_ver == 1) { 488 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 489 } else if (package_header->header_ver == 2) { 490 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 491 } else { 492 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 493 package_header->header_ver); 494 return 0; 495 } 496 497 /* 498 * We should always have space for max_entries, 499 * even if not all are used 500 */ 501 package_size += max_entries * sizeof(struct intel_fw_info); 502 if (rem_size < package_size) 503 goto error_truncated; 504 505 if (package_header->header_len * 4 != package_size) { 506 drm_err(&i915->drm, "DMC firmware has wrong package header length " 507 "(%u bytes)\n", package_size); 508 return 0; 509 } 510 511 num_entries = package_header->num_entries; 512 if (WARN_ON(package_header->num_entries > max_entries)) 513 num_entries = max_entries; 514 515 fw_info = (const struct intel_fw_info *) 516 ((u8 *)package_header + sizeof(*package_header)); 517 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 518 package_header->header_ver); 519 520 /* dmc_offset is in dwords */ 521 return package_size; 522 523 error_truncated: 524 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 525 return 0; 526 } 527 528 /* Return number of bytes parsed or 0 on error */ 529 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 530 struct intel_css_header *css_header, 531 size_t rem_size) 532 { 533 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 534 535 if (rem_size < sizeof(struct intel_css_header)) { 536 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 537 return 0; 538 } 539 540 if (sizeof(struct intel_css_header) != 541 (css_header->header_len * 4)) { 542 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 543 "(%u bytes)\n", 544 (css_header->header_len * 4)); 545 return 0; 546 } 547 548 if (dmc->required_version && 549 css_header->version != dmc->required_version) { 550 drm_info(&i915->drm, "Refusing to load DMC firmware v%u.%u," 551 " please use v%u.%u\n", 552 DMC_VERSION_MAJOR(css_header->version), 553 DMC_VERSION_MINOR(css_header->version), 554 DMC_VERSION_MAJOR(dmc->required_version), 555 DMC_VERSION_MINOR(dmc->required_version)); 556 return 0; 557 } 558 559 dmc->version = css_header->version; 560 561 return sizeof(struct intel_css_header); 562 } 563 564 static void parse_dmc_fw(struct drm_i915_private *dev_priv, 565 const struct firmware *fw) 566 { 567 struct intel_css_header *css_header; 568 struct intel_package_header *package_header; 569 struct intel_dmc_header_base *dmc_header; 570 struct intel_dmc *dmc = &dev_priv->dmc; 571 struct stepping_info display_info = { '*', '*'}; 572 const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info); 573 u32 readcount = 0; 574 u32 r, offset; 575 int id; 576 577 if (!fw) 578 return; 579 580 /* Extract CSS Header information */ 581 css_header = (struct intel_css_header *)fw->data; 582 r = parse_dmc_fw_css(dmc, css_header, fw->size); 583 if (!r) 584 return; 585 586 readcount += r; 587 588 /* Extract Package Header information */ 589 package_header = (struct intel_package_header *)&fw->data[readcount]; 590 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 591 if (!r) 592 return; 593 594 readcount += r; 595 596 for (id = 0; id < DMC_FW_MAX; id++) { 597 if (!dev_priv->dmc.dmc_info[id].present) 598 continue; 599 600 offset = readcount + dmc->dmc_info[id].dmc_offset * 4; 601 if (offset > fw->size) { 602 drm_err(&dev_priv->drm, "Reading beyond the fw_size\n"); 603 continue; 604 } 605 606 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 607 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id); 608 } 609 } 610 611 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv) 612 { 613 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 614 dev_priv->dmc.wakeref = 615 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 616 } 617 618 static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv) 619 { 620 intel_wakeref_t wakeref __maybe_unused = 621 fetch_and_zero(&dev_priv->dmc.wakeref); 622 623 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 624 } 625 626 static void dmc_load_work_fn(struct work_struct *work) 627 { 628 struct drm_i915_private *dev_priv; 629 struct intel_dmc *dmc; 630 const struct firmware *fw = NULL; 631 632 dev_priv = container_of(work, typeof(*dev_priv), dmc.work); 633 dmc = &dev_priv->dmc; 634 635 request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev); 636 parse_dmc_fw(dev_priv, fw); 637 638 if (intel_dmc_has_payload(dev_priv)) { 639 intel_dmc_load_program(dev_priv); 640 intel_dmc_runtime_pm_put(dev_priv); 641 642 drm_info(&dev_priv->drm, 643 "Finished loading DMC firmware %s (v%u.%u)\n", 644 dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version), 645 DMC_VERSION_MINOR(dmc->version)); 646 } else { 647 drm_notice(&dev_priv->drm, 648 "Failed to load DMC firmware %s." 649 " Disabling runtime power management.\n", 650 dmc->fw_path); 651 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s", 652 INTEL_UC_FIRMWARE_URL); 653 } 654 655 release_firmware(fw); 656 } 657 658 /** 659 * intel_dmc_ucode_init() - initialize the firmware loading. 660 * @dev_priv: i915 drm device. 661 * 662 * This function is called at the time of loading the display driver to read 663 * firmware from a .bin file and copied into a internal memory. 664 */ 665 void intel_dmc_ucode_init(struct drm_i915_private *dev_priv) 666 { 667 struct intel_dmc *dmc = &dev_priv->dmc; 668 669 INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn); 670 671 if (!HAS_DMC(dev_priv)) 672 return; 673 674 /* 675 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 676 * runtime-suspend. 677 * 678 * On error, we return with the rpm wakeref held to prevent runtime 679 * suspend as runtime suspend *requires* a working DMC for whatever 680 * reason. 681 */ 682 intel_dmc_runtime_pm_get(dev_priv); 683 684 if (IS_ALDERLAKE_P(dev_priv)) { 685 dmc->fw_path = ADLP_DMC_PATH; 686 dmc->required_version = ADLP_DMC_VERSION_REQUIRED; 687 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 688 } else if (IS_ALDERLAKE_S(dev_priv)) { 689 dmc->fw_path = ADLS_DMC_PATH; 690 dmc->required_version = ADLS_DMC_VERSION_REQUIRED; 691 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 692 } else if (IS_DG1(dev_priv)) { 693 dmc->fw_path = DG1_DMC_PATH; 694 dmc->required_version = DG1_DMC_VERSION_REQUIRED; 695 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 696 } else if (IS_ROCKETLAKE(dev_priv)) { 697 dmc->fw_path = RKL_DMC_PATH; 698 dmc->required_version = RKL_DMC_VERSION_REQUIRED; 699 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 700 } else if (DISPLAY_VER(dev_priv) >= 12) { 701 dmc->fw_path = TGL_DMC_PATH; 702 dmc->required_version = TGL_DMC_VERSION_REQUIRED; 703 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 704 } else if (DISPLAY_VER(dev_priv) == 11) { 705 dmc->fw_path = ICL_DMC_PATH; 706 dmc->required_version = ICL_DMC_VERSION_REQUIRED; 707 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE; 708 } else if (IS_GEMINILAKE(dev_priv)) { 709 dmc->fw_path = GLK_DMC_PATH; 710 dmc->required_version = GLK_DMC_VERSION_REQUIRED; 711 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE; 712 } else if (IS_KABYLAKE(dev_priv) || 713 IS_COFFEELAKE(dev_priv) || 714 IS_COMETLAKE(dev_priv)) { 715 dmc->fw_path = KBL_DMC_PATH; 716 dmc->required_version = KBL_DMC_VERSION_REQUIRED; 717 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE; 718 } else if (IS_SKYLAKE(dev_priv)) { 719 dmc->fw_path = SKL_DMC_PATH; 720 dmc->required_version = SKL_DMC_VERSION_REQUIRED; 721 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE; 722 } else if (IS_BROXTON(dev_priv)) { 723 dmc->fw_path = BXT_DMC_PATH; 724 dmc->required_version = BXT_DMC_VERSION_REQUIRED; 725 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE; 726 } 727 728 if (dev_priv->params.dmc_firmware_path) { 729 if (strlen(dev_priv->params.dmc_firmware_path) == 0) { 730 dmc->fw_path = NULL; 731 drm_info(&dev_priv->drm, 732 "Disabling DMC firmware and runtime PM\n"); 733 return; 734 } 735 736 dmc->fw_path = dev_priv->params.dmc_firmware_path; 737 /* Bypass version check for firmware override. */ 738 dmc->required_version = 0; 739 } 740 741 if (!dmc->fw_path) { 742 drm_dbg_kms(&dev_priv->drm, 743 "No known DMC firmware for platform, disabling runtime PM\n"); 744 return; 745 } 746 747 drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path); 748 schedule_work(&dev_priv->dmc.work); 749 } 750 751 /** 752 * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend 753 * @dev_priv: i915 drm device 754 * 755 * Prepare the DMC firmware before entering system suspend. This includes 756 * flushing pending work items and releasing any resources acquired during 757 * init. 758 */ 759 void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv) 760 { 761 if (!HAS_DMC(dev_priv)) 762 return; 763 764 flush_work(&dev_priv->dmc.work); 765 766 /* Drop the reference held in case DMC isn't loaded. */ 767 if (!intel_dmc_has_payload(dev_priv)) 768 intel_dmc_runtime_pm_put(dev_priv); 769 } 770 771 /** 772 * intel_dmc_ucode_resume() - init DMC firmware during system resume 773 * @dev_priv: i915 drm device 774 * 775 * Reinitialize the DMC firmware during system resume, reacquiring any 776 * resources released in intel_dmc_ucode_suspend(). 777 */ 778 void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv) 779 { 780 if (!HAS_DMC(dev_priv)) 781 return; 782 783 /* 784 * Reacquire the reference to keep RPM disabled in case DMC isn't 785 * loaded. 786 */ 787 if (!intel_dmc_has_payload(dev_priv)) 788 intel_dmc_runtime_pm_get(dev_priv); 789 } 790 791 /** 792 * intel_dmc_ucode_fini() - unload the DMC firmware. 793 * @dev_priv: i915 drm device. 794 * 795 * Firmmware unloading includes freeing the internal memory and reset the 796 * firmware loading status. 797 */ 798 void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv) 799 { 800 int id; 801 802 if (!HAS_DMC(dev_priv)) 803 return; 804 805 intel_dmc_ucode_suspend(dev_priv); 806 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 807 808 for (id = 0; id < DMC_FW_MAX; id++) 809 kfree(dev_priv->dmc.dmc_info[id].payload); 810 } 811