1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_de.h" 30 #include "intel_dmc.h" 31 #include "intel_dmc_regs.h" 32 33 /** 34 * DOC: DMC Firmware Support 35 * 36 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 37 * engine to save and restore the state of display engine when it enter into 38 * low-power state and comes back to normal. 39 */ 40 41 enum intel_dmc_id { 42 DMC_FW_MAIN = 0, 43 DMC_FW_PIPEA, 44 DMC_FW_PIPEB, 45 DMC_FW_PIPEC, 46 DMC_FW_PIPED, 47 DMC_FW_MAX 48 }; 49 50 struct intel_dmc { 51 struct drm_i915_private *i915; 52 struct work_struct work; 53 const char *fw_path; 54 u32 max_fw_size; /* bytes */ 55 u32 version; 56 struct dmc_fw_info { 57 u32 mmio_count; 58 i915_reg_t mmioaddr[20]; 59 u32 mmiodata[20]; 60 u32 dmc_offset; 61 u32 start_mmioaddr; 62 u32 dmc_fw_size; /*dwords */ 63 u32 *payload; 64 bool present; 65 } dmc_info[DMC_FW_MAX]; 66 }; 67 68 /* Note: This may be NULL. */ 69 static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915) 70 { 71 return i915->display.dmc.dmc; 72 } 73 74 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 75 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 76 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 77 78 #define DMC_PATH(platform) \ 79 "i915/" __stringify(platform) "_dmc.bin" 80 81 /* 82 * New DMC additions should not use this. This is used solely to remain 83 * compatible with systems that have not yet updated DMC blobs to use 84 * unversioned file names. 85 */ 86 #define DMC_LEGACY_PATH(platform, major, minor) \ 87 "i915/" \ 88 __stringify(platform) "_dmc_ver" \ 89 __stringify(major) "_" \ 90 __stringify(minor) ".bin" 91 92 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 93 94 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 95 96 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 97 MODULE_FIRMWARE(DG2_DMC_PATH); 98 99 #define ADLP_DMC_PATH DMC_PATH(adlp) 100 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 101 MODULE_FIRMWARE(ADLP_DMC_PATH); 102 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 103 104 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 105 MODULE_FIRMWARE(ADLS_DMC_PATH); 106 107 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 108 MODULE_FIRMWARE(DG1_DMC_PATH); 109 110 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 111 MODULE_FIRMWARE(RKL_DMC_PATH); 112 113 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 114 MODULE_FIRMWARE(TGL_DMC_PATH); 115 116 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 117 #define ICL_DMC_MAX_FW_SIZE 0x6000 118 MODULE_FIRMWARE(ICL_DMC_PATH); 119 120 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 121 #define GLK_DMC_MAX_FW_SIZE 0x4000 122 MODULE_FIRMWARE(GLK_DMC_PATH); 123 124 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 125 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 126 MODULE_FIRMWARE(KBL_DMC_PATH); 127 128 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 129 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 130 MODULE_FIRMWARE(SKL_DMC_PATH); 131 132 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 133 #define BXT_DMC_MAX_FW_SIZE 0x3000 134 MODULE_FIRMWARE(BXT_DMC_PATH); 135 136 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 137 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 138 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 139 #define DMC_V1_MAX_MMIO_COUNT 8 140 #define DMC_V3_MAX_MMIO_COUNT 20 141 #define DMC_V1_MMIO_START_RANGE 0x80000 142 143 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 144 145 struct intel_css_header { 146 /* 0x09 for DMC */ 147 u32 module_type; 148 149 /* Includes the DMC specific header in dwords */ 150 u32 header_len; 151 152 /* always value would be 0x10000 */ 153 u32 header_ver; 154 155 /* Not used */ 156 u32 module_id; 157 158 /* Not used */ 159 u32 module_vendor; 160 161 /* in YYYYMMDD format */ 162 u32 date; 163 164 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 165 u32 size; 166 167 /* Not used */ 168 u32 key_size; 169 170 /* Not used */ 171 u32 modulus_size; 172 173 /* Not used */ 174 u32 exponent_size; 175 176 /* Not used */ 177 u32 reserved1[12]; 178 179 /* Major Minor */ 180 u32 version; 181 182 /* Not used */ 183 u32 reserved2[8]; 184 185 /* Not used */ 186 u32 kernel_header_info; 187 } __packed; 188 189 struct intel_fw_info { 190 u8 reserved1; 191 192 /* reserved on package_header version 1, must be 0 on version 2 */ 193 u8 dmc_id; 194 195 /* Stepping (A, B, C, ..., *). * is a wildcard */ 196 char stepping; 197 198 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 199 char substepping; 200 201 u32 offset; 202 u32 reserved2; 203 } __packed; 204 205 struct intel_package_header { 206 /* DMC container header length in dwords */ 207 u8 header_len; 208 209 /* 0x01, 0x02 */ 210 u8 header_ver; 211 212 u8 reserved[10]; 213 214 /* Number of valid entries in the FWInfo array below */ 215 u32 num_entries; 216 } __packed; 217 218 struct intel_dmc_header_base { 219 /* always value would be 0x40403E3E */ 220 u32 signature; 221 222 /* DMC binary header length */ 223 u8 header_len; 224 225 /* 0x01 */ 226 u8 header_ver; 227 228 /* Reserved */ 229 u16 dmcc_ver; 230 231 /* Major, Minor */ 232 u32 project; 233 234 /* Firmware program size (excluding header) in dwords */ 235 u32 fw_size; 236 237 /* Major Minor version */ 238 u32 fw_version; 239 } __packed; 240 241 struct intel_dmc_header_v1 { 242 struct intel_dmc_header_base base; 243 244 /* Number of valid MMIO cycles present. */ 245 u32 mmio_count; 246 247 /* MMIO address */ 248 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 249 250 /* MMIO data */ 251 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 252 253 /* FW filename */ 254 char dfile[32]; 255 256 u32 reserved1[2]; 257 } __packed; 258 259 struct intel_dmc_header_v3 { 260 struct intel_dmc_header_base base; 261 262 /* DMC RAM start MMIO address */ 263 u32 start_mmioaddr; 264 265 u32 reserved[9]; 266 267 /* FW filename */ 268 char dfile[32]; 269 270 /* Number of valid MMIO cycles present. */ 271 u32 mmio_count; 272 273 /* MMIO address */ 274 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 275 276 /* MMIO data */ 277 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 278 } __packed; 279 280 struct stepping_info { 281 char stepping; 282 char substepping; 283 }; 284 285 #define for_each_dmc_id(__dmc_id) \ 286 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 287 288 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 289 { 290 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 291 } 292 293 static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id dmc_id) 294 { 295 struct intel_dmc *dmc = i915_to_dmc(i915); 296 297 return dmc && dmc->dmc_info[dmc_id].payload; 298 } 299 300 bool intel_dmc_has_payload(struct drm_i915_private *i915) 301 { 302 return has_dmc_id_fw(i915, DMC_FW_MAIN); 303 } 304 305 static const struct stepping_info * 306 intel_get_stepping_info(struct drm_i915_private *i915, 307 struct stepping_info *si) 308 { 309 const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step); 310 311 si->stepping = step_name[0]; 312 si->substepping = step_name[1]; 313 return si; 314 } 315 316 static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915) 317 { 318 /* The below bit doesn't need to be cleared ever afterwards */ 319 intel_de_rmw(i915, DC_STATE_DEBUG, 0, 320 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 321 intel_de_posting_read(i915, DC_STATE_DEBUG); 322 } 323 324 static void disable_event_handler(struct drm_i915_private *i915, 325 i915_reg_t ctl_reg, i915_reg_t htp_reg) 326 { 327 intel_de_write(i915, ctl_reg, 328 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 329 DMC_EVT_CTL_TYPE_EDGE_0_1) | 330 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 331 DMC_EVT_CTL_EVENT_ID_FALSE)); 332 intel_de_write(i915, htp_reg, 0); 333 } 334 335 static void 336 disable_flip_queue_event(struct drm_i915_private *i915, 337 i915_reg_t ctl_reg, i915_reg_t htp_reg) 338 { 339 u32 event_ctl; 340 u32 event_htp; 341 342 event_ctl = intel_de_read(i915, ctl_reg); 343 event_htp = intel_de_read(i915, htp_reg); 344 if (event_ctl != (DMC_EVT_CTL_ENABLE | 345 DMC_EVT_CTL_RECURRING | 346 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 347 DMC_EVT_CTL_TYPE_EDGE_0_1) | 348 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 349 DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) || 350 !event_htp) { 351 drm_dbg_kms(&i915->drm, 352 "Unexpected DMC event configuration (control %08x htp %08x)\n", 353 event_ctl, event_htp); 354 return; 355 } 356 357 disable_event_handler(i915, ctl_reg, htp_reg); 358 } 359 360 static bool 361 get_flip_queue_event_regs(struct drm_i915_private *i915, enum intel_dmc_id dmc_id, 362 i915_reg_t *ctl_reg, i915_reg_t *htp_reg) 363 { 364 if (dmc_id == DMC_FW_MAIN) { 365 if (DISPLAY_VER(i915) == 12) { 366 *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3); 367 *htp_reg = DMC_EVT_HTP(i915, dmc_id, 3); 368 369 return true; 370 } 371 } else if (dmc_id >= DMC_FW_PIPEA && dmc_id <= DMC_FW_PIPED) { 372 if (IS_DG2(i915)) { 373 *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2); 374 *htp_reg = DMC_EVT_HTP(i915, dmc_id, 2); 375 376 return true; 377 } 378 } 379 380 return false; 381 } 382 383 static void 384 disable_all_flip_queue_events(struct drm_i915_private *i915) 385 { 386 enum intel_dmc_id dmc_id; 387 388 /* TODO: check if the following applies to all D13+ platforms. */ 389 if (!IS_DG2(i915) && !IS_TIGERLAKE(i915)) 390 return; 391 392 for_each_dmc_id(dmc_id) { 393 i915_reg_t ctl_reg; 394 i915_reg_t htp_reg; 395 396 if (!has_dmc_id_fw(i915, dmc_id)) 397 continue; 398 399 if (!get_flip_queue_event_regs(i915, dmc_id, &ctl_reg, &htp_reg)) 400 continue; 401 402 disable_flip_queue_event(i915, ctl_reg, htp_reg); 403 } 404 } 405 406 static void disable_all_event_handlers(struct drm_i915_private *i915) 407 { 408 enum intel_dmc_id dmc_id; 409 410 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 411 if (DISPLAY_VER(i915) < 12) 412 return; 413 414 for_each_dmc_id(dmc_id) { 415 int handler; 416 417 if (!has_dmc_id_fw(i915, dmc_id)) 418 continue; 419 420 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 421 disable_event_handler(i915, 422 DMC_EVT_CTL(i915, dmc_id, handler), 423 DMC_EVT_HTP(i915, dmc_id, handler)); 424 } 425 } 426 427 static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 428 { 429 enum pipe pipe; 430 431 if (DISPLAY_VER(i915) < 13) 432 return; 433 434 /* 435 * Wa_16015201720:adl-p,dg2, mtl 436 * The WA requires clock gating to be disabled all the time 437 * for pipe A and B. 438 * For pipe C and D clock gating needs to be disabled only 439 * during initializing the firmware. 440 */ 441 if (enable) 442 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 443 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 444 0, PIPEDMC_GATING_DIS); 445 else 446 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 447 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 448 PIPEDMC_GATING_DIS, 0); 449 } 450 451 void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe) 452 { 453 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 454 455 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) 456 return; 457 458 if (DISPLAY_VER(i915) >= 14) 459 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 460 else 461 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 462 } 463 464 void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe) 465 { 466 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 467 468 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) 469 return; 470 471 if (DISPLAY_VER(i915) >= 14) 472 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 473 else 474 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 475 } 476 477 /** 478 * intel_dmc_load_program() - write the firmware from memory to register. 479 * @i915: i915 drm device. 480 * 481 * DMC firmware is read from a .bin file and kept in internal memory one time. 482 * Everytime display comes back from low power state this function is called to 483 * copy the firmware from internal memory to registers. 484 */ 485 void intel_dmc_load_program(struct drm_i915_private *i915) 486 { 487 struct i915_power_domains *power_domains = &i915->display.power.domains; 488 struct intel_dmc *dmc = i915_to_dmc(i915); 489 enum intel_dmc_id dmc_id; 490 u32 i; 491 492 if (!intel_dmc_has_payload(i915)) 493 return; 494 495 pipedmc_clock_gating_wa(i915, true); 496 497 disable_all_event_handlers(i915); 498 499 assert_rpm_wakelock_held(&i915->runtime_pm); 500 501 preempt_disable(); 502 503 for_each_dmc_id(dmc_id) { 504 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 505 intel_de_write_fw(i915, 506 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 507 dmc->dmc_info[dmc_id].payload[i]); 508 } 509 } 510 511 preempt_enable(); 512 513 for_each_dmc_id(dmc_id) { 514 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 515 intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i], 516 dmc->dmc_info[dmc_id].mmiodata[i]); 517 } 518 } 519 520 power_domains->dc_state = 0; 521 522 gen9_set_dc_state_debugmask(i915); 523 524 /* 525 * Flip queue events need to be disabled before enabling DC5/6. 526 * i915 doesn't use the flip queue feature, so disable it already 527 * here. 528 */ 529 disable_all_flip_queue_events(i915); 530 531 pipedmc_clock_gating_wa(i915, false); 532 } 533 534 /** 535 * intel_dmc_disable_program() - disable the firmware 536 * @i915: i915 drm device 537 * 538 * Disable all event handlers in the firmware, making sure the firmware is 539 * inactive after the display is uninitialized. 540 */ 541 void intel_dmc_disable_program(struct drm_i915_private *i915) 542 { 543 if (!intel_dmc_has_payload(i915)) 544 return; 545 546 pipedmc_clock_gating_wa(i915, true); 547 disable_all_event_handlers(i915); 548 pipedmc_clock_gating_wa(i915, false); 549 } 550 551 void assert_dmc_loaded(struct drm_i915_private *i915) 552 { 553 struct intel_dmc *dmc = i915_to_dmc(i915); 554 555 drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n"); 556 drm_WARN_ONCE(&i915->drm, dmc && 557 !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 558 "DMC program storage start is NULL\n"); 559 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), 560 "DMC SSP Base Not fine\n"); 561 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), 562 "DMC HTP Not fine\n"); 563 } 564 565 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 566 const struct stepping_info *si) 567 { 568 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 569 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 570 /* 571 * If we don't find a more specific one from above two checks, we 572 * then check for the generic one to be sure to work even with 573 * "broken firmware" 574 */ 575 (si->stepping == '*' && si->substepping == fw_info->substepping) || 576 (fw_info->stepping == '*' && fw_info->substepping == '*')) 577 return true; 578 579 return false; 580 } 581 582 /* 583 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 584 * already sanitized. 585 */ 586 static void dmc_set_fw_offset(struct intel_dmc *dmc, 587 const struct intel_fw_info *fw_info, 588 unsigned int num_entries, 589 const struct stepping_info *si, 590 u8 package_ver) 591 { 592 struct drm_i915_private *i915 = dmc->i915; 593 enum intel_dmc_id dmc_id; 594 unsigned int i; 595 596 for (i = 0; i < num_entries; i++) { 597 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 598 599 if (!is_valid_dmc_id(dmc_id)) { 600 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", dmc_id); 601 continue; 602 } 603 604 /* More specific versions come first, so we don't even have to 605 * check for the stepping since we already found a previous FW 606 * for this id. 607 */ 608 if (dmc->dmc_info[dmc_id].present) 609 continue; 610 611 if (fw_info_matches_stepping(&fw_info[i], si)) { 612 dmc->dmc_info[dmc_id].present = true; 613 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 614 } 615 } 616 } 617 618 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 619 const u32 *mmioaddr, u32 mmio_count, 620 int header_ver, enum intel_dmc_id dmc_id) 621 { 622 struct drm_i915_private *i915 = dmc->i915; 623 u32 start_range, end_range; 624 int i; 625 626 if (header_ver == 1) { 627 start_range = DMC_MMIO_START_RANGE; 628 end_range = DMC_MMIO_END_RANGE; 629 } else if (dmc_id == DMC_FW_MAIN) { 630 start_range = TGL_MAIN_MMIO_START; 631 end_range = TGL_MAIN_MMIO_END; 632 } else if (DISPLAY_VER(i915) >= 13) { 633 start_range = ADLP_PIPE_MMIO_START; 634 end_range = ADLP_PIPE_MMIO_END; 635 } else if (DISPLAY_VER(i915) >= 12) { 636 start_range = TGL_PIPE_MMIO_START(dmc_id); 637 end_range = TGL_PIPE_MMIO_END(dmc_id); 638 } else { 639 drm_warn(&i915->drm, "Unknown mmio range for sanity check"); 640 return false; 641 } 642 643 for (i = 0; i < mmio_count; i++) { 644 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 645 return false; 646 } 647 648 return true; 649 } 650 651 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 652 const struct intel_dmc_header_base *dmc_header, 653 size_t rem_size, enum intel_dmc_id dmc_id) 654 { 655 struct drm_i915_private *i915 = dmc->i915; 656 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 657 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 658 const u32 *mmioaddr, *mmiodata; 659 u32 mmio_count, mmio_count_max, start_mmioaddr; 660 u8 *payload; 661 662 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 663 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 664 665 /* 666 * Check if we can access common fields, we will checkc again below 667 * after we have read the version 668 */ 669 if (rem_size < sizeof(struct intel_dmc_header_base)) 670 goto error_truncated; 671 672 /* Cope with small differences between v1 and v3 */ 673 if (dmc_header->header_ver == 3) { 674 const struct intel_dmc_header_v3 *v3 = 675 (const struct intel_dmc_header_v3 *)dmc_header; 676 677 if (rem_size < sizeof(struct intel_dmc_header_v3)) 678 goto error_truncated; 679 680 mmioaddr = v3->mmioaddr; 681 mmiodata = v3->mmiodata; 682 mmio_count = v3->mmio_count; 683 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 684 /* header_len is in dwords */ 685 header_len_bytes = dmc_header->header_len * 4; 686 start_mmioaddr = v3->start_mmioaddr; 687 dmc_header_size = sizeof(*v3); 688 } else if (dmc_header->header_ver == 1) { 689 const struct intel_dmc_header_v1 *v1 = 690 (const struct intel_dmc_header_v1 *)dmc_header; 691 692 if (rem_size < sizeof(struct intel_dmc_header_v1)) 693 goto error_truncated; 694 695 mmioaddr = v1->mmioaddr; 696 mmiodata = v1->mmiodata; 697 mmio_count = v1->mmio_count; 698 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 699 header_len_bytes = dmc_header->header_len; 700 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 701 dmc_header_size = sizeof(*v1); 702 } else { 703 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 704 dmc_header->header_ver); 705 return 0; 706 } 707 708 if (header_len_bytes != dmc_header_size) { 709 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 710 "(%u bytes)\n", header_len_bytes); 711 return 0; 712 } 713 714 /* Cache the dmc header info. */ 715 if (mmio_count > mmio_count_max) { 716 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 717 return 0; 718 } 719 720 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 721 dmc_header->header_ver, dmc_id)) { 722 drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); 723 return 0; 724 } 725 726 for (i = 0; i < mmio_count; i++) { 727 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 728 dmc_info->mmiodata[i] = mmiodata[i]; 729 } 730 dmc_info->mmio_count = mmio_count; 731 dmc_info->start_mmioaddr = start_mmioaddr; 732 733 rem_size -= header_len_bytes; 734 735 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 736 payload_size = dmc_header->fw_size * 4; 737 if (rem_size < payload_size) 738 goto error_truncated; 739 740 if (payload_size > dmc->max_fw_size) { 741 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 742 return 0; 743 } 744 dmc_info->dmc_fw_size = dmc_header->fw_size; 745 746 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 747 if (!dmc_info->payload) 748 return 0; 749 750 payload = (u8 *)(dmc_header) + header_len_bytes; 751 memcpy(dmc_info->payload, payload, payload_size); 752 753 return header_len_bytes + payload_size; 754 755 error_truncated: 756 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 757 return 0; 758 } 759 760 static u32 761 parse_dmc_fw_package(struct intel_dmc *dmc, 762 const struct intel_package_header *package_header, 763 const struct stepping_info *si, 764 size_t rem_size) 765 { 766 struct drm_i915_private *i915 = dmc->i915; 767 u32 package_size = sizeof(struct intel_package_header); 768 u32 num_entries, max_entries; 769 const struct intel_fw_info *fw_info; 770 771 if (rem_size < package_size) 772 goto error_truncated; 773 774 if (package_header->header_ver == 1) { 775 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 776 } else if (package_header->header_ver == 2) { 777 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 778 } else { 779 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 780 package_header->header_ver); 781 return 0; 782 } 783 784 /* 785 * We should always have space for max_entries, 786 * even if not all are used 787 */ 788 package_size += max_entries * sizeof(struct intel_fw_info); 789 if (rem_size < package_size) 790 goto error_truncated; 791 792 if (package_header->header_len * 4 != package_size) { 793 drm_err(&i915->drm, "DMC firmware has wrong package header length " 794 "(%u bytes)\n", package_size); 795 return 0; 796 } 797 798 num_entries = package_header->num_entries; 799 if (WARN_ON(package_header->num_entries > max_entries)) 800 num_entries = max_entries; 801 802 fw_info = (const struct intel_fw_info *) 803 ((u8 *)package_header + sizeof(*package_header)); 804 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 805 package_header->header_ver); 806 807 /* dmc_offset is in dwords */ 808 return package_size; 809 810 error_truncated: 811 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 812 return 0; 813 } 814 815 /* Return number of bytes parsed or 0 on error */ 816 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 817 struct intel_css_header *css_header, 818 size_t rem_size) 819 { 820 struct drm_i915_private *i915 = dmc->i915; 821 822 if (rem_size < sizeof(struct intel_css_header)) { 823 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 824 return 0; 825 } 826 827 if (sizeof(struct intel_css_header) != 828 (css_header->header_len * 4)) { 829 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 830 "(%u bytes)\n", 831 (css_header->header_len * 4)); 832 return 0; 833 } 834 835 dmc->version = css_header->version; 836 837 return sizeof(struct intel_css_header); 838 } 839 840 static void parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 841 { 842 struct drm_i915_private *i915 = dmc->i915; 843 struct intel_css_header *css_header; 844 struct intel_package_header *package_header; 845 struct intel_dmc_header_base *dmc_header; 846 struct stepping_info display_info = { '*', '*'}; 847 const struct stepping_info *si = intel_get_stepping_info(i915, &display_info); 848 enum intel_dmc_id dmc_id; 849 u32 readcount = 0; 850 u32 r, offset; 851 852 if (!fw) 853 return; 854 855 /* Extract CSS Header information */ 856 css_header = (struct intel_css_header *)fw->data; 857 r = parse_dmc_fw_css(dmc, css_header, fw->size); 858 if (!r) 859 return; 860 861 readcount += r; 862 863 /* Extract Package Header information */ 864 package_header = (struct intel_package_header *)&fw->data[readcount]; 865 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 866 if (!r) 867 return; 868 869 readcount += r; 870 871 for_each_dmc_id(dmc_id) { 872 if (!dmc->dmc_info[dmc_id].present) 873 continue; 874 875 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 876 if (offset > fw->size) { 877 drm_err(&i915->drm, "Reading beyond the fw_size\n"); 878 continue; 879 } 880 881 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 882 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 883 } 884 } 885 886 static void intel_dmc_runtime_pm_get(struct drm_i915_private *i915) 887 { 888 drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); 889 i915->display.dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 890 } 891 892 static void intel_dmc_runtime_pm_put(struct drm_i915_private *i915) 893 { 894 intel_wakeref_t wakeref __maybe_unused = 895 fetch_and_zero(&i915->display.dmc.wakeref); 896 897 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 898 } 899 900 static const char *dmc_fallback_path(struct drm_i915_private *i915) 901 { 902 if (IS_ALDERLAKE_P(i915)) 903 return ADLP_DMC_FALLBACK_PATH; 904 905 return NULL; 906 } 907 908 static void dmc_load_work_fn(struct work_struct *work) 909 { 910 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 911 struct drm_i915_private *i915 = dmc->i915; 912 const struct firmware *fw = NULL; 913 const char *fallback_path; 914 int err; 915 916 err = request_firmware(&fw, dmc->fw_path, i915->drm.dev); 917 918 if (err == -ENOENT && !i915->params.dmc_firmware_path) { 919 fallback_path = dmc_fallback_path(i915); 920 if (fallback_path) { 921 drm_dbg_kms(&i915->drm, "%s not found, falling back to %s\n", 922 dmc->fw_path, fallback_path); 923 err = request_firmware(&fw, fallback_path, i915->drm.dev); 924 if (err == 0) 925 dmc->fw_path = fallback_path; 926 } 927 } 928 929 parse_dmc_fw(dmc, fw); 930 931 if (intel_dmc_has_payload(i915)) { 932 intel_dmc_load_program(i915); 933 intel_dmc_runtime_pm_put(i915); 934 935 drm_info(&i915->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 936 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 937 DMC_VERSION_MINOR(dmc->version)); 938 } else { 939 drm_notice(&i915->drm, 940 "Failed to load DMC firmware %s." 941 " Disabling runtime power management.\n", 942 dmc->fw_path); 943 drm_notice(&i915->drm, "DMC firmware homepage: %s", 944 INTEL_UC_FIRMWARE_URL); 945 } 946 947 release_firmware(fw); 948 } 949 950 /** 951 * intel_dmc_init() - initialize the firmware loading. 952 * @i915: i915 drm device. 953 * 954 * This function is called at the time of loading the display driver to read 955 * firmware from a .bin file and copied into a internal memory. 956 */ 957 void intel_dmc_init(struct drm_i915_private *i915) 958 { 959 struct intel_dmc *dmc; 960 961 if (!HAS_DMC(i915)) 962 return; 963 964 /* 965 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 966 * runtime-suspend. 967 * 968 * On error, we return with the rpm wakeref held to prevent runtime 969 * suspend as runtime suspend *requires* a working DMC for whatever 970 * reason. 971 */ 972 intel_dmc_runtime_pm_get(i915); 973 974 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); 975 if (!dmc) 976 return; 977 978 dmc->i915 = i915; 979 980 INIT_WORK(&dmc->work, dmc_load_work_fn); 981 982 if (IS_DG2(i915)) { 983 dmc->fw_path = DG2_DMC_PATH; 984 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 985 } else if (IS_ALDERLAKE_P(i915)) { 986 dmc->fw_path = ADLP_DMC_PATH; 987 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 988 } else if (IS_ALDERLAKE_S(i915)) { 989 dmc->fw_path = ADLS_DMC_PATH; 990 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 991 } else if (IS_DG1(i915)) { 992 dmc->fw_path = DG1_DMC_PATH; 993 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 994 } else if (IS_ROCKETLAKE(i915)) { 995 dmc->fw_path = RKL_DMC_PATH; 996 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 997 } else if (IS_TIGERLAKE(i915)) { 998 dmc->fw_path = TGL_DMC_PATH; 999 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 1000 } else if (DISPLAY_VER(i915) == 11) { 1001 dmc->fw_path = ICL_DMC_PATH; 1002 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE; 1003 } else if (IS_GEMINILAKE(i915)) { 1004 dmc->fw_path = GLK_DMC_PATH; 1005 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE; 1006 } else if (IS_KABYLAKE(i915) || 1007 IS_COFFEELAKE(i915) || 1008 IS_COMETLAKE(i915)) { 1009 dmc->fw_path = KBL_DMC_PATH; 1010 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE; 1011 } else if (IS_SKYLAKE(i915)) { 1012 dmc->fw_path = SKL_DMC_PATH; 1013 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE; 1014 } else if (IS_BROXTON(i915)) { 1015 dmc->fw_path = BXT_DMC_PATH; 1016 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE; 1017 } 1018 1019 if (i915->params.dmc_firmware_path) { 1020 if (strlen(i915->params.dmc_firmware_path) == 0) { 1021 drm_info(&i915->drm, 1022 "Disabling DMC firmware and runtime PM\n"); 1023 goto out; 1024 } 1025 1026 dmc->fw_path = i915->params.dmc_firmware_path; 1027 } 1028 1029 if (!dmc->fw_path) { 1030 drm_dbg_kms(&i915->drm, 1031 "No known DMC firmware for platform, disabling runtime PM\n"); 1032 goto out; 1033 } 1034 1035 i915->display.dmc.dmc = dmc; 1036 1037 drm_dbg_kms(&i915->drm, "Loading %s\n", dmc->fw_path); 1038 schedule_work(&dmc->work); 1039 1040 return; 1041 1042 out: 1043 kfree(dmc); 1044 } 1045 1046 /** 1047 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1048 * @i915: i915 drm device 1049 * 1050 * Prepare the DMC firmware before entering system suspend. This includes 1051 * flushing pending work items and releasing any resources acquired during 1052 * init. 1053 */ 1054 void intel_dmc_suspend(struct drm_i915_private *i915) 1055 { 1056 struct intel_dmc *dmc = i915_to_dmc(i915); 1057 1058 if (!HAS_DMC(i915)) 1059 return; 1060 1061 if (dmc) 1062 flush_work(&dmc->work); 1063 1064 /* Drop the reference held in case DMC isn't loaded. */ 1065 if (!intel_dmc_has_payload(i915)) 1066 intel_dmc_runtime_pm_put(i915); 1067 } 1068 1069 /** 1070 * intel_dmc_resume() - init DMC firmware during system resume 1071 * @i915: i915 drm device 1072 * 1073 * Reinitialize the DMC firmware during system resume, reacquiring any 1074 * resources released in intel_dmc_suspend(). 1075 */ 1076 void intel_dmc_resume(struct drm_i915_private *i915) 1077 { 1078 if (!HAS_DMC(i915)) 1079 return; 1080 1081 /* 1082 * Reacquire the reference to keep RPM disabled in case DMC isn't 1083 * loaded. 1084 */ 1085 if (!intel_dmc_has_payload(i915)) 1086 intel_dmc_runtime_pm_get(i915); 1087 } 1088 1089 /** 1090 * intel_dmc_fini() - unload the DMC firmware. 1091 * @i915: i915 drm device. 1092 * 1093 * Firmmware unloading includes freeing the internal memory and reset the 1094 * firmware loading status. 1095 */ 1096 void intel_dmc_fini(struct drm_i915_private *i915) 1097 { 1098 struct intel_dmc *dmc = i915_to_dmc(i915); 1099 enum intel_dmc_id dmc_id; 1100 1101 if (!HAS_DMC(i915)) 1102 return; 1103 1104 intel_dmc_suspend(i915); 1105 drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); 1106 1107 if (dmc) { 1108 for_each_dmc_id(dmc_id) 1109 kfree(dmc->dmc_info[dmc_id].payload); 1110 1111 kfree(dmc); 1112 i915->display.dmc.dmc = NULL; 1113 } 1114 } 1115 1116 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, 1117 struct drm_i915_private *i915) 1118 { 1119 struct intel_dmc *dmc = i915_to_dmc(i915); 1120 1121 if (!HAS_DMC(i915)) 1122 return; 1123 1124 i915_error_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1125 i915_error_printf(m, "DMC loaded: %s\n", 1126 str_yes_no(intel_dmc_has_payload(i915))); 1127 if (dmc) 1128 i915_error_printf(m, "DMC fw version: %d.%d\n", 1129 DMC_VERSION_MAJOR(dmc->version), 1130 DMC_VERSION_MINOR(dmc->version)); 1131 } 1132 1133 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1134 { 1135 struct drm_i915_private *i915 = m->private; 1136 struct intel_dmc *dmc = i915_to_dmc(i915); 1137 intel_wakeref_t wakeref; 1138 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1139 1140 if (!HAS_DMC(i915)) 1141 return -ENODEV; 1142 1143 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1144 1145 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1146 seq_printf(m, "fw loaded: %s\n", 1147 str_yes_no(intel_dmc_has_payload(i915))); 1148 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1149 seq_printf(m, "Pipe A fw needed: %s\n", 1150 str_yes_no(GRAPHICS_VER(i915) >= 12)); 1151 seq_printf(m, "Pipe A fw loaded: %s\n", 1152 str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEA))); 1153 seq_printf(m, "Pipe B fw needed: %s\n", 1154 str_yes_no(IS_ALDERLAKE_P(i915) || 1155 DISPLAY_VER(i915) >= 14)); 1156 seq_printf(m, "Pipe B fw loaded: %s\n", 1157 str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEB))); 1158 1159 if (!intel_dmc_has_payload(i915)) 1160 goto out; 1161 1162 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1163 DMC_VERSION_MINOR(dmc->version)); 1164 1165 if (DISPLAY_VER(i915) >= 12) { 1166 i915_reg_t dc3co_reg; 1167 1168 if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) { 1169 dc3co_reg = DG1_DMC_DEBUG3; 1170 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1171 } else { 1172 dc3co_reg = TGL_DMC_DEBUG3; 1173 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1174 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1175 } 1176 1177 seq_printf(m, "DC3CO count: %d\n", 1178 intel_de_read(i915, dc3co_reg)); 1179 } else { 1180 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : 1181 SKL_DMC_DC3_DC5_COUNT; 1182 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) 1183 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1184 } 1185 1186 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); 1187 if (i915_mmio_reg_valid(dc6_reg)) 1188 seq_printf(m, "DC5 -> DC6 count: %d\n", 1189 intel_de_read(i915, dc6_reg)); 1190 1191 seq_printf(m, "program base: 0x%08x\n", 1192 intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1193 1194 out: 1195 seq_printf(m, "ssp base: 0x%08x\n", 1196 intel_de_read(i915, DMC_SSP_BASE)); 1197 seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL)); 1198 1199 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1200 1201 return 0; 1202 } 1203 1204 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1205 1206 void intel_dmc_debugfs_register(struct drm_i915_private *i915) 1207 { 1208 struct drm_minor *minor = i915->drm.primary; 1209 1210 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 1211 i915, &intel_dmc_debugfs_status_fops); 1212 } 1213