1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_de.h" 30 #include "intel_dmc.h" 31 #include "intel_dmc_regs.h" 32 33 /** 34 * DOC: DMC Firmware Support 35 * 36 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 37 * engine to save and restore the state of display engine when it enter into 38 * low-power state and comes back to normal. 39 */ 40 41 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 42 43 enum intel_dmc_id { 44 DMC_FW_MAIN = 0, 45 DMC_FW_PIPEA, 46 DMC_FW_PIPEB, 47 DMC_FW_PIPEC, 48 DMC_FW_PIPED, 49 DMC_FW_MAX 50 }; 51 52 struct intel_dmc { 53 struct drm_i915_private *i915; 54 struct work_struct work; 55 const char *fw_path; 56 u32 max_fw_size; /* bytes */ 57 u32 version; 58 struct dmc_fw_info { 59 u32 mmio_count; 60 i915_reg_t mmioaddr[20]; 61 u32 mmiodata[20]; 62 u32 dmc_offset; 63 u32 start_mmioaddr; 64 u32 dmc_fw_size; /*dwords */ 65 u32 *payload; 66 bool present; 67 } dmc_info[DMC_FW_MAX]; 68 }; 69 70 /* Note: This may be NULL. */ 71 static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915) 72 { 73 return i915->display.dmc.dmc; 74 } 75 76 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 77 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 78 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 79 80 #define DMC_PATH(platform) \ 81 "i915/" __stringify(platform) "_dmc.bin" 82 83 /* 84 * New DMC additions should not use this. This is used solely to remain 85 * compatible with systems that have not yet updated DMC blobs to use 86 * unversioned file names. 87 */ 88 #define DMC_LEGACY_PATH(platform, major, minor) \ 89 "i915/" \ 90 __stringify(platform) "_dmc_ver" \ 91 __stringify(major) "_" \ 92 __stringify(minor) ".bin" 93 94 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 95 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 96 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 97 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 98 99 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 100 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 101 102 #define MTL_DMC_PATH DMC_PATH(mtl) 103 MODULE_FIRMWARE(MTL_DMC_PATH); 104 105 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 106 MODULE_FIRMWARE(DG2_DMC_PATH); 107 108 #define ADLP_DMC_PATH DMC_PATH(adlp) 109 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 110 MODULE_FIRMWARE(ADLP_DMC_PATH); 111 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 112 113 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 114 MODULE_FIRMWARE(ADLS_DMC_PATH); 115 116 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 117 MODULE_FIRMWARE(DG1_DMC_PATH); 118 119 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 120 MODULE_FIRMWARE(RKL_DMC_PATH); 121 122 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 123 MODULE_FIRMWARE(TGL_DMC_PATH); 124 125 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 126 #define ICL_DMC_MAX_FW_SIZE 0x6000 127 MODULE_FIRMWARE(ICL_DMC_PATH); 128 129 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 130 #define GLK_DMC_MAX_FW_SIZE 0x4000 131 MODULE_FIRMWARE(GLK_DMC_PATH); 132 133 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 134 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 135 MODULE_FIRMWARE(KBL_DMC_PATH); 136 137 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 138 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 139 MODULE_FIRMWARE(SKL_DMC_PATH); 140 141 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 142 #define BXT_DMC_MAX_FW_SIZE 0x3000 143 MODULE_FIRMWARE(BXT_DMC_PATH); 144 145 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 146 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 147 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 148 #define DMC_V1_MAX_MMIO_COUNT 8 149 #define DMC_V3_MAX_MMIO_COUNT 20 150 #define DMC_V1_MMIO_START_RANGE 0x80000 151 152 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 153 154 struct intel_css_header { 155 /* 0x09 for DMC */ 156 u32 module_type; 157 158 /* Includes the DMC specific header in dwords */ 159 u32 header_len; 160 161 /* always value would be 0x10000 */ 162 u32 header_ver; 163 164 /* Not used */ 165 u32 module_id; 166 167 /* Not used */ 168 u32 module_vendor; 169 170 /* in YYYYMMDD format */ 171 u32 date; 172 173 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 174 u32 size; 175 176 /* Not used */ 177 u32 key_size; 178 179 /* Not used */ 180 u32 modulus_size; 181 182 /* Not used */ 183 u32 exponent_size; 184 185 /* Not used */ 186 u32 reserved1[12]; 187 188 /* Major Minor */ 189 u32 version; 190 191 /* Not used */ 192 u32 reserved2[8]; 193 194 /* Not used */ 195 u32 kernel_header_info; 196 } __packed; 197 198 struct intel_fw_info { 199 u8 reserved1; 200 201 /* reserved on package_header version 1, must be 0 on version 2 */ 202 u8 dmc_id; 203 204 /* Stepping (A, B, C, ..., *). * is a wildcard */ 205 char stepping; 206 207 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 208 char substepping; 209 210 u32 offset; 211 u32 reserved2; 212 } __packed; 213 214 struct intel_package_header { 215 /* DMC container header length in dwords */ 216 u8 header_len; 217 218 /* 0x01, 0x02 */ 219 u8 header_ver; 220 221 u8 reserved[10]; 222 223 /* Number of valid entries in the FWInfo array below */ 224 u32 num_entries; 225 } __packed; 226 227 struct intel_dmc_header_base { 228 /* always value would be 0x40403E3E */ 229 u32 signature; 230 231 /* DMC binary header length */ 232 u8 header_len; 233 234 /* 0x01 */ 235 u8 header_ver; 236 237 /* Reserved */ 238 u16 dmcc_ver; 239 240 /* Major, Minor */ 241 u32 project; 242 243 /* Firmware program size (excluding header) in dwords */ 244 u32 fw_size; 245 246 /* Major Minor version */ 247 u32 fw_version; 248 } __packed; 249 250 struct intel_dmc_header_v1 { 251 struct intel_dmc_header_base base; 252 253 /* Number of valid MMIO cycles present. */ 254 u32 mmio_count; 255 256 /* MMIO address */ 257 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 258 259 /* MMIO data */ 260 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 261 262 /* FW filename */ 263 char dfile[32]; 264 265 u32 reserved1[2]; 266 } __packed; 267 268 struct intel_dmc_header_v3 { 269 struct intel_dmc_header_base base; 270 271 /* DMC RAM start MMIO address */ 272 u32 start_mmioaddr; 273 274 u32 reserved[9]; 275 276 /* FW filename */ 277 char dfile[32]; 278 279 /* Number of valid MMIO cycles present. */ 280 u32 mmio_count; 281 282 /* MMIO address */ 283 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 284 285 /* MMIO data */ 286 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 287 } __packed; 288 289 struct stepping_info { 290 char stepping; 291 char substepping; 292 }; 293 294 #define for_each_dmc_id(__dmc_id) \ 295 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 296 297 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 298 { 299 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 300 } 301 302 static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id dmc_id) 303 { 304 struct intel_dmc *dmc = i915_to_dmc(i915); 305 306 return dmc && dmc->dmc_info[dmc_id].payload; 307 } 308 309 bool intel_dmc_has_payload(struct drm_i915_private *i915) 310 { 311 return has_dmc_id_fw(i915, DMC_FW_MAIN); 312 } 313 314 static const struct stepping_info * 315 intel_get_stepping_info(struct drm_i915_private *i915, 316 struct stepping_info *si) 317 { 318 const char *step_name = intel_display_step_name(i915); 319 320 si->stepping = step_name[0]; 321 si->substepping = step_name[1]; 322 return si; 323 } 324 325 static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915) 326 { 327 /* The below bit doesn't need to be cleared ever afterwards */ 328 intel_de_rmw(i915, DC_STATE_DEBUG, 0, 329 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 330 intel_de_posting_read(i915, DC_STATE_DEBUG); 331 } 332 333 static void disable_event_handler(struct drm_i915_private *i915, 334 i915_reg_t ctl_reg, i915_reg_t htp_reg) 335 { 336 intel_de_write(i915, ctl_reg, 337 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 338 DMC_EVT_CTL_TYPE_EDGE_0_1) | 339 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 340 DMC_EVT_CTL_EVENT_ID_FALSE)); 341 intel_de_write(i915, htp_reg, 0); 342 } 343 344 static void disable_all_event_handlers(struct drm_i915_private *i915) 345 { 346 enum intel_dmc_id dmc_id; 347 348 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 349 if (DISPLAY_VER(i915) < 12) 350 return; 351 352 for_each_dmc_id(dmc_id) { 353 int handler; 354 355 if (!has_dmc_id_fw(i915, dmc_id)) 356 continue; 357 358 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 359 disable_event_handler(i915, 360 DMC_EVT_CTL(i915, dmc_id, handler), 361 DMC_EVT_HTP(i915, dmc_id, handler)); 362 } 363 } 364 365 static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 366 { 367 enum pipe pipe; 368 369 /* 370 * Wa_16015201720:adl-p,dg2 371 * The WA requires clock gating to be disabled all the time 372 * for pipe A and B. 373 * For pipe C and D clock gating needs to be disabled only 374 * during initializing the firmware. 375 */ 376 if (enable) 377 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 378 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 379 0, PIPEDMC_GATING_DIS); 380 else 381 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 382 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 383 PIPEDMC_GATING_DIS, 0); 384 } 385 386 static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915) 387 { 388 /* 389 * Wa_16015201720 390 * The WA requires clock gating to be disabled all the time 391 * for pipe A and B. 392 */ 393 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, 394 MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); 395 } 396 397 static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 398 { 399 if (DISPLAY_VER(i915) >= 14 && enable) 400 mtl_pipedmc_clock_gating_wa(i915); 401 else if (DISPLAY_VER(i915) == 13) 402 adlp_pipedmc_clock_gating_wa(i915, enable); 403 } 404 405 void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe) 406 { 407 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 408 409 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) 410 return; 411 412 if (DISPLAY_VER(i915) >= 14) 413 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 414 else 415 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 416 } 417 418 void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe) 419 { 420 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 421 422 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) 423 return; 424 425 if (DISPLAY_VER(i915) >= 14) 426 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 427 else 428 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 429 } 430 431 static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915, 432 enum intel_dmc_id dmc_id, i915_reg_t reg) 433 { 434 u32 offset = i915_mmio_reg_offset(reg); 435 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0)); 436 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 437 438 return offset >= start && offset < end; 439 } 440 441 static bool is_dmc_evt_htp_reg(struct drm_i915_private *i915, 442 enum intel_dmc_id dmc_id, i915_reg_t reg) 443 { 444 u32 offset = i915_mmio_reg_offset(reg); 445 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, 0)); 446 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 447 448 return offset >= start && offset < end; 449 } 450 451 static bool disable_dmc_evt(struct drm_i915_private *i915, 452 enum intel_dmc_id dmc_id, 453 i915_reg_t reg, u32 data) 454 { 455 if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg)) 456 return false; 457 458 /* keep all pipe DMC events disabled by default */ 459 if (dmc_id != DMC_FW_MAIN) 460 return true; 461 462 /* also disable the flip queue event on the main DMC on TGL */ 463 if (IS_TIGERLAKE(i915) && 464 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC) 465 return true; 466 467 /* also disable the HRR event on the main DMC on TGL/ADLS */ 468 if ((IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915)) && 469 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A) 470 return true; 471 472 return false; 473 } 474 475 static u32 dmc_mmiodata(struct drm_i915_private *i915, 476 struct intel_dmc *dmc, 477 enum intel_dmc_id dmc_id, int i) 478 { 479 if (disable_dmc_evt(i915, dmc_id, 480 dmc->dmc_info[dmc_id].mmioaddr[i], 481 dmc->dmc_info[dmc_id].mmiodata[i])) 482 return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 483 DMC_EVT_CTL_TYPE_EDGE_0_1) | 484 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 485 DMC_EVT_CTL_EVENT_ID_FALSE); 486 else 487 return dmc->dmc_info[dmc_id].mmiodata[i]; 488 } 489 490 /** 491 * intel_dmc_load_program() - write the firmware from memory to register. 492 * @i915: i915 drm device. 493 * 494 * DMC firmware is read from a .bin file and kept in internal memory one time. 495 * Everytime display comes back from low power state this function is called to 496 * copy the firmware from internal memory to registers. 497 */ 498 void intel_dmc_load_program(struct drm_i915_private *i915) 499 { 500 struct i915_power_domains *power_domains = &i915->display.power.domains; 501 struct intel_dmc *dmc = i915_to_dmc(i915); 502 enum intel_dmc_id dmc_id; 503 u32 i; 504 505 if (!intel_dmc_has_payload(i915)) 506 return; 507 508 pipedmc_clock_gating_wa(i915, true); 509 510 disable_all_event_handlers(i915); 511 512 assert_rpm_wakelock_held(&i915->runtime_pm); 513 514 preempt_disable(); 515 516 for_each_dmc_id(dmc_id) { 517 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 518 intel_de_write_fw(i915, 519 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 520 dmc->dmc_info[dmc_id].payload[i]); 521 } 522 } 523 524 preempt_enable(); 525 526 for_each_dmc_id(dmc_id) { 527 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 528 intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i], 529 dmc_mmiodata(i915, dmc, dmc_id, i)); 530 } 531 } 532 533 power_domains->dc_state = 0; 534 535 gen9_set_dc_state_debugmask(i915); 536 537 pipedmc_clock_gating_wa(i915, false); 538 } 539 540 /** 541 * intel_dmc_disable_program() - disable the firmware 542 * @i915: i915 drm device 543 * 544 * Disable all event handlers in the firmware, making sure the firmware is 545 * inactive after the display is uninitialized. 546 */ 547 void intel_dmc_disable_program(struct drm_i915_private *i915) 548 { 549 if (!intel_dmc_has_payload(i915)) 550 return; 551 552 pipedmc_clock_gating_wa(i915, true); 553 disable_all_event_handlers(i915); 554 pipedmc_clock_gating_wa(i915, false); 555 556 intel_dmc_wl_disable(i915); 557 } 558 559 void assert_dmc_loaded(struct drm_i915_private *i915) 560 { 561 struct intel_dmc *dmc = i915_to_dmc(i915); 562 563 drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n"); 564 drm_WARN_ONCE(&i915->drm, dmc && 565 !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 566 "DMC program storage start is NULL\n"); 567 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), 568 "DMC SSP Base Not fine\n"); 569 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), 570 "DMC HTP Not fine\n"); 571 } 572 573 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 574 const struct stepping_info *si) 575 { 576 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 577 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 578 /* 579 * If we don't find a more specific one from above two checks, we 580 * then check for the generic one to be sure to work even with 581 * "broken firmware" 582 */ 583 (si->stepping == '*' && si->substepping == fw_info->substepping) || 584 (fw_info->stepping == '*' && fw_info->substepping == '*')) 585 return true; 586 587 return false; 588 } 589 590 /* 591 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 592 * already sanitized. 593 */ 594 static void dmc_set_fw_offset(struct intel_dmc *dmc, 595 const struct intel_fw_info *fw_info, 596 unsigned int num_entries, 597 const struct stepping_info *si, 598 u8 package_ver) 599 { 600 struct drm_i915_private *i915 = dmc->i915; 601 enum intel_dmc_id dmc_id; 602 unsigned int i; 603 604 for (i = 0; i < num_entries; i++) { 605 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 606 607 if (!is_valid_dmc_id(dmc_id)) { 608 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", dmc_id); 609 continue; 610 } 611 612 /* More specific versions come first, so we don't even have to 613 * check for the stepping since we already found a previous FW 614 * for this id. 615 */ 616 if (dmc->dmc_info[dmc_id].present) 617 continue; 618 619 if (fw_info_matches_stepping(&fw_info[i], si)) { 620 dmc->dmc_info[dmc_id].present = true; 621 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 622 } 623 } 624 } 625 626 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 627 const u32 *mmioaddr, u32 mmio_count, 628 int header_ver, enum intel_dmc_id dmc_id) 629 { 630 struct drm_i915_private *i915 = dmc->i915; 631 u32 start_range, end_range; 632 int i; 633 634 if (header_ver == 1) { 635 start_range = DMC_MMIO_START_RANGE; 636 end_range = DMC_MMIO_END_RANGE; 637 } else if (dmc_id == DMC_FW_MAIN) { 638 start_range = TGL_MAIN_MMIO_START; 639 end_range = TGL_MAIN_MMIO_END; 640 } else if (DISPLAY_VER(i915) >= 13) { 641 start_range = ADLP_PIPE_MMIO_START; 642 end_range = ADLP_PIPE_MMIO_END; 643 } else if (DISPLAY_VER(i915) >= 12) { 644 start_range = TGL_PIPE_MMIO_START(dmc_id); 645 end_range = TGL_PIPE_MMIO_END(dmc_id); 646 } else { 647 drm_warn(&i915->drm, "Unknown mmio range for sanity check"); 648 return false; 649 } 650 651 for (i = 0; i < mmio_count; i++) { 652 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 653 return false; 654 } 655 656 return true; 657 } 658 659 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 660 const struct intel_dmc_header_base *dmc_header, 661 size_t rem_size, enum intel_dmc_id dmc_id) 662 { 663 struct drm_i915_private *i915 = dmc->i915; 664 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 665 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 666 const u32 *mmioaddr, *mmiodata; 667 u32 mmio_count, mmio_count_max, start_mmioaddr; 668 u8 *payload; 669 670 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 671 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 672 673 /* 674 * Check if we can access common fields, we will checkc again below 675 * after we have read the version 676 */ 677 if (rem_size < sizeof(struct intel_dmc_header_base)) 678 goto error_truncated; 679 680 /* Cope with small differences between v1 and v3 */ 681 if (dmc_header->header_ver == 3) { 682 const struct intel_dmc_header_v3 *v3 = 683 (const struct intel_dmc_header_v3 *)dmc_header; 684 685 if (rem_size < sizeof(struct intel_dmc_header_v3)) 686 goto error_truncated; 687 688 mmioaddr = v3->mmioaddr; 689 mmiodata = v3->mmiodata; 690 mmio_count = v3->mmio_count; 691 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 692 /* header_len is in dwords */ 693 header_len_bytes = dmc_header->header_len * 4; 694 start_mmioaddr = v3->start_mmioaddr; 695 dmc_header_size = sizeof(*v3); 696 } else if (dmc_header->header_ver == 1) { 697 const struct intel_dmc_header_v1 *v1 = 698 (const struct intel_dmc_header_v1 *)dmc_header; 699 700 if (rem_size < sizeof(struct intel_dmc_header_v1)) 701 goto error_truncated; 702 703 mmioaddr = v1->mmioaddr; 704 mmiodata = v1->mmiodata; 705 mmio_count = v1->mmio_count; 706 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 707 header_len_bytes = dmc_header->header_len; 708 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 709 dmc_header_size = sizeof(*v1); 710 } else { 711 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 712 dmc_header->header_ver); 713 return 0; 714 } 715 716 if (header_len_bytes != dmc_header_size) { 717 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 718 "(%u bytes)\n", header_len_bytes); 719 return 0; 720 } 721 722 /* Cache the dmc header info. */ 723 if (mmio_count > mmio_count_max) { 724 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 725 return 0; 726 } 727 728 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 729 dmc_header->header_ver, dmc_id)) { 730 drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); 731 return 0; 732 } 733 734 drm_dbg_kms(&i915->drm, "DMC %d:\n", dmc_id); 735 for (i = 0; i < mmio_count; i++) { 736 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 737 dmc_info->mmiodata[i] = mmiodata[i]; 738 739 drm_dbg_kms(&i915->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 740 i, mmioaddr[i], mmiodata[i], 741 is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 742 is_dmc_evt_htp_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 743 disable_dmc_evt(i915, dmc_id, dmc_info->mmioaddr[i], 744 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 745 } 746 dmc_info->mmio_count = mmio_count; 747 dmc_info->start_mmioaddr = start_mmioaddr; 748 749 rem_size -= header_len_bytes; 750 751 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 752 payload_size = dmc_header->fw_size * 4; 753 if (rem_size < payload_size) 754 goto error_truncated; 755 756 if (payload_size > dmc->max_fw_size) { 757 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 758 return 0; 759 } 760 dmc_info->dmc_fw_size = dmc_header->fw_size; 761 762 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 763 if (!dmc_info->payload) 764 return 0; 765 766 payload = (u8 *)(dmc_header) + header_len_bytes; 767 memcpy(dmc_info->payload, payload, payload_size); 768 769 return header_len_bytes + payload_size; 770 771 error_truncated: 772 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 773 return 0; 774 } 775 776 static u32 777 parse_dmc_fw_package(struct intel_dmc *dmc, 778 const struct intel_package_header *package_header, 779 const struct stepping_info *si, 780 size_t rem_size) 781 { 782 struct drm_i915_private *i915 = dmc->i915; 783 u32 package_size = sizeof(struct intel_package_header); 784 u32 num_entries, max_entries; 785 const struct intel_fw_info *fw_info; 786 787 if (rem_size < package_size) 788 goto error_truncated; 789 790 if (package_header->header_ver == 1) { 791 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 792 } else if (package_header->header_ver == 2) { 793 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 794 } else { 795 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 796 package_header->header_ver); 797 return 0; 798 } 799 800 /* 801 * We should always have space for max_entries, 802 * even if not all are used 803 */ 804 package_size += max_entries * sizeof(struct intel_fw_info); 805 if (rem_size < package_size) 806 goto error_truncated; 807 808 if (package_header->header_len * 4 != package_size) { 809 drm_err(&i915->drm, "DMC firmware has wrong package header length " 810 "(%u bytes)\n", package_size); 811 return 0; 812 } 813 814 num_entries = package_header->num_entries; 815 if (WARN_ON(package_header->num_entries > max_entries)) 816 num_entries = max_entries; 817 818 fw_info = (const struct intel_fw_info *) 819 ((u8 *)package_header + sizeof(*package_header)); 820 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 821 package_header->header_ver); 822 823 /* dmc_offset is in dwords */ 824 return package_size; 825 826 error_truncated: 827 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 828 return 0; 829 } 830 831 /* Return number of bytes parsed or 0 on error */ 832 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 833 struct intel_css_header *css_header, 834 size_t rem_size) 835 { 836 struct drm_i915_private *i915 = dmc->i915; 837 838 if (rem_size < sizeof(struct intel_css_header)) { 839 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 840 return 0; 841 } 842 843 if (sizeof(struct intel_css_header) != 844 (css_header->header_len * 4)) { 845 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 846 "(%u bytes)\n", 847 (css_header->header_len * 4)); 848 return 0; 849 } 850 851 dmc->version = css_header->version; 852 853 return sizeof(struct intel_css_header); 854 } 855 856 static void parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 857 { 858 struct drm_i915_private *i915 = dmc->i915; 859 struct intel_css_header *css_header; 860 struct intel_package_header *package_header; 861 struct intel_dmc_header_base *dmc_header; 862 struct stepping_info display_info = { '*', '*'}; 863 const struct stepping_info *si = intel_get_stepping_info(i915, &display_info); 864 enum intel_dmc_id dmc_id; 865 u32 readcount = 0; 866 u32 r, offset; 867 868 if (!fw) 869 return; 870 871 /* Extract CSS Header information */ 872 css_header = (struct intel_css_header *)fw->data; 873 r = parse_dmc_fw_css(dmc, css_header, fw->size); 874 if (!r) 875 return; 876 877 readcount += r; 878 879 /* Extract Package Header information */ 880 package_header = (struct intel_package_header *)&fw->data[readcount]; 881 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 882 if (!r) 883 return; 884 885 readcount += r; 886 887 for_each_dmc_id(dmc_id) { 888 if (!dmc->dmc_info[dmc_id].present) 889 continue; 890 891 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 892 if (offset > fw->size) { 893 drm_err(&i915->drm, "Reading beyond the fw_size\n"); 894 continue; 895 } 896 897 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 898 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 899 } 900 } 901 902 static void intel_dmc_runtime_pm_get(struct drm_i915_private *i915) 903 { 904 drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); 905 i915->display.dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 906 } 907 908 static void intel_dmc_runtime_pm_put(struct drm_i915_private *i915) 909 { 910 intel_wakeref_t wakeref __maybe_unused = 911 fetch_and_zero(&i915->display.dmc.wakeref); 912 913 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 914 } 915 916 static const char *dmc_fallback_path(struct drm_i915_private *i915) 917 { 918 if (IS_ALDERLAKE_P(i915)) 919 return ADLP_DMC_FALLBACK_PATH; 920 921 return NULL; 922 } 923 924 static void dmc_load_work_fn(struct work_struct *work) 925 { 926 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 927 struct drm_i915_private *i915 = dmc->i915; 928 const struct firmware *fw = NULL; 929 const char *fallback_path; 930 int err; 931 932 err = request_firmware(&fw, dmc->fw_path, i915->drm.dev); 933 934 if (err == -ENOENT && !i915->params.dmc_firmware_path) { 935 fallback_path = dmc_fallback_path(i915); 936 if (fallback_path) { 937 drm_dbg_kms(&i915->drm, "%s not found, falling back to %s\n", 938 dmc->fw_path, fallback_path); 939 err = request_firmware(&fw, fallback_path, i915->drm.dev); 940 if (err == 0) 941 dmc->fw_path = fallback_path; 942 } 943 } 944 945 parse_dmc_fw(dmc, fw); 946 947 if (intel_dmc_has_payload(i915)) { 948 intel_dmc_load_program(i915); 949 intel_dmc_runtime_pm_put(i915); 950 951 drm_info(&i915->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 952 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 953 DMC_VERSION_MINOR(dmc->version)); 954 } else { 955 drm_notice(&i915->drm, 956 "Failed to load DMC firmware %s." 957 " Disabling runtime power management.\n", 958 dmc->fw_path); 959 drm_notice(&i915->drm, "DMC firmware homepage: %s", 960 INTEL_DMC_FIRMWARE_URL); 961 } 962 963 release_firmware(fw); 964 } 965 966 /** 967 * intel_dmc_init() - initialize the firmware loading. 968 * @i915: i915 drm device. 969 * 970 * This function is called at the time of loading the display driver to read 971 * firmware from a .bin file and copied into a internal memory. 972 */ 973 void intel_dmc_init(struct drm_i915_private *i915) 974 { 975 struct intel_dmc *dmc; 976 977 if (!HAS_DMC(i915)) 978 return; 979 980 /* 981 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 982 * runtime-suspend. 983 * 984 * On error, we return with the rpm wakeref held to prevent runtime 985 * suspend as runtime suspend *requires* a working DMC for whatever 986 * reason. 987 */ 988 intel_dmc_runtime_pm_get(i915); 989 990 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); 991 if (!dmc) 992 return; 993 994 dmc->i915 = i915; 995 996 INIT_WORK(&dmc->work, dmc_load_work_fn); 997 998 if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) { 999 dmc->fw_path = XE2LPD_DMC_PATH; 1000 dmc->max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 1001 } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) { 1002 dmc->fw_path = MTL_DMC_PATH; 1003 dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 1004 } else if (IS_DG2(i915)) { 1005 dmc->fw_path = DG2_DMC_PATH; 1006 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 1007 } else if (IS_ALDERLAKE_P(i915)) { 1008 dmc->fw_path = ADLP_DMC_PATH; 1009 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 1010 } else if (IS_ALDERLAKE_S(i915)) { 1011 dmc->fw_path = ADLS_DMC_PATH; 1012 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 1013 } else if (IS_DG1(i915)) { 1014 dmc->fw_path = DG1_DMC_PATH; 1015 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 1016 } else if (IS_ROCKETLAKE(i915)) { 1017 dmc->fw_path = RKL_DMC_PATH; 1018 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 1019 } else if (IS_TIGERLAKE(i915)) { 1020 dmc->fw_path = TGL_DMC_PATH; 1021 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 1022 } else if (DISPLAY_VER(i915) == 11) { 1023 dmc->fw_path = ICL_DMC_PATH; 1024 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE; 1025 } else if (IS_GEMINILAKE(i915)) { 1026 dmc->fw_path = GLK_DMC_PATH; 1027 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE; 1028 } else if (IS_KABYLAKE(i915) || 1029 IS_COFFEELAKE(i915) || 1030 IS_COMETLAKE(i915)) { 1031 dmc->fw_path = KBL_DMC_PATH; 1032 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE; 1033 } else if (IS_SKYLAKE(i915)) { 1034 dmc->fw_path = SKL_DMC_PATH; 1035 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE; 1036 } else if (IS_BROXTON(i915)) { 1037 dmc->fw_path = BXT_DMC_PATH; 1038 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE; 1039 } 1040 1041 if (i915->params.dmc_firmware_path) { 1042 if (strlen(i915->params.dmc_firmware_path) == 0) { 1043 drm_info(&i915->drm, 1044 "Disabling DMC firmware and runtime PM\n"); 1045 goto out; 1046 } 1047 1048 dmc->fw_path = i915->params.dmc_firmware_path; 1049 } 1050 1051 if (!dmc->fw_path) { 1052 drm_dbg_kms(&i915->drm, 1053 "No known DMC firmware for platform, disabling runtime PM\n"); 1054 goto out; 1055 } 1056 1057 i915->display.dmc.dmc = dmc; 1058 1059 drm_dbg_kms(&i915->drm, "Loading %s\n", dmc->fw_path); 1060 queue_work(i915->unordered_wq, &dmc->work); 1061 1062 return; 1063 1064 out: 1065 kfree(dmc); 1066 } 1067 1068 /** 1069 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1070 * @i915: i915 drm device 1071 * 1072 * Prepare the DMC firmware before entering system suspend. This includes 1073 * flushing pending work items and releasing any resources acquired during 1074 * init. 1075 */ 1076 void intel_dmc_suspend(struct drm_i915_private *i915) 1077 { 1078 struct intel_dmc *dmc = i915_to_dmc(i915); 1079 1080 if (!HAS_DMC(i915)) 1081 return; 1082 1083 if (dmc) 1084 flush_work(&dmc->work); 1085 1086 intel_dmc_wl_disable(i915); 1087 1088 /* Drop the reference held in case DMC isn't loaded. */ 1089 if (!intel_dmc_has_payload(i915)) 1090 intel_dmc_runtime_pm_put(i915); 1091 } 1092 1093 /** 1094 * intel_dmc_resume() - init DMC firmware during system resume 1095 * @i915: i915 drm device 1096 * 1097 * Reinitialize the DMC firmware during system resume, reacquiring any 1098 * resources released in intel_dmc_suspend(). 1099 */ 1100 void intel_dmc_resume(struct drm_i915_private *i915) 1101 { 1102 if (!HAS_DMC(i915)) 1103 return; 1104 1105 /* 1106 * Reacquire the reference to keep RPM disabled in case DMC isn't 1107 * loaded. 1108 */ 1109 if (!intel_dmc_has_payload(i915)) 1110 intel_dmc_runtime_pm_get(i915); 1111 } 1112 1113 /** 1114 * intel_dmc_fini() - unload the DMC firmware. 1115 * @i915: i915 drm device. 1116 * 1117 * Firmmware unloading includes freeing the internal memory and reset the 1118 * firmware loading status. 1119 */ 1120 void intel_dmc_fini(struct drm_i915_private *i915) 1121 { 1122 struct intel_dmc *dmc = i915_to_dmc(i915); 1123 enum intel_dmc_id dmc_id; 1124 1125 if (!HAS_DMC(i915)) 1126 return; 1127 1128 intel_dmc_suspend(i915); 1129 drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); 1130 1131 if (dmc) { 1132 for_each_dmc_id(dmc_id) 1133 kfree(dmc->dmc_info[dmc_id].payload); 1134 1135 kfree(dmc); 1136 i915->display.dmc.dmc = NULL; 1137 } 1138 } 1139 1140 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, 1141 struct drm_i915_private *i915) 1142 { 1143 struct intel_dmc *dmc = i915_to_dmc(i915); 1144 1145 if (!HAS_DMC(i915)) 1146 return; 1147 1148 i915_error_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1149 i915_error_printf(m, "DMC loaded: %s\n", 1150 str_yes_no(intel_dmc_has_payload(i915))); 1151 if (dmc) 1152 i915_error_printf(m, "DMC fw version: %d.%d\n", 1153 DMC_VERSION_MAJOR(dmc->version), 1154 DMC_VERSION_MINOR(dmc->version)); 1155 } 1156 1157 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1158 { 1159 struct drm_i915_private *i915 = m->private; 1160 struct intel_dmc *dmc = i915_to_dmc(i915); 1161 intel_wakeref_t wakeref; 1162 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1163 1164 if (!HAS_DMC(i915)) 1165 return -ENODEV; 1166 1167 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1168 1169 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1170 seq_printf(m, "fw loaded: %s\n", 1171 str_yes_no(intel_dmc_has_payload(i915))); 1172 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1173 seq_printf(m, "Pipe A fw needed: %s\n", 1174 str_yes_no(DISPLAY_VER(i915) >= 12)); 1175 seq_printf(m, "Pipe A fw loaded: %s\n", 1176 str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEA))); 1177 seq_printf(m, "Pipe B fw needed: %s\n", 1178 str_yes_no(IS_ALDERLAKE_P(i915) || 1179 DISPLAY_VER(i915) >= 14)); 1180 seq_printf(m, "Pipe B fw loaded: %s\n", 1181 str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEB))); 1182 1183 if (!intel_dmc_has_payload(i915)) 1184 goto out; 1185 1186 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1187 DMC_VERSION_MINOR(dmc->version)); 1188 1189 if (DISPLAY_VER(i915) >= 12) { 1190 i915_reg_t dc3co_reg; 1191 1192 if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) { 1193 dc3co_reg = DG1_DMC_DEBUG3; 1194 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1195 } else { 1196 dc3co_reg = TGL_DMC_DEBUG3; 1197 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1198 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1199 } 1200 1201 seq_printf(m, "DC3CO count: %d\n", 1202 intel_de_read(i915, dc3co_reg)); 1203 } else { 1204 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : 1205 SKL_DMC_DC3_DC5_COUNT; 1206 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) 1207 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1208 } 1209 1210 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); 1211 if (i915_mmio_reg_valid(dc6_reg)) 1212 seq_printf(m, "DC5 -> DC6 count: %d\n", 1213 intel_de_read(i915, dc6_reg)); 1214 1215 seq_printf(m, "program base: 0x%08x\n", 1216 intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1217 1218 out: 1219 seq_printf(m, "ssp base: 0x%08x\n", 1220 intel_de_read(i915, DMC_SSP_BASE)); 1221 seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL)); 1222 1223 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1224 1225 return 0; 1226 } 1227 1228 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1229 1230 void intel_dmc_debugfs_register(struct drm_i915_private *i915) 1231 { 1232 struct drm_minor *minor = i915->drm.primary; 1233 1234 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 1235 i915, &intel_dmc_debugfs_status_fops); 1236 } 1237