1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 #include <drm/drm_vblank.h> 28 29 #include <drm/drm_file.h> 30 #include <drm/drm_print.h> 31 32 #include "i915_reg.h" 33 #include "i915_utils.h" 34 #include "intel_crtc.h" 35 #include "intel_de.h" 36 #include "intel_display_power_well.h" 37 #include "intel_display_regs.h" 38 #include "intel_display_rpm.h" 39 #include "intel_display_types.h" 40 #include "intel_dmc.h" 41 #include "intel_dmc_regs.h" 42 #include "intel_flipq.h" 43 #include "intel_step.h" 44 45 /** 46 * DOC: DMC Firmware Support 47 * 48 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 49 * engine to save and restore the state of display engine when it enter into 50 * low-power state and comes back to normal. 51 */ 52 53 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 54 55 enum intel_dmc_id { 56 DMC_FW_MAIN = 0, 57 DMC_FW_PIPEA, 58 DMC_FW_PIPEB, 59 DMC_FW_PIPEC, 60 DMC_FW_PIPED, 61 DMC_FW_MAX 62 }; 63 64 struct intel_dmc { 65 struct intel_display *display; 66 struct work_struct work; 67 const char *fw_path; 68 u32 max_fw_size; /* bytes */ 69 u32 version; 70 struct { 71 u32 dc5_start; 72 u32 count; 73 } dc6_allowed; 74 struct dmc_fw_info { 75 u32 mmio_count; 76 i915_reg_t mmioaddr[20]; 77 u32 mmiodata[20]; 78 u32 dmc_offset; 79 u32 start_mmioaddr; 80 u32 dmc_fw_size; /*dwords */ 81 u32 *payload; 82 bool present; 83 } dmc_info[DMC_FW_MAX]; 84 }; 85 86 /* Note: This may be NULL. */ 87 static struct intel_dmc *display_to_dmc(struct intel_display *display) 88 { 89 return display->dmc.dmc; 90 } 91 92 static const char *dmc_firmware_param(struct intel_display *display) 93 { 94 const char *p = display->params.dmc_firmware_path; 95 96 return p && *p ? p : NULL; 97 } 98 99 static bool dmc_firmware_param_disabled(struct intel_display *display) 100 { 101 const char *p = dmc_firmware_param(display); 102 103 /* Magic path to indicate disabled */ 104 return p && !strcmp(p, "/dev/null"); 105 } 106 107 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 108 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 109 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 110 111 #define DMC_PATH(platform) \ 112 "i915/" __stringify(platform) "_dmc.bin" 113 114 /* 115 * New DMC additions should not use this. This is used solely to remain 116 * compatible with systems that have not yet updated DMC blobs to use 117 * unversioned file names. 118 */ 119 #define DMC_LEGACY_PATH(platform, major, minor) \ 120 "i915/" \ 121 __stringify(platform) "_dmc_ver" \ 122 __stringify(major) "_" \ 123 __stringify(minor) ".bin" 124 125 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 126 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 127 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 128 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 129 130 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd) 131 MODULE_FIRMWARE(XE3LPD_DMC_PATH); 132 133 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 134 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 135 136 #define BMG_DMC_PATH DMC_PATH(bmg) 137 MODULE_FIRMWARE(BMG_DMC_PATH); 138 139 #define MTL_DMC_PATH DMC_PATH(mtl) 140 MODULE_FIRMWARE(MTL_DMC_PATH); 141 142 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 143 MODULE_FIRMWARE(DG2_DMC_PATH); 144 145 #define ADLP_DMC_PATH DMC_PATH(adlp) 146 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 147 MODULE_FIRMWARE(ADLP_DMC_PATH); 148 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 149 150 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 151 MODULE_FIRMWARE(ADLS_DMC_PATH); 152 153 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 154 MODULE_FIRMWARE(DG1_DMC_PATH); 155 156 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 157 MODULE_FIRMWARE(RKL_DMC_PATH); 158 159 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 160 MODULE_FIRMWARE(TGL_DMC_PATH); 161 162 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 163 #define ICL_DMC_MAX_FW_SIZE 0x6000 164 MODULE_FIRMWARE(ICL_DMC_PATH); 165 166 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 167 #define GLK_DMC_MAX_FW_SIZE 0x4000 168 MODULE_FIRMWARE(GLK_DMC_PATH); 169 170 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 171 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 172 MODULE_FIRMWARE(KBL_DMC_PATH); 173 174 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 175 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 176 MODULE_FIRMWARE(SKL_DMC_PATH); 177 178 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 179 #define BXT_DMC_MAX_FW_SIZE 0x3000 180 MODULE_FIRMWARE(BXT_DMC_PATH); 181 182 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) 183 { 184 const char *fw_path = NULL; 185 u32 max_fw_size = 0; 186 187 if (DISPLAY_VERx100(display) == 3002 || 188 DISPLAY_VERx100(display) == 3000) { 189 fw_path = XE3LPD_DMC_PATH; 190 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 191 } else if (DISPLAY_VERx100(display) == 2000) { 192 fw_path = XE2LPD_DMC_PATH; 193 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 194 } else if (DISPLAY_VERx100(display) == 1401) { 195 fw_path = BMG_DMC_PATH; 196 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 197 } else if (DISPLAY_VERx100(display) == 1400) { 198 fw_path = MTL_DMC_PATH; 199 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 200 } else if (display->platform.dg2) { 201 fw_path = DG2_DMC_PATH; 202 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 203 } else if (display->platform.alderlake_p) { 204 fw_path = ADLP_DMC_PATH; 205 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 206 } else if (display->platform.alderlake_s) { 207 fw_path = ADLS_DMC_PATH; 208 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 209 } else if (display->platform.dg1) { 210 fw_path = DG1_DMC_PATH; 211 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 212 } else if (display->platform.rocketlake) { 213 fw_path = RKL_DMC_PATH; 214 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 215 } else if (display->platform.tigerlake) { 216 fw_path = TGL_DMC_PATH; 217 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 218 } else if (DISPLAY_VER(display) == 11) { 219 fw_path = ICL_DMC_PATH; 220 max_fw_size = ICL_DMC_MAX_FW_SIZE; 221 } else if (display->platform.geminilake) { 222 fw_path = GLK_DMC_PATH; 223 max_fw_size = GLK_DMC_MAX_FW_SIZE; 224 } else if (display->platform.kabylake || 225 display->platform.coffeelake || 226 display->platform.cometlake) { 227 fw_path = KBL_DMC_PATH; 228 max_fw_size = KBL_DMC_MAX_FW_SIZE; 229 } else if (display->platform.skylake) { 230 fw_path = SKL_DMC_PATH; 231 max_fw_size = SKL_DMC_MAX_FW_SIZE; 232 } else if (display->platform.broxton) { 233 fw_path = BXT_DMC_PATH; 234 max_fw_size = BXT_DMC_MAX_FW_SIZE; 235 } 236 237 *size = max_fw_size; 238 239 return fw_path; 240 } 241 242 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 243 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 244 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 245 #define DMC_V1_MAX_MMIO_COUNT 8 246 #define DMC_V3_MAX_MMIO_COUNT 20 247 #define DMC_V1_MMIO_START_RANGE 0x80000 248 249 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 250 251 struct intel_css_header { 252 /* 0x09 for DMC */ 253 u32 module_type; 254 255 /* Includes the DMC specific header in dwords */ 256 u32 header_len; 257 258 /* always value would be 0x10000 */ 259 u32 header_ver; 260 261 /* Not used */ 262 u32 module_id; 263 264 /* Not used */ 265 u32 module_vendor; 266 267 /* in YYYYMMDD format */ 268 u32 date; 269 270 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 271 u32 size; 272 273 /* Not used */ 274 u32 key_size; 275 276 /* Not used */ 277 u32 modulus_size; 278 279 /* Not used */ 280 u32 exponent_size; 281 282 /* Not used */ 283 u32 reserved1[12]; 284 285 /* Major Minor */ 286 u32 version; 287 288 /* Not used */ 289 u32 reserved2[8]; 290 291 /* Not used */ 292 u32 kernel_header_info; 293 } __packed; 294 295 struct intel_fw_info { 296 u8 reserved1; 297 298 /* reserved on package_header version 1, must be 0 on version 2 */ 299 u8 dmc_id; 300 301 /* Stepping (A, B, C, ..., *). * is a wildcard */ 302 char stepping; 303 304 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 305 char substepping; 306 307 u32 offset; 308 u32 reserved2; 309 } __packed; 310 311 struct intel_package_header { 312 /* DMC container header length in dwords */ 313 u8 header_len; 314 315 /* 0x01, 0x02 */ 316 u8 header_ver; 317 318 u8 reserved[10]; 319 320 /* Number of valid entries in the FWInfo array below */ 321 u32 num_entries; 322 } __packed; 323 324 struct intel_dmc_header_base { 325 /* always value would be 0x40403E3E */ 326 u32 signature; 327 328 /* DMC binary header length */ 329 u8 header_len; 330 331 /* 0x01 */ 332 u8 header_ver; 333 334 /* Reserved */ 335 u16 dmcc_ver; 336 337 /* Major, Minor */ 338 u32 project; 339 340 /* Firmware program size (excluding header) in dwords */ 341 u32 fw_size; 342 343 /* Major Minor version */ 344 u32 fw_version; 345 } __packed; 346 347 struct intel_dmc_header_v1 { 348 struct intel_dmc_header_base base; 349 350 /* Number of valid MMIO cycles present. */ 351 u32 mmio_count; 352 353 /* MMIO address */ 354 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 355 356 /* MMIO data */ 357 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 358 359 /* FW filename */ 360 char dfile[32]; 361 362 u32 reserved1[2]; 363 } __packed; 364 365 struct intel_dmc_header_v3 { 366 struct intel_dmc_header_base base; 367 368 /* DMC RAM start MMIO address */ 369 u32 start_mmioaddr; 370 371 u32 reserved[9]; 372 373 /* FW filename */ 374 char dfile[32]; 375 376 /* Number of valid MMIO cycles present. */ 377 u32 mmio_count; 378 379 /* MMIO address */ 380 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 381 382 /* MMIO data */ 383 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 384 } __packed; 385 386 struct stepping_info { 387 char stepping; 388 char substepping; 389 }; 390 391 #define for_each_dmc_id(__dmc_id) \ 392 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 393 394 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 395 { 396 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 397 } 398 399 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) 400 { 401 struct intel_dmc *dmc = display_to_dmc(display); 402 403 return dmc && dmc->dmc_info[dmc_id].payload; 404 } 405 406 bool intel_dmc_has_payload(struct intel_display *display) 407 { 408 return has_dmc_id_fw(display, DMC_FW_MAIN); 409 } 410 411 static const struct stepping_info * 412 intel_get_stepping_info(struct intel_display *display, 413 struct stepping_info *si) 414 { 415 const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display)); 416 417 si->stepping = step_name[0]; 418 si->substepping = step_name[1]; 419 return si; 420 } 421 422 static void gen9_set_dc_state_debugmask(struct intel_display *display) 423 { 424 /* The below bit doesn't need to be cleared ever afterwards */ 425 intel_de_rmw(display, DC_STATE_DEBUG, 0, 426 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 427 intel_de_posting_read(display, DC_STATE_DEBUG); 428 } 429 430 static void disable_event_handler(struct intel_display *display, 431 i915_reg_t ctl_reg, i915_reg_t htp_reg) 432 { 433 intel_de_write(display, ctl_reg, 434 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 435 DMC_EVT_CTL_TYPE_EDGE_0_1) | 436 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 437 DMC_EVENT_FALSE)); 438 intel_de_write(display, htp_reg, 0); 439 } 440 441 static void disable_all_event_handlers(struct intel_display *display, 442 enum intel_dmc_id dmc_id) 443 { 444 int handler; 445 446 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 447 if (DISPLAY_VER(display) < 12) 448 return; 449 450 if (!has_dmc_id_fw(display, dmc_id)) 451 return; 452 453 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 454 disable_event_handler(display, 455 DMC_EVT_CTL(display, dmc_id, handler), 456 DMC_EVT_HTP(display, dmc_id, handler)); 457 } 458 459 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 460 { 461 enum pipe pipe; 462 463 /* 464 * Wa_16015201720:adl-p,dg2 465 * The WA requires clock gating to be disabled all the time 466 * for pipe A and B. 467 * For pipe C and D clock gating needs to be disabled only 468 * during initializing the firmware. 469 */ 470 if (enable) 471 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 472 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 473 0, PIPEDMC_GATING_DIS); 474 else 475 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 476 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 477 PIPEDMC_GATING_DIS, 0); 478 } 479 480 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) 481 { 482 /* 483 * Wa_16015201720 484 * The WA requires clock gating to be disabled all the time 485 * for pipe A and B. 486 */ 487 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, 488 MTL_PIPEDMC_GATING_DIS(PIPE_A) | 489 MTL_PIPEDMC_GATING_DIS(PIPE_B)); 490 } 491 492 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 493 { 494 if (display->platform.meteorlake && enable) 495 mtl_pipedmc_clock_gating_wa(display); 496 else if (DISPLAY_VER(display) == 13) 497 adlp_pipedmc_clock_gating_wa(display, enable); 498 } 499 500 static u32 pipedmc_interrupt_mask(struct intel_display *display) 501 { 502 /* 503 * FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B 504 * triggering it during the first DC state transition. Figure 505 * out what is going on... 506 */ 507 return PIPEDMC_FLIPQ_PROG_DONE | 508 PIPEDMC_GTT_FAULT | 509 PIPEDMC_ATS_FAULT; 510 } 511 512 static u32 dmc_evt_ctl_disable(void) 513 { 514 return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 515 DMC_EVT_CTL_TYPE_EDGE_0_1) | 516 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 517 DMC_EVENT_FALSE); 518 } 519 520 static bool is_dmc_evt_ctl_reg(struct intel_display *display, 521 enum intel_dmc_id dmc_id, i915_reg_t reg) 522 { 523 u32 offset = i915_mmio_reg_offset(reg); 524 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); 525 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 526 527 return offset >= start && offset < end; 528 } 529 530 static bool is_dmc_evt_htp_reg(struct intel_display *display, 531 enum intel_dmc_id dmc_id, i915_reg_t reg) 532 { 533 u32 offset = i915_mmio_reg_offset(reg); 534 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); 535 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 536 537 return offset >= start && offset < end; 538 } 539 540 static bool is_event_handler(struct intel_display *display, 541 enum intel_dmc_id dmc_id, 542 unsigned int event_id, 543 i915_reg_t reg, u32 data) 544 { 545 return is_dmc_evt_ctl_reg(display, dmc_id, reg) && 546 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id; 547 } 548 549 static bool fixup_dmc_evt(struct intel_display *display, 550 enum intel_dmc_id dmc_id, 551 i915_reg_t reg_ctl, u32 *data_ctl, 552 i915_reg_t reg_htp, u32 *data_htp) 553 { 554 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl)) 555 return false; 556 557 if (!is_dmc_evt_htp_reg(display, dmc_id, reg_htp)) 558 return false; 559 560 /* make sure reg_ctl and reg_htp are for the same event */ 561 if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != 562 i915_mmio_reg_offset(reg_htp) - i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0))) 563 return false; 564 565 /* 566 * On ADL-S the HRR event handler is not restored after DC6. 567 * Clear it to zero from the beginning to avoid mismatches later. 568 */ 569 if (display->platform.alderlake_s && dmc_id == DMC_FW_MAIN && 570 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { 571 *data_ctl = 0; 572 *data_htp = 0; 573 return true; 574 } 575 576 return false; 577 } 578 579 static bool disable_dmc_evt(struct intel_display *display, 580 enum intel_dmc_id dmc_id, 581 i915_reg_t reg, u32 data) 582 { 583 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) 584 return false; 585 586 /* keep all pipe DMC events disabled by default */ 587 if (dmc_id != DMC_FW_MAIN) 588 return true; 589 590 /* also disable the flip queue event on the main DMC on TGL */ 591 if (display->platform.tigerlake && 592 is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data)) 593 return true; 594 595 /* also disable the HRR event on the main DMC on TGL/ADLS */ 596 if ((display->platform.tigerlake || display->platform.alderlake_s) && 597 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg, data)) 598 return true; 599 600 return false; 601 } 602 603 static u32 dmc_mmiodata(struct intel_display *display, 604 struct intel_dmc *dmc, 605 enum intel_dmc_id dmc_id, int i) 606 { 607 if (disable_dmc_evt(display, dmc_id, 608 dmc->dmc_info[dmc_id].mmioaddr[i], 609 dmc->dmc_info[dmc_id].mmiodata[i])) 610 return dmc_evt_ctl_disable(); 611 else 612 return dmc->dmc_info[dmc_id].mmiodata[i]; 613 } 614 615 static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id) 616 { 617 struct intel_dmc *dmc = display_to_dmc(display); 618 int i; 619 620 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 621 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], 622 dmc_mmiodata(display, dmc, dmc_id, i)); 623 } 624 } 625 626 static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id) 627 { 628 struct intel_dmc *dmc = display_to_dmc(display); 629 int i; 630 631 disable_all_event_handlers(display, dmc_id); 632 633 preempt_disable(); 634 635 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 636 intel_de_write_fw(display, 637 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 638 dmc->dmc_info[dmc_id].payload[i]); 639 } 640 641 preempt_enable(); 642 643 dmc_load_mmio(display, dmc_id); 644 } 645 646 static void assert_dmc_loaded(struct intel_display *display, 647 enum intel_dmc_id dmc_id) 648 { 649 struct intel_dmc *dmc = display_to_dmc(display); 650 u32 expected, found; 651 int i; 652 653 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 654 return; 655 656 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); 657 expected = dmc->dmc_info[dmc_id].payload[0]; 658 659 drm_WARN(display->drm, found != expected, 660 "DMC %d program storage start incorrect (expected 0x%x, current 0x%x)\n", 661 dmc_id, expected, found); 662 663 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 664 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 665 666 found = intel_de_read(display, reg); 667 expected = dmc_mmiodata(display, dmc, dmc_id, i); 668 669 /* once set DMC_EVT_CTL_ENABLE can't be cleared :/ */ 670 if (is_dmc_evt_ctl_reg(display, dmc_id, reg)) { 671 found &= ~DMC_EVT_CTL_ENABLE; 672 expected &= ~DMC_EVT_CTL_ENABLE; 673 } 674 675 drm_WARN(display->drm, found != expected, 676 "DMC %d mmio[%d]/0x%x incorrect (expected 0x%x, current 0x%x)\n", 677 dmc_id, i, i915_mmio_reg_offset(reg), expected, found); 678 } 679 } 680 681 void assert_main_dmc_loaded(struct intel_display *display) 682 { 683 assert_dmc_loaded(display, DMC_FW_MAIN); 684 } 685 686 static bool need_pipedmc_load_program(struct intel_display *display) 687 { 688 /* On TGL/derivatives pipe DMC state is lost when PG1 is disabled */ 689 return DISPLAY_VER(display) == 12; 690 } 691 692 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe) 693 { 694 /* 695 * PTL: 696 * - pipe A/B DMC doesn't need save/restore 697 * - pipe C/D DMC is in PG0, needs manual save/restore 698 */ 699 if (DISPLAY_VER(display) == 30) 700 return pipe >= PIPE_C; 701 702 /* 703 * FIXME LNL unclear, main DMC firmware has the pipe DMC A/B PG0 704 * save/restore, but so far unable to see the loss of pipe DMC state 705 * in action. Are we just failing to turn off PG0 due to some other 706 * SoC level stuff? 707 */ 708 if (DISPLAY_VER(display) == 20) 709 return false; 710 711 /* 712 * FIXME BMG untested, main DMC firmware has the 713 * pipe DMC A/B PG0 save/restore... 714 */ 715 if (display->platform.battlemage) 716 return false; 717 718 /* 719 * DG2: 720 * - Pipe DMCs presumably in PG0? 721 * - No DC6, and even DC9 doesn't seem to result 722 * in loss of DMC state for whatever reason 723 */ 724 if (display->platform.dg2) 725 return false; 726 727 /* 728 * ADL/MTL: 729 * - pipe A/B DMC is in PG0, saved/restored by the main DMC 730 * - pipe C/D DMC is in PG0, needs manual save/restore 731 */ 732 if (IS_DISPLAY_VER(display, 13, 14)) 733 return pipe >= PIPE_C; 734 735 return false; 736 } 737 738 static bool can_enable_pipedmc(const struct intel_crtc_state *crtc_state) 739 { 740 struct intel_display *display = to_intel_display(crtc_state); 741 742 /* 743 * On TGL/derivatives pipe DMC state is lost when PG1 is disabled. 744 * Do not even enable the pipe DMC when that can happen outside 745 * of driver control (PSR+DC5/6). 746 */ 747 if (DISPLAY_VER(display) == 12 && crtc_state->has_psr) 748 return false; 749 750 return true; 751 } 752 753 void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state) 754 { 755 struct intel_display *display = to_intel_display(crtc_state); 756 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 757 enum pipe pipe = crtc->pipe; 758 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 759 760 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 761 return; 762 763 if (!can_enable_pipedmc(crtc_state)) { 764 intel_dmc_disable_pipe(crtc_state); 765 return; 766 } 767 768 if (need_pipedmc_load_program(display)) 769 dmc_load_program(display, dmc_id); 770 else if (need_pipedmc_load_mmio(display, pipe)) 771 dmc_load_mmio(display, dmc_id); 772 773 assert_dmc_loaded(display, dmc_id); 774 775 if (DISPLAY_VER(display) >= 20) { 776 intel_flipq_reset(display, pipe); 777 778 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 779 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display)); 780 } 781 782 if (DISPLAY_VER(display) >= 14) 783 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 784 else 785 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 786 } 787 788 void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state) 789 { 790 struct intel_display *display = to_intel_display(crtc_state); 791 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 792 enum pipe pipe = crtc->pipe; 793 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 794 795 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 796 return; 797 798 if (DISPLAY_VER(display) >= 14) 799 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 800 else 801 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 802 803 if (DISPLAY_VER(display) >= 20) { 804 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0); 805 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 806 807 intel_flipq_reset(display, pipe); 808 } 809 } 810 811 static void dmc_configure_event(struct intel_display *display, 812 enum intel_dmc_id dmc_id, 813 unsigned int event_id, 814 bool enable) 815 { 816 struct intel_dmc *dmc = display_to_dmc(display); 817 int num_handlers = 0; 818 int i; 819 820 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 821 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 822 u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; 823 824 if (!is_event_handler(display, dmc_id, event_id, reg, data)) 825 continue; 826 827 intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable()); 828 num_handlers++; 829 } 830 831 drm_WARN_ONCE(display->drm, num_handlers != 1, 832 "DMC %d has %d handlers for event 0x%x\n", 833 dmc_id, num_handlers, event_id); 834 } 835 836 /** 837 * intel_dmc_block_pkgc() - block PKG C-state 838 * @display: display instance 839 * @pipe: pipe which register use to block 840 * @block: block/unblock 841 * 842 * This interface is target for Wa_16025596647 usage. I.e. to set/clear 843 * PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register. 844 */ 845 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, 846 bool block) 847 { 848 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), 849 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, block ? 850 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0); 851 } 852 853 /** 854 * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG 855 * C-state exit 856 * @display: display instance 857 * @pipe: pipe which register use to block 858 * @enable: enable/disable 859 * 860 * This interface is target for Wa_16025596647 usage. I.e. start the package C 861 * exit at the start of the undelayed vblank 862 */ 863 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, 864 enum pipe pipe, bool enable) 865 { 866 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 867 868 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable); 869 } 870 871 /** 872 * intel_dmc_load_program() - write the firmware from memory to register. 873 * @display: display instance 874 * 875 * DMC firmware is read from a .bin file and kept in internal memory one time. 876 * Everytime display comes back from low power state this function is called to 877 * copy the firmware from internal memory to registers. 878 */ 879 void intel_dmc_load_program(struct intel_display *display) 880 { 881 struct i915_power_domains *power_domains = &display->power.domains; 882 enum intel_dmc_id dmc_id; 883 884 if (!intel_dmc_has_payload(display)) 885 return; 886 887 assert_display_rpm_held(display); 888 889 pipedmc_clock_gating_wa(display, true); 890 891 for_each_dmc_id(dmc_id) { 892 dmc_load_program(display, dmc_id); 893 assert_dmc_loaded(display, dmc_id); 894 } 895 896 if (DISPLAY_VER(display) >= 20) 897 intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL, 898 PIPE_D_DMC_W2_PTS_CONFIG_SELECT(PIPE_D) | 899 PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) | 900 PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) | 901 PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A)); 902 903 power_domains->dc_state = 0; 904 905 gen9_set_dc_state_debugmask(display); 906 907 pipedmc_clock_gating_wa(display, false); 908 } 909 910 /** 911 * intel_dmc_disable_program() - disable the firmware 912 * @display: display instance 913 * 914 * Disable all event handlers in the firmware, making sure the firmware is 915 * inactive after the display is uninitialized. 916 */ 917 void intel_dmc_disable_program(struct intel_display *display) 918 { 919 enum intel_dmc_id dmc_id; 920 921 if (!intel_dmc_has_payload(display)) 922 return; 923 924 pipedmc_clock_gating_wa(display, true); 925 926 for_each_dmc_id(dmc_id) 927 disable_all_event_handlers(display, dmc_id); 928 929 pipedmc_clock_gating_wa(display, false); 930 } 931 932 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 933 const struct stepping_info *si) 934 { 935 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 936 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 937 /* 938 * If we don't find a more specific one from above two checks, we 939 * then check for the generic one to be sure to work even with 940 * "broken firmware" 941 */ 942 (si->stepping == '*' && si->substepping == fw_info->substepping) || 943 (fw_info->stepping == '*' && fw_info->substepping == '*')) 944 return true; 945 946 return false; 947 } 948 949 /* 950 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 951 * already sanitized. 952 */ 953 static void dmc_set_fw_offset(struct intel_dmc *dmc, 954 const struct intel_fw_info *fw_info, 955 unsigned int num_entries, 956 const struct stepping_info *si, 957 u8 package_ver) 958 { 959 struct intel_display *display = dmc->display; 960 enum intel_dmc_id dmc_id; 961 unsigned int i; 962 963 for (i = 0; i < num_entries; i++) { 964 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 965 966 if (!is_valid_dmc_id(dmc_id)) { 967 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); 968 continue; 969 } 970 971 /* More specific versions come first, so we don't even have to 972 * check for the stepping since we already found a previous FW 973 * for this id. 974 */ 975 if (dmc->dmc_info[dmc_id].present) 976 continue; 977 978 if (fw_info_matches_stepping(&fw_info[i], si)) { 979 dmc->dmc_info[dmc_id].present = true; 980 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 981 } 982 } 983 } 984 985 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 986 const u32 *mmioaddr, u32 mmio_count, 987 int header_ver, enum intel_dmc_id dmc_id) 988 { 989 struct intel_display *display = dmc->display; 990 u32 start_range, end_range; 991 int i; 992 993 if (header_ver == 1) { 994 start_range = DMC_MMIO_START_RANGE; 995 end_range = DMC_MMIO_END_RANGE; 996 } else if (dmc_id == DMC_FW_MAIN) { 997 start_range = TGL_MAIN_MMIO_START; 998 end_range = TGL_MAIN_MMIO_END; 999 } else if (DISPLAY_VER(display) >= 13) { 1000 start_range = ADLP_PIPE_MMIO_START; 1001 end_range = ADLP_PIPE_MMIO_END; 1002 } else if (DISPLAY_VER(display) >= 12) { 1003 start_range = TGL_PIPE_MMIO_START(dmc_id); 1004 end_range = TGL_PIPE_MMIO_END(dmc_id); 1005 } else { 1006 drm_warn(display->drm, "Unknown mmio range for sanity check"); 1007 return false; 1008 } 1009 1010 for (i = 0; i < mmio_count; i++) { 1011 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 1012 return false; 1013 } 1014 1015 return true; 1016 } 1017 1018 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 1019 const struct intel_dmc_header_base *dmc_header, 1020 size_t rem_size, enum intel_dmc_id dmc_id) 1021 { 1022 struct intel_display *display = dmc->display; 1023 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 1024 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 1025 const u32 *mmioaddr, *mmiodata; 1026 u32 mmio_count, mmio_count_max, start_mmioaddr; 1027 u8 *payload; 1028 1029 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 1030 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 1031 1032 /* 1033 * Check if we can access common fields, we will checkc again below 1034 * after we have read the version 1035 */ 1036 if (rem_size < sizeof(struct intel_dmc_header_base)) 1037 goto error_truncated; 1038 1039 /* Cope with small differences between v1 and v3 */ 1040 if (dmc_header->header_ver == 3) { 1041 const struct intel_dmc_header_v3 *v3 = 1042 (const struct intel_dmc_header_v3 *)dmc_header; 1043 1044 if (rem_size < sizeof(struct intel_dmc_header_v3)) 1045 goto error_truncated; 1046 1047 mmioaddr = v3->mmioaddr; 1048 mmiodata = v3->mmiodata; 1049 mmio_count = v3->mmio_count; 1050 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 1051 /* header_len is in dwords */ 1052 header_len_bytes = dmc_header->header_len * 4; 1053 start_mmioaddr = v3->start_mmioaddr; 1054 dmc_header_size = sizeof(*v3); 1055 } else if (dmc_header->header_ver == 1) { 1056 const struct intel_dmc_header_v1 *v1 = 1057 (const struct intel_dmc_header_v1 *)dmc_header; 1058 1059 if (rem_size < sizeof(struct intel_dmc_header_v1)) 1060 goto error_truncated; 1061 1062 mmioaddr = v1->mmioaddr; 1063 mmiodata = v1->mmiodata; 1064 mmio_count = v1->mmio_count; 1065 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 1066 header_len_bytes = dmc_header->header_len; 1067 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 1068 dmc_header_size = sizeof(*v1); 1069 } else { 1070 drm_err(display->drm, "Unknown DMC fw header version: %u\n", 1071 dmc_header->header_ver); 1072 return 0; 1073 } 1074 1075 if (header_len_bytes != dmc_header_size) { 1076 drm_err(display->drm, "DMC firmware has wrong dmc header length " 1077 "(%u bytes)\n", header_len_bytes); 1078 return 0; 1079 } 1080 1081 /* Cache the dmc header info. */ 1082 if (mmio_count > mmio_count_max) { 1083 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 1084 return 0; 1085 } 1086 1087 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 1088 dmc_header->header_ver, dmc_id)) { 1089 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); 1090 return 0; 1091 } 1092 1093 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); 1094 for (i = 0; i < mmio_count; i++) { 1095 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 1096 dmc_info->mmiodata[i] = mmiodata[i]; 1097 } 1098 1099 for (i = 0; i < mmio_count - 1; i++) { 1100 u32 orig_mmiodata[2] = { 1101 dmc_info->mmiodata[i], 1102 dmc_info->mmiodata[i+1], 1103 }; 1104 1105 if (!fixup_dmc_evt(display, dmc_id, 1106 dmc_info->mmioaddr[i], &dmc_info->mmiodata[i], 1107 dmc_info->mmioaddr[i+1], &dmc_info->mmiodata[i+1])) 1108 continue; 1109 1110 drm_dbg_kms(display->drm, 1111 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_CTL)\n", 1112 i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), 1113 orig_mmiodata[0], dmc_info->mmiodata[i]); 1114 drm_dbg_kms(display->drm, 1115 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_HTP)\n", 1116 i+1, i915_mmio_reg_offset(dmc_info->mmioaddr[i+1]), 1117 orig_mmiodata[1], dmc_info->mmiodata[i+1]); 1118 } 1119 1120 for (i = 0; i < mmio_count; i++) { 1121 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 1122 i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i], 1123 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 1124 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 1125 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], 1126 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 1127 } 1128 dmc_info->mmio_count = mmio_count; 1129 dmc_info->start_mmioaddr = start_mmioaddr; 1130 1131 rem_size -= header_len_bytes; 1132 1133 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 1134 payload_size = dmc_header->fw_size * 4; 1135 if (rem_size < payload_size) 1136 goto error_truncated; 1137 1138 if (payload_size > dmc->max_fw_size) { 1139 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); 1140 return 0; 1141 } 1142 dmc_info->dmc_fw_size = dmc_header->fw_size; 1143 1144 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 1145 if (!dmc_info->payload) 1146 return 0; 1147 1148 payload = (u8 *)(dmc_header) + header_len_bytes; 1149 memcpy(dmc_info->payload, payload, payload_size); 1150 1151 return header_len_bytes + payload_size; 1152 1153 error_truncated: 1154 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1155 return 0; 1156 } 1157 1158 static u32 1159 parse_dmc_fw_package(struct intel_dmc *dmc, 1160 const struct intel_package_header *package_header, 1161 const struct stepping_info *si, 1162 size_t rem_size) 1163 { 1164 struct intel_display *display = dmc->display; 1165 u32 package_size = sizeof(struct intel_package_header); 1166 u32 num_entries, max_entries; 1167 const struct intel_fw_info *fw_info; 1168 1169 if (rem_size < package_size) 1170 goto error_truncated; 1171 1172 if (package_header->header_ver == 1) { 1173 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 1174 } else if (package_header->header_ver == 2) { 1175 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 1176 } else { 1177 drm_err(display->drm, "DMC firmware has unknown header version %u\n", 1178 package_header->header_ver); 1179 return 0; 1180 } 1181 1182 /* 1183 * We should always have space for max_entries, 1184 * even if not all are used 1185 */ 1186 package_size += max_entries * sizeof(struct intel_fw_info); 1187 if (rem_size < package_size) 1188 goto error_truncated; 1189 1190 if (package_header->header_len * 4 != package_size) { 1191 drm_err(display->drm, "DMC firmware has wrong package header length " 1192 "(%u bytes)\n", package_size); 1193 return 0; 1194 } 1195 1196 num_entries = package_header->num_entries; 1197 if (WARN_ON(package_header->num_entries > max_entries)) 1198 num_entries = max_entries; 1199 1200 fw_info = (const struct intel_fw_info *) 1201 ((u8 *)package_header + sizeof(*package_header)); 1202 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 1203 package_header->header_ver); 1204 1205 /* dmc_offset is in dwords */ 1206 return package_size; 1207 1208 error_truncated: 1209 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1210 return 0; 1211 } 1212 1213 /* Return number of bytes parsed or 0 on error */ 1214 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 1215 struct intel_css_header *css_header, 1216 size_t rem_size) 1217 { 1218 struct intel_display *display = dmc->display; 1219 1220 if (rem_size < sizeof(struct intel_css_header)) { 1221 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1222 return 0; 1223 } 1224 1225 if (sizeof(struct intel_css_header) != 1226 (css_header->header_len * 4)) { 1227 drm_err(display->drm, "DMC firmware has wrong CSS header length " 1228 "(%u bytes)\n", 1229 (css_header->header_len * 4)); 1230 return 0; 1231 } 1232 1233 dmc->version = css_header->version; 1234 1235 return sizeof(struct intel_css_header); 1236 } 1237 1238 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 1239 { 1240 struct intel_display *display = dmc->display; 1241 struct intel_css_header *css_header; 1242 struct intel_package_header *package_header; 1243 struct intel_dmc_header_base *dmc_header; 1244 struct stepping_info display_info = { '*', '*'}; 1245 const struct stepping_info *si = intel_get_stepping_info(display, &display_info); 1246 enum intel_dmc_id dmc_id; 1247 u32 readcount = 0; 1248 u32 r, offset; 1249 1250 if (!fw) 1251 return -EINVAL; 1252 1253 /* Extract CSS Header information */ 1254 css_header = (struct intel_css_header *)fw->data; 1255 r = parse_dmc_fw_css(dmc, css_header, fw->size); 1256 if (!r) 1257 return -EINVAL; 1258 1259 readcount += r; 1260 1261 /* Extract Package Header information */ 1262 package_header = (struct intel_package_header *)&fw->data[readcount]; 1263 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 1264 if (!r) 1265 return -EINVAL; 1266 1267 readcount += r; 1268 1269 for_each_dmc_id(dmc_id) { 1270 if (!dmc->dmc_info[dmc_id].present) 1271 continue; 1272 1273 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 1274 if (offset > fw->size) { 1275 drm_err(display->drm, "Reading beyond the fw_size\n"); 1276 continue; 1277 } 1278 1279 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 1280 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 1281 } 1282 1283 if (!intel_dmc_has_payload(display)) { 1284 drm_err(display->drm, "DMC firmware main program not found\n"); 1285 return -ENOENT; 1286 } 1287 1288 return 0; 1289 } 1290 1291 static void intel_dmc_runtime_pm_get(struct intel_display *display) 1292 { 1293 drm_WARN_ON(display->drm, display->dmc.wakeref); 1294 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); 1295 } 1296 1297 static void intel_dmc_runtime_pm_put(struct intel_display *display) 1298 { 1299 intel_wakeref_t wakeref __maybe_unused = 1300 fetch_and_zero(&display->dmc.wakeref); 1301 1302 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 1303 } 1304 1305 static const char *dmc_fallback_path(struct intel_display *display) 1306 { 1307 if (display->platform.alderlake_p) 1308 return ADLP_DMC_FALLBACK_PATH; 1309 1310 return NULL; 1311 } 1312 1313 static void dmc_load_work_fn(struct work_struct *work) 1314 { 1315 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1316 struct intel_display *display = dmc->display; 1317 const struct firmware *fw = NULL; 1318 const char *fallback_path; 1319 int err; 1320 1321 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); 1322 1323 if (err == -ENOENT && !dmc_firmware_param(display)) { 1324 fallback_path = dmc_fallback_path(display); 1325 if (fallback_path) { 1326 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", 1327 dmc->fw_path, fallback_path); 1328 err = request_firmware(&fw, fallback_path, display->drm->dev); 1329 if (err == 0) 1330 dmc->fw_path = fallback_path; 1331 } 1332 } 1333 1334 if (err) { 1335 drm_notice(display->drm, 1336 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1337 dmc->fw_path, ERR_PTR(err)); 1338 drm_notice(display->drm, "DMC firmware homepage: %s", 1339 INTEL_DMC_FIRMWARE_URL); 1340 return; 1341 } 1342 1343 err = parse_dmc_fw(dmc, fw); 1344 if (err) { 1345 drm_notice(display->drm, 1346 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1347 dmc->fw_path, ERR_PTR(err)); 1348 goto out; 1349 } 1350 1351 intel_dmc_load_program(display); 1352 intel_dmc_runtime_pm_put(display); 1353 1354 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1355 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1356 DMC_VERSION_MINOR(dmc->version)); 1357 1358 out: 1359 release_firmware(fw); 1360 } 1361 1362 /** 1363 * intel_dmc_init() - initialize the firmware loading. 1364 * @display: display instance 1365 * 1366 * This function is called at the time of loading the display driver to read 1367 * firmware from a .bin file and copied into a internal memory. 1368 */ 1369 void intel_dmc_init(struct intel_display *display) 1370 { 1371 struct intel_dmc *dmc; 1372 1373 if (!HAS_DMC(display)) 1374 return; 1375 1376 /* 1377 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1378 * runtime-suspend. 1379 * 1380 * On error, we return with the rpm wakeref held to prevent runtime 1381 * suspend as runtime suspend *requires* a working DMC for whatever 1382 * reason. 1383 */ 1384 intel_dmc_runtime_pm_get(display); 1385 1386 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); 1387 if (!dmc) 1388 return; 1389 1390 dmc->display = display; 1391 1392 INIT_WORK(&dmc->work, dmc_load_work_fn); 1393 1394 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); 1395 1396 if (dmc_firmware_param_disabled(display)) { 1397 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); 1398 goto out; 1399 } 1400 1401 if (dmc_firmware_param(display)) 1402 dmc->fw_path = dmc_firmware_param(display); 1403 1404 if (!dmc->fw_path) { 1405 drm_dbg_kms(display->drm, 1406 "No known DMC firmware for platform, disabling runtime PM\n"); 1407 goto out; 1408 } 1409 1410 display->dmc.dmc = dmc; 1411 1412 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); 1413 queue_work(display->wq.unordered, &dmc->work); 1414 1415 return; 1416 1417 out: 1418 kfree(dmc); 1419 } 1420 1421 /** 1422 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1423 * @display: display instance 1424 * 1425 * Prepare the DMC firmware before entering system suspend. This includes 1426 * flushing pending work items and releasing any resources acquired during 1427 * init. 1428 */ 1429 void intel_dmc_suspend(struct intel_display *display) 1430 { 1431 struct intel_dmc *dmc = display_to_dmc(display); 1432 1433 if (!HAS_DMC(display)) 1434 return; 1435 1436 if (dmc) 1437 flush_work(&dmc->work); 1438 1439 /* Drop the reference held in case DMC isn't loaded. */ 1440 if (!intel_dmc_has_payload(display)) 1441 intel_dmc_runtime_pm_put(display); 1442 } 1443 1444 void intel_dmc_wait_fw_load(struct intel_display *display) 1445 { 1446 struct intel_dmc *dmc = display_to_dmc(display); 1447 1448 if (!HAS_DMC(display)) 1449 return; 1450 1451 if (dmc) 1452 flush_work(&dmc->work); 1453 } 1454 1455 /** 1456 * intel_dmc_resume() - init DMC firmware during system resume 1457 * @display: display instance 1458 * 1459 * Reinitialize the DMC firmware during system resume, reacquiring any 1460 * resources released in intel_dmc_suspend(). 1461 */ 1462 void intel_dmc_resume(struct intel_display *display) 1463 { 1464 if (!HAS_DMC(display)) 1465 return; 1466 1467 /* 1468 * Reacquire the reference to keep RPM disabled in case DMC isn't 1469 * loaded. 1470 */ 1471 if (!intel_dmc_has_payload(display)) 1472 intel_dmc_runtime_pm_get(display); 1473 } 1474 1475 /** 1476 * intel_dmc_fini() - unload the DMC firmware. 1477 * @display: display instance 1478 * 1479 * Firmmware unloading includes freeing the internal memory and reset the 1480 * firmware loading status. 1481 */ 1482 void intel_dmc_fini(struct intel_display *display) 1483 { 1484 struct intel_dmc *dmc = display_to_dmc(display); 1485 enum intel_dmc_id dmc_id; 1486 1487 if (!HAS_DMC(display)) 1488 return; 1489 1490 intel_dmc_suspend(display); 1491 drm_WARN_ON(display->drm, display->dmc.wakeref); 1492 1493 if (dmc) { 1494 for_each_dmc_id(dmc_id) 1495 kfree(dmc->dmc_info[dmc_id].payload); 1496 1497 kfree(dmc); 1498 display->dmc.dmc = NULL; 1499 } 1500 } 1501 1502 struct intel_dmc_snapshot { 1503 bool initialized; 1504 bool loaded; 1505 u32 version; 1506 }; 1507 1508 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) 1509 { 1510 struct intel_dmc *dmc = display_to_dmc(display); 1511 struct intel_dmc_snapshot *snapshot; 1512 1513 if (!HAS_DMC(display)) 1514 return NULL; 1515 1516 snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); 1517 if (!snapshot) 1518 return NULL; 1519 1520 snapshot->initialized = dmc; 1521 snapshot->loaded = intel_dmc_has_payload(display); 1522 if (dmc) 1523 snapshot->version = dmc->version; 1524 1525 return snapshot; 1526 } 1527 1528 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p) 1529 { 1530 if (!snapshot) 1531 return; 1532 1533 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized)); 1534 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded)); 1535 if (snapshot->initialized) 1536 drm_printf(p, "DMC fw version: %d.%d\n", 1537 DMC_VERSION_MAJOR(snapshot->version), 1538 DMC_VERSION_MINOR(snapshot->version)); 1539 } 1540 1541 void intel_dmc_update_dc6_allowed_count(struct intel_display *display, 1542 bool start_tracking) 1543 { 1544 struct intel_dmc *dmc = display_to_dmc(display); 1545 u32 dc5_cur_count; 1546 1547 if (DISPLAY_VER(dmc->display) < 14) 1548 return; 1549 1550 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT); 1551 1552 if (!start_tracking) 1553 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start; 1554 1555 dmc->dc6_allowed.dc5_start = dc5_cur_count; 1556 } 1557 1558 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count) 1559 { 1560 struct i915_power_domains *power_domains = &display->power.domains; 1561 struct intel_dmc *dmc = display_to_dmc(display); 1562 bool dc6_enabled; 1563 1564 if (DISPLAY_VER(display) < 14) 1565 return false; 1566 1567 mutex_lock(&power_domains->lock); 1568 dc6_enabled = intel_de_read(display, DC_STATE_EN) & 1569 DC_STATE_EN_UPTO_DC6; 1570 if (dc6_enabled) 1571 intel_dmc_update_dc6_allowed_count(display, false); 1572 1573 *count = dmc->dc6_allowed.count; 1574 mutex_unlock(&power_domains->lock); 1575 1576 return true; 1577 } 1578 1579 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1580 { 1581 struct intel_display *display = m->private; 1582 struct intel_dmc *dmc = display_to_dmc(display); 1583 struct ref_tracker *wakeref; 1584 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1585 u32 dc6_allowed_count; 1586 1587 if (!HAS_DMC(display)) 1588 return -ENODEV; 1589 1590 wakeref = intel_display_rpm_get(display); 1591 1592 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1593 seq_printf(m, "fw loaded: %s\n", 1594 str_yes_no(intel_dmc_has_payload(display))); 1595 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1596 seq_printf(m, "Pipe A fw needed: %s\n", 1597 str_yes_no(DISPLAY_VER(display) >= 12)); 1598 seq_printf(m, "Pipe A fw loaded: %s\n", 1599 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); 1600 seq_printf(m, "Pipe B fw needed: %s\n", 1601 str_yes_no(display->platform.alderlake_p || 1602 DISPLAY_VER(display) >= 14)); 1603 seq_printf(m, "Pipe B fw loaded: %s\n", 1604 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); 1605 1606 if (!intel_dmc_has_payload(display)) 1607 goto out; 1608 1609 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1610 DMC_VERSION_MINOR(dmc->version)); 1611 1612 if (DISPLAY_VER(display) >= 12) { 1613 i915_reg_t dc3co_reg; 1614 1615 if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { 1616 dc3co_reg = DG1_DMC_DEBUG3; 1617 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1618 } else { 1619 dc3co_reg = TGL_DMC_DEBUG3; 1620 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1621 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1622 } 1623 1624 seq_printf(m, "DC3CO count: %d\n", 1625 intel_de_read(display, dc3co_reg)); 1626 } else { 1627 dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT : 1628 SKL_DMC_DC3_DC5_COUNT; 1629 if (!display->platform.geminilake && !display->platform.broxton) 1630 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1631 } 1632 1633 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); 1634 1635 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) 1636 seq_printf(m, "DC5 -> DC6 allowed count: %d\n", 1637 dc6_allowed_count); 1638 else if (i915_mmio_reg_valid(dc6_reg)) 1639 seq_printf(m, "DC5 -> DC6 count: %d\n", 1640 intel_de_read(display, dc6_reg)); 1641 1642 seq_printf(m, "program base: 0x%08x\n", 1643 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1644 1645 out: 1646 seq_printf(m, "ssp base: 0x%08x\n", 1647 intel_de_read(display, DMC_SSP_BASE)); 1648 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); 1649 1650 intel_display_rpm_put(display, wakeref); 1651 1652 return 0; 1653 } 1654 1655 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1656 1657 void intel_dmc_debugfs_register(struct intel_display *display) 1658 { 1659 debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root, 1660 display, &intel_dmc_debugfs_status_fops); 1661 } 1662 1663 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe) 1664 { 1665 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 1666 u32 tmp = 0, int_vector; 1667 1668 if (DISPLAY_VER(display) >= 20) { 1669 tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe)); 1670 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp); 1671 1672 if (tmp & PIPEDMC_FLIPQ_PROG_DONE) { 1673 spin_lock(&display->drm->event_lock); 1674 1675 if (crtc->flipq_event) { 1676 /* 1677 * Update vblank counter/timestamp in case it 1678 * hasn't been done yet for this frame. 1679 */ 1680 drm_crtc_accurate_vblank_count(&crtc->base); 1681 1682 drm_crtc_send_vblank_event(&crtc->base, crtc->flipq_event); 1683 crtc->flipq_event = NULL; 1684 } 1685 1686 spin_unlock(&display->drm->event_lock); 1687 } 1688 1689 if (tmp & PIPEDMC_ATS_FAULT) 1690 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n", 1691 crtc->base.base.id, crtc->base.name); 1692 if (tmp & PIPEDMC_GTT_FAULT) 1693 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n", 1694 crtc->base.base.id, crtc->base.name); 1695 if (tmp & PIPEDMC_ERROR) 1696 drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC error\n", 1697 crtc->base.base.id, crtc->base.name); 1698 } 1699 1700 int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK; 1701 if (tmp == 0 && int_vector != 0) 1702 drm_err(display->drm, "[CRTC:%d:%s]] PIPEDMC interrupt vector 0x%x\n", 1703 crtc->base.base.id, crtc->base.name, tmp); 1704 } 1705 1706 void intel_pipedmc_enable_event(struct intel_crtc *crtc, 1707 enum pipedmc_event_id event) 1708 { 1709 struct intel_display *display = to_intel_display(crtc); 1710 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1711 1712 dmc_configure_event(display, dmc_id, event, true); 1713 } 1714 1715 void intel_pipedmc_disable_event(struct intel_crtc *crtc, 1716 enum pipedmc_event_id event) 1717 { 1718 struct intel_display *display = to_intel_display(crtc); 1719 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1720 1721 dmc_configure_event(display, dmc_id, event, false); 1722 } 1723 1724 u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc) 1725 { 1726 struct intel_display *display = to_intel_display(crtc); 1727 struct intel_dmc *dmc = display_to_dmc(display); 1728 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1729 1730 return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0; 1731 } 1732