1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 28 #include "i915_drv.h" 29 #include "i915_reg.h" 30 #include "intel_de.h" 31 #include "intel_dmc.h" 32 #include "intel_dmc_regs.h" 33 34 /** 35 * DOC: DMC Firmware Support 36 * 37 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 38 * engine to save and restore the state of display engine when it enter into 39 * low-power state and comes back to normal. 40 */ 41 42 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 43 44 enum intel_dmc_id { 45 DMC_FW_MAIN = 0, 46 DMC_FW_PIPEA, 47 DMC_FW_PIPEB, 48 DMC_FW_PIPEC, 49 DMC_FW_PIPED, 50 DMC_FW_MAX 51 }; 52 53 struct intel_dmc { 54 struct drm_i915_private *i915; 55 struct work_struct work; 56 const char *fw_path; 57 u32 max_fw_size; /* bytes */ 58 u32 version; 59 struct dmc_fw_info { 60 u32 mmio_count; 61 i915_reg_t mmioaddr[20]; 62 u32 mmiodata[20]; 63 u32 dmc_offset; 64 u32 start_mmioaddr; 65 u32 dmc_fw_size; /*dwords */ 66 u32 *payload; 67 bool present; 68 } dmc_info[DMC_FW_MAX]; 69 }; 70 71 /* Note: This may be NULL. */ 72 static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915) 73 { 74 return i915->display.dmc.dmc; 75 } 76 77 static const char *dmc_firmware_param(struct drm_i915_private *i915) 78 { 79 const char *p = i915->display.params.dmc_firmware_path; 80 81 return p && *p ? p : NULL; 82 } 83 84 static bool dmc_firmware_param_disabled(struct drm_i915_private *i915) 85 { 86 const char *p = dmc_firmware_param(i915); 87 88 /* Magic path to indicate disabled */ 89 return p && !strcmp(p, "/dev/null"); 90 } 91 92 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 93 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 94 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 95 96 #define DMC_PATH(platform) \ 97 "i915/" __stringify(platform) "_dmc.bin" 98 99 /* 100 * New DMC additions should not use this. This is used solely to remain 101 * compatible with systems that have not yet updated DMC blobs to use 102 * unversioned file names. 103 */ 104 #define DMC_LEGACY_PATH(platform, major, minor) \ 105 "i915/" \ 106 __stringify(platform) "_dmc_ver" \ 107 __stringify(major) "_" \ 108 __stringify(minor) ".bin" 109 110 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 111 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 112 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 113 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 114 115 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 116 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 117 118 #define MTL_DMC_PATH DMC_PATH(mtl) 119 MODULE_FIRMWARE(MTL_DMC_PATH); 120 121 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 122 MODULE_FIRMWARE(DG2_DMC_PATH); 123 124 #define ADLP_DMC_PATH DMC_PATH(adlp) 125 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 126 MODULE_FIRMWARE(ADLP_DMC_PATH); 127 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 128 129 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 130 MODULE_FIRMWARE(ADLS_DMC_PATH); 131 132 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 133 MODULE_FIRMWARE(DG1_DMC_PATH); 134 135 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 136 MODULE_FIRMWARE(RKL_DMC_PATH); 137 138 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 139 MODULE_FIRMWARE(TGL_DMC_PATH); 140 141 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 142 #define ICL_DMC_MAX_FW_SIZE 0x6000 143 MODULE_FIRMWARE(ICL_DMC_PATH); 144 145 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 146 #define GLK_DMC_MAX_FW_SIZE 0x4000 147 MODULE_FIRMWARE(GLK_DMC_PATH); 148 149 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 150 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 151 MODULE_FIRMWARE(KBL_DMC_PATH); 152 153 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 154 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 155 MODULE_FIRMWARE(SKL_DMC_PATH); 156 157 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 158 #define BXT_DMC_MAX_FW_SIZE 0x3000 159 MODULE_FIRMWARE(BXT_DMC_PATH); 160 161 static const char *dmc_firmware_default(struct drm_i915_private *i915, u32 *size) 162 { 163 const char *fw_path = NULL; 164 u32 max_fw_size = 0; 165 166 if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) { 167 fw_path = XE2LPD_DMC_PATH; 168 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 169 } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) { 170 fw_path = MTL_DMC_PATH; 171 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 172 } else if (IS_DG2(i915)) { 173 fw_path = DG2_DMC_PATH; 174 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 175 } else if (IS_ALDERLAKE_P(i915)) { 176 fw_path = ADLP_DMC_PATH; 177 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 178 } else if (IS_ALDERLAKE_S(i915)) { 179 fw_path = ADLS_DMC_PATH; 180 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 181 } else if (IS_DG1(i915)) { 182 fw_path = DG1_DMC_PATH; 183 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 184 } else if (IS_ROCKETLAKE(i915)) { 185 fw_path = RKL_DMC_PATH; 186 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 187 } else if (IS_TIGERLAKE(i915)) { 188 fw_path = TGL_DMC_PATH; 189 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 190 } else if (DISPLAY_VER(i915) == 11) { 191 fw_path = ICL_DMC_PATH; 192 max_fw_size = ICL_DMC_MAX_FW_SIZE; 193 } else if (IS_GEMINILAKE(i915)) { 194 fw_path = GLK_DMC_PATH; 195 max_fw_size = GLK_DMC_MAX_FW_SIZE; 196 } else if (IS_KABYLAKE(i915) || 197 IS_COFFEELAKE(i915) || 198 IS_COMETLAKE(i915)) { 199 fw_path = KBL_DMC_PATH; 200 max_fw_size = KBL_DMC_MAX_FW_SIZE; 201 } else if (IS_SKYLAKE(i915)) { 202 fw_path = SKL_DMC_PATH; 203 max_fw_size = SKL_DMC_MAX_FW_SIZE; 204 } else if (IS_BROXTON(i915)) { 205 fw_path = BXT_DMC_PATH; 206 max_fw_size = BXT_DMC_MAX_FW_SIZE; 207 } 208 209 *size = max_fw_size; 210 211 return fw_path; 212 } 213 214 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 215 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 216 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 217 #define DMC_V1_MAX_MMIO_COUNT 8 218 #define DMC_V3_MAX_MMIO_COUNT 20 219 #define DMC_V1_MMIO_START_RANGE 0x80000 220 221 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 222 223 struct intel_css_header { 224 /* 0x09 for DMC */ 225 u32 module_type; 226 227 /* Includes the DMC specific header in dwords */ 228 u32 header_len; 229 230 /* always value would be 0x10000 */ 231 u32 header_ver; 232 233 /* Not used */ 234 u32 module_id; 235 236 /* Not used */ 237 u32 module_vendor; 238 239 /* in YYYYMMDD format */ 240 u32 date; 241 242 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 243 u32 size; 244 245 /* Not used */ 246 u32 key_size; 247 248 /* Not used */ 249 u32 modulus_size; 250 251 /* Not used */ 252 u32 exponent_size; 253 254 /* Not used */ 255 u32 reserved1[12]; 256 257 /* Major Minor */ 258 u32 version; 259 260 /* Not used */ 261 u32 reserved2[8]; 262 263 /* Not used */ 264 u32 kernel_header_info; 265 } __packed; 266 267 struct intel_fw_info { 268 u8 reserved1; 269 270 /* reserved on package_header version 1, must be 0 on version 2 */ 271 u8 dmc_id; 272 273 /* Stepping (A, B, C, ..., *). * is a wildcard */ 274 char stepping; 275 276 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 277 char substepping; 278 279 u32 offset; 280 u32 reserved2; 281 } __packed; 282 283 struct intel_package_header { 284 /* DMC container header length in dwords */ 285 u8 header_len; 286 287 /* 0x01, 0x02 */ 288 u8 header_ver; 289 290 u8 reserved[10]; 291 292 /* Number of valid entries in the FWInfo array below */ 293 u32 num_entries; 294 } __packed; 295 296 struct intel_dmc_header_base { 297 /* always value would be 0x40403E3E */ 298 u32 signature; 299 300 /* DMC binary header length */ 301 u8 header_len; 302 303 /* 0x01 */ 304 u8 header_ver; 305 306 /* Reserved */ 307 u16 dmcc_ver; 308 309 /* Major, Minor */ 310 u32 project; 311 312 /* Firmware program size (excluding header) in dwords */ 313 u32 fw_size; 314 315 /* Major Minor version */ 316 u32 fw_version; 317 } __packed; 318 319 struct intel_dmc_header_v1 { 320 struct intel_dmc_header_base base; 321 322 /* Number of valid MMIO cycles present. */ 323 u32 mmio_count; 324 325 /* MMIO address */ 326 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 327 328 /* MMIO data */ 329 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 330 331 /* FW filename */ 332 char dfile[32]; 333 334 u32 reserved1[2]; 335 } __packed; 336 337 struct intel_dmc_header_v3 { 338 struct intel_dmc_header_base base; 339 340 /* DMC RAM start MMIO address */ 341 u32 start_mmioaddr; 342 343 u32 reserved[9]; 344 345 /* FW filename */ 346 char dfile[32]; 347 348 /* Number of valid MMIO cycles present. */ 349 u32 mmio_count; 350 351 /* MMIO address */ 352 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 353 354 /* MMIO data */ 355 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 356 } __packed; 357 358 struct stepping_info { 359 char stepping; 360 char substepping; 361 }; 362 363 #define for_each_dmc_id(__dmc_id) \ 364 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 365 366 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 367 { 368 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 369 } 370 371 static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id dmc_id) 372 { 373 struct intel_dmc *dmc = i915_to_dmc(i915); 374 375 return dmc && dmc->dmc_info[dmc_id].payload; 376 } 377 378 bool intel_dmc_has_payload(struct drm_i915_private *i915) 379 { 380 return has_dmc_id_fw(i915, DMC_FW_MAIN); 381 } 382 383 static const struct stepping_info * 384 intel_get_stepping_info(struct drm_i915_private *i915, 385 struct stepping_info *si) 386 { 387 const char *step_name = intel_display_step_name(i915); 388 389 si->stepping = step_name[0]; 390 si->substepping = step_name[1]; 391 return si; 392 } 393 394 static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915) 395 { 396 /* The below bit doesn't need to be cleared ever afterwards */ 397 intel_de_rmw(i915, DC_STATE_DEBUG, 0, 398 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 399 intel_de_posting_read(i915, DC_STATE_DEBUG); 400 } 401 402 static void disable_event_handler(struct drm_i915_private *i915, 403 i915_reg_t ctl_reg, i915_reg_t htp_reg) 404 { 405 intel_de_write(i915, ctl_reg, 406 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 407 DMC_EVT_CTL_TYPE_EDGE_0_1) | 408 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 409 DMC_EVT_CTL_EVENT_ID_FALSE)); 410 intel_de_write(i915, htp_reg, 0); 411 } 412 413 static void disable_all_event_handlers(struct drm_i915_private *i915) 414 { 415 enum intel_dmc_id dmc_id; 416 417 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 418 if (DISPLAY_VER(i915) < 12) 419 return; 420 421 for_each_dmc_id(dmc_id) { 422 int handler; 423 424 if (!has_dmc_id_fw(i915, dmc_id)) 425 continue; 426 427 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 428 disable_event_handler(i915, 429 DMC_EVT_CTL(i915, dmc_id, handler), 430 DMC_EVT_HTP(i915, dmc_id, handler)); 431 } 432 } 433 434 static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 435 { 436 enum pipe pipe; 437 438 /* 439 * Wa_16015201720:adl-p,dg2 440 * The WA requires clock gating to be disabled all the time 441 * for pipe A and B. 442 * For pipe C and D clock gating needs to be disabled only 443 * during initializing the firmware. 444 */ 445 if (enable) 446 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 447 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 448 0, PIPEDMC_GATING_DIS); 449 else 450 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 451 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), 452 PIPEDMC_GATING_DIS, 0); 453 } 454 455 static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915) 456 { 457 /* 458 * Wa_16015201720 459 * The WA requires clock gating to be disabled all the time 460 * for pipe A and B. 461 */ 462 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, 463 MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); 464 } 465 466 static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 467 { 468 if (DISPLAY_VER(i915) >= 14 && enable) 469 mtl_pipedmc_clock_gating_wa(i915); 470 else if (DISPLAY_VER(i915) == 13) 471 adlp_pipedmc_clock_gating_wa(i915, enable); 472 } 473 474 void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe) 475 { 476 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 477 478 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) 479 return; 480 481 if (DISPLAY_VER(i915) >= 14) 482 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 483 else 484 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 485 } 486 487 void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe) 488 { 489 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 490 491 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) 492 return; 493 494 if (DISPLAY_VER(i915) >= 14) 495 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 496 else 497 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 498 } 499 500 static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915, 501 enum intel_dmc_id dmc_id, i915_reg_t reg) 502 { 503 u32 offset = i915_mmio_reg_offset(reg); 504 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0)); 505 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 506 507 return offset >= start && offset < end; 508 } 509 510 static bool is_dmc_evt_htp_reg(struct drm_i915_private *i915, 511 enum intel_dmc_id dmc_id, i915_reg_t reg) 512 { 513 u32 offset = i915_mmio_reg_offset(reg); 514 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, 0)); 515 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 516 517 return offset >= start && offset < end; 518 } 519 520 static bool disable_dmc_evt(struct drm_i915_private *i915, 521 enum intel_dmc_id dmc_id, 522 i915_reg_t reg, u32 data) 523 { 524 if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg)) 525 return false; 526 527 /* keep all pipe DMC events disabled by default */ 528 if (dmc_id != DMC_FW_MAIN) 529 return true; 530 531 /* also disable the flip queue event on the main DMC on TGL */ 532 if (IS_TIGERLAKE(i915) && 533 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC) 534 return true; 535 536 /* also disable the HRR event on the main DMC on TGL/ADLS */ 537 if ((IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915)) && 538 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A) 539 return true; 540 541 return false; 542 } 543 544 static u32 dmc_mmiodata(struct drm_i915_private *i915, 545 struct intel_dmc *dmc, 546 enum intel_dmc_id dmc_id, int i) 547 { 548 if (disable_dmc_evt(i915, dmc_id, 549 dmc->dmc_info[dmc_id].mmioaddr[i], 550 dmc->dmc_info[dmc_id].mmiodata[i])) 551 return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 552 DMC_EVT_CTL_TYPE_EDGE_0_1) | 553 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 554 DMC_EVT_CTL_EVENT_ID_FALSE); 555 else 556 return dmc->dmc_info[dmc_id].mmiodata[i]; 557 } 558 559 /** 560 * intel_dmc_load_program() - write the firmware from memory to register. 561 * @i915: i915 drm device. 562 * 563 * DMC firmware is read from a .bin file and kept in internal memory one time. 564 * Everytime display comes back from low power state this function is called to 565 * copy the firmware from internal memory to registers. 566 */ 567 void intel_dmc_load_program(struct drm_i915_private *i915) 568 { 569 struct i915_power_domains *power_domains = &i915->display.power.domains; 570 struct intel_dmc *dmc = i915_to_dmc(i915); 571 enum intel_dmc_id dmc_id; 572 u32 i; 573 574 if (!intel_dmc_has_payload(i915)) 575 return; 576 577 pipedmc_clock_gating_wa(i915, true); 578 579 disable_all_event_handlers(i915); 580 581 assert_rpm_wakelock_held(&i915->runtime_pm); 582 583 preempt_disable(); 584 585 for_each_dmc_id(dmc_id) { 586 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 587 intel_de_write_fw(i915, 588 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 589 dmc->dmc_info[dmc_id].payload[i]); 590 } 591 } 592 593 preempt_enable(); 594 595 for_each_dmc_id(dmc_id) { 596 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 597 intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i], 598 dmc_mmiodata(i915, dmc, dmc_id, i)); 599 } 600 } 601 602 power_domains->dc_state = 0; 603 604 gen9_set_dc_state_debugmask(i915); 605 606 pipedmc_clock_gating_wa(i915, false); 607 } 608 609 /** 610 * intel_dmc_disable_program() - disable the firmware 611 * @i915: i915 drm device 612 * 613 * Disable all event handlers in the firmware, making sure the firmware is 614 * inactive after the display is uninitialized. 615 */ 616 void intel_dmc_disable_program(struct drm_i915_private *i915) 617 { 618 if (!intel_dmc_has_payload(i915)) 619 return; 620 621 pipedmc_clock_gating_wa(i915, true); 622 disable_all_event_handlers(i915); 623 pipedmc_clock_gating_wa(i915, false); 624 625 intel_dmc_wl_disable(&i915->display); 626 } 627 628 void assert_dmc_loaded(struct drm_i915_private *i915) 629 { 630 struct intel_dmc *dmc = i915_to_dmc(i915); 631 632 drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n"); 633 drm_WARN_ONCE(&i915->drm, dmc && 634 !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 635 "DMC program storage start is NULL\n"); 636 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), 637 "DMC SSP Base Not fine\n"); 638 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), 639 "DMC HTP Not fine\n"); 640 } 641 642 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 643 const struct stepping_info *si) 644 { 645 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 646 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 647 /* 648 * If we don't find a more specific one from above two checks, we 649 * then check for the generic one to be sure to work even with 650 * "broken firmware" 651 */ 652 (si->stepping == '*' && si->substepping == fw_info->substepping) || 653 (fw_info->stepping == '*' && fw_info->substepping == '*')) 654 return true; 655 656 return false; 657 } 658 659 /* 660 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 661 * already sanitized. 662 */ 663 static void dmc_set_fw_offset(struct intel_dmc *dmc, 664 const struct intel_fw_info *fw_info, 665 unsigned int num_entries, 666 const struct stepping_info *si, 667 u8 package_ver) 668 { 669 struct drm_i915_private *i915 = dmc->i915; 670 enum intel_dmc_id dmc_id; 671 unsigned int i; 672 673 for (i = 0; i < num_entries; i++) { 674 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 675 676 if (!is_valid_dmc_id(dmc_id)) { 677 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", dmc_id); 678 continue; 679 } 680 681 /* More specific versions come first, so we don't even have to 682 * check for the stepping since we already found a previous FW 683 * for this id. 684 */ 685 if (dmc->dmc_info[dmc_id].present) 686 continue; 687 688 if (fw_info_matches_stepping(&fw_info[i], si)) { 689 dmc->dmc_info[dmc_id].present = true; 690 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 691 } 692 } 693 } 694 695 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 696 const u32 *mmioaddr, u32 mmio_count, 697 int header_ver, enum intel_dmc_id dmc_id) 698 { 699 struct drm_i915_private *i915 = dmc->i915; 700 u32 start_range, end_range; 701 int i; 702 703 if (header_ver == 1) { 704 start_range = DMC_MMIO_START_RANGE; 705 end_range = DMC_MMIO_END_RANGE; 706 } else if (dmc_id == DMC_FW_MAIN) { 707 start_range = TGL_MAIN_MMIO_START; 708 end_range = TGL_MAIN_MMIO_END; 709 } else if (DISPLAY_VER(i915) >= 13) { 710 start_range = ADLP_PIPE_MMIO_START; 711 end_range = ADLP_PIPE_MMIO_END; 712 } else if (DISPLAY_VER(i915) >= 12) { 713 start_range = TGL_PIPE_MMIO_START(dmc_id); 714 end_range = TGL_PIPE_MMIO_END(dmc_id); 715 } else { 716 drm_warn(&i915->drm, "Unknown mmio range for sanity check"); 717 return false; 718 } 719 720 for (i = 0; i < mmio_count; i++) { 721 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 722 return false; 723 } 724 725 return true; 726 } 727 728 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 729 const struct intel_dmc_header_base *dmc_header, 730 size_t rem_size, enum intel_dmc_id dmc_id) 731 { 732 struct drm_i915_private *i915 = dmc->i915; 733 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 734 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 735 const u32 *mmioaddr, *mmiodata; 736 u32 mmio_count, mmio_count_max, start_mmioaddr; 737 u8 *payload; 738 739 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 740 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 741 742 /* 743 * Check if we can access common fields, we will checkc again below 744 * after we have read the version 745 */ 746 if (rem_size < sizeof(struct intel_dmc_header_base)) 747 goto error_truncated; 748 749 /* Cope with small differences between v1 and v3 */ 750 if (dmc_header->header_ver == 3) { 751 const struct intel_dmc_header_v3 *v3 = 752 (const struct intel_dmc_header_v3 *)dmc_header; 753 754 if (rem_size < sizeof(struct intel_dmc_header_v3)) 755 goto error_truncated; 756 757 mmioaddr = v3->mmioaddr; 758 mmiodata = v3->mmiodata; 759 mmio_count = v3->mmio_count; 760 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 761 /* header_len is in dwords */ 762 header_len_bytes = dmc_header->header_len * 4; 763 start_mmioaddr = v3->start_mmioaddr; 764 dmc_header_size = sizeof(*v3); 765 } else if (dmc_header->header_ver == 1) { 766 const struct intel_dmc_header_v1 *v1 = 767 (const struct intel_dmc_header_v1 *)dmc_header; 768 769 if (rem_size < sizeof(struct intel_dmc_header_v1)) 770 goto error_truncated; 771 772 mmioaddr = v1->mmioaddr; 773 mmiodata = v1->mmiodata; 774 mmio_count = v1->mmio_count; 775 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 776 header_len_bytes = dmc_header->header_len; 777 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 778 dmc_header_size = sizeof(*v1); 779 } else { 780 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 781 dmc_header->header_ver); 782 return 0; 783 } 784 785 if (header_len_bytes != dmc_header_size) { 786 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 787 "(%u bytes)\n", header_len_bytes); 788 return 0; 789 } 790 791 /* Cache the dmc header info. */ 792 if (mmio_count > mmio_count_max) { 793 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 794 return 0; 795 } 796 797 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 798 dmc_header->header_ver, dmc_id)) { 799 drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); 800 return 0; 801 } 802 803 drm_dbg_kms(&i915->drm, "DMC %d:\n", dmc_id); 804 for (i = 0; i < mmio_count; i++) { 805 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 806 dmc_info->mmiodata[i] = mmiodata[i]; 807 808 drm_dbg_kms(&i915->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 809 i, mmioaddr[i], mmiodata[i], 810 is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 811 is_dmc_evt_htp_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 812 disable_dmc_evt(i915, dmc_id, dmc_info->mmioaddr[i], 813 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 814 } 815 dmc_info->mmio_count = mmio_count; 816 dmc_info->start_mmioaddr = start_mmioaddr; 817 818 rem_size -= header_len_bytes; 819 820 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 821 payload_size = dmc_header->fw_size * 4; 822 if (rem_size < payload_size) 823 goto error_truncated; 824 825 if (payload_size > dmc->max_fw_size) { 826 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 827 return 0; 828 } 829 dmc_info->dmc_fw_size = dmc_header->fw_size; 830 831 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 832 if (!dmc_info->payload) 833 return 0; 834 835 payload = (u8 *)(dmc_header) + header_len_bytes; 836 memcpy(dmc_info->payload, payload, payload_size); 837 838 return header_len_bytes + payload_size; 839 840 error_truncated: 841 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 842 return 0; 843 } 844 845 static u32 846 parse_dmc_fw_package(struct intel_dmc *dmc, 847 const struct intel_package_header *package_header, 848 const struct stepping_info *si, 849 size_t rem_size) 850 { 851 struct drm_i915_private *i915 = dmc->i915; 852 u32 package_size = sizeof(struct intel_package_header); 853 u32 num_entries, max_entries; 854 const struct intel_fw_info *fw_info; 855 856 if (rem_size < package_size) 857 goto error_truncated; 858 859 if (package_header->header_ver == 1) { 860 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 861 } else if (package_header->header_ver == 2) { 862 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 863 } else { 864 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 865 package_header->header_ver); 866 return 0; 867 } 868 869 /* 870 * We should always have space for max_entries, 871 * even if not all are used 872 */ 873 package_size += max_entries * sizeof(struct intel_fw_info); 874 if (rem_size < package_size) 875 goto error_truncated; 876 877 if (package_header->header_len * 4 != package_size) { 878 drm_err(&i915->drm, "DMC firmware has wrong package header length " 879 "(%u bytes)\n", package_size); 880 return 0; 881 } 882 883 num_entries = package_header->num_entries; 884 if (WARN_ON(package_header->num_entries > max_entries)) 885 num_entries = max_entries; 886 887 fw_info = (const struct intel_fw_info *) 888 ((u8 *)package_header + sizeof(*package_header)); 889 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 890 package_header->header_ver); 891 892 /* dmc_offset is in dwords */ 893 return package_size; 894 895 error_truncated: 896 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 897 return 0; 898 } 899 900 /* Return number of bytes parsed or 0 on error */ 901 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 902 struct intel_css_header *css_header, 903 size_t rem_size) 904 { 905 struct drm_i915_private *i915 = dmc->i915; 906 907 if (rem_size < sizeof(struct intel_css_header)) { 908 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 909 return 0; 910 } 911 912 if (sizeof(struct intel_css_header) != 913 (css_header->header_len * 4)) { 914 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 915 "(%u bytes)\n", 916 (css_header->header_len * 4)); 917 return 0; 918 } 919 920 dmc->version = css_header->version; 921 922 return sizeof(struct intel_css_header); 923 } 924 925 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 926 { 927 struct drm_i915_private *i915 = dmc->i915; 928 struct intel_css_header *css_header; 929 struct intel_package_header *package_header; 930 struct intel_dmc_header_base *dmc_header; 931 struct stepping_info display_info = { '*', '*'}; 932 const struct stepping_info *si = intel_get_stepping_info(i915, &display_info); 933 enum intel_dmc_id dmc_id; 934 u32 readcount = 0; 935 u32 r, offset; 936 937 if (!fw) 938 return -EINVAL; 939 940 /* Extract CSS Header information */ 941 css_header = (struct intel_css_header *)fw->data; 942 r = parse_dmc_fw_css(dmc, css_header, fw->size); 943 if (!r) 944 return -EINVAL; 945 946 readcount += r; 947 948 /* Extract Package Header information */ 949 package_header = (struct intel_package_header *)&fw->data[readcount]; 950 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 951 if (!r) 952 return -EINVAL; 953 954 readcount += r; 955 956 for_each_dmc_id(dmc_id) { 957 if (!dmc->dmc_info[dmc_id].present) 958 continue; 959 960 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 961 if (offset > fw->size) { 962 drm_err(&i915->drm, "Reading beyond the fw_size\n"); 963 continue; 964 } 965 966 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 967 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 968 } 969 970 if (!intel_dmc_has_payload(i915)) { 971 drm_err(&i915->drm, "DMC firmware main program not found\n"); 972 return -ENOENT; 973 } 974 975 return 0; 976 } 977 978 static void intel_dmc_runtime_pm_get(struct drm_i915_private *i915) 979 { 980 drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); 981 i915->display.dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); 982 } 983 984 static void intel_dmc_runtime_pm_put(struct drm_i915_private *i915) 985 { 986 intel_wakeref_t wakeref __maybe_unused = 987 fetch_and_zero(&i915->display.dmc.wakeref); 988 989 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 990 } 991 992 static const char *dmc_fallback_path(struct drm_i915_private *i915) 993 { 994 if (IS_ALDERLAKE_P(i915)) 995 return ADLP_DMC_FALLBACK_PATH; 996 997 return NULL; 998 } 999 1000 static void dmc_load_work_fn(struct work_struct *work) 1001 { 1002 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1003 struct drm_i915_private *i915 = dmc->i915; 1004 const struct firmware *fw = NULL; 1005 const char *fallback_path; 1006 int err; 1007 1008 err = request_firmware(&fw, dmc->fw_path, i915->drm.dev); 1009 1010 if (err == -ENOENT && !dmc_firmware_param(i915)) { 1011 fallback_path = dmc_fallback_path(i915); 1012 if (fallback_path) { 1013 drm_dbg_kms(&i915->drm, "%s not found, falling back to %s\n", 1014 dmc->fw_path, fallback_path); 1015 err = request_firmware(&fw, fallback_path, i915->drm.dev); 1016 if (err == 0) 1017 dmc->fw_path = fallback_path; 1018 } 1019 } 1020 1021 if (err) { 1022 drm_notice(&i915->drm, 1023 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1024 dmc->fw_path, ERR_PTR(err)); 1025 drm_notice(&i915->drm, "DMC firmware homepage: %s", 1026 INTEL_DMC_FIRMWARE_URL); 1027 return; 1028 } 1029 1030 err = parse_dmc_fw(dmc, fw); 1031 if (err) { 1032 drm_notice(&i915->drm, 1033 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1034 dmc->fw_path, ERR_PTR(err)); 1035 goto out; 1036 } 1037 1038 intel_dmc_load_program(i915); 1039 intel_dmc_runtime_pm_put(i915); 1040 1041 drm_info(&i915->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1042 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1043 DMC_VERSION_MINOR(dmc->version)); 1044 1045 out: 1046 release_firmware(fw); 1047 } 1048 1049 /** 1050 * intel_dmc_init() - initialize the firmware loading. 1051 * @i915: i915 drm device. 1052 * 1053 * This function is called at the time of loading the display driver to read 1054 * firmware from a .bin file and copied into a internal memory. 1055 */ 1056 void intel_dmc_init(struct drm_i915_private *i915) 1057 { 1058 struct intel_dmc *dmc; 1059 1060 if (!HAS_DMC(i915)) 1061 return; 1062 1063 /* 1064 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1065 * runtime-suspend. 1066 * 1067 * On error, we return with the rpm wakeref held to prevent runtime 1068 * suspend as runtime suspend *requires* a working DMC for whatever 1069 * reason. 1070 */ 1071 intel_dmc_runtime_pm_get(i915); 1072 1073 dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); 1074 if (!dmc) 1075 return; 1076 1077 dmc->i915 = i915; 1078 1079 INIT_WORK(&dmc->work, dmc_load_work_fn); 1080 1081 dmc->fw_path = dmc_firmware_default(i915, &dmc->max_fw_size); 1082 1083 if (dmc_firmware_param_disabled(i915)) { 1084 drm_info(&i915->drm, "Disabling DMC firmware and runtime PM\n"); 1085 goto out; 1086 } 1087 1088 if (dmc_firmware_param(i915)) 1089 dmc->fw_path = dmc_firmware_param(i915); 1090 1091 if (!dmc->fw_path) { 1092 drm_dbg_kms(&i915->drm, 1093 "No known DMC firmware for platform, disabling runtime PM\n"); 1094 goto out; 1095 } 1096 1097 i915->display.dmc.dmc = dmc; 1098 1099 drm_dbg_kms(&i915->drm, "Loading %s\n", dmc->fw_path); 1100 queue_work(i915->unordered_wq, &dmc->work); 1101 1102 return; 1103 1104 out: 1105 kfree(dmc); 1106 } 1107 1108 /** 1109 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1110 * @i915: i915 drm device 1111 * 1112 * Prepare the DMC firmware before entering system suspend. This includes 1113 * flushing pending work items and releasing any resources acquired during 1114 * init. 1115 */ 1116 void intel_dmc_suspend(struct drm_i915_private *i915) 1117 { 1118 struct intel_dmc *dmc = i915_to_dmc(i915); 1119 1120 if (!HAS_DMC(i915)) 1121 return; 1122 1123 if (dmc) 1124 flush_work(&dmc->work); 1125 1126 intel_dmc_wl_disable(&i915->display); 1127 1128 /* Drop the reference held in case DMC isn't loaded. */ 1129 if (!intel_dmc_has_payload(i915)) 1130 intel_dmc_runtime_pm_put(i915); 1131 } 1132 1133 /** 1134 * intel_dmc_resume() - init DMC firmware during system resume 1135 * @i915: i915 drm device 1136 * 1137 * Reinitialize the DMC firmware during system resume, reacquiring any 1138 * resources released in intel_dmc_suspend(). 1139 */ 1140 void intel_dmc_resume(struct drm_i915_private *i915) 1141 { 1142 if (!HAS_DMC(i915)) 1143 return; 1144 1145 /* 1146 * Reacquire the reference to keep RPM disabled in case DMC isn't 1147 * loaded. 1148 */ 1149 if (!intel_dmc_has_payload(i915)) 1150 intel_dmc_runtime_pm_get(i915); 1151 } 1152 1153 /** 1154 * intel_dmc_fini() - unload the DMC firmware. 1155 * @i915: i915 drm device. 1156 * 1157 * Firmmware unloading includes freeing the internal memory and reset the 1158 * firmware loading status. 1159 */ 1160 void intel_dmc_fini(struct drm_i915_private *i915) 1161 { 1162 struct intel_dmc *dmc = i915_to_dmc(i915); 1163 enum intel_dmc_id dmc_id; 1164 1165 if (!HAS_DMC(i915)) 1166 return; 1167 1168 intel_dmc_suspend(i915); 1169 drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); 1170 1171 if (dmc) { 1172 for_each_dmc_id(dmc_id) 1173 kfree(dmc->dmc_info[dmc_id].payload); 1174 1175 kfree(dmc); 1176 i915->display.dmc.dmc = NULL; 1177 } 1178 } 1179 1180 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, 1181 struct drm_i915_private *i915) 1182 { 1183 struct intel_dmc *dmc = i915_to_dmc(i915); 1184 1185 if (!HAS_DMC(i915)) 1186 return; 1187 1188 i915_error_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1189 i915_error_printf(m, "DMC loaded: %s\n", 1190 str_yes_no(intel_dmc_has_payload(i915))); 1191 if (dmc) 1192 i915_error_printf(m, "DMC fw version: %d.%d\n", 1193 DMC_VERSION_MAJOR(dmc->version), 1194 DMC_VERSION_MINOR(dmc->version)); 1195 } 1196 1197 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1198 { 1199 struct drm_i915_private *i915 = m->private; 1200 struct intel_dmc *dmc = i915_to_dmc(i915); 1201 intel_wakeref_t wakeref; 1202 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1203 1204 if (!HAS_DMC(i915)) 1205 return -ENODEV; 1206 1207 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 1208 1209 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1210 seq_printf(m, "fw loaded: %s\n", 1211 str_yes_no(intel_dmc_has_payload(i915))); 1212 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1213 seq_printf(m, "Pipe A fw needed: %s\n", 1214 str_yes_no(DISPLAY_VER(i915) >= 12)); 1215 seq_printf(m, "Pipe A fw loaded: %s\n", 1216 str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEA))); 1217 seq_printf(m, "Pipe B fw needed: %s\n", 1218 str_yes_no(IS_ALDERLAKE_P(i915) || 1219 DISPLAY_VER(i915) >= 14)); 1220 seq_printf(m, "Pipe B fw loaded: %s\n", 1221 str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEB))); 1222 1223 if (!intel_dmc_has_payload(i915)) 1224 goto out; 1225 1226 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1227 DMC_VERSION_MINOR(dmc->version)); 1228 1229 if (DISPLAY_VER(i915) >= 12) { 1230 i915_reg_t dc3co_reg; 1231 1232 if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) { 1233 dc3co_reg = DG1_DMC_DEBUG3; 1234 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1235 } else { 1236 dc3co_reg = TGL_DMC_DEBUG3; 1237 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1238 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1239 } 1240 1241 seq_printf(m, "DC3CO count: %d\n", 1242 intel_de_read(i915, dc3co_reg)); 1243 } else { 1244 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : 1245 SKL_DMC_DC3_DC5_COUNT; 1246 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) 1247 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1248 } 1249 1250 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); 1251 if (i915_mmio_reg_valid(dc6_reg)) 1252 seq_printf(m, "DC5 -> DC6 count: %d\n", 1253 intel_de_read(i915, dc6_reg)); 1254 1255 seq_printf(m, "program base: 0x%08x\n", 1256 intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1257 1258 out: 1259 seq_printf(m, "ssp base: 0x%08x\n", 1260 intel_de_read(i915, DMC_SSP_BASE)); 1261 seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL)); 1262 1263 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1264 1265 return 0; 1266 } 1267 1268 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1269 1270 void intel_dmc_debugfs_register(struct drm_i915_private *i915) 1271 { 1272 struct drm_minor *minor = i915->drm.primary; 1273 1274 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 1275 i915, &intel_dmc_debugfs_status_fops); 1276 } 1277