1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 #include <drm/intel/step.h> 8 9 #include "intel_de.h" 10 #include "intel_display_core.h" 11 #include "intel_display_regs.h" 12 #include "intel_display_wa.h" 13 14 static void gen11_display_wa_apply(struct intel_display *display) 15 { 16 /* Wa_14010594013 */ 17 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP); 18 } 19 20 static void xe_d_display_wa_apply(struct intel_display *display) 21 { 22 /* Wa_14013723622 */ 23 intel_de_rmw(display, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0); 24 } 25 26 static void adlp_display_wa_apply(struct intel_display *display) 27 { 28 /* Wa_22011091694:adlp */ 29 intel_de_rmw(display, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); 30 31 /* Bspec/49189 Initialize Sequence */ 32 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0); 33 } 34 35 static void xe3plpd_display_wa_apply(struct intel_display *display) 36 { 37 /* Wa_22021451799 */ 38 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, DMG_GATING_DIS); 39 } 40 41 void intel_display_wa_apply(struct intel_display *display) 42 { 43 if (DISPLAY_VER(display) == 35) 44 xe3plpd_display_wa_apply(display); 45 else if (display->platform.alderlake_p) 46 adlp_display_wa_apply(display); 47 else if (DISPLAY_VER(display) == 12) 48 xe_d_display_wa_apply(display); 49 else if (DISPLAY_VER(display) == 11) 50 gen11_display_wa_apply(display); 51 } 52 53 /* 54 * Wa_16025573575: 55 * Fixes: Issue with bitbashing on Xe3 based platforms. 56 * Workaround: Set masks bits in GPIO CTL and preserve it during bitbashing sequence. 57 */ 58 static bool intel_display_needs_wa_16025573575(struct intel_display *display) 59 { 60 return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002 || 61 DISPLAY_VERx100(display) == 3500; 62 } 63 64 /* 65 * Wa_14011503117: 66 * Fixes: Before enabling the scaler DE fatal error is masked 67 * Workaround: Unmask the DE fatal error register after enabling the scaler 68 * and after waiting of at least 1 frame. 69 */ 70 bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name) 71 { 72 switch (wa) { 73 case INTEL_DISPLAY_WA_1409120013: 74 return IS_DISPLAY_VER(display, 11, 12); 75 case INTEL_DISPLAY_WA_1409767108: 76 return (display->platform.alderlake_s || 77 (display->platform.rocketlake && 78 IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))); 79 case INTEL_DISPLAY_WA_13012396614: 80 return DISPLAY_VERx100(display) == 3000 || 81 DISPLAY_VERx100(display) == 3500; 82 case INTEL_DISPLAY_WA_14010477008: 83 return display->platform.dg1 || display->platform.rocketlake || 84 (display->platform.tigerlake && 85 IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)); 86 case INTEL_DISPLAY_WA_14010480278: 87 return (IS_DISPLAY_VER(display, 10, 12)); 88 case INTEL_DISPLAY_WA_14010547955: 89 return display->platform.dg2; 90 case INTEL_DISPLAY_WA_14010685332: 91 return INTEL_PCH_TYPE(display) >= PCH_CNP && 92 INTEL_PCH_TYPE(display) < PCH_DG1; 93 case INTEL_DISPLAY_WA_14011294188: 94 return INTEL_PCH_TYPE(display) >= PCH_TGP && 95 INTEL_PCH_TYPE(display) < PCH_DG1; 96 case INTEL_DISPLAY_WA_14011503030: 97 case INTEL_DISPLAY_WA_14011503117: 98 case INTEL_DISPLAY_WA_22012358565: 99 return DISPLAY_VER(display) == 13; 100 case INTEL_DISPLAY_WA_14011508470: 101 return (IS_DISPLAY_VERx100(display, 1200, 1300)); 102 case INTEL_DISPLAY_WA_14011765242: 103 return display->platform.alderlake_s && 104 IS_DISPLAY_STEP(display, STEP_A0, STEP_A2); 105 case INTEL_DISPLAY_WA_14014143976: 106 return IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER); 107 case INTEL_DISPLAY_WA_14016740474: 108 return IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0); 109 case INTEL_DISPLAY_WA_14020863754: 110 return DISPLAY_VERx100(display) == 3000 || 111 DISPLAY_VERx100(display) == 2000 || 112 DISPLAY_VERx100(display) == 1401; 113 case INTEL_DISPLAY_WA_14025769978: 114 return DISPLAY_VER(display) == 35; 115 case INTEL_DISPLAY_WA_14026643300: 116 return DISPLAY_VER(display) == 35; 117 case INTEL_DISPLAY_WA_15013987218: 118 return DISPLAY_VER(display) == 20; 119 case INTEL_DISPLAY_WA_15018326506: 120 return display->platform.battlemage; 121 case INTEL_DISPLAY_WA_16011303918: 122 case INTEL_DISPLAY_WA_22011320316: 123 return display->platform.alderlake_p && 124 IS_DISPLAY_STEP(display, STEP_A0, STEP_B0); 125 case INTEL_DISPLAY_WA_16011181250: 126 return display->platform.rocketlake || display->platform.alderlake_s || 127 display->platform.dg2; 128 case INTEL_DISPLAY_WA_16011342517: 129 return display->platform.alderlake_p && 130 IS_DISPLAY_STEP(display, STEP_A0, STEP_D0); 131 case INTEL_DISPLAY_WA_16011863758: 132 return DISPLAY_VER(display) >= 11; 133 case INTEL_DISPLAY_WA_16023588340: 134 return intel_display_needs_wa_16023588340(display); 135 case INTEL_DISPLAY_WA_16025573575: 136 return intel_display_needs_wa_16025573575(display); 137 case INTEL_DISPLAY_WA_16025596647: 138 return DISPLAY_VER(display) == 20 && 139 IS_DISPLAY_VERx100_STEP(display, 3000, 140 STEP_A0, STEP_B0); 141 case INTEL_DISPLAY_WA_16029024088: 142 return DISPLAY_VER(display) >= 35; 143 case INTEL_DISPLAY_WA_16030862157: 144 return DISPLAY_VER(display) == 35; 145 case INTEL_DISPLAY_WA_18034343758: 146 return DISPLAY_VER(display) == 20 || 147 (display->platform.pantherlake && 148 IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)); 149 case INTEL_DISPLAY_WA_22010178259: 150 return DISPLAY_VER(display) == 12; 151 case INTEL_DISPLAY_WA_22010947358: 152 return display->platform.alderlake_p; 153 case INTEL_DISPLAY_WA_22012278275: 154 return display->platform.alderlake_p && 155 IS_DISPLAY_STEP(display, STEP_A0, STEP_E0); 156 case INTEL_DISPLAY_WA_22014263786: 157 return IS_DISPLAY_VERx100(display, 1100, 1400); 158 case INTEL_DISPLAY_WA_22021048059: 159 return IS_DISPLAY_VER(display, 14, 35); 160 default: 161 drm_WARN(display->drm, 1, "Missing Wa: %s\n", name); 162 break; 163 } 164 165 return false; 166 } 167