1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_REG_DEFS_H__ 7 #define __INTEL_DISPLAY_REG_DEFS_H__ 8 9 #include "i915_reg_defs.h" 10 11 typedef i915_reg_t intel_reg_t; 12 13 static inline u32 intel_reg_offset(intel_reg_t r) 14 { 15 return r.reg; 16 } 17 18 static inline bool intel_reg_equal(intel_reg_t a, intel_reg_t b) 19 { 20 return intel_reg_offset(a) == intel_reg_offset(b); 21 } 22 23 static inline bool intel_reg_valid(intel_reg_t r) 24 { 25 return !intel_reg_equal(r, INVALID_MMIO_REG); 26 } 27 28 /* A triplet for IMR/IER/IIR registers. */ 29 struct intel_irq_regs { 30 intel_reg_t imr; 31 intel_reg_t ier; 32 intel_reg_t iir; 33 }; 34 35 #define INTEL_IRQ_REGS(_imr, _ier, _iir) \ 36 ((const struct intel_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) }) 37 38 struct intel_error_regs { 39 intel_reg_t emr; 40 intel_reg_t eir; 41 }; 42 43 #define INTEL_ERROR_REGS(_emr, _eir) \ 44 ((const struct intel_error_regs){ .emr = (_emr), .eir = (_eir) }) 45 46 #define VLV_DISPLAY_BASE 0x180000 47 48 /* 49 * Named helper wrappers around _PICK_EVEN() and _PICK_EVEN_2RANGES(). 50 */ 51 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 52 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 53 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 54 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 55 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 56 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) 57 58 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 59 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 60 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 61 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 62 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 63 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) 64 65 #define _MMIO_BASE_PIPE3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) 66 #define _MMIO_BASE_PORT3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) 67 68 /* 69 * Device info offset array based helpers for groups of registers with unevenly 70 * spaced base offsets. 71 */ 72 73 #define _MMIO_PIPE2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_PIPE_OFFSET((display), (pipe)) + (reg)) 74 #define _MMIO_TRANS2(display, trans, reg) _MMIO(INTEL_DISPLAY_DEVICE_TRANS_OFFSET((display), (trans)) + (reg)) 75 #define _MMIO_CURSOR2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_CURSOR_OFFSET((display), (pipe)) + (reg)) 76 77 #endif /* __INTEL_DISPLAY_REG_DEFS_H__ */ 78