1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_REG_DEFS_H__ 7 #define __INTEL_DISPLAY_REG_DEFS_H__ 8 9 #include "i915_reg_defs.h" 10 11 #define VLV_DISPLAY_BASE 0x180000 12 13 /* 14 * Named helper wrappers around _PICK_EVEN() and _PICK_EVEN_2RANGES(). 15 */ 16 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 17 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 18 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 19 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 20 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 21 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) 22 23 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 24 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 25 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 26 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 27 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 28 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) 29 30 #define _MMIO_BASE_PIPE3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) 31 #define _MMIO_BASE_PORT3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) 32 33 /* 34 * Device info offset array based helpers for groups of registers with unevenly 35 * spaced base offsets. 36 */ 37 38 #define _MMIO_PIPE2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_PIPE_OFFSET((display), (pipe)) + (reg)) 39 #define _MMIO_TRANS2(display, trans, reg) _MMIO(INTEL_DISPLAY_DEVICE_TRANS_OFFSET((display), (trans)) + (reg)) 40 #define _MMIO_CURSOR2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_CURSOR_OFFSET((display), (pipe)) + (reg)) 41 42 #endif /* __INTEL_DISPLAY_REG_DEFS_H__ */ 43