1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_irq.h" 8 #include "i915_reg.h" 9 #include "intel_backlight_regs.h" 10 #include "intel_combo_phy.h" 11 #include "intel_combo_phy_regs.h" 12 #include "intel_crt.h" 13 #include "intel_de.h" 14 #include "intel_display_irq.h" 15 #include "intel_display_power_well.h" 16 #include "intel_display_types.h" 17 #include "intel_dkl_phy.h" 18 #include "intel_dkl_phy_regs.h" 19 #include "intel_dmc.h" 20 #include "intel_dmc_wl.h" 21 #include "intel_dp_aux_regs.h" 22 #include "intel_dpio_phy.h" 23 #include "intel_dpll.h" 24 #include "intel_hotplug.h" 25 #include "intel_pcode.h" 26 #include "intel_pps.h" 27 #include "intel_tc.h" 28 #include "intel_vga.h" 29 #include "skl_watermark.h" 30 #include "vlv_dpio_phy_regs.h" 31 #include "vlv_sideband.h" 32 #include "vlv_sideband_reg.h" 33 34 struct i915_power_well_regs { 35 i915_reg_t bios; 36 i915_reg_t driver; 37 i915_reg_t kvmr; 38 i915_reg_t debug; 39 }; 40 41 struct i915_power_well_ops { 42 const struct i915_power_well_regs *regs; 43 /* 44 * Synchronize the well's hw state to match the current sw state, for 45 * example enable/disable it based on the current refcount. Called 46 * during driver init and resume time, possibly after first calling 47 * the enable/disable handlers. 48 */ 49 void (*sync_hw)(struct drm_i915_private *i915, 50 struct i915_power_well *power_well); 51 /* 52 * Enable the well and resources that depend on it (for example 53 * interrupts located on the well). Called after the 0->1 refcount 54 * transition. 55 */ 56 void (*enable)(struct drm_i915_private *i915, 57 struct i915_power_well *power_well); 58 /* 59 * Disable the well and resources that depend on it. Called after 60 * the 1->0 refcount transition. 61 */ 62 void (*disable)(struct drm_i915_private *i915, 63 struct i915_power_well *power_well); 64 /* Returns the hw enabled state. */ 65 bool (*is_enabled)(struct drm_i915_private *i915, 66 struct i915_power_well *power_well); 67 }; 68 69 static const struct i915_power_well_instance * 70 i915_power_well_instance(const struct i915_power_well *power_well) 71 { 72 return &power_well->desc->instances->list[power_well->instance_idx]; 73 } 74 75 struct i915_power_well * 76 lookup_power_well(struct drm_i915_private *i915, 77 enum i915_power_well_id power_well_id) 78 { 79 struct i915_power_well *power_well; 80 81 for_each_power_well(i915, power_well) 82 if (i915_power_well_instance(power_well)->id == power_well_id) 83 return power_well; 84 85 /* 86 * It's not feasible to add error checking code to the callers since 87 * this condition really shouldn't happen and it doesn't even make sense 88 * to abort things like display initialization sequences. Just return 89 * the first power well and hope the WARN gets reported so we can fix 90 * our driver. 91 */ 92 drm_WARN(&i915->drm, 1, 93 "Power well %d not defined for this platform\n", 94 power_well_id); 95 return &i915->display.power.domains.power_wells[0]; 96 } 97 98 void intel_power_well_enable(struct drm_i915_private *i915, 99 struct i915_power_well *power_well) 100 { 101 drm_dbg_kms(&i915->drm, "enabling %s\n", intel_power_well_name(power_well)); 102 power_well->desc->ops->enable(i915, power_well); 103 power_well->hw_enabled = true; 104 } 105 106 void intel_power_well_disable(struct drm_i915_private *i915, 107 struct i915_power_well *power_well) 108 { 109 drm_dbg_kms(&i915->drm, "disabling %s\n", intel_power_well_name(power_well)); 110 power_well->hw_enabled = false; 111 power_well->desc->ops->disable(i915, power_well); 112 } 113 114 void intel_power_well_sync_hw(struct drm_i915_private *i915, 115 struct i915_power_well *power_well) 116 { 117 power_well->desc->ops->sync_hw(i915, power_well); 118 power_well->hw_enabled = 119 power_well->desc->ops->is_enabled(i915, power_well); 120 } 121 122 void intel_power_well_get(struct drm_i915_private *i915, 123 struct i915_power_well *power_well) 124 { 125 if (!power_well->count++) 126 intel_power_well_enable(i915, power_well); 127 } 128 129 void intel_power_well_put(struct drm_i915_private *i915, 130 struct i915_power_well *power_well) 131 { 132 drm_WARN(&i915->drm, !power_well->count, 133 "Use count on power well %s is already zero", 134 i915_power_well_instance(power_well)->name); 135 136 if (!--power_well->count) 137 intel_power_well_disable(i915, power_well); 138 } 139 140 bool intel_power_well_is_enabled(struct drm_i915_private *i915, 141 struct i915_power_well *power_well) 142 { 143 return power_well->desc->ops->is_enabled(i915, power_well); 144 } 145 146 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well) 147 { 148 return power_well->hw_enabled; 149 } 150 151 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 152 enum i915_power_well_id power_well_id) 153 { 154 struct i915_power_well *power_well; 155 156 power_well = lookup_power_well(dev_priv, power_well_id); 157 158 return intel_power_well_is_enabled(dev_priv, power_well); 159 } 160 161 bool intel_power_well_is_always_on(struct i915_power_well *power_well) 162 { 163 return power_well->desc->always_on; 164 } 165 166 const char *intel_power_well_name(struct i915_power_well *power_well) 167 { 168 return i915_power_well_instance(power_well)->name; 169 } 170 171 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well) 172 { 173 return &power_well->domains; 174 } 175 176 int intel_power_well_refcount(struct i915_power_well *power_well) 177 { 178 return power_well->count; 179 } 180 181 /* 182 * Starting with Haswell, we have a "Power Down Well" that can be turned off 183 * when not needed anymore. We have 4 registers that can request the power well 184 * to be enabled, and it will only be disabled if none of the registers is 185 * requesting it to be enabled. 186 */ 187 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, 188 u8 irq_pipe_mask, bool has_vga) 189 { 190 struct intel_display *display = &dev_priv->display; 191 192 if (has_vga) 193 intel_vga_reset_io_mem(display); 194 195 if (irq_pipe_mask) 196 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); 197 } 198 199 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, 200 u8 irq_pipe_mask) 201 { 202 if (irq_pipe_mask) 203 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); 204 } 205 206 #define ICL_AUX_PW_TO_PHY(pw_idx) \ 207 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + PHY_A) 208 209 #define ICL_AUX_PW_TO_CH(pw_idx) \ 210 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) 211 212 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ 213 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) 214 215 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well) 216 { 217 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 218 219 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : 220 ICL_AUX_PW_TO_CH(pw_idx); 221 } 222 223 static struct intel_digital_port * 224 aux_ch_to_digital_port(struct drm_i915_private *dev_priv, 225 enum aux_ch aux_ch) 226 { 227 struct intel_encoder *encoder; 228 229 for_each_intel_encoder(&dev_priv->drm, encoder) { 230 struct intel_digital_port *dig_port; 231 232 /* We'll check the MST primary port */ 233 if (encoder->type == INTEL_OUTPUT_DP_MST) 234 continue; 235 236 dig_port = enc_to_dig_port(encoder); 237 238 if (dig_port && dig_port->aux_ch == aux_ch) 239 return dig_port; 240 } 241 242 return NULL; 243 } 244 245 static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915, 246 const struct i915_power_well *power_well) 247 { 248 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 249 struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch); 250 251 /* 252 * FIXME should we care about the (VBT defined) dig_port->aux_ch 253 * relationship or should this be purely defined by the hardware layout? 254 * Currently if the port doesn't appear in the VBT, or if it's declared 255 * as HDMI-only and routed to a combo PHY, the encoder either won't be 256 * present at all or it will not have an aux_ch assigned. 257 */ 258 return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE; 259 } 260 261 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 262 struct i915_power_well *power_well, 263 bool timeout_expected) 264 { 265 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 266 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 267 int timeout = power_well->desc->enable_timeout ? : 1; 268 269 /* 270 * For some power wells we're not supposed to watch the status bit for 271 * an ack, but rather just wait a fixed amount of time and then 272 * proceed. This is only used on DG2. 273 */ 274 if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) { 275 usleep_range(600, 1200); 276 return; 277 } 278 279 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 280 if (intel_de_wait_for_set(dev_priv, regs->driver, 281 HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) { 282 drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n", 283 intel_power_well_name(power_well)); 284 285 drm_WARN_ON(&dev_priv->drm, !timeout_expected); 286 287 } 288 } 289 290 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, 291 const struct i915_power_well_regs *regs, 292 int pw_idx) 293 { 294 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 295 u32 ret; 296 297 ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0; 298 ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0; 299 if (regs->kvmr.reg) 300 ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0; 301 ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0; 302 303 return ret; 304 } 305 306 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, 307 struct i915_power_well *power_well) 308 { 309 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 310 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 311 bool disabled; 312 u32 reqs; 313 314 /* 315 * Bspec doesn't require waiting for PWs to get disabled, but still do 316 * this for paranoia. The known cases where a PW will be forced on: 317 * - a KVMR request on any power well via the KVMR request register 318 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 319 * DEBUG request registers 320 * Skip the wait in case any of the request bits are set and print a 321 * diagnostic message. 322 */ 323 wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) & 324 HSW_PWR_WELL_CTL_STATE(pw_idx))) || 325 (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1); 326 if (disabled) 327 return; 328 329 drm_dbg_kms(&dev_priv->drm, 330 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 331 intel_power_well_name(power_well), 332 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 333 } 334 335 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, 336 enum skl_power_gate pg) 337 { 338 /* Timeout 5us for PG#0, for other PGs 1us */ 339 drm_WARN_ON(&dev_priv->drm, 340 intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS, 341 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 342 } 343 344 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 345 struct i915_power_well *power_well) 346 { 347 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 348 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 349 350 if (power_well->desc->has_fuses) { 351 enum skl_power_gate pg; 352 353 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 354 SKL_PW_CTL_IDX_TO_PG(pw_idx); 355 356 /* Wa_16013190616:adlp */ 357 if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1) 358 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 359 360 /* 361 * For PW1 we have to wait both for the PW0/PG0 fuse state 362 * before enabling the power well and PW1/PG1's own fuse 363 * state after the enabling. For all other power wells with 364 * fuses we only have to wait for that PW/PG's fuse state 365 * after the enabling. 366 */ 367 if (pg == SKL_PG1) 368 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); 369 } 370 371 intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 372 373 hsw_wait_for_power_well_enable(dev_priv, power_well, false); 374 375 if (power_well->desc->has_fuses) { 376 enum skl_power_gate pg; 377 378 pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 379 SKL_PW_CTL_IDX_TO_PG(pw_idx); 380 gen9_wait_for_power_well_fuses(dev_priv, pg); 381 } 382 383 hsw_power_well_post_enable(dev_priv, 384 power_well->desc->irq_pipe_mask, 385 power_well->desc->has_vga); 386 } 387 388 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 389 struct i915_power_well *power_well) 390 { 391 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 392 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 393 394 hsw_power_well_pre_disable(dev_priv, 395 power_well->desc->irq_pipe_mask); 396 397 intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 398 hsw_wait_for_power_well_disable(dev_priv, power_well); 399 } 400 401 static bool intel_aux_ch_is_edp(struct drm_i915_private *i915, enum aux_ch aux_ch) 402 { 403 struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch); 404 405 return dig_port && dig_port->base.type == INTEL_OUTPUT_EDP; 406 } 407 408 static void 409 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 410 struct i915_power_well *power_well) 411 { 412 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 413 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 414 415 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); 416 417 intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 418 419 /* 420 * FIXME not sure if we should derive the PHY from the pw_idx, or 421 * from the VBT defined AUX_CH->DDI->PHY mapping. 422 */ 423 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 424 0, ICL_LANE_ENABLE_AUX); 425 426 hsw_wait_for_power_well_enable(dev_priv, power_well, false); 427 428 /* Display WA #1178: icl */ 429 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && 430 !intel_aux_ch_is_edp(dev_priv, ICL_AUX_PW_TO_CH(pw_idx))) 431 intel_de_rmw(dev_priv, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), 432 0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI); 433 } 434 435 static void 436 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, 437 struct i915_power_well *power_well) 438 { 439 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 440 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 441 442 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); 443 444 /* 445 * FIXME not sure if we should derive the PHY from the pw_idx, or 446 * from the VBT defined AUX_CH->DDI->PHY mapping. 447 */ 448 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 449 ICL_LANE_ENABLE_AUX, 0); 450 451 intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 452 453 hsw_wait_for_power_well_disable(dev_priv, power_well); 454 } 455 456 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 457 458 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, 459 struct i915_power_well *power_well, 460 struct intel_digital_port *dig_port) 461 { 462 if (drm_WARN_ON(&dev_priv->drm, !dig_port)) 463 return; 464 465 if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 466 return; 467 468 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port)); 469 } 470 471 #else 472 473 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, 474 struct i915_power_well *power_well, 475 struct intel_digital_port *dig_port) 476 { 477 } 478 479 #endif 480 481 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1) 482 483 static void icl_tc_cold_exit(struct drm_i915_private *i915) 484 { 485 int ret, tries = 0; 486 487 while (1) { 488 ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0, 489 250, 1); 490 if (ret != -EAGAIN || ++tries == 3) 491 break; 492 msleep(1); 493 } 494 495 /* Spec states that TC cold exit can take up to 1ms to complete */ 496 if (!ret) 497 msleep(1); 498 499 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */ 500 drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" : 501 "succeeded"); 502 } 503 504 static void 505 icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 506 struct i915_power_well *power_well) 507 { 508 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 509 struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch); 510 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 511 bool is_tbt = power_well->desc->is_tc_tbt; 512 bool timeout_expected; 513 514 icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port); 515 516 intel_de_rmw(dev_priv, DP_AUX_CH_CTL(aux_ch), 517 DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0); 518 519 intel_de_rmw(dev_priv, regs->driver, 520 0, 521 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); 522 523 /* 524 * An AUX timeout is expected if the TBT DP tunnel is down, 525 * or need to enable AUX on a legacy TypeC port as part of the TC-cold 526 * exit sequence. 527 */ 528 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port); 529 if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 530 icl_tc_cold_exit(dev_priv); 531 532 hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected); 533 534 if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) { 535 enum tc_port tc_port; 536 537 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); 538 539 if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) & 540 DKL_CMN_UC_DW27_UC_HEALTH, 1)) 541 drm_warn(&dev_priv->drm, 542 "Timeout waiting TC uC health\n"); 543 } 544 } 545 546 static void 547 icl_aux_power_well_enable(struct drm_i915_private *dev_priv, 548 struct i915_power_well *power_well) 549 { 550 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 551 552 if (intel_phy_is_tc(dev_priv, phy)) 553 return icl_tc_phy_aux_power_well_enable(dev_priv, power_well); 554 else if (IS_ICELAKE(dev_priv)) 555 return icl_combo_phy_aux_power_well_enable(dev_priv, 556 power_well); 557 else 558 return hsw_power_well_enable(dev_priv, power_well); 559 } 560 561 static void 562 icl_aux_power_well_disable(struct drm_i915_private *dev_priv, 563 struct i915_power_well *power_well) 564 { 565 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 566 567 if (intel_phy_is_tc(dev_priv, phy)) 568 return hsw_power_well_disable(dev_priv, power_well); 569 else if (IS_ICELAKE(dev_priv)) 570 return icl_combo_phy_aux_power_well_disable(dev_priv, 571 power_well); 572 else 573 return hsw_power_well_disable(dev_priv, power_well); 574 } 575 576 /* 577 * We should only use the power well if we explicitly asked the hardware to 578 * enable it, so check if it's enabled and also check if we've requested it to 579 * be enabled. 580 */ 581 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 582 struct i915_power_well *power_well) 583 { 584 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 585 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 586 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 587 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | 588 HSW_PWR_WELL_CTL_STATE(pw_idx); 589 u32 val; 590 591 val = intel_de_read(dev_priv, regs->driver); 592 593 /* 594 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 595 * and the MISC_IO PW will be not restored, so check instead for the 596 * BIOS's own request bits, which are forced-on for these power wells 597 * when exiting DC5/6. 598 */ 599 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 600 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 601 val |= intel_de_read(dev_priv, regs->bios); 602 603 return (val & mask) == mask; 604 } 605 606 static void assert_can_enable_dc9(struct intel_display *display) 607 { 608 struct drm_i915_private *dev_priv = to_i915(display->drm); 609 610 drm_WARN_ONCE(display->drm, 611 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), 612 "DC9 already programmed to be enabled.\n"); 613 drm_WARN_ONCE(display->drm, 614 intel_de_read(display, DC_STATE_EN) & 615 DC_STATE_EN_UPTO_DC5, 616 "DC5 still not disabled to enable DC9.\n"); 617 drm_WARN_ONCE(display->drm, 618 intel_de_read(display, HSW_PWR_WELL_CTL2) & 619 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 620 "Power well 2 on.\n"); 621 drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), 622 "Interrupts not disabled yet.\n"); 623 624 /* 625 * TODO: check for the following to verify the conditions to enter DC9 626 * state are satisfied: 627 * 1] Check relevant display engine registers to verify if mode set 628 * disable sequence was followed. 629 * 2] Check if display uninitialize sequence is initialized. 630 */ 631 } 632 633 static void assert_can_disable_dc9(struct intel_display *display) 634 { 635 struct drm_i915_private *dev_priv = to_i915(display->drm); 636 637 drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), 638 "Interrupts not disabled yet.\n"); 639 drm_WARN_ONCE(display->drm, 640 intel_de_read(display, DC_STATE_EN) & 641 DC_STATE_EN_UPTO_DC5, 642 "DC5 still not disabled.\n"); 643 644 /* 645 * TODO: check for the following to verify DC9 state was indeed 646 * entered before programming to disable it: 647 * 1] Check relevant display engine registers to verify if mode 648 * set disable sequence was followed. 649 * 2] Check if display uninitialize sequence is initialized. 650 */ 651 } 652 653 static void gen9_write_dc_state(struct intel_display *display, 654 u32 state) 655 { 656 int rewrites = 0; 657 int rereads = 0; 658 u32 v; 659 660 intel_de_write(display, DC_STATE_EN, state); 661 662 /* It has been observed that disabling the dc6 state sometimes 663 * doesn't stick and dmc keeps returning old value. Make sure 664 * the write really sticks enough times and also force rewrite until 665 * we are confident that state is exactly what we want. 666 */ 667 do { 668 v = intel_de_read(display, DC_STATE_EN); 669 670 if (v != state) { 671 intel_de_write(display, DC_STATE_EN, state); 672 rewrites++; 673 rereads = 0; 674 } else if (rereads++ > 5) { 675 break; 676 } 677 678 } while (rewrites < 100); 679 680 if (v != state) 681 drm_err(display->drm, 682 "Writing dc state to 0x%x failed, now 0x%x\n", 683 state, v); 684 685 /* Most of the times we need one retry, avoid spam */ 686 if (rewrites > 1) 687 drm_dbg_kms(display->drm, 688 "Rewrote dc state to 0x%x %d times\n", 689 state, rewrites); 690 } 691 692 static u32 gen9_dc_mask(struct intel_display *display) 693 { 694 struct drm_i915_private *dev_priv = to_i915(display->drm); 695 u32 mask; 696 697 mask = DC_STATE_EN_UPTO_DC5; 698 699 if (DISPLAY_VER(display) >= 12) 700 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 701 | DC_STATE_EN_DC9; 702 else if (DISPLAY_VER(display) == 11) 703 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; 704 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 705 mask |= DC_STATE_EN_DC9; 706 else 707 mask |= DC_STATE_EN_UPTO_DC6; 708 709 return mask; 710 } 711 712 void gen9_sanitize_dc_state(struct intel_display *display) 713 { 714 struct i915_power_domains *power_domains = &display->power.domains; 715 u32 val; 716 717 if (!HAS_DISPLAY(display)) 718 return; 719 720 val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display); 721 722 drm_dbg_kms(display->drm, 723 "Resetting DC state tracking from %02x to %02x\n", 724 power_domains->dc_state, val); 725 power_domains->dc_state = val; 726 } 727 728 /** 729 * gen9_set_dc_state - set target display C power state 730 * @display: display instance 731 * @state: target DC power state 732 * - DC_STATE_DISABLE 733 * - DC_STATE_EN_UPTO_DC5 734 * - DC_STATE_EN_UPTO_DC6 735 * - DC_STATE_EN_DC9 736 * 737 * Signal to DMC firmware/HW the target DC power state passed in @state. 738 * DMC/HW can turn off individual display clocks and power rails when entering 739 * a deeper DC power state (higher in number) and turns these back when exiting 740 * that state to a shallower power state (lower in number). The HW will decide 741 * when to actually enter a given state on an on-demand basis, for instance 742 * depending on the active state of display pipes. The state of display 743 * registers backed by affected power rails are saved/restored as needed. 744 * 745 * Based on the above enabling a deeper DC power state is asynchronous wrt. 746 * enabling it. Disabling a deeper power state is synchronous: for instance 747 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 748 * back on and register state is restored. This is guaranteed by the MMIO write 749 * to DC_STATE_EN blocking until the state is restored. 750 */ 751 void gen9_set_dc_state(struct intel_display *display, u32 state) 752 { 753 struct i915_power_domains *power_domains = &display->power.domains; 754 u32 val; 755 u32 mask; 756 757 if (!HAS_DISPLAY(display)) 758 return; 759 760 if (drm_WARN_ON_ONCE(display->drm, 761 state & ~power_domains->allowed_dc_mask)) 762 state &= power_domains->allowed_dc_mask; 763 764 val = intel_de_read(display, DC_STATE_EN); 765 mask = gen9_dc_mask(display); 766 drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", 767 val & mask, state); 768 769 /* Check if DMC is ignoring our DC state requests */ 770 if ((val & mask) != power_domains->dc_state) 771 drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n", 772 power_domains->dc_state, val & mask); 773 774 val &= ~mask; 775 val |= state; 776 777 gen9_write_dc_state(display, val); 778 779 power_domains->dc_state = val & mask; 780 } 781 782 static void tgl_enable_dc3co(struct intel_display *display) 783 { 784 drm_dbg_kms(display->drm, "Enabling DC3CO\n"); 785 gen9_set_dc_state(display, DC_STATE_EN_DC3CO); 786 } 787 788 static void tgl_disable_dc3co(struct intel_display *display) 789 { 790 drm_dbg_kms(display->drm, "Disabling DC3CO\n"); 791 intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); 792 gen9_set_dc_state(display, DC_STATE_DISABLE); 793 /* 794 * Delay of 200us DC3CO Exit time B.Spec 49196 795 */ 796 usleep_range(200, 210); 797 } 798 799 static void assert_can_enable_dc5(struct intel_display *display) 800 { 801 struct drm_i915_private *dev_priv = to_i915(display->drm); 802 enum i915_power_well_id high_pg; 803 804 /* Power wells at this level and above must be disabled for DC5 entry */ 805 if (DISPLAY_VER(display) == 12) 806 high_pg = ICL_DISP_PW_3; 807 else 808 high_pg = SKL_DISP_PW_2; 809 810 drm_WARN_ONCE(display->drm, 811 intel_display_power_well_is_enabled(dev_priv, high_pg), 812 "Power wells above platform's DC5 limit still enabled.\n"); 813 814 drm_WARN_ONCE(display->drm, 815 (intel_de_read(display, DC_STATE_EN) & 816 DC_STATE_EN_UPTO_DC5), 817 "DC5 already programmed to be enabled.\n"); 818 assert_rpm_wakelock_held(&dev_priv->runtime_pm); 819 820 assert_dmc_loaded(display); 821 } 822 823 void gen9_enable_dc5(struct intel_display *display) 824 { 825 struct drm_i915_private *dev_priv = to_i915(display->drm); 826 827 assert_can_enable_dc5(display); 828 829 drm_dbg_kms(display->drm, "Enabling DC5\n"); 830 831 /* Wa Display #1183: skl,kbl,cfl */ 832 if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv)) 833 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 834 0, SKL_SELECT_ALTERNATE_DC_EXIT); 835 836 intel_dmc_wl_enable(display); 837 838 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); 839 } 840 841 static void assert_can_enable_dc6(struct intel_display *display) 842 { 843 drm_WARN_ONCE(display->drm, 844 (intel_de_read(display, UTIL_PIN_CTL) & 845 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == 846 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 847 "Utility pin enabled in PWM mode\n"); 848 drm_WARN_ONCE(display->drm, 849 (intel_de_read(display, DC_STATE_EN) & 850 DC_STATE_EN_UPTO_DC6), 851 "DC6 already programmed to be enabled.\n"); 852 853 assert_dmc_loaded(display); 854 } 855 856 void skl_enable_dc6(struct intel_display *display) 857 { 858 struct drm_i915_private *dev_priv = to_i915(display->drm); 859 860 assert_can_enable_dc6(display); 861 862 drm_dbg_kms(display->drm, "Enabling DC6\n"); 863 864 /* Wa Display #1183: skl,kbl,cfl */ 865 if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv)) 866 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 867 0, SKL_SELECT_ALTERNATE_DC_EXIT); 868 869 intel_dmc_wl_enable(display); 870 871 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); 872 } 873 874 void bxt_enable_dc9(struct intel_display *display) 875 { 876 struct drm_i915_private *dev_priv = to_i915(display->drm); 877 878 assert_can_enable_dc9(display); 879 880 drm_dbg_kms(display->drm, "Enabling DC9\n"); 881 /* 882 * Power sequencer reset is not needed on 883 * platforms with South Display Engine on PCH, 884 * because PPS registers are always on. 885 */ 886 if (!HAS_PCH_SPLIT(dev_priv)) 887 intel_pps_reset_all(display); 888 gen9_set_dc_state(display, DC_STATE_EN_DC9); 889 } 890 891 void bxt_disable_dc9(struct intel_display *display) 892 { 893 assert_can_disable_dc9(display); 894 895 drm_dbg_kms(display->drm, "Disabling DC9\n"); 896 897 gen9_set_dc_state(display, DC_STATE_DISABLE); 898 899 intel_pps_unlock_regs_wa(display); 900 } 901 902 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 903 struct i915_power_well *power_well) 904 { 905 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 906 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 907 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 908 u32 bios_req = intel_de_read(dev_priv, regs->bios); 909 910 /* Take over the request bit if set by BIOS. */ 911 if (bios_req & mask) { 912 u32 drv_req = intel_de_read(dev_priv, regs->driver); 913 914 if (!(drv_req & mask)) 915 intel_de_write(dev_priv, regs->driver, drv_req | mask); 916 intel_de_write(dev_priv, regs->bios, bios_req & ~mask); 917 } 918 } 919 920 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 921 struct i915_power_well *power_well) 922 { 923 bxt_dpio_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 924 } 925 926 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 927 struct i915_power_well *power_well) 928 { 929 bxt_dpio_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 930 } 931 932 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, 933 struct i915_power_well *power_well) 934 { 935 return bxt_dpio_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 936 } 937 938 static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv) 939 { 940 struct i915_power_well *power_well; 941 942 power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A); 943 if (intel_power_well_refcount(power_well) > 0) 944 bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 945 946 power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 947 if (intel_power_well_refcount(power_well) > 0) 948 bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy); 949 950 if (IS_GEMINILAKE(dev_priv)) { 951 power_well = lookup_power_well(dev_priv, 952 GLK_DISP_PW_DPIO_CMN_C); 953 if (intel_power_well_refcount(power_well) > 0) 954 bxt_dpio_phy_verify_state(dev_priv, 955 i915_power_well_instance(power_well)->bxt.phy); 956 } 957 } 958 959 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 960 struct i915_power_well *power_well) 961 { 962 struct intel_display *display = &dev_priv->display; 963 964 return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && 965 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); 966 } 967 968 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) 969 { 970 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv); 971 u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices; 972 973 drm_WARN(&dev_priv->drm, 974 hw_enabled_dbuf_slices != enabled_dbuf_slices, 975 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 976 hw_enabled_dbuf_slices, 977 enabled_dbuf_slices); 978 } 979 980 void gen9_disable_dc_states(struct intel_display *display) 981 { 982 struct drm_i915_private *dev_priv = to_i915(display->drm); 983 struct i915_power_domains *power_domains = &display->power.domains; 984 struct intel_cdclk_config cdclk_config = {}; 985 986 if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { 987 tgl_disable_dc3co(display); 988 return; 989 } 990 991 gen9_set_dc_state(display, DC_STATE_DISABLE); 992 993 if (!HAS_DISPLAY(display)) 994 return; 995 996 intel_dmc_wl_disable(display); 997 998 intel_cdclk_get_cdclk(display, &cdclk_config); 999 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 1000 drm_WARN_ON(display->drm, 1001 intel_cdclk_clock_changed(&display->cdclk.hw, 1002 &cdclk_config)); 1003 1004 gen9_assert_dbuf_enabled(dev_priv); 1005 1006 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1007 bxt_verify_dpio_phy_power_wells(dev_priv); 1008 1009 if (DISPLAY_VER(display) >= 11) 1010 /* 1011 * DMC retains HW context only for port A, the other combo 1012 * PHY's HW context for port B is lost after DC transitions, 1013 * so we need to restore it manually. 1014 */ 1015 intel_combo_phy_init(dev_priv); 1016 } 1017 1018 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 1019 struct i915_power_well *power_well) 1020 { 1021 struct intel_display *display = &dev_priv->display; 1022 1023 gen9_disable_dc_states(display); 1024 } 1025 1026 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 1027 struct i915_power_well *power_well) 1028 { 1029 struct intel_display *display = &dev_priv->display; 1030 struct i915_power_domains *power_domains = &display->power.domains; 1031 1032 if (!intel_dmc_has_payload(display)) 1033 return; 1034 1035 switch (power_domains->target_dc_state) { 1036 case DC_STATE_EN_DC3CO: 1037 tgl_enable_dc3co(display); 1038 break; 1039 case DC_STATE_EN_UPTO_DC6: 1040 skl_enable_dc6(display); 1041 break; 1042 case DC_STATE_EN_UPTO_DC5: 1043 gen9_enable_dc5(display); 1044 break; 1045 } 1046 } 1047 1048 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, 1049 struct i915_power_well *power_well) 1050 { 1051 } 1052 1053 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 1054 struct i915_power_well *power_well) 1055 { 1056 } 1057 1058 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 1059 struct i915_power_well *power_well) 1060 { 1061 return true; 1062 } 1063 1064 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, 1065 struct i915_power_well *power_well) 1066 { 1067 struct intel_display *display = &dev_priv->display; 1068 1069 if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0) 1070 i830_enable_pipe(display, PIPE_A); 1071 if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0) 1072 i830_enable_pipe(display, PIPE_B); 1073 } 1074 1075 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, 1076 struct i915_power_well *power_well) 1077 { 1078 struct intel_display *display = &dev_priv->display; 1079 1080 i830_disable_pipe(display, PIPE_B); 1081 i830_disable_pipe(display, PIPE_A); 1082 } 1083 1084 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, 1085 struct i915_power_well *power_well) 1086 { 1087 struct intel_display *display = &dev_priv->display; 1088 1089 return intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE && 1090 intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; 1091 } 1092 1093 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, 1094 struct i915_power_well *power_well) 1095 { 1096 if (intel_power_well_refcount(power_well) > 0) 1097 i830_pipes_power_well_enable(dev_priv, power_well); 1098 else 1099 i830_pipes_power_well_disable(dev_priv, power_well); 1100 } 1101 1102 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 1103 struct i915_power_well *power_well, bool enable) 1104 { 1105 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1106 u32 mask; 1107 u32 state; 1108 u32 ctrl; 1109 1110 mask = PUNIT_PWRGT_MASK(pw_idx); 1111 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : 1112 PUNIT_PWRGT_PWR_GATE(pw_idx); 1113 1114 vlv_punit_get(dev_priv); 1115 1116 #define COND \ 1117 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 1118 1119 if (COND) 1120 goto out; 1121 1122 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 1123 ctrl &= ~mask; 1124 ctrl |= state; 1125 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 1126 1127 if (wait_for(COND, 100)) 1128 drm_err(&dev_priv->drm, 1129 "timeout setting power well state %08x (%08x)\n", 1130 state, 1131 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 1132 1133 #undef COND 1134 1135 out: 1136 vlv_punit_put(dev_priv); 1137 } 1138 1139 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 1140 struct i915_power_well *power_well) 1141 { 1142 vlv_set_power_well(dev_priv, power_well, true); 1143 } 1144 1145 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 1146 struct i915_power_well *power_well) 1147 { 1148 vlv_set_power_well(dev_priv, power_well, false); 1149 } 1150 1151 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 1152 struct i915_power_well *power_well) 1153 { 1154 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1155 bool enabled = false; 1156 u32 mask; 1157 u32 state; 1158 u32 ctrl; 1159 1160 mask = PUNIT_PWRGT_MASK(pw_idx); 1161 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); 1162 1163 vlv_punit_get(dev_priv); 1164 1165 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 1166 /* 1167 * We only ever set the power-on and power-gate states, anything 1168 * else is unexpected. 1169 */ 1170 drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1171 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 1172 if (state == ctrl) 1173 enabled = true; 1174 1175 /* 1176 * A transient state at this point would mean some unexpected party 1177 * is poking at the power controls too. 1178 */ 1179 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 1180 drm_WARN_ON(&dev_priv->drm, ctrl != state); 1181 1182 vlv_punit_put(dev_priv); 1183 1184 return enabled; 1185 } 1186 1187 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 1188 { 1189 /* 1190 * On driver load, a pipe may be active and driving a DSI display. 1191 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1192 * (and never recovering) in this case. intel_dsi_post_disable() will 1193 * clear it when we turn off the display. 1194 */ 1195 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), 1196 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE); 1197 1198 /* 1199 * Disable trickle feed and enable pnd deadline calculation 1200 */ 1201 intel_de_write(dev_priv, MI_ARB_VLV, 1202 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1203 intel_de_write(dev_priv, CBR1_VLV, 0); 1204 1205 drm_WARN_ON(&dev_priv->drm, DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq == 0); 1206 intel_de_write(dev_priv, RAWCLK_FREQ_VLV, 1207 DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq, 1208 1000)); 1209 } 1210 1211 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 1212 { 1213 struct intel_display *display = &dev_priv->display; 1214 struct intel_encoder *encoder; 1215 enum pipe pipe; 1216 1217 /* 1218 * Enable the CRI clock source so we can get at the 1219 * display and the reference clock for VGA 1220 * hotplug / manual detection. Supposedly DSI also 1221 * needs the ref clock up and running. 1222 * 1223 * CHV DPLL B/C have some issues if VGA mode is enabled. 1224 */ 1225 for_each_pipe(dev_priv, pipe) { 1226 u32 val = intel_de_read(dev_priv, DPLL(dev_priv, pipe)); 1227 1228 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1229 if (pipe != PIPE_A) 1230 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1231 1232 intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); 1233 } 1234 1235 vlv_init_display_clock_gating(dev_priv); 1236 1237 spin_lock_irq(&dev_priv->irq_lock); 1238 valleyview_enable_display_irqs(dev_priv); 1239 spin_unlock_irq(&dev_priv->irq_lock); 1240 1241 /* 1242 * During driver initialization/resume we can avoid restoring the 1243 * part of the HW/SW state that will be inited anyway explicitly. 1244 */ 1245 if (dev_priv->display.power.domains.initializing) 1246 return; 1247 1248 intel_hpd_init(dev_priv); 1249 intel_hpd_poll_disable(dev_priv); 1250 1251 /* Re-enable the ADPA, if we have one */ 1252 for_each_intel_encoder(&dev_priv->drm, encoder) { 1253 if (encoder->type == INTEL_OUTPUT_ANALOG) 1254 intel_crt_reset(&encoder->base); 1255 } 1256 1257 intel_vga_redisable_power_on(display); 1258 1259 intel_pps_unlock_regs_wa(display); 1260 } 1261 1262 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 1263 { 1264 struct intel_display *display = &dev_priv->display; 1265 1266 spin_lock_irq(&dev_priv->irq_lock); 1267 valleyview_disable_display_irqs(dev_priv); 1268 spin_unlock_irq(&dev_priv->irq_lock); 1269 1270 /* make sure we're done processing display irqs */ 1271 intel_synchronize_irq(dev_priv); 1272 1273 intel_pps_reset_all(display); 1274 1275 /* Prevent us from re-enabling polling on accident in late suspend */ 1276 if (!dev_priv->drm.dev->power.is_suspended) 1277 intel_hpd_poll_enable(dev_priv); 1278 } 1279 1280 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 1281 struct i915_power_well *power_well) 1282 { 1283 vlv_set_power_well(dev_priv, power_well, true); 1284 1285 vlv_display_power_well_init(dev_priv); 1286 } 1287 1288 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 1289 struct i915_power_well *power_well) 1290 { 1291 vlv_display_power_well_deinit(dev_priv); 1292 1293 vlv_set_power_well(dev_priv, power_well, false); 1294 } 1295 1296 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1297 struct i915_power_well *power_well) 1298 { 1299 /* since ref/cri clock was enabled */ 1300 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1301 1302 vlv_set_power_well(dev_priv, power_well, true); 1303 1304 /* 1305 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1306 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1307 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1308 * b. The other bits such as sfr settings / modesel may all 1309 * be set to 0. 1310 * 1311 * This should only be done on init and resume from S3 with 1312 * both PLLs disabled, or we risk losing DPIO and PLL 1313 * synchronization. 1314 */ 1315 intel_de_rmw(dev_priv, DPIO_CTL, 0, DPIO_CMNRST); 1316 } 1317 1318 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1319 struct i915_power_well *power_well) 1320 { 1321 enum pipe pipe; 1322 1323 for_each_pipe(dev_priv, pipe) 1324 assert_pll_disabled(dev_priv, pipe); 1325 1326 /* Assert common reset */ 1327 intel_de_rmw(dev_priv, DPIO_CTL, DPIO_CMNRST, 0); 1328 1329 vlv_set_power_well(dev_priv, power_well, false); 1330 } 1331 1332 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1333 1334 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1335 { 1336 struct i915_power_well *cmn_bc = 1337 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1338 struct i915_power_well *cmn_d = 1339 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); 1340 u32 phy_control = dev_priv->display.power.chv_phy_control; 1341 u32 phy_status = 0; 1342 u32 phy_status_mask = 0xffffffff; 1343 1344 /* 1345 * The BIOS can leave the PHY is some weird state 1346 * where it doesn't fully power down some parts. 1347 * Disable the asserts until the PHY has been fully 1348 * reset (ie. the power well has been disabled at 1349 * least once). 1350 */ 1351 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0]) 1352 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1353 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1354 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1355 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1356 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1357 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1358 1359 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1]) 1360 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1361 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1362 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1363 1364 if (intel_power_well_is_enabled(dev_priv, cmn_bc)) { 1365 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1366 1367 /* this assumes override is only used to enable lanes */ 1368 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1369 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1370 1371 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1372 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1373 1374 /* CL1 is on whenever anything is on in either channel */ 1375 if (BITS_SET(phy_control, 1376 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1377 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1378 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1379 1380 /* 1381 * The DPLLB check accounts for the pipe B + port A usage 1382 * with CL2 powered up but all the lanes in the second channel 1383 * powered down. 1384 */ 1385 if (BITS_SET(phy_control, 1386 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1387 (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1388 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1389 1390 if (BITS_SET(phy_control, 1391 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1392 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1393 if (BITS_SET(phy_control, 1394 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1395 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1396 1397 if (BITS_SET(phy_control, 1398 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1399 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1400 if (BITS_SET(phy_control, 1401 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1402 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1403 } 1404 1405 if (intel_power_well_is_enabled(dev_priv, cmn_d)) { 1406 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1407 1408 /* this assumes override is only used to enable lanes */ 1409 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1410 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1411 1412 if (BITS_SET(phy_control, 1413 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1414 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1415 1416 if (BITS_SET(phy_control, 1417 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1418 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1419 if (BITS_SET(phy_control, 1420 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1421 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1422 } 1423 1424 phy_status &= phy_status_mask; 1425 1426 /* 1427 * The PHY may be busy with some initial calibration and whatnot, 1428 * so the power state can take a while to actually change. 1429 */ 1430 if (intel_de_wait(dev_priv, DISPLAY_PHY_STATUS, 1431 phy_status_mask, phy_status, 10)) 1432 drm_err(&dev_priv->drm, 1433 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1434 intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask, 1435 phy_status, dev_priv->display.power.chv_phy_control); 1436 } 1437 1438 #undef BITS_SET 1439 1440 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1441 struct i915_power_well *power_well) 1442 { 1443 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1444 enum dpio_phy phy; 1445 u32 tmp; 1446 1447 drm_WARN_ON_ONCE(&dev_priv->drm, 1448 id != VLV_DISP_PW_DPIO_CMN_BC && 1449 id != CHV_DISP_PW_DPIO_CMN_D); 1450 1451 if (id == VLV_DISP_PW_DPIO_CMN_BC) 1452 phy = DPIO_PHY0; 1453 else 1454 phy = DPIO_PHY1; 1455 1456 /* since ref/cri clock was enabled */ 1457 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1458 vlv_set_power_well(dev_priv, power_well, true); 1459 1460 /* Poll for phypwrgood signal */ 1461 if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS, 1462 PHY_POWERGOOD(phy), 1)) 1463 drm_err(&dev_priv->drm, "Display PHY %d is not power up\n", 1464 phy); 1465 1466 vlv_dpio_get(dev_priv); 1467 1468 /* Enable dynamic power down */ 1469 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW28); 1470 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1471 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1472 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp); 1473 1474 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1475 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1); 1476 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1477 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW6_CH1, tmp); 1478 } else { 1479 /* 1480 * Force the non-existing CL2 off. BXT does this 1481 * too, so maybe it saves some power even though 1482 * CL2 doesn't exist? 1483 */ 1484 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW30); 1485 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1486 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW30, tmp); 1487 } 1488 1489 vlv_dpio_put(dev_priv); 1490 1491 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1492 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1493 dev_priv->display.power.chv_phy_control); 1494 1495 drm_dbg_kms(&dev_priv->drm, 1496 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1497 phy, dev_priv->display.power.chv_phy_control); 1498 1499 assert_chv_phy_status(dev_priv); 1500 } 1501 1502 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1503 struct i915_power_well *power_well) 1504 { 1505 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1506 enum dpio_phy phy; 1507 1508 drm_WARN_ON_ONCE(&dev_priv->drm, 1509 id != VLV_DISP_PW_DPIO_CMN_BC && 1510 id != CHV_DISP_PW_DPIO_CMN_D); 1511 1512 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1513 phy = DPIO_PHY0; 1514 assert_pll_disabled(dev_priv, PIPE_A); 1515 assert_pll_disabled(dev_priv, PIPE_B); 1516 } else { 1517 phy = DPIO_PHY1; 1518 assert_pll_disabled(dev_priv, PIPE_C); 1519 } 1520 1521 dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1522 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1523 dev_priv->display.power.chv_phy_control); 1524 1525 vlv_set_power_well(dev_priv, power_well, false); 1526 1527 drm_dbg_kms(&dev_priv->drm, 1528 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1529 phy, dev_priv->display.power.chv_phy_control); 1530 1531 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1532 dev_priv->display.power.chv_phy_assert[phy] = true; 1533 1534 assert_chv_phy_status(dev_priv); 1535 } 1536 1537 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1538 enum dpio_channel ch, bool override, unsigned int mask) 1539 { 1540 u32 reg, val, expected, actual; 1541 1542 /* 1543 * The BIOS can leave the PHY is some weird state 1544 * where it doesn't fully power down some parts. 1545 * Disable the asserts until the PHY has been fully 1546 * reset (ie. the power well has been disabled at 1547 * least once). 1548 */ 1549 if (!dev_priv->display.power.chv_phy_assert[phy]) 1550 return; 1551 1552 if (ch == DPIO_CH0) 1553 reg = CHV_CMN_DW0_CH0; 1554 else 1555 reg = CHV_CMN_DW6_CH1; 1556 1557 vlv_dpio_get(dev_priv); 1558 val = vlv_dpio_read(dev_priv, phy, reg); 1559 vlv_dpio_put(dev_priv); 1560 1561 /* 1562 * This assumes !override is only used when the port is disabled. 1563 * All lanes should power down even without the override when 1564 * the port is disabled. 1565 */ 1566 if (!override || mask == 0xf) { 1567 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1568 /* 1569 * If CH1 common lane is not active anymore 1570 * (eg. for pipe B DPLL) the entire channel will 1571 * shut down, which causes the common lane registers 1572 * to read as 0. That means we can't actually check 1573 * the lane power down status bits, but as the entire 1574 * register reads as 0 it's a good indication that the 1575 * channel is indeed entirely powered down. 1576 */ 1577 if (ch == DPIO_CH1 && val == 0) 1578 expected = 0; 1579 } else if (mask != 0x0) { 1580 expected = DPIO_ANYDL_POWERDOWN; 1581 } else { 1582 expected = 0; 1583 } 1584 1585 if (ch == DPIO_CH0) 1586 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 | 1587 DPIO_ALLDL_POWERDOWN_CH0, val); 1588 else 1589 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 | 1590 DPIO_ALLDL_POWERDOWN_CH1, val); 1591 1592 drm_WARN(&dev_priv->drm, actual != expected, 1593 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1594 !!(actual & DPIO_ALLDL_POWERDOWN), 1595 !!(actual & DPIO_ANYDL_POWERDOWN), 1596 !!(expected & DPIO_ALLDL_POWERDOWN), 1597 !!(expected & DPIO_ANYDL_POWERDOWN), 1598 reg, val); 1599 } 1600 1601 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1602 enum dpio_channel ch, bool override) 1603 { 1604 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1605 bool was_override; 1606 1607 mutex_lock(&power_domains->lock); 1608 1609 was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1610 1611 if (override == was_override) 1612 goto out; 1613 1614 if (override) 1615 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1616 else 1617 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1618 1619 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1620 dev_priv->display.power.chv_phy_control); 1621 1622 drm_dbg_kms(&dev_priv->drm, 1623 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1624 phy, ch, dev_priv->display.power.chv_phy_control); 1625 1626 assert_chv_phy_status(dev_priv); 1627 1628 out: 1629 mutex_unlock(&power_domains->lock); 1630 1631 return was_override; 1632 } 1633 1634 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1635 bool override, unsigned int mask) 1636 { 1637 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1638 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1639 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1640 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 1641 1642 mutex_lock(&power_domains->lock); 1643 1644 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1645 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1646 1647 if (override) 1648 dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1649 else 1650 dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1651 1652 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1653 dev_priv->display.power.chv_phy_control); 1654 1655 drm_dbg_kms(&dev_priv->drm, 1656 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1657 phy, ch, mask, dev_priv->display.power.chv_phy_control); 1658 1659 assert_chv_phy_status(dev_priv); 1660 1661 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1662 1663 mutex_unlock(&power_domains->lock); 1664 } 1665 1666 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1667 struct i915_power_well *power_well) 1668 { 1669 enum pipe pipe = PIPE_A; 1670 bool enabled; 1671 u32 state, ctrl; 1672 1673 vlv_punit_get(dev_priv); 1674 1675 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); 1676 /* 1677 * We only ever set the power-on and power-gate states, anything 1678 * else is unexpected. 1679 */ 1680 drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) && 1681 state != DP_SSS_PWR_GATE(pipe)); 1682 enabled = state == DP_SSS_PWR_ON(pipe); 1683 1684 /* 1685 * A transient state at this point would mean some unexpected party 1686 * is poking at the power controls too. 1687 */ 1688 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); 1689 drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state); 1690 1691 vlv_punit_put(dev_priv); 1692 1693 return enabled; 1694 } 1695 1696 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1697 struct i915_power_well *power_well, 1698 bool enable) 1699 { 1700 enum pipe pipe = PIPE_A; 1701 u32 state; 1702 u32 ctrl; 1703 1704 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1705 1706 vlv_punit_get(dev_priv); 1707 1708 #define COND \ 1709 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) 1710 1711 if (COND) 1712 goto out; 1713 1714 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 1715 ctrl &= ~DP_SSC_MASK(pipe); 1716 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1717 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl); 1718 1719 if (wait_for(COND, 100)) 1720 drm_err(&dev_priv->drm, 1721 "timeout setting power well state %08x (%08x)\n", 1722 state, 1723 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); 1724 1725 #undef COND 1726 1727 out: 1728 vlv_punit_put(dev_priv); 1729 } 1730 1731 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1732 struct i915_power_well *power_well) 1733 { 1734 intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1735 dev_priv->display.power.chv_phy_control); 1736 } 1737 1738 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1739 struct i915_power_well *power_well) 1740 { 1741 chv_set_pipe_power_well(dev_priv, power_well, true); 1742 1743 vlv_display_power_well_init(dev_priv); 1744 } 1745 1746 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1747 struct i915_power_well *power_well) 1748 { 1749 vlv_display_power_well_deinit(dev_priv); 1750 1751 chv_set_pipe_power_well(dev_priv, power_well, false); 1752 } 1753 1754 static void 1755 tgl_tc_cold_request(struct drm_i915_private *i915, bool block) 1756 { 1757 u8 tries = 0; 1758 int ret; 1759 1760 while (1) { 1761 u32 low_val; 1762 u32 high_val = 0; 1763 1764 if (block) 1765 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ; 1766 else 1767 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ; 1768 1769 /* 1770 * Spec states that we should timeout the request after 200us 1771 * but the function below will timeout after 500us 1772 */ 1773 ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val); 1774 if (ret == 0) { 1775 if (block && 1776 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED)) 1777 ret = -EIO; 1778 else 1779 break; 1780 } 1781 1782 if (++tries == 3) 1783 break; 1784 1785 msleep(1); 1786 } 1787 1788 if (ret) 1789 drm_err(&i915->drm, "TC cold %sblock failed\n", 1790 block ? "" : "un"); 1791 else 1792 drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n", 1793 block ? "" : "un"); 1794 } 1795 1796 static void 1797 tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915, 1798 struct i915_power_well *power_well) 1799 { 1800 tgl_tc_cold_request(i915, true); 1801 } 1802 1803 static void 1804 tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915, 1805 struct i915_power_well *power_well) 1806 { 1807 tgl_tc_cold_request(i915, false); 1808 } 1809 1810 static void 1811 tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915, 1812 struct i915_power_well *power_well) 1813 { 1814 if (intel_power_well_refcount(power_well) > 0) 1815 tgl_tc_cold_off_power_well_enable(i915, power_well); 1816 else 1817 tgl_tc_cold_off_power_well_disable(i915, power_well); 1818 } 1819 1820 static bool 1821 tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv, 1822 struct i915_power_well *power_well) 1823 { 1824 /* 1825 * Not the correctly implementation but there is no way to just read it 1826 * from PCODE, so returning count to avoid state mismatch errors 1827 */ 1828 return intel_power_well_refcount(power_well); 1829 } 1830 1831 static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv, 1832 struct i915_power_well *power_well) 1833 { 1834 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1835 enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 1836 1837 if (intel_phy_is_tc(dev_priv, phy)) 1838 icl_tc_port_assert_ref_held(dev_priv, power_well, 1839 aux_ch_to_digital_port(dev_priv, aux_ch)); 1840 1841 intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch), 1842 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1843 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1844 1845 /* 1846 * The power status flag cannot be used to determine whether aux 1847 * power wells have finished powering up. Instead we're 1848 * expected to just wait a fixed 600us after raising the request 1849 * bit. 1850 */ 1851 usleep_range(600, 1200); 1852 } 1853 1854 static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv, 1855 struct i915_power_well *power_well) 1856 { 1857 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1858 1859 intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch), 1860 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1861 0); 1862 usleep_range(10, 30); 1863 } 1864 1865 static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv, 1866 struct i915_power_well *power_well) 1867 { 1868 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1869 1870 return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch)) & 1871 XELPDP_DP_AUX_CH_CTL_POWER_STATUS; 1872 } 1873 1874 static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv, 1875 struct i915_power_well *power_well) 1876 { 1877 intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL, 1878 XE2LPD_PICA_CTL_POWER_REQUEST); 1879 1880 if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL, 1881 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1882 drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n"); 1883 1884 drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled"); 1885 } 1886 } 1887 1888 static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv, 1889 struct i915_power_well *power_well) 1890 { 1891 intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL, 0); 1892 1893 if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL, 1894 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1895 drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n"); 1896 1897 drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled"); 1898 } 1899 } 1900 1901 static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv, 1902 struct i915_power_well *power_well) 1903 { 1904 return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) & 1905 XE2LPD_PICA_CTL_POWER_STATUS; 1906 } 1907 1908 const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1909 .sync_hw = i9xx_power_well_sync_hw_noop, 1910 .enable = i9xx_always_on_power_well_noop, 1911 .disable = i9xx_always_on_power_well_noop, 1912 .is_enabled = i9xx_always_on_power_well_enabled, 1913 }; 1914 1915 const struct i915_power_well_ops chv_pipe_power_well_ops = { 1916 .sync_hw = chv_pipe_power_well_sync_hw, 1917 .enable = chv_pipe_power_well_enable, 1918 .disable = chv_pipe_power_well_disable, 1919 .is_enabled = chv_pipe_power_well_enabled, 1920 }; 1921 1922 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1923 .sync_hw = i9xx_power_well_sync_hw_noop, 1924 .enable = chv_dpio_cmn_power_well_enable, 1925 .disable = chv_dpio_cmn_power_well_disable, 1926 .is_enabled = vlv_power_well_enabled, 1927 }; 1928 1929 const struct i915_power_well_ops i830_pipes_power_well_ops = { 1930 .sync_hw = i830_pipes_power_well_sync_hw, 1931 .enable = i830_pipes_power_well_enable, 1932 .disable = i830_pipes_power_well_disable, 1933 .is_enabled = i830_pipes_power_well_enabled, 1934 }; 1935 1936 static const struct i915_power_well_regs hsw_power_well_regs = { 1937 .bios = HSW_PWR_WELL_CTL1, 1938 .driver = HSW_PWR_WELL_CTL2, 1939 .kvmr = HSW_PWR_WELL_CTL3, 1940 .debug = HSW_PWR_WELL_CTL4, 1941 }; 1942 1943 const struct i915_power_well_ops hsw_power_well_ops = { 1944 .regs = &hsw_power_well_regs, 1945 .sync_hw = hsw_power_well_sync_hw, 1946 .enable = hsw_power_well_enable, 1947 .disable = hsw_power_well_disable, 1948 .is_enabled = hsw_power_well_enabled, 1949 }; 1950 1951 const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1952 .sync_hw = i9xx_power_well_sync_hw_noop, 1953 .enable = gen9_dc_off_power_well_enable, 1954 .disable = gen9_dc_off_power_well_disable, 1955 .is_enabled = gen9_dc_off_power_well_enabled, 1956 }; 1957 1958 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1959 .sync_hw = i9xx_power_well_sync_hw_noop, 1960 .enable = bxt_dpio_cmn_power_well_enable, 1961 .disable = bxt_dpio_cmn_power_well_disable, 1962 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1963 }; 1964 1965 const struct i915_power_well_ops vlv_display_power_well_ops = { 1966 .sync_hw = i9xx_power_well_sync_hw_noop, 1967 .enable = vlv_display_power_well_enable, 1968 .disable = vlv_display_power_well_disable, 1969 .is_enabled = vlv_power_well_enabled, 1970 }; 1971 1972 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1973 .sync_hw = i9xx_power_well_sync_hw_noop, 1974 .enable = vlv_dpio_cmn_power_well_enable, 1975 .disable = vlv_dpio_cmn_power_well_disable, 1976 .is_enabled = vlv_power_well_enabled, 1977 }; 1978 1979 const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1980 .sync_hw = i9xx_power_well_sync_hw_noop, 1981 .enable = vlv_power_well_enable, 1982 .disable = vlv_power_well_disable, 1983 .is_enabled = vlv_power_well_enabled, 1984 }; 1985 1986 static const struct i915_power_well_regs icl_aux_power_well_regs = { 1987 .bios = ICL_PWR_WELL_CTL_AUX1, 1988 .driver = ICL_PWR_WELL_CTL_AUX2, 1989 .debug = ICL_PWR_WELL_CTL_AUX4, 1990 }; 1991 1992 const struct i915_power_well_ops icl_aux_power_well_ops = { 1993 .regs = &icl_aux_power_well_regs, 1994 .sync_hw = hsw_power_well_sync_hw, 1995 .enable = icl_aux_power_well_enable, 1996 .disable = icl_aux_power_well_disable, 1997 .is_enabled = hsw_power_well_enabled, 1998 }; 1999 2000 static const struct i915_power_well_regs icl_ddi_power_well_regs = { 2001 .bios = ICL_PWR_WELL_CTL_DDI1, 2002 .driver = ICL_PWR_WELL_CTL_DDI2, 2003 .debug = ICL_PWR_WELL_CTL_DDI4, 2004 }; 2005 2006 const struct i915_power_well_ops icl_ddi_power_well_ops = { 2007 .regs = &icl_ddi_power_well_regs, 2008 .sync_hw = hsw_power_well_sync_hw, 2009 .enable = hsw_power_well_enable, 2010 .disable = hsw_power_well_disable, 2011 .is_enabled = hsw_power_well_enabled, 2012 }; 2013 2014 const struct i915_power_well_ops tgl_tc_cold_off_ops = { 2015 .sync_hw = tgl_tc_cold_off_power_well_sync_hw, 2016 .enable = tgl_tc_cold_off_power_well_enable, 2017 .disable = tgl_tc_cold_off_power_well_disable, 2018 .is_enabled = tgl_tc_cold_off_power_well_is_enabled, 2019 }; 2020 2021 const struct i915_power_well_ops xelpdp_aux_power_well_ops = { 2022 .sync_hw = i9xx_power_well_sync_hw_noop, 2023 .enable = xelpdp_aux_power_well_enable, 2024 .disable = xelpdp_aux_power_well_disable, 2025 .is_enabled = xelpdp_aux_power_well_enabled, 2026 }; 2027 2028 const struct i915_power_well_ops xe2lpd_pica_power_well_ops = { 2029 .sync_hw = i9xx_power_well_sync_hw_noop, 2030 .enable = xe2lpd_pica_power_well_enable, 2031 .disable = xe2lpd_pica_power_well_disable, 2032 .is_enabled = xe2lpd_pica_power_well_enabled, 2033 }; 2034