1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <linux/iopoll.h> 7 8 #include "i915_drv.h" 9 #include "i915_irq.h" 10 #include "i915_reg.h" 11 #include "intel_backlight_regs.h" 12 #include "intel_combo_phy.h" 13 #include "intel_combo_phy_regs.h" 14 #include "intel_crt.h" 15 #include "intel_de.h" 16 #include "intel_display_irq.h" 17 #include "intel_display_power_well.h" 18 #include "intel_display_regs.h" 19 #include "intel_display_rpm.h" 20 #include "intel_display_types.h" 21 #include "intel_dkl_phy.h" 22 #include "intel_dkl_phy_regs.h" 23 #include "intel_dmc.h" 24 #include "intel_dmc_wl.h" 25 #include "intel_dp_aux_regs.h" 26 #include "intel_dpio_phy.h" 27 #include "intel_dpll.h" 28 #include "intel_hotplug.h" 29 #include "intel_pcode.h" 30 #include "intel_pps.h" 31 #include "intel_psr.h" 32 #include "intel_tc.h" 33 #include "intel_vga.h" 34 #include "skl_watermark.h" 35 #include "vlv_dpio_phy_regs.h" 36 #include "vlv_iosf_sb_reg.h" 37 #include "vlv_sideband.h" 38 39 /* 40 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 41 * 42 * {ICL,SKL}_DISP_PW1_IDX..{ICL,SKL}_DISP_PW4_IDX -> PG1..PG4 43 */ 44 static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx) 45 { 46 int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1; 47 48 return pw_idx - pw1_idx + SKL_PG1; 49 } 50 51 struct i915_power_well_regs { 52 i915_reg_t bios; 53 i915_reg_t driver; 54 i915_reg_t kvmr; 55 i915_reg_t debug; 56 }; 57 58 struct i915_power_well_ops { 59 const struct i915_power_well_regs *regs; 60 /* 61 * Synchronize the well's hw state to match the current sw state, for 62 * example enable/disable it based on the current refcount. Called 63 * during driver init and resume time, possibly after first calling 64 * the enable/disable handlers. 65 */ 66 void (*sync_hw)(struct intel_display *display, 67 struct i915_power_well *power_well); 68 /* 69 * Enable the well and resources that depend on it (for example 70 * interrupts located on the well). Called after the 0->1 refcount 71 * transition. 72 */ 73 void (*enable)(struct intel_display *display, 74 struct i915_power_well *power_well); 75 /* 76 * Disable the well and resources that depend on it. Called after 77 * the 1->0 refcount transition. 78 */ 79 void (*disable)(struct intel_display *display, 80 struct i915_power_well *power_well); 81 /* Returns the hw enabled state. */ 82 bool (*is_enabled)(struct intel_display *display, 83 struct i915_power_well *power_well); 84 }; 85 86 static const struct i915_power_well_instance * 87 i915_power_well_instance(const struct i915_power_well *power_well) 88 { 89 return &power_well->desc->instances->list[power_well->instance_idx]; 90 } 91 92 struct i915_power_well * 93 lookup_power_well(struct intel_display *display, 94 enum i915_power_well_id power_well_id) 95 { 96 struct i915_power_well *power_well; 97 98 for_each_power_well(display, power_well) 99 if (i915_power_well_instance(power_well)->id == power_well_id) 100 return power_well; 101 102 /* 103 * It's not feasible to add error checking code to the callers since 104 * this condition really shouldn't happen and it doesn't even make sense 105 * to abort things like display initialization sequences. Just return 106 * the first power well and hope the WARN gets reported so we can fix 107 * our driver. 108 */ 109 drm_WARN(display->drm, 1, 110 "Power well %d not defined for this platform\n", 111 power_well_id); 112 return &display->power.domains.power_wells[0]; 113 } 114 115 void intel_power_well_enable(struct intel_display *display, 116 struct i915_power_well *power_well) 117 { 118 drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well)); 119 power_well->desc->ops->enable(display, power_well); 120 power_well->hw_enabled = true; 121 } 122 123 void intel_power_well_disable(struct intel_display *display, 124 struct i915_power_well *power_well) 125 { 126 drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well)); 127 power_well->hw_enabled = false; 128 power_well->desc->ops->disable(display, power_well); 129 } 130 131 void intel_power_well_sync_hw(struct intel_display *display, 132 struct i915_power_well *power_well) 133 { 134 power_well->desc->ops->sync_hw(display, power_well); 135 power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well); 136 } 137 138 void intel_power_well_get(struct intel_display *display, 139 struct i915_power_well *power_well) 140 { 141 if (!power_well->count++) 142 intel_power_well_enable(display, power_well); 143 } 144 145 void intel_power_well_put(struct intel_display *display, 146 struct i915_power_well *power_well) 147 { 148 drm_WARN(display->drm, !power_well->count, 149 "Use count on power well %s is already zero", 150 i915_power_well_instance(power_well)->name); 151 152 if (!--power_well->count) 153 intel_power_well_disable(display, power_well); 154 } 155 156 bool intel_power_well_is_enabled(struct intel_display *display, 157 struct i915_power_well *power_well) 158 { 159 return power_well->desc->ops->is_enabled(display, power_well); 160 } 161 162 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well) 163 { 164 return power_well->hw_enabled; 165 } 166 167 bool intel_display_power_well_is_enabled(struct intel_display *display, 168 enum i915_power_well_id power_well_id) 169 { 170 struct i915_power_well *power_well; 171 172 power_well = lookup_power_well(display, power_well_id); 173 174 return intel_power_well_is_enabled(display, power_well); 175 } 176 177 bool intel_power_well_is_always_on(struct i915_power_well *power_well) 178 { 179 return power_well->desc->always_on; 180 } 181 182 const char *intel_power_well_name(struct i915_power_well *power_well) 183 { 184 return i915_power_well_instance(power_well)->name; 185 } 186 187 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well) 188 { 189 return &power_well->domains; 190 } 191 192 int intel_power_well_refcount(struct i915_power_well *power_well) 193 { 194 return power_well->count; 195 } 196 197 /* 198 * Starting with Haswell, we have a "Power Down Well" that can be turned off 199 * when not needed anymore. We have 4 registers that can request the power well 200 * to be enabled, and it will only be disabled if none of the registers is 201 * requesting it to be enabled. 202 */ 203 static void hsw_power_well_post_enable(struct intel_display *display, 204 u8 irq_pipe_mask, bool has_vga) 205 { 206 if (has_vga) 207 intel_vga_reset_io_mem(display); 208 209 if (irq_pipe_mask) 210 gen8_irq_power_well_post_enable(display, irq_pipe_mask); 211 } 212 213 static void hsw_power_well_pre_disable(struct intel_display *display, 214 u8 irq_pipe_mask) 215 { 216 if (irq_pipe_mask) 217 gen8_irq_power_well_pre_disable(display, irq_pipe_mask); 218 } 219 220 #define ICL_AUX_PW_TO_PHY(pw_idx) \ 221 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + PHY_A) 222 223 #define ICL_AUX_PW_TO_CH(pw_idx) \ 224 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) 225 226 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ 227 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) 228 229 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well) 230 { 231 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 232 233 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : 234 ICL_AUX_PW_TO_CH(pw_idx); 235 } 236 237 static struct intel_digital_port * 238 aux_ch_to_digital_port(struct intel_display *display, 239 enum aux_ch aux_ch) 240 { 241 struct intel_encoder *encoder; 242 243 for_each_intel_encoder(display->drm, encoder) { 244 struct intel_digital_port *dig_port; 245 246 /* We'll check the MST primary port */ 247 if (encoder->type == INTEL_OUTPUT_DP_MST) 248 continue; 249 250 dig_port = enc_to_dig_port(encoder); 251 252 if (dig_port && dig_port->aux_ch == aux_ch) 253 return dig_port; 254 } 255 256 return NULL; 257 } 258 259 static enum phy icl_aux_pw_to_phy(struct intel_display *display, 260 const struct i915_power_well *power_well) 261 { 262 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 263 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 264 265 /* 266 * FIXME should we care about the (VBT defined) dig_port->aux_ch 267 * relationship or should this be purely defined by the hardware layout? 268 * Currently if the port doesn't appear in the VBT, or if it's declared 269 * as HDMI-only and routed to a combo PHY, the encoder either won't be 270 * present at all or it will not have an aux_ch assigned. 271 */ 272 return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE; 273 } 274 275 static void hsw_wait_for_power_well_enable(struct intel_display *display, 276 struct i915_power_well *power_well, 277 bool timeout_expected) 278 { 279 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 280 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 281 int timeout = power_well->desc->enable_timeout ? : 1; 282 283 /* 284 * For some power wells we're not supposed to watch the status bit for 285 * an ack, but rather just wait a fixed amount of time and then 286 * proceed. This is only used on DG2. 287 */ 288 if (display->platform.dg2 && power_well->desc->fixed_enable_delay) { 289 usleep_range(600, 1200); 290 return; 291 } 292 293 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 294 if (intel_de_wait_for_set(display, regs->driver, 295 HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) { 296 drm_dbg_kms(display->drm, "%s power well enable timeout\n", 297 intel_power_well_name(power_well)); 298 299 drm_WARN_ON(display->drm, !timeout_expected); 300 301 } 302 } 303 304 static u32 hsw_power_well_requesters(struct intel_display *display, 305 const struct i915_power_well_regs *regs, 306 int pw_idx) 307 { 308 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 309 u32 ret; 310 311 ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0; 312 ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0; 313 if (regs->kvmr.reg) 314 ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0; 315 ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0; 316 317 return ret; 318 } 319 320 static void hsw_wait_for_power_well_disable(struct intel_display *display, 321 struct i915_power_well *power_well) 322 { 323 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 324 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 325 u32 reqs; 326 int ret; 327 328 /* 329 * Bspec doesn't require waiting for PWs to get disabled, but still do 330 * this for paranoia. The known cases where a PW will be forced on: 331 * - a KVMR request on any power well via the KVMR request register 332 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 333 * DEBUG request registers 334 * Skip the wait in case any of the request bits are set and print a 335 * diagnostic message. 336 */ 337 reqs = hsw_power_well_requesters(display, regs, pw_idx); 338 339 ret = intel_de_wait_for_clear(display, regs->driver, 340 HSW_PWR_WELL_CTL_STATE(pw_idx), 341 reqs ? 0 : 1); 342 if (!ret) 343 return; 344 345 /* Refresh requesters in case they popped up during the wait. */ 346 if (!reqs) 347 reqs = hsw_power_well_requesters(display, regs, pw_idx); 348 349 drm_dbg_kms(display->drm, 350 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 351 intel_power_well_name(power_well), 352 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 353 } 354 355 static void gen9_wait_for_power_well_fuses(struct intel_display *display, 356 enum skl_power_gate pg) 357 { 358 /* Timeout 5us for PG#0, for other PGs 1us */ 359 drm_WARN_ON(display->drm, 360 intel_de_wait_for_set(display, SKL_FUSE_STATUS, 361 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 362 } 363 364 static void hsw_power_well_enable(struct intel_display *display, 365 struct i915_power_well *power_well) 366 { 367 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 368 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 369 370 if (power_well->desc->has_fuses) { 371 enum skl_power_gate pg; 372 373 pg = pw_idx_to_pg(display, pw_idx); 374 375 /* Wa_16013190616:adlp */ 376 if (display->platform.alderlake_p && pg == SKL_PG1) 377 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 378 379 /* 380 * For PW1 we have to wait both for the PW0/PG0 fuse state 381 * before enabling the power well and PW1/PG1's own fuse 382 * state after the enabling. For all other power wells with 383 * fuses we only have to wait for that PW/PG's fuse state 384 * after the enabling. 385 */ 386 if (pg == SKL_PG1) 387 gen9_wait_for_power_well_fuses(display, SKL_PG0); 388 } 389 390 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 391 392 hsw_wait_for_power_well_enable(display, power_well, false); 393 394 if (power_well->desc->has_fuses) { 395 enum skl_power_gate pg; 396 397 pg = pw_idx_to_pg(display, pw_idx); 398 399 gen9_wait_for_power_well_fuses(display, pg); 400 } 401 402 hsw_power_well_post_enable(display, 403 power_well->desc->irq_pipe_mask, 404 power_well->desc->has_vga); 405 } 406 407 static void hsw_power_well_disable(struct intel_display *display, 408 struct i915_power_well *power_well) 409 { 410 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 411 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 412 413 hsw_power_well_pre_disable(display, 414 power_well->desc->irq_pipe_mask); 415 416 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 417 hsw_wait_for_power_well_disable(display, power_well); 418 } 419 420 static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch) 421 { 422 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 423 424 return dig_port && dig_port->base.type == INTEL_OUTPUT_EDP; 425 } 426 427 static void 428 icl_combo_phy_aux_power_well_enable(struct intel_display *display, 429 struct i915_power_well *power_well) 430 { 431 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 432 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 433 434 drm_WARN_ON(display->drm, !display->platform.icelake); 435 436 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 437 438 /* 439 * FIXME not sure if we should derive the PHY from the pw_idx, or 440 * from the VBT defined AUX_CH->DDI->PHY mapping. 441 */ 442 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 443 0, ICL_LANE_ENABLE_AUX); 444 445 hsw_wait_for_power_well_enable(display, power_well, false); 446 447 /* Display WA #1178: icl */ 448 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && 449 !intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx))) 450 intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), 451 0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI); 452 } 453 454 static void 455 icl_combo_phy_aux_power_well_disable(struct intel_display *display, 456 struct i915_power_well *power_well) 457 { 458 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 459 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 460 461 drm_WARN_ON(display->drm, !display->platform.icelake); 462 463 /* 464 * FIXME not sure if we should derive the PHY from the pw_idx, or 465 * from the VBT defined AUX_CH->DDI->PHY mapping. 466 */ 467 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 468 ICL_LANE_ENABLE_AUX, 0); 469 470 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 471 472 hsw_wait_for_power_well_disable(display, power_well); 473 } 474 475 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 476 477 static void icl_tc_port_assert_ref_held(struct intel_display *display, 478 struct i915_power_well *power_well, 479 struct intel_digital_port *dig_port) 480 { 481 if (drm_WARN_ON(display->drm, !dig_port)) 482 return; 483 484 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 485 return; 486 487 drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port)); 488 } 489 490 #else 491 492 static void icl_tc_port_assert_ref_held(struct intel_display *display, 493 struct i915_power_well *power_well, 494 struct intel_digital_port *dig_port) 495 { 496 } 497 498 #endif 499 500 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1) 501 502 static void icl_tc_cold_exit(struct intel_display *display) 503 { 504 int ret, tries = 0; 505 506 while (1) { 507 ret = intel_pcode_write(display->drm, ICL_PCODE_EXIT_TCCOLD, 0); 508 if (ret != -EAGAIN || ++tries == 3) 509 break; 510 msleep(1); 511 } 512 513 /* Spec states that TC cold exit can take up to 1ms to complete */ 514 if (!ret) 515 msleep(1); 516 517 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */ 518 drm_dbg_kms(display->drm, "TC cold block %s\n", ret ? "failed" : 519 "succeeded"); 520 } 521 522 static void 523 icl_tc_phy_aux_power_well_enable(struct intel_display *display, 524 struct i915_power_well *power_well) 525 { 526 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 527 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 528 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 529 bool is_tbt = power_well->desc->is_tc_tbt; 530 bool timeout_expected; 531 u32 val; 532 int ret; 533 534 icl_tc_port_assert_ref_held(display, power_well, dig_port); 535 536 intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), 537 DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0); 538 539 intel_de_rmw(display, regs->driver, 540 0, 541 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); 542 543 /* 544 * An AUX timeout is expected if the TBT DP tunnel is down, 545 * or need to enable AUX on a legacy TypeC port as part of the TC-cold 546 * exit sequence. 547 */ 548 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port); 549 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 550 icl_tc_cold_exit(display); 551 552 hsw_wait_for_power_well_enable(display, power_well, timeout_expected); 553 554 if (DISPLAY_VER(display) >= 12 && !is_tbt) { 555 enum tc_port tc_port; 556 557 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); 558 559 ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)), 560 val & DKL_CMN_UC_DW27_UC_HEALTH, 561 100, 1000, false); 562 if (ret) 563 drm_warn(display->drm, "Timeout waiting TC uC health\n"); 564 } 565 } 566 567 static void 568 icl_aux_power_well_enable(struct intel_display *display, 569 struct i915_power_well *power_well) 570 { 571 enum phy phy = icl_aux_pw_to_phy(display, power_well); 572 573 if (intel_phy_is_tc(display, phy)) 574 return icl_tc_phy_aux_power_well_enable(display, power_well); 575 else if (display->platform.icelake) 576 return icl_combo_phy_aux_power_well_enable(display, 577 power_well); 578 else 579 return hsw_power_well_enable(display, power_well); 580 } 581 582 static void 583 icl_aux_power_well_disable(struct intel_display *display, 584 struct i915_power_well *power_well) 585 { 586 enum phy phy = icl_aux_pw_to_phy(display, power_well); 587 588 if (intel_phy_is_tc(display, phy)) 589 return hsw_power_well_disable(display, power_well); 590 else if (display->platform.icelake) 591 return icl_combo_phy_aux_power_well_disable(display, 592 power_well); 593 else 594 return hsw_power_well_disable(display, power_well); 595 } 596 597 /* 598 * We should only use the power well if we explicitly asked the hardware to 599 * enable it, so check if it's enabled and also check if we've requested it to 600 * be enabled. 601 */ 602 static bool hsw_power_well_enabled(struct intel_display *display, 603 struct i915_power_well *power_well) 604 { 605 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 606 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 607 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 608 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | 609 HSW_PWR_WELL_CTL_STATE(pw_idx); 610 u32 val; 611 612 val = intel_de_read(display, regs->driver); 613 614 /* 615 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 616 * and the MISC_IO PW will be not restored, so check instead for the 617 * BIOS's own request bits, which are forced-on for these power wells 618 * when exiting DC5/6. 619 */ 620 if (DISPLAY_VER(display) == 9 && !display->platform.broxton && 621 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 622 val |= intel_de_read(display, regs->bios); 623 624 return (val & mask) == mask; 625 } 626 627 static void assert_can_enable_dc9(struct intel_display *display) 628 { 629 struct drm_i915_private *dev_priv = to_i915(display->drm); 630 631 drm_WARN_ONCE(display->drm, 632 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), 633 "DC9 already programmed to be enabled.\n"); 634 drm_WARN_ONCE(display->drm, 635 intel_de_read(display, DC_STATE_EN) & 636 DC_STATE_EN_UPTO_DC5, 637 "DC5 still not disabled to enable DC9.\n"); 638 drm_WARN_ONCE(display->drm, 639 intel_de_read(display, HSW_PWR_WELL_CTL2) & 640 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 641 "Power well 2 on.\n"); 642 drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), 643 "Interrupts not disabled yet.\n"); 644 645 /* 646 * TODO: check for the following to verify the conditions to enter DC9 647 * state are satisfied: 648 * 1] Check relevant display engine registers to verify if mode set 649 * disable sequence was followed. 650 * 2] Check if display uninitialize sequence is initialized. 651 */ 652 } 653 654 static void assert_can_disable_dc9(struct intel_display *display) 655 { 656 struct drm_i915_private *dev_priv = to_i915(display->drm); 657 658 drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), 659 "Interrupts not disabled yet.\n"); 660 drm_WARN_ONCE(display->drm, 661 intel_de_read(display, DC_STATE_EN) & 662 DC_STATE_EN_UPTO_DC5, 663 "DC5 still not disabled.\n"); 664 665 /* 666 * TODO: check for the following to verify DC9 state was indeed 667 * entered before programming to disable it: 668 * 1] Check relevant display engine registers to verify if mode 669 * set disable sequence was followed. 670 * 2] Check if display uninitialize sequence is initialized. 671 */ 672 } 673 674 static void gen9_write_dc_state(struct intel_display *display, 675 u32 state) 676 { 677 int rewrites = 0; 678 int rereads = 0; 679 u32 v; 680 681 intel_de_write(display, DC_STATE_EN, state); 682 683 /* It has been observed that disabling the dc6 state sometimes 684 * doesn't stick and dmc keeps returning old value. Make sure 685 * the write really sticks enough times and also force rewrite until 686 * we are confident that state is exactly what we want. 687 */ 688 do { 689 v = intel_de_read(display, DC_STATE_EN); 690 691 if (v != state) { 692 intel_de_write(display, DC_STATE_EN, state); 693 rewrites++; 694 rereads = 0; 695 } else if (rereads++ > 5) { 696 break; 697 } 698 699 } while (rewrites < 100); 700 701 if (v != state) 702 drm_err(display->drm, 703 "Writing dc state to 0x%x failed, now 0x%x\n", 704 state, v); 705 706 /* Most of the times we need one retry, avoid spam */ 707 if (rewrites > 1) 708 drm_dbg_kms(display->drm, 709 "Rewrote dc state to 0x%x %d times\n", 710 state, rewrites); 711 } 712 713 static u32 gen9_dc_mask(struct intel_display *display) 714 { 715 u32 mask; 716 717 mask = DC_STATE_EN_UPTO_DC5; 718 719 if (DISPLAY_VER(display) >= 12) 720 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 721 | DC_STATE_EN_DC9; 722 else if (DISPLAY_VER(display) == 11) 723 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; 724 else if (display->platform.geminilake || display->platform.broxton) 725 mask |= DC_STATE_EN_DC9; 726 else 727 mask |= DC_STATE_EN_UPTO_DC6; 728 729 return mask; 730 } 731 732 void gen9_sanitize_dc_state(struct intel_display *display) 733 { 734 struct i915_power_domains *power_domains = &display->power.domains; 735 u32 val; 736 737 if (!HAS_DISPLAY(display)) 738 return; 739 740 val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display); 741 742 drm_dbg_kms(display->drm, 743 "Resetting DC state tracking from %02x to %02x\n", 744 power_domains->dc_state, val); 745 power_domains->dc_state = val; 746 } 747 748 /** 749 * gen9_set_dc_state - set target display C power state 750 * @display: display instance 751 * @state: target DC power state 752 * - DC_STATE_DISABLE 753 * - DC_STATE_EN_UPTO_DC5 754 * - DC_STATE_EN_UPTO_DC6 755 * - DC_STATE_EN_DC9 756 * 757 * Signal to DMC firmware/HW the target DC power state passed in @state. 758 * DMC/HW can turn off individual display clocks and power rails when entering 759 * a deeper DC power state (higher in number) and turns these back when exiting 760 * that state to a shallower power state (lower in number). The HW will decide 761 * when to actually enter a given state on an on-demand basis, for instance 762 * depending on the active state of display pipes. The state of display 763 * registers backed by affected power rails are saved/restored as needed. 764 * 765 * Based on the above enabling a deeper DC power state is asynchronous wrt. 766 * enabling it. Disabling a deeper power state is synchronous: for instance 767 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 768 * back on and register state is restored. This is guaranteed by the MMIO write 769 * to DC_STATE_EN blocking until the state is restored. 770 */ 771 void gen9_set_dc_state(struct intel_display *display, u32 state) 772 { 773 struct i915_power_domains *power_domains = &display->power.domains; 774 bool dc6_was_enabled, enable_dc6; 775 u32 mask; 776 u32 val; 777 778 if (!HAS_DISPLAY(display)) 779 return; 780 781 if (drm_WARN_ON_ONCE(display->drm, 782 state & ~power_domains->allowed_dc_mask)) 783 state &= power_domains->allowed_dc_mask; 784 785 if (!power_domains->initializing) 786 intel_psr_notify_dc5_dc6(display); 787 788 val = intel_de_read(display, DC_STATE_EN); 789 mask = gen9_dc_mask(display); 790 drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", 791 val & mask, state); 792 793 /* Check if DMC is ignoring our DC state requests */ 794 if ((val & mask) != power_domains->dc_state) 795 drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n", 796 power_domains->dc_state, val & mask); 797 798 enable_dc6 = state & DC_STATE_EN_UPTO_DC6; 799 dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6; 800 if (!dc6_was_enabled && enable_dc6) 801 intel_dmc_update_dc6_allowed_count(display, true); 802 803 val &= ~mask; 804 val |= state; 805 806 gen9_write_dc_state(display, val); 807 808 if (!enable_dc6 && dc6_was_enabled) 809 intel_dmc_update_dc6_allowed_count(display, false); 810 811 power_domains->dc_state = val & mask; 812 } 813 814 static void tgl_enable_dc3co(struct intel_display *display) 815 { 816 drm_dbg_kms(display->drm, "Enabling DC3CO\n"); 817 gen9_set_dc_state(display, DC_STATE_EN_DC3CO); 818 } 819 820 static void tgl_disable_dc3co(struct intel_display *display) 821 { 822 drm_dbg_kms(display->drm, "Disabling DC3CO\n"); 823 intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); 824 gen9_set_dc_state(display, DC_STATE_DISABLE); 825 /* 826 * Delay of 200us DC3CO Exit time B.Spec 49196 827 */ 828 usleep_range(200, 210); 829 } 830 831 static void assert_can_enable_dc5(struct intel_display *display) 832 { 833 enum i915_power_well_id high_pg; 834 835 /* Power wells at this level and above must be disabled for DC5 entry */ 836 if (DISPLAY_VER(display) == 12) 837 high_pg = ICL_DISP_PW_3; 838 else 839 high_pg = SKL_DISP_PW_2; 840 841 drm_WARN_ONCE(display->drm, 842 intel_display_power_well_is_enabled(display, high_pg), 843 "Power wells above platform's DC5 limit still enabled.\n"); 844 845 drm_WARN_ONCE(display->drm, 846 (intel_de_read(display, DC_STATE_EN) & 847 DC_STATE_EN_UPTO_DC5), 848 "DC5 already programmed to be enabled.\n"); 849 850 assert_display_rpm_held(display); 851 852 assert_main_dmc_loaded(display); 853 } 854 855 void gen9_enable_dc5(struct intel_display *display) 856 { 857 assert_can_enable_dc5(display); 858 859 drm_dbg_kms(display->drm, "Enabling DC5\n"); 860 861 /* Wa Display #1183: skl,kbl,cfl */ 862 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 863 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 864 0, SKL_SELECT_ALTERNATE_DC_EXIT); 865 866 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5); 867 868 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); 869 } 870 871 static void assert_can_enable_dc6(struct intel_display *display) 872 { 873 drm_WARN_ONCE(display->drm, 874 (intel_de_read(display, UTIL_PIN_CTL) & 875 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == 876 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 877 "Utility pin enabled in PWM mode\n"); 878 drm_WARN_ONCE(display->drm, 879 (intel_de_read(display, DC_STATE_EN) & 880 DC_STATE_EN_UPTO_DC6), 881 "DC6 already programmed to be enabled.\n"); 882 883 assert_main_dmc_loaded(display); 884 } 885 886 void skl_enable_dc6(struct intel_display *display) 887 { 888 assert_can_enable_dc6(display); 889 890 drm_dbg_kms(display->drm, "Enabling DC6\n"); 891 892 /* Wa Display #1183: skl,kbl,cfl */ 893 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 894 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 895 0, SKL_SELECT_ALTERNATE_DC_EXIT); 896 897 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6); 898 899 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); 900 } 901 902 void bxt_enable_dc9(struct intel_display *display) 903 { 904 assert_can_enable_dc9(display); 905 906 drm_dbg_kms(display->drm, "Enabling DC9\n"); 907 /* 908 * Power sequencer reset is needed on BXT/GLK, because the PPS registers 909 * aren't always on, unlike with South Display Engine on PCH. 910 */ 911 if (display->platform.broxton || display->platform.geminilake) 912 bxt_pps_reset_all(display); 913 gen9_set_dc_state(display, DC_STATE_EN_DC9); 914 } 915 916 void bxt_disable_dc9(struct intel_display *display) 917 { 918 assert_can_disable_dc9(display); 919 920 drm_dbg_kms(display->drm, "Disabling DC9\n"); 921 922 gen9_set_dc_state(display, DC_STATE_DISABLE); 923 924 intel_pps_unlock_regs_wa(display); 925 } 926 927 static void hsw_power_well_sync_hw(struct intel_display *display, 928 struct i915_power_well *power_well) 929 { 930 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 931 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 932 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 933 u32 bios_req = intel_de_read(display, regs->bios); 934 935 /* Take over the request bit if set by BIOS. */ 936 if (bios_req & mask) { 937 u32 drv_req = intel_de_read(display, regs->driver); 938 939 if (!(drv_req & mask)) 940 intel_de_write(display, regs->driver, drv_req | mask); 941 intel_de_write(display, regs->bios, bios_req & ~mask); 942 } 943 } 944 945 static void bxt_dpio_cmn_power_well_enable(struct intel_display *display, 946 struct i915_power_well *power_well) 947 { 948 bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy); 949 } 950 951 static void bxt_dpio_cmn_power_well_disable(struct intel_display *display, 952 struct i915_power_well *power_well) 953 { 954 bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy); 955 } 956 957 static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display, 958 struct i915_power_well *power_well) 959 { 960 return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy); 961 } 962 963 static void bxt_verify_dpio_phy_power_wells(struct intel_display *display) 964 { 965 struct i915_power_well *power_well; 966 967 power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A); 968 if (intel_power_well_refcount(power_well) > 0) 969 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 970 971 power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 972 if (intel_power_well_refcount(power_well) > 0) 973 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 974 975 if (display->platform.geminilake) { 976 power_well = lookup_power_well(display, 977 GLK_DISP_PW_DPIO_CMN_C); 978 if (intel_power_well_refcount(power_well) > 0) 979 bxt_dpio_phy_verify_state(display, 980 i915_power_well_instance(power_well)->bxt.phy); 981 } 982 } 983 984 static bool gen9_dc_off_power_well_enabled(struct intel_display *display, 985 struct i915_power_well *power_well) 986 { 987 return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && 988 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); 989 } 990 991 static void gen9_assert_dbuf_enabled(struct intel_display *display) 992 { 993 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display); 994 u8 enabled_dbuf_slices = display->dbuf.enabled_slices; 995 996 drm_WARN(display->drm, 997 hw_enabled_dbuf_slices != enabled_dbuf_slices, 998 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 999 hw_enabled_dbuf_slices, 1000 enabled_dbuf_slices); 1001 } 1002 1003 void gen9_disable_dc_states(struct intel_display *display) 1004 { 1005 struct i915_power_domains *power_domains = &display->power.domains; 1006 struct intel_cdclk_config cdclk_config = {}; 1007 u32 old_state = power_domains->dc_state; 1008 1009 if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { 1010 tgl_disable_dc3co(display); 1011 return; 1012 } 1013 1014 if (HAS_DISPLAY(display)) { 1015 intel_dmc_wl_get_noreg(display); 1016 gen9_set_dc_state(display, DC_STATE_DISABLE); 1017 intel_dmc_wl_put_noreg(display); 1018 } else { 1019 gen9_set_dc_state(display, DC_STATE_DISABLE); 1020 return; 1021 } 1022 1023 if (old_state == DC_STATE_EN_UPTO_DC5 || 1024 old_state == DC_STATE_EN_UPTO_DC6) 1025 intel_dmc_wl_disable(display); 1026 1027 intel_cdclk_get_cdclk(display, &cdclk_config); 1028 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 1029 drm_WARN_ON(display->drm, 1030 intel_cdclk_clock_changed(&display->cdclk.hw, 1031 &cdclk_config)); 1032 1033 gen9_assert_dbuf_enabled(display); 1034 1035 if (display->platform.geminilake || display->platform.broxton) 1036 bxt_verify_dpio_phy_power_wells(display); 1037 1038 if (DISPLAY_VER(display) >= 11) 1039 /* 1040 * DMC retains HW context only for port A, the other combo 1041 * PHY's HW context for port B is lost after DC transitions, 1042 * so we need to restore it manually. 1043 */ 1044 intel_combo_phy_init(display); 1045 } 1046 1047 static void gen9_dc_off_power_well_enable(struct intel_display *display, 1048 struct i915_power_well *power_well) 1049 { 1050 gen9_disable_dc_states(display); 1051 } 1052 1053 static void gen9_dc_off_power_well_disable(struct intel_display *display, 1054 struct i915_power_well *power_well) 1055 { 1056 struct i915_power_domains *power_domains = &display->power.domains; 1057 1058 if (!intel_dmc_has_payload(display)) 1059 return; 1060 1061 switch (power_domains->target_dc_state) { 1062 case DC_STATE_EN_DC3CO: 1063 tgl_enable_dc3co(display); 1064 break; 1065 case DC_STATE_EN_UPTO_DC6: 1066 skl_enable_dc6(display); 1067 break; 1068 case DC_STATE_EN_UPTO_DC5: 1069 gen9_enable_dc5(display); 1070 break; 1071 } 1072 } 1073 1074 static void i9xx_power_well_sync_hw_noop(struct intel_display *display, 1075 struct i915_power_well *power_well) 1076 { 1077 } 1078 1079 static void i9xx_always_on_power_well_noop(struct intel_display *display, 1080 struct i915_power_well *power_well) 1081 { 1082 } 1083 1084 static bool i9xx_always_on_power_well_enabled(struct intel_display *display, 1085 struct i915_power_well *power_well) 1086 { 1087 return true; 1088 } 1089 1090 static void i830_pipes_power_well_enable(struct intel_display *display, 1091 struct i915_power_well *power_well) 1092 { 1093 if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) 1094 i830_enable_pipe(display, PIPE_A); 1095 if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0) 1096 i830_enable_pipe(display, PIPE_B); 1097 } 1098 1099 static void i830_pipes_power_well_disable(struct intel_display *display, 1100 struct i915_power_well *power_well) 1101 { 1102 i830_disable_pipe(display, PIPE_B); 1103 i830_disable_pipe(display, PIPE_A); 1104 } 1105 1106 static bool i830_pipes_power_well_enabled(struct intel_display *display, 1107 struct i915_power_well *power_well) 1108 { 1109 return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && 1110 intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; 1111 } 1112 1113 static void i830_pipes_power_well_sync_hw(struct intel_display *display, 1114 struct i915_power_well *power_well) 1115 { 1116 if (intel_power_well_refcount(power_well) > 0) 1117 i830_pipes_power_well_enable(display, power_well); 1118 else 1119 i830_pipes_power_well_disable(display, power_well); 1120 } 1121 1122 static void vlv_set_power_well(struct intel_display *display, 1123 struct i915_power_well *power_well, bool enable) 1124 { 1125 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1126 u32 mask; 1127 u32 state; 1128 u32 ctrl; 1129 u32 val; 1130 int ret; 1131 1132 mask = PUNIT_PWRGT_MASK(pw_idx); 1133 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : 1134 PUNIT_PWRGT_PWR_GATE(pw_idx); 1135 1136 vlv_punit_get(display->drm); 1137 1138 val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS); 1139 if ((val & mask) == state) 1140 goto out; 1141 1142 ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL); 1143 ctrl &= ~mask; 1144 ctrl |= state; 1145 vlv_punit_write(display->drm, PUNIT_REG_PWRGT_CTRL, ctrl); 1146 1147 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS), 1148 (val & mask) == state, 1149 500, 100 * 1000, false); 1150 if (ret) 1151 drm_err(display->drm, 1152 "timeout setting power well state %08x (%08x)\n", 1153 state, 1154 vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL)); 1155 1156 out: 1157 vlv_punit_put(display->drm); 1158 } 1159 1160 static void vlv_power_well_enable(struct intel_display *display, 1161 struct i915_power_well *power_well) 1162 { 1163 vlv_set_power_well(display, power_well, true); 1164 } 1165 1166 static void vlv_power_well_disable(struct intel_display *display, 1167 struct i915_power_well *power_well) 1168 { 1169 vlv_set_power_well(display, power_well, false); 1170 } 1171 1172 static bool vlv_power_well_enabled(struct intel_display *display, 1173 struct i915_power_well *power_well) 1174 { 1175 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1176 bool enabled = false; 1177 u32 mask; 1178 u32 state; 1179 u32 ctrl; 1180 1181 mask = PUNIT_PWRGT_MASK(pw_idx); 1182 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); 1183 1184 vlv_punit_get(display->drm); 1185 1186 state = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask; 1187 /* 1188 * We only ever set the power-on and power-gate states, anything 1189 * else is unexpected. 1190 */ 1191 drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1192 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 1193 if (state == ctrl) 1194 enabled = true; 1195 1196 /* 1197 * A transient state at this point would mean some unexpected party 1198 * is poking at the power controls too. 1199 */ 1200 ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL) & mask; 1201 drm_WARN_ON(display->drm, ctrl != state); 1202 1203 vlv_punit_put(display->drm); 1204 1205 return enabled; 1206 } 1207 1208 static void vlv_init_display_clock_gating(struct intel_display *display) 1209 { 1210 /* 1211 * On driver load, a pipe may be active and driving a DSI display. 1212 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1213 * (and never recovering) in this case. intel_dsi_post_disable() will 1214 * clear it when we turn off the display. 1215 */ 1216 intel_de_rmw(display, VLV_DSPCLK_GATE_D, 1217 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE); 1218 1219 /* 1220 * Disable trickle feed and enable pnd deadline calculation 1221 */ 1222 intel_de_write(display, MI_ARB_VLV, 1223 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1224 intel_de_write(display, CBR1_VLV, 0); 1225 1226 drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0); 1227 intel_de_write(display, RAWCLK_FREQ_VLV, 1228 DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 1229 1000)); 1230 } 1231 1232 static void vlv_display_power_well_init(struct intel_display *display) 1233 { 1234 struct intel_encoder *encoder; 1235 enum pipe pipe; 1236 1237 /* 1238 * Enable the CRI clock source so we can get at the 1239 * display and the reference clock for VGA 1240 * hotplug / manual detection. Supposedly DSI also 1241 * needs the ref clock up and running. 1242 * 1243 * CHV DPLL B/C have some issues if VGA mode is enabled. 1244 */ 1245 for_each_pipe(display, pipe) { 1246 u32 val = intel_de_read(display, DPLL(display, pipe)); 1247 1248 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1249 if (pipe != PIPE_A) 1250 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1251 1252 intel_de_write(display, DPLL(display, pipe), val); 1253 } 1254 1255 vlv_init_display_clock_gating(display); 1256 1257 valleyview_enable_display_irqs(display); 1258 1259 /* 1260 * During driver initialization/resume we can avoid restoring the 1261 * part of the HW/SW state that will be inited anyway explicitly. 1262 */ 1263 if (display->power.domains.initializing) 1264 return; 1265 1266 intel_hpd_init(display); 1267 intel_hpd_poll_disable(display); 1268 1269 /* Re-enable the ADPA, if we have one */ 1270 for_each_intel_encoder(display->drm, encoder) { 1271 if (encoder->type == INTEL_OUTPUT_ANALOG) 1272 intel_crt_reset(&encoder->base); 1273 } 1274 1275 intel_vga_disable(display); 1276 1277 intel_pps_unlock_regs_wa(display); 1278 } 1279 1280 static void vlv_display_power_well_deinit(struct intel_display *display) 1281 { 1282 struct drm_i915_private *dev_priv = to_i915(display->drm); 1283 1284 valleyview_disable_display_irqs(display); 1285 1286 /* make sure we're done processing display irqs */ 1287 intel_synchronize_irq(dev_priv); 1288 1289 vlv_pps_reset_all(display); 1290 1291 /* Prevent us from re-enabling polling on accident in late suspend */ 1292 if (!display->drm->dev->power.is_suspended) 1293 intel_hpd_poll_enable(display); 1294 } 1295 1296 static void vlv_display_power_well_enable(struct intel_display *display, 1297 struct i915_power_well *power_well) 1298 { 1299 vlv_set_power_well(display, power_well, true); 1300 1301 vlv_display_power_well_init(display); 1302 } 1303 1304 static void vlv_display_power_well_disable(struct intel_display *display, 1305 struct i915_power_well *power_well) 1306 { 1307 vlv_display_power_well_deinit(display); 1308 1309 vlv_set_power_well(display, power_well, false); 1310 } 1311 1312 static void vlv_dpio_cmn_power_well_enable(struct intel_display *display, 1313 struct i915_power_well *power_well) 1314 { 1315 /* since ref/cri clock was enabled */ 1316 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1317 1318 vlv_set_power_well(display, power_well, true); 1319 1320 /* 1321 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1322 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1323 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1324 * b. The other bits such as sfr settings / modesel may all 1325 * be set to 0. 1326 * 1327 * This should only be done on init and resume from S3 with 1328 * both PLLs disabled, or we risk losing DPIO and PLL 1329 * synchronization. 1330 */ 1331 intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST); 1332 } 1333 1334 static void vlv_dpio_cmn_power_well_disable(struct intel_display *display, 1335 struct i915_power_well *power_well) 1336 { 1337 enum pipe pipe; 1338 1339 for_each_pipe(display, pipe) 1340 assert_pll_disabled(display, pipe); 1341 1342 /* Assert common reset */ 1343 intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); 1344 1345 vlv_set_power_well(display, power_well, false); 1346 } 1347 1348 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1349 1350 static void assert_chv_phy_status(struct intel_display *display) 1351 { 1352 struct i915_power_well *cmn_bc = 1353 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1354 struct i915_power_well *cmn_d = 1355 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1356 u32 phy_control = display->power.chv_phy_control; 1357 u32 phy_status = 0; 1358 u32 phy_status_mask = 0xffffffff; 1359 1360 /* 1361 * The BIOS can leave the PHY is some weird state 1362 * where it doesn't fully power down some parts. 1363 * Disable the asserts until the PHY has been fully 1364 * reset (ie. the power well has been disabled at 1365 * least once). 1366 */ 1367 if (!display->power.chv_phy_assert[DPIO_PHY0]) 1368 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1369 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1370 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1371 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1372 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1373 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1374 1375 if (!display->power.chv_phy_assert[DPIO_PHY1]) 1376 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1377 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1378 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1379 1380 if (intel_power_well_is_enabled(display, cmn_bc)) { 1381 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1382 1383 /* this assumes override is only used to enable lanes */ 1384 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1385 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1386 1387 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1388 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1389 1390 /* CL1 is on whenever anything is on in either channel */ 1391 if (BITS_SET(phy_control, 1392 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1393 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1394 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1395 1396 /* 1397 * The DPLLB check accounts for the pipe B + port A usage 1398 * with CL2 powered up but all the lanes in the second channel 1399 * powered down. 1400 */ 1401 if (BITS_SET(phy_control, 1402 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1403 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1404 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1405 1406 if (BITS_SET(phy_control, 1407 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1408 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1409 if (BITS_SET(phy_control, 1410 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1411 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1412 1413 if (BITS_SET(phy_control, 1414 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1415 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1416 if (BITS_SET(phy_control, 1417 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1418 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1419 } 1420 1421 if (intel_power_well_is_enabled(display, cmn_d)) { 1422 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1423 1424 /* this assumes override is only used to enable lanes */ 1425 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1426 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1427 1428 if (BITS_SET(phy_control, 1429 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1430 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1431 1432 if (BITS_SET(phy_control, 1433 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1434 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1435 if (BITS_SET(phy_control, 1436 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1437 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1438 } 1439 1440 phy_status &= phy_status_mask; 1441 1442 /* 1443 * The PHY may be busy with some initial calibration and whatnot, 1444 * so the power state can take a while to actually change. 1445 */ 1446 if (intel_de_wait(display, DISPLAY_PHY_STATUS, 1447 phy_status_mask, phy_status, 10)) 1448 drm_err(display->drm, 1449 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1450 intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask, 1451 phy_status, display->power.chv_phy_control); 1452 } 1453 1454 #undef BITS_SET 1455 1456 static void chv_dpio_cmn_power_well_enable(struct intel_display *display, 1457 struct i915_power_well *power_well) 1458 { 1459 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1460 enum dpio_phy phy; 1461 u32 tmp; 1462 1463 drm_WARN_ON_ONCE(display->drm, 1464 id != VLV_DISP_PW_DPIO_CMN_BC && 1465 id != CHV_DISP_PW_DPIO_CMN_D); 1466 1467 if (id == VLV_DISP_PW_DPIO_CMN_BC) 1468 phy = DPIO_PHY0; 1469 else 1470 phy = DPIO_PHY1; 1471 1472 /* since ref/cri clock was enabled */ 1473 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1474 vlv_set_power_well(display, power_well, true); 1475 1476 /* Poll for phypwrgood signal */ 1477 if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS, 1478 PHY_POWERGOOD(phy), 1)) 1479 drm_err(display->drm, "Display PHY %d is not power up\n", 1480 phy); 1481 1482 vlv_dpio_get(display->drm); 1483 1484 /* Enable dynamic power down */ 1485 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW28); 1486 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1487 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1488 vlv_dpio_write(display->drm, phy, CHV_CMN_DW28, tmp); 1489 1490 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1491 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW6_CH1); 1492 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1493 vlv_dpio_write(display->drm, phy, CHV_CMN_DW6_CH1, tmp); 1494 } else { 1495 /* 1496 * Force the non-existing CL2 off. BXT does this 1497 * too, so maybe it saves some power even though 1498 * CL2 doesn't exist? 1499 */ 1500 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW30); 1501 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1502 vlv_dpio_write(display->drm, phy, CHV_CMN_DW30, tmp); 1503 } 1504 1505 vlv_dpio_put(display->drm); 1506 1507 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1508 intel_de_write(display, DISPLAY_PHY_CONTROL, 1509 display->power.chv_phy_control); 1510 1511 drm_dbg_kms(display->drm, 1512 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1513 phy, display->power.chv_phy_control); 1514 1515 assert_chv_phy_status(display); 1516 } 1517 1518 static void chv_dpio_cmn_power_well_disable(struct intel_display *display, 1519 struct i915_power_well *power_well) 1520 { 1521 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1522 enum dpio_phy phy; 1523 1524 drm_WARN_ON_ONCE(display->drm, 1525 id != VLV_DISP_PW_DPIO_CMN_BC && 1526 id != CHV_DISP_PW_DPIO_CMN_D); 1527 1528 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1529 phy = DPIO_PHY0; 1530 assert_pll_disabled(display, PIPE_A); 1531 assert_pll_disabled(display, PIPE_B); 1532 } else { 1533 phy = DPIO_PHY1; 1534 assert_pll_disabled(display, PIPE_C); 1535 } 1536 1537 display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1538 intel_de_write(display, DISPLAY_PHY_CONTROL, 1539 display->power.chv_phy_control); 1540 1541 vlv_set_power_well(display, power_well, false); 1542 1543 drm_dbg_kms(display->drm, 1544 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1545 phy, display->power.chv_phy_control); 1546 1547 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1548 display->power.chv_phy_assert[phy] = true; 1549 1550 assert_chv_phy_status(display); 1551 } 1552 1553 static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy, 1554 enum dpio_channel ch, bool override, unsigned int mask) 1555 { 1556 u32 reg, val, expected, actual; 1557 1558 /* 1559 * The BIOS can leave the PHY is some weird state 1560 * where it doesn't fully power down some parts. 1561 * Disable the asserts until the PHY has been fully 1562 * reset (ie. the power well has been disabled at 1563 * least once). 1564 */ 1565 if (!display->power.chv_phy_assert[phy]) 1566 return; 1567 1568 if (ch == DPIO_CH0) 1569 reg = CHV_CMN_DW0_CH0; 1570 else 1571 reg = CHV_CMN_DW6_CH1; 1572 1573 vlv_dpio_get(display->drm); 1574 val = vlv_dpio_read(display->drm, phy, reg); 1575 vlv_dpio_put(display->drm); 1576 1577 /* 1578 * This assumes !override is only used when the port is disabled. 1579 * All lanes should power down even without the override when 1580 * the port is disabled. 1581 */ 1582 if (!override || mask == 0xf) { 1583 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1584 /* 1585 * If CH1 common lane is not active anymore 1586 * (eg. for pipe B DPLL) the entire channel will 1587 * shut down, which causes the common lane registers 1588 * to read as 0. That means we can't actually check 1589 * the lane power down status bits, but as the entire 1590 * register reads as 0 it's a good indication that the 1591 * channel is indeed entirely powered down. 1592 */ 1593 if (ch == DPIO_CH1 && val == 0) 1594 expected = 0; 1595 } else if (mask != 0x0) { 1596 expected = DPIO_ANYDL_POWERDOWN; 1597 } else { 1598 expected = 0; 1599 } 1600 1601 if (ch == DPIO_CH0) 1602 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 | 1603 DPIO_ALLDL_POWERDOWN_CH0, val); 1604 else 1605 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 | 1606 DPIO_ALLDL_POWERDOWN_CH1, val); 1607 1608 drm_WARN(display->drm, actual != expected, 1609 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1610 !!(actual & DPIO_ALLDL_POWERDOWN), 1611 !!(actual & DPIO_ANYDL_POWERDOWN), 1612 !!(expected & DPIO_ALLDL_POWERDOWN), 1613 !!(expected & DPIO_ANYDL_POWERDOWN), 1614 reg, val); 1615 } 1616 1617 bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy, 1618 enum dpio_channel ch, bool override) 1619 { 1620 struct i915_power_domains *power_domains = &display->power.domains; 1621 bool was_override; 1622 1623 mutex_lock(&power_domains->lock); 1624 1625 was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1626 1627 if (override == was_override) 1628 goto out; 1629 1630 if (override) 1631 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1632 else 1633 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1634 1635 intel_de_write(display, DISPLAY_PHY_CONTROL, 1636 display->power.chv_phy_control); 1637 1638 drm_dbg_kms(display->drm, 1639 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1640 phy, ch, display->power.chv_phy_control); 1641 1642 assert_chv_phy_status(display); 1643 1644 out: 1645 mutex_unlock(&power_domains->lock); 1646 1647 return was_override; 1648 } 1649 1650 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1651 bool override, unsigned int mask) 1652 { 1653 struct intel_display *display = to_intel_display(encoder); 1654 struct i915_power_domains *power_domains = &display->power.domains; 1655 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1656 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 1657 1658 mutex_lock(&power_domains->lock); 1659 1660 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1661 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1662 1663 if (override) 1664 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1665 else 1666 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1667 1668 intel_de_write(display, DISPLAY_PHY_CONTROL, 1669 display->power.chv_phy_control); 1670 1671 drm_dbg_kms(display->drm, 1672 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1673 phy, ch, mask, display->power.chv_phy_control); 1674 1675 assert_chv_phy_status(display); 1676 1677 assert_chv_phy_powergate(display, phy, ch, override, mask); 1678 1679 mutex_unlock(&power_domains->lock); 1680 } 1681 1682 static bool chv_pipe_power_well_enabled(struct intel_display *display, 1683 struct i915_power_well *power_well) 1684 { 1685 enum pipe pipe = PIPE_A; 1686 bool enabled; 1687 u32 state, ctrl; 1688 1689 vlv_punit_get(display->drm); 1690 1691 state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); 1692 /* 1693 * We only ever set the power-on and power-gate states, anything 1694 * else is unexpected. 1695 */ 1696 drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) && 1697 state != DP_SSS_PWR_GATE(pipe)); 1698 enabled = state == DP_SSS_PWR_ON(pipe); 1699 1700 /* 1701 * A transient state at this point would mean some unexpected party 1702 * is poking at the power controls too. 1703 */ 1704 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); 1705 drm_WARN_ON(display->drm, ctrl << 16 != state); 1706 1707 vlv_punit_put(display->drm); 1708 1709 return enabled; 1710 } 1711 1712 static void chv_set_pipe_power_well(struct intel_display *display, 1713 struct i915_power_well *power_well, 1714 bool enable) 1715 { 1716 enum pipe pipe = PIPE_A; 1717 u32 state; 1718 u32 ctrl; 1719 int ret; 1720 1721 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1722 1723 vlv_punit_get(display->drm); 1724 1725 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 1726 if ((ctrl & DP_SSS_MASK(pipe)) == state) 1727 goto out; 1728 1729 ctrl &= ~DP_SSC_MASK(pipe); 1730 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1731 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, ctrl); 1732 1733 ret = poll_timeout_us(ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), 1734 (ctrl & DP_SSS_MASK(pipe)) == state, 1735 500, 100 * 1000, false); 1736 if (ret) 1737 drm_err(display->drm, 1738 "timeout setting power well state %08x (%08x)\n", 1739 state, 1740 vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM)); 1741 1742 #undef COND 1743 1744 out: 1745 vlv_punit_put(display->drm); 1746 } 1747 1748 static void chv_pipe_power_well_sync_hw(struct intel_display *display, 1749 struct i915_power_well *power_well) 1750 { 1751 intel_de_write(display, DISPLAY_PHY_CONTROL, 1752 display->power.chv_phy_control); 1753 } 1754 1755 static void chv_pipe_power_well_enable(struct intel_display *display, 1756 struct i915_power_well *power_well) 1757 { 1758 chv_set_pipe_power_well(display, power_well, true); 1759 1760 vlv_display_power_well_init(display); 1761 } 1762 1763 static void chv_pipe_power_well_disable(struct intel_display *display, 1764 struct i915_power_well *power_well) 1765 { 1766 vlv_display_power_well_deinit(display); 1767 1768 chv_set_pipe_power_well(display, power_well, false); 1769 } 1770 1771 static void 1772 tgl_tc_cold_request(struct intel_display *display, bool block) 1773 { 1774 u8 tries = 0; 1775 int ret; 1776 1777 while (1) { 1778 u32 low_val; 1779 u32 high_val = 0; 1780 1781 if (block) 1782 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ; 1783 else 1784 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ; 1785 1786 /* 1787 * Spec states that we should timeout the request after 200us 1788 * but the function below will timeout after 500us 1789 */ 1790 ret = intel_pcode_read(display->drm, TGL_PCODE_TCCOLD, &low_val, &high_val); 1791 if (ret == 0) { 1792 if (block && 1793 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED)) 1794 ret = -EIO; 1795 else 1796 break; 1797 } 1798 1799 if (++tries == 3) 1800 break; 1801 1802 msleep(1); 1803 } 1804 1805 if (ret) 1806 drm_err(display->drm, "TC cold %sblock failed\n", block ? "" : "un"); 1807 else 1808 drm_dbg_kms(display->drm, "TC cold %sblock succeeded\n", 1809 block ? "" : "un"); 1810 } 1811 1812 static void 1813 tgl_tc_cold_off_power_well_enable(struct intel_display *display, 1814 struct i915_power_well *power_well) 1815 { 1816 tgl_tc_cold_request(display, true); 1817 } 1818 1819 static void 1820 tgl_tc_cold_off_power_well_disable(struct intel_display *display, 1821 struct i915_power_well *power_well) 1822 { 1823 tgl_tc_cold_request(display, false); 1824 } 1825 1826 static void 1827 tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display, 1828 struct i915_power_well *power_well) 1829 { 1830 if (intel_power_well_refcount(power_well) > 0) 1831 tgl_tc_cold_off_power_well_enable(display, power_well); 1832 else 1833 tgl_tc_cold_off_power_well_disable(display, power_well); 1834 } 1835 1836 static bool 1837 tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display, 1838 struct i915_power_well *power_well) 1839 { 1840 /* 1841 * Not the correctly implementation but there is no way to just read it 1842 * from PCODE, so returning count to avoid state mismatch errors 1843 */ 1844 return intel_power_well_refcount(power_well); 1845 } 1846 1847 static void xelpdp_aux_power_well_enable(struct intel_display *display, 1848 struct i915_power_well *power_well) 1849 { 1850 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1851 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1852 1853 if (intel_phy_is_tc(display, phy)) 1854 icl_tc_port_assert_ref_held(display, power_well, 1855 aux_ch_to_digital_port(display, aux_ch)); 1856 1857 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1858 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1859 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1860 1861 /* 1862 * The power status flag cannot be used to determine whether aux 1863 * power wells have finished powering up. Instead we're 1864 * expected to just wait a fixed 600us after raising the request 1865 * bit. 1866 */ 1867 usleep_range(600, 1200); 1868 } 1869 1870 static void xelpdp_aux_power_well_disable(struct intel_display *display, 1871 struct i915_power_well *power_well) 1872 { 1873 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1874 1875 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1876 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1877 0); 1878 usleep_range(10, 30); 1879 } 1880 1881 static bool xelpdp_aux_power_well_enabled(struct intel_display *display, 1882 struct i915_power_well *power_well) 1883 { 1884 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1885 1886 return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) & 1887 XELPDP_DP_AUX_CH_CTL_POWER_STATUS; 1888 } 1889 1890 static void xe2lpd_pica_power_well_enable(struct intel_display *display, 1891 struct i915_power_well *power_well) 1892 { 1893 intel_de_write(display, XE2LPD_PICA_PW_CTL, 1894 XE2LPD_PICA_CTL_POWER_REQUEST); 1895 1896 if (intel_de_wait_for_set(display, XE2LPD_PICA_PW_CTL, 1897 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1898 drm_dbg_kms(display->drm, "pica power well enable timeout\n"); 1899 1900 drm_WARN(display->drm, 1, "Power well PICA timeout when enabled"); 1901 } 1902 } 1903 1904 static void xe2lpd_pica_power_well_disable(struct intel_display *display, 1905 struct i915_power_well *power_well) 1906 { 1907 intel_de_write(display, XE2LPD_PICA_PW_CTL, 0); 1908 1909 if (intel_de_wait_for_clear(display, XE2LPD_PICA_PW_CTL, 1910 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1911 drm_dbg_kms(display->drm, "pica power well disable timeout\n"); 1912 1913 drm_WARN(display->drm, 1, "Power well PICA timeout when disabled"); 1914 } 1915 } 1916 1917 static bool xe2lpd_pica_power_well_enabled(struct intel_display *display, 1918 struct i915_power_well *power_well) 1919 { 1920 return intel_de_read(display, XE2LPD_PICA_PW_CTL) & 1921 XE2LPD_PICA_CTL_POWER_STATUS; 1922 } 1923 1924 const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1925 .sync_hw = i9xx_power_well_sync_hw_noop, 1926 .enable = i9xx_always_on_power_well_noop, 1927 .disable = i9xx_always_on_power_well_noop, 1928 .is_enabled = i9xx_always_on_power_well_enabled, 1929 }; 1930 1931 const struct i915_power_well_ops chv_pipe_power_well_ops = { 1932 .sync_hw = chv_pipe_power_well_sync_hw, 1933 .enable = chv_pipe_power_well_enable, 1934 .disable = chv_pipe_power_well_disable, 1935 .is_enabled = chv_pipe_power_well_enabled, 1936 }; 1937 1938 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1939 .sync_hw = i9xx_power_well_sync_hw_noop, 1940 .enable = chv_dpio_cmn_power_well_enable, 1941 .disable = chv_dpio_cmn_power_well_disable, 1942 .is_enabled = vlv_power_well_enabled, 1943 }; 1944 1945 const struct i915_power_well_ops i830_pipes_power_well_ops = { 1946 .sync_hw = i830_pipes_power_well_sync_hw, 1947 .enable = i830_pipes_power_well_enable, 1948 .disable = i830_pipes_power_well_disable, 1949 .is_enabled = i830_pipes_power_well_enabled, 1950 }; 1951 1952 static const struct i915_power_well_regs hsw_power_well_regs = { 1953 .bios = HSW_PWR_WELL_CTL1, 1954 .driver = HSW_PWR_WELL_CTL2, 1955 .kvmr = HSW_PWR_WELL_CTL3, 1956 .debug = HSW_PWR_WELL_CTL4, 1957 }; 1958 1959 const struct i915_power_well_ops hsw_power_well_ops = { 1960 .regs = &hsw_power_well_regs, 1961 .sync_hw = hsw_power_well_sync_hw, 1962 .enable = hsw_power_well_enable, 1963 .disable = hsw_power_well_disable, 1964 .is_enabled = hsw_power_well_enabled, 1965 }; 1966 1967 const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1968 .sync_hw = i9xx_power_well_sync_hw_noop, 1969 .enable = gen9_dc_off_power_well_enable, 1970 .disable = gen9_dc_off_power_well_disable, 1971 .is_enabled = gen9_dc_off_power_well_enabled, 1972 }; 1973 1974 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1975 .sync_hw = i9xx_power_well_sync_hw_noop, 1976 .enable = bxt_dpio_cmn_power_well_enable, 1977 .disable = bxt_dpio_cmn_power_well_disable, 1978 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1979 }; 1980 1981 const struct i915_power_well_ops vlv_display_power_well_ops = { 1982 .sync_hw = i9xx_power_well_sync_hw_noop, 1983 .enable = vlv_display_power_well_enable, 1984 .disable = vlv_display_power_well_disable, 1985 .is_enabled = vlv_power_well_enabled, 1986 }; 1987 1988 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1989 .sync_hw = i9xx_power_well_sync_hw_noop, 1990 .enable = vlv_dpio_cmn_power_well_enable, 1991 .disable = vlv_dpio_cmn_power_well_disable, 1992 .is_enabled = vlv_power_well_enabled, 1993 }; 1994 1995 const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1996 .sync_hw = i9xx_power_well_sync_hw_noop, 1997 .enable = vlv_power_well_enable, 1998 .disable = vlv_power_well_disable, 1999 .is_enabled = vlv_power_well_enabled, 2000 }; 2001 2002 static const struct i915_power_well_regs icl_aux_power_well_regs = { 2003 .bios = ICL_PWR_WELL_CTL_AUX1, 2004 .driver = ICL_PWR_WELL_CTL_AUX2, 2005 .debug = ICL_PWR_WELL_CTL_AUX4, 2006 }; 2007 2008 const struct i915_power_well_ops icl_aux_power_well_ops = { 2009 .regs = &icl_aux_power_well_regs, 2010 .sync_hw = hsw_power_well_sync_hw, 2011 .enable = icl_aux_power_well_enable, 2012 .disable = icl_aux_power_well_disable, 2013 .is_enabled = hsw_power_well_enabled, 2014 }; 2015 2016 static const struct i915_power_well_regs icl_ddi_power_well_regs = { 2017 .bios = ICL_PWR_WELL_CTL_DDI1, 2018 .driver = ICL_PWR_WELL_CTL_DDI2, 2019 .debug = ICL_PWR_WELL_CTL_DDI4, 2020 }; 2021 2022 const struct i915_power_well_ops icl_ddi_power_well_ops = { 2023 .regs = &icl_ddi_power_well_regs, 2024 .sync_hw = hsw_power_well_sync_hw, 2025 .enable = hsw_power_well_enable, 2026 .disable = hsw_power_well_disable, 2027 .is_enabled = hsw_power_well_enabled, 2028 }; 2029 2030 const struct i915_power_well_ops tgl_tc_cold_off_ops = { 2031 .sync_hw = tgl_tc_cold_off_power_well_sync_hw, 2032 .enable = tgl_tc_cold_off_power_well_enable, 2033 .disable = tgl_tc_cold_off_power_well_disable, 2034 .is_enabled = tgl_tc_cold_off_power_well_is_enabled, 2035 }; 2036 2037 const struct i915_power_well_ops xelpdp_aux_power_well_ops = { 2038 .sync_hw = i9xx_power_well_sync_hw_noop, 2039 .enable = xelpdp_aux_power_well_enable, 2040 .disable = xelpdp_aux_power_well_disable, 2041 .is_enabled = xelpdp_aux_power_well_enabled, 2042 }; 2043 2044 const struct i915_power_well_ops xe2lpd_pica_power_well_ops = { 2045 .sync_hw = i9xx_power_well_sync_hw_noop, 2046 .enable = xe2lpd_pica_power_well_enable, 2047 .disable = xe2lpd_pica_power_well_disable, 2048 .is_enabled = xe2lpd_pica_power_well_enabled, 2049 }; 2050