1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <linux/iopoll.h> 7 8 #include <drm/drm_print.h> 9 #include <drm/intel/intel_pcode_regs.h> 10 11 #include "intel_backlight_regs.h" 12 #include "intel_combo_phy.h" 13 #include "intel_combo_phy_regs.h" 14 #include "intel_crt.h" 15 #include "intel_de.h" 16 #include "intel_display_irq.h" 17 #include "intel_display_power_well.h" 18 #include "intel_display_regs.h" 19 #include "intel_display_rpm.h" 20 #include "intel_display_types.h" 21 #include "intel_display_wa.h" 22 #include "intel_dkl_phy.h" 23 #include "intel_dkl_phy_regs.h" 24 #include "intel_dmc.h" 25 #include "intel_dmc_wl.h" 26 #include "intel_dp_aux_regs.h" 27 #include "intel_dpio_phy.h" 28 #include "intel_dpll.h" 29 #include "intel_hotplug.h" 30 #include "intel_parent.h" 31 #include "intel_pps.h" 32 #include "intel_psr.h" 33 #include "intel_tc.h" 34 #include "intel_vga.h" 35 #include "skl_watermark.h" 36 #include "vlv_dpio_phy_regs.h" 37 #include "vlv_sideband.h" 38 39 /* 40 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 41 * 42 * {ICL,SKL}_DISP_PW1_IDX..{ICL,SKL}_DISP_PW4_IDX -> PG1..PG4 43 */ 44 static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx) 45 { 46 int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1; 47 48 return pw_idx - pw1_idx + SKL_PG1; 49 } 50 51 struct i915_power_well_regs { 52 intel_reg_t bios; 53 intel_reg_t driver; 54 intel_reg_t kvmr; 55 intel_reg_t debug; 56 }; 57 58 struct i915_power_well_ops { 59 const struct i915_power_well_regs *regs; 60 /* 61 * Synchronize the well's hw state to match the current sw state, for 62 * example enable/disable it based on the current refcount. Called 63 * during driver init and resume time, possibly after first calling 64 * the enable/disable handlers. 65 */ 66 void (*sync_hw)(struct intel_display *display, 67 struct i915_power_well *power_well); 68 /* 69 * Enable the well and resources that depend on it (for example 70 * interrupts located on the well). Called after the 0->1 refcount 71 * transition. 72 */ 73 void (*enable)(struct intel_display *display, 74 struct i915_power_well *power_well); 75 /* 76 * Disable the well and resources that depend on it. Called after 77 * the 1->0 refcount transition. 78 */ 79 void (*disable)(struct intel_display *display, 80 struct i915_power_well *power_well); 81 /* Returns the hw enabled state. */ 82 bool (*is_enabled)(struct intel_display *display, 83 struct i915_power_well *power_well); 84 }; 85 86 static const struct i915_power_well_instance * 87 i915_power_well_instance(const struct i915_power_well *power_well) 88 { 89 return &power_well->desc->instances->list[power_well->instance_idx]; 90 } 91 92 struct i915_power_well * 93 lookup_power_well(struct intel_display *display, 94 enum i915_power_well_id power_well_id) 95 { 96 struct i915_power_well *power_well; 97 98 for_each_power_well(display, power_well) 99 if (i915_power_well_instance(power_well)->id == power_well_id) 100 return power_well; 101 102 /* 103 * It's not feasible to add error checking code to the callers since 104 * this condition really shouldn't happen and it doesn't even make sense 105 * to abort things like display initialization sequences. Just return 106 * the first power well and hope the WARN gets reported so we can fix 107 * our driver. 108 */ 109 drm_WARN(display->drm, 1, 110 "Power well %d not defined for this platform\n", 111 power_well_id); 112 return &display->power.domains.power_wells[0]; 113 } 114 115 void intel_power_well_enable(struct intel_display *display, 116 struct i915_power_well *power_well) 117 { 118 drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well)); 119 power_well->desc->ops->enable(display, power_well); 120 power_well->hw_enabled = true; 121 } 122 123 void intel_power_well_disable(struct intel_display *display, 124 struct i915_power_well *power_well) 125 { 126 drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well)); 127 power_well->hw_enabled = false; 128 power_well->desc->ops->disable(display, power_well); 129 } 130 131 void intel_power_well_sync_hw(struct intel_display *display, 132 struct i915_power_well *power_well) 133 { 134 power_well->desc->ops->sync_hw(display, power_well); 135 power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well); 136 } 137 138 void intel_power_well_get(struct intel_display *display, 139 struct i915_power_well *power_well) 140 { 141 if (!power_well->count++) 142 intel_power_well_enable(display, power_well); 143 } 144 145 void intel_power_well_put(struct intel_display *display, 146 struct i915_power_well *power_well) 147 { 148 drm_WARN(display->drm, !power_well->count, 149 "Use count on power well %s is already zero", 150 i915_power_well_instance(power_well)->name); 151 152 if (!--power_well->count) 153 intel_power_well_disable(display, power_well); 154 } 155 156 bool intel_power_well_is_enabled(struct intel_display *display, 157 struct i915_power_well *power_well) 158 { 159 return power_well->desc->ops->is_enabled(display, power_well); 160 } 161 162 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well) 163 { 164 return power_well->hw_enabled; 165 } 166 167 bool intel_display_power_well_is_enabled(struct intel_display *display, 168 enum i915_power_well_id power_well_id) 169 { 170 struct i915_power_well *power_well; 171 172 power_well = lookup_power_well(display, power_well_id); 173 174 return intel_power_well_is_enabled(display, power_well); 175 } 176 177 bool intel_power_well_is_always_on(struct i915_power_well *power_well) 178 { 179 return power_well->desc->always_on; 180 } 181 182 const char *intel_power_well_name(struct i915_power_well *power_well) 183 { 184 return i915_power_well_instance(power_well)->name; 185 } 186 187 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well) 188 { 189 return &power_well->domains; 190 } 191 192 int intel_power_well_refcount(struct i915_power_well *power_well) 193 { 194 return power_well->count; 195 } 196 197 static u32 dss_pipe_gating_bits(u8 irq_pipe_mask) 198 { 199 u32 bits = 0; 200 201 if (irq_pipe_mask & BIT(PIPE_A)) 202 bits |= DSS_PIPE_A_GATING_DISABLED; 203 if (irq_pipe_mask & BIT(PIPE_B)) 204 bits |= DSS_PIPE_B_GATING_DISABLED; 205 if (irq_pipe_mask & BIT(PIPE_C)) 206 bits |= DSS_PIPE_C_GATING_DISABLED; 207 if (irq_pipe_mask & BIT(PIPE_D)) 208 bits |= DSS_PIPE_D_GATING_DISABLED; 209 210 return bits; 211 } 212 213 static void dss_pipe_gating_enable_disable(struct intel_display *display, 214 u8 irq_pipe_mask, 215 bool disable) 216 { 217 u32 bits = dss_pipe_gating_bits(irq_pipe_mask); 218 u32 clear, set; 219 220 if (!bits) 221 return; 222 223 /* 224 * Single intel_de_rmw() for both enable/disable: 225 * - disable == true, set bits (disable clock gating) 226 * - disable == false, clear bits (re-enable clock gating) 227 */ 228 set = disable ? bits : 0; 229 clear = disable ? 0 : bits; 230 231 intel_de_rmw(display, CLKGATE_DIS_DSSDSC, clear, set); 232 233 drm_dbg_kms(display->drm, 234 "DSS clock gating %sd for pipe_mask=0x%x (CLKGATE_DIS_DSSDSC=0x%08x)\n", 235 str_enable_disable(!disable), irq_pipe_mask, 236 intel_de_read(display, CLKGATE_DIS_DSSDSC)); 237 } 238 239 /* 240 * Starting with Haswell, we have a "Power Down Well" that can be turned off 241 * when not needed anymore. We have 4 registers that can request the power well 242 * to be enabled, and it will only be disabled if none of the registers is 243 * requesting it to be enabled. 244 */ 245 static void hsw_power_well_post_enable(struct intel_display *display, 246 u8 irq_pipe_mask) 247 { 248 if (irq_pipe_mask) { 249 gen8_irq_power_well_post_enable(display, irq_pipe_mask); 250 251 if (intel_display_wa(display, INTEL_DISPLAY_WA_22021048059)) 252 dss_pipe_gating_enable_disable(display, irq_pipe_mask, false); 253 } 254 } 255 256 static void hsw_power_well_pre_disable(struct intel_display *display, 257 u8 irq_pipe_mask) 258 { 259 if (irq_pipe_mask) { 260 if (intel_display_wa(display, INTEL_DISPLAY_WA_22021048059)) 261 dss_pipe_gating_enable_disable(display, irq_pipe_mask, true); 262 263 gen8_irq_power_well_pre_disable(display, irq_pipe_mask); 264 } 265 } 266 267 #define ICL_AUX_PW_TO_PHY(pw_idx) \ 268 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + PHY_A) 269 270 #define ICL_AUX_PW_TO_CH(pw_idx) \ 271 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) 272 273 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ 274 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) 275 276 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well) 277 { 278 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 279 280 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : 281 ICL_AUX_PW_TO_CH(pw_idx); 282 } 283 284 static struct intel_digital_port * 285 aux_ch_to_digital_port(struct intel_display *display, 286 enum aux_ch aux_ch) 287 { 288 struct intel_encoder *encoder; 289 290 for_each_intel_encoder(display->drm, encoder) { 291 struct intel_digital_port *dig_port; 292 293 /* We'll check the MST primary port */ 294 if (encoder->type == INTEL_OUTPUT_DP_MST) 295 continue; 296 297 dig_port = enc_to_dig_port(encoder); 298 299 if (dig_port && dig_port->aux_ch == aux_ch) 300 return dig_port; 301 } 302 303 return NULL; 304 } 305 306 static struct intel_encoder * 307 icl_aux_pw_to_encoder(struct intel_display *display, 308 const struct i915_power_well *power_well) 309 { 310 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 311 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 312 313 /* 314 * FIXME should we care about the (VBT defined) dig_port->aux_ch 315 * relationship or should this be purely defined by the hardware layout? 316 * Currently if the port doesn't appear in the VBT, or if it's declared 317 * as HDMI-only and routed to a combo PHY, the encoder either won't be 318 * present at all or it will not have an aux_ch assigned. 319 */ 320 return dig_port ? &dig_port->base : NULL; 321 } 322 323 static enum phy icl_aux_pw_to_phy(struct intel_display *display, 324 const struct i915_power_well *power_well) 325 { 326 struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well); 327 328 return encoder ? intel_encoder_to_phy(encoder) : PHY_NONE; 329 } 330 331 static bool icl_aux_pw_is_tc_phy(struct intel_display *display, 332 const struct i915_power_well *power_well) 333 { 334 struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well); 335 336 return encoder && intel_encoder_is_tc(encoder); 337 } 338 339 static void hsw_wait_for_power_well_enable(struct intel_display *display, 340 struct i915_power_well *power_well, 341 bool timeout_expected) 342 { 343 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 344 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 345 int timeout = power_well->desc->enable_timeout ? : 1; 346 347 /* 348 * For some power wells we're not supposed to watch the status bit for 349 * an ack, but rather just wait a fixed amount of time and then 350 * proceed. This is only used on DG2. 351 */ 352 if (display->platform.dg2 && power_well->desc->fixed_enable_delay) { 353 usleep_range(600, 1200); 354 return; 355 } 356 357 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 358 if (intel_de_wait_for_set_ms(display, regs->driver, 359 HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) { 360 drm_dbg_kms(display->drm, "%s power well enable timeout\n", 361 intel_power_well_name(power_well)); 362 363 drm_WARN_ON(display->drm, !timeout_expected); 364 365 } 366 } 367 368 static u32 hsw_power_well_requesters(struct intel_display *display, 369 const struct i915_power_well_regs *regs, 370 int pw_idx) 371 { 372 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 373 u32 ret; 374 375 ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0; 376 ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0; 377 if (regs->kvmr.reg) 378 ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0; 379 ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0; 380 381 return ret; 382 } 383 384 static void hsw_wait_for_power_well_disable(struct intel_display *display, 385 struct i915_power_well *power_well) 386 { 387 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 388 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 389 u32 reqs; 390 int ret; 391 392 /* 393 * Bspec doesn't require waiting for PWs to get disabled, but still do 394 * this for paranoia. The known cases where a PW will be forced on: 395 * - a KVMR request on any power well via the KVMR request register 396 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 397 * DEBUG request registers 398 * Skip the wait in case any of the request bits are set and print a 399 * diagnostic message. 400 */ 401 reqs = hsw_power_well_requesters(display, regs, pw_idx); 402 403 ret = intel_de_wait_for_clear_ms(display, regs->driver, 404 HSW_PWR_WELL_CTL_STATE(pw_idx), 405 reqs ? 0 : 1); 406 if (!ret) 407 return; 408 409 /* Refresh requesters in case they popped up during the wait. */ 410 if (!reqs) 411 reqs = hsw_power_well_requesters(display, regs, pw_idx); 412 413 drm_dbg_kms(display->drm, 414 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 415 intel_power_well_name(power_well), 416 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 417 } 418 419 static void gen9_wait_for_power_well_fuses(struct intel_display *display, 420 enum skl_power_gate pg) 421 { 422 /* Timeout 5us for PG#0, for other PGs 1us */ 423 drm_WARN_ON(display->drm, 424 intel_de_wait_for_set_ms(display, SKL_FUSE_STATUS, 425 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 426 } 427 428 static void hsw_power_well_enable(struct intel_display *display, 429 struct i915_power_well *power_well) 430 { 431 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 432 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 433 434 if (power_well->desc->has_fuses) { 435 enum skl_power_gate pg; 436 437 pg = pw_idx_to_pg(display, pw_idx); 438 439 /* Wa_16013190616:adlp */ 440 if (display->platform.alderlake_p && pg == SKL_PG1) 441 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 442 443 /* 444 * For PW1 we have to wait both for the PW0/PG0 fuse state 445 * before enabling the power well and PW1/PG1's own fuse 446 * state after the enabling. For all other power wells with 447 * fuses we only have to wait for that PW/PG's fuse state 448 * after the enabling. 449 */ 450 if (pg == SKL_PG1) 451 gen9_wait_for_power_well_fuses(display, SKL_PG0); 452 } 453 454 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 455 456 hsw_wait_for_power_well_enable(display, power_well, false); 457 458 if (power_well->desc->has_fuses) { 459 enum skl_power_gate pg; 460 461 pg = pw_idx_to_pg(display, pw_idx); 462 463 gen9_wait_for_power_well_fuses(display, pg); 464 } 465 466 hsw_power_well_post_enable(display, 467 power_well->desc->irq_pipe_mask); 468 } 469 470 static void hsw_power_well_disable(struct intel_display *display, 471 struct i915_power_well *power_well) 472 { 473 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 474 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 475 476 hsw_power_well_pre_disable(display, 477 power_well->desc->irq_pipe_mask); 478 479 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 480 hsw_wait_for_power_well_disable(display, power_well); 481 } 482 483 static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch) 484 { 485 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 486 487 return dig_port && dig_port->base.type == INTEL_OUTPUT_EDP; 488 } 489 490 static void 491 icl_combo_phy_aux_power_well_enable(struct intel_display *display, 492 struct i915_power_well *power_well) 493 { 494 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 495 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 496 497 drm_WARN_ON(display->drm, !display->platform.icelake); 498 499 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 500 501 /* 502 * FIXME not sure if we should derive the PHY from the pw_idx, or 503 * from the VBT defined AUX_CH->DDI->PHY mapping. 504 */ 505 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 506 0, ICL_LANE_ENABLE_AUX); 507 508 hsw_wait_for_power_well_enable(display, power_well, false); 509 510 /* Display WA #1178: icl */ 511 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && 512 !intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx))) 513 intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), 514 0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI); 515 } 516 517 static void 518 icl_combo_phy_aux_power_well_disable(struct intel_display *display, 519 struct i915_power_well *power_well) 520 { 521 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 522 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 523 524 drm_WARN_ON(display->drm, !display->platform.icelake); 525 526 /* 527 * FIXME not sure if we should derive the PHY from the pw_idx, or 528 * from the VBT defined AUX_CH->DDI->PHY mapping. 529 */ 530 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 531 ICL_LANE_ENABLE_AUX, 0); 532 533 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 534 535 hsw_wait_for_power_well_disable(display, power_well); 536 } 537 538 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 539 540 static void icl_tc_port_assert_ref_held(struct intel_display *display, 541 struct i915_power_well *power_well, 542 struct intel_digital_port *dig_port) 543 { 544 if (drm_WARN_ON(display->drm, !dig_port)) 545 return; 546 547 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 548 return; 549 550 drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port)); 551 } 552 553 #else 554 555 static void icl_tc_port_assert_ref_held(struct intel_display *display, 556 struct i915_power_well *power_well, 557 struct intel_digital_port *dig_port) 558 { 559 } 560 561 #endif 562 563 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1) 564 565 static void icl_tc_cold_exit(struct intel_display *display) 566 { 567 int ret, tries = 0; 568 569 while (1) { 570 ret = intel_parent_pcode_write(display, ICL_PCODE_EXIT_TCCOLD, 0); 571 if (ret != -EAGAIN || ++tries == 3) 572 break; 573 msleep(1); 574 } 575 576 /* Spec states that TC cold exit can take up to 1ms to complete */ 577 if (!ret) 578 msleep(1); 579 580 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */ 581 drm_dbg_kms(display->drm, "TC cold block %s\n", ret ? "failed" : 582 "succeeded"); 583 } 584 585 static void 586 icl_tc_phy_aux_power_well_enable(struct intel_display *display, 587 struct i915_power_well *power_well) 588 { 589 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 590 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 591 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 592 bool is_tbt = power_well->desc->is_tc_tbt; 593 bool timeout_expected; 594 u32 val; 595 int ret; 596 597 icl_tc_port_assert_ref_held(display, power_well, dig_port); 598 599 intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), 600 DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0); 601 602 intel_de_rmw(display, regs->driver, 603 0, 604 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); 605 606 /* 607 * An AUX timeout is expected if the TBT DP tunnel is down, 608 * or need to enable AUX on a legacy TypeC port as part of the TC-cold 609 * exit sequence. 610 */ 611 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port); 612 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 613 icl_tc_cold_exit(display); 614 615 hsw_wait_for_power_well_enable(display, power_well, timeout_expected); 616 617 if (DISPLAY_VER(display) >= 12 && !is_tbt) { 618 enum tc_port tc_port; 619 620 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); 621 622 ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)), 623 val & DKL_CMN_UC_DW27_UC_HEALTH, 624 100, 1000, false); 625 if (ret) 626 drm_warn(display->drm, "Timeout waiting TC uC health\n"); 627 } 628 } 629 630 static void 631 icl_aux_power_well_enable(struct intel_display *display, 632 struct i915_power_well *power_well) 633 { 634 if (icl_aux_pw_is_tc_phy(display, power_well)) 635 return icl_tc_phy_aux_power_well_enable(display, power_well); 636 else if (display->platform.icelake) 637 return icl_combo_phy_aux_power_well_enable(display, 638 power_well); 639 else 640 return hsw_power_well_enable(display, power_well); 641 } 642 643 static void 644 icl_aux_power_well_disable(struct intel_display *display, 645 struct i915_power_well *power_well) 646 { 647 if (icl_aux_pw_is_tc_phy(display, power_well)) 648 return hsw_power_well_disable(display, power_well); 649 else if (display->platform.icelake) 650 return icl_combo_phy_aux_power_well_disable(display, 651 power_well); 652 else 653 return hsw_power_well_disable(display, power_well); 654 } 655 656 /* 657 * We should only use the power well if we explicitly asked the hardware to 658 * enable it, so check if it's enabled and also check if we've requested it to 659 * be enabled. 660 */ 661 static bool hsw_power_well_enabled(struct intel_display *display, 662 struct i915_power_well *power_well) 663 { 664 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 665 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 666 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 667 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | 668 HSW_PWR_WELL_CTL_STATE(pw_idx); 669 u32 val; 670 671 val = intel_de_read(display, regs->driver); 672 673 /* 674 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 675 * and the MISC_IO PW will be not restored, so check instead for the 676 * BIOS's own request bits, which are forced-on for these power wells 677 * when exiting DC5/6. 678 */ 679 if (DISPLAY_VER(display) == 9 && !display->platform.broxton && 680 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 681 val |= intel_de_read(display, regs->bios); 682 683 return (val & mask) == mask; 684 } 685 686 static void assert_can_enable_dc9(struct intel_display *display) 687 { 688 drm_WARN_ONCE(display->drm, 689 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), 690 "DC9 already programmed to be enabled.\n"); 691 drm_WARN_ONCE(display->drm, 692 intel_de_read(display, DC_STATE_EN) & 693 DC_STATE_EN_UPTO_DC5, 694 "DC5 still not disabled to enable DC9.\n"); 695 drm_WARN_ONCE(display->drm, 696 intel_de_read(display, HSW_PWR_WELL_CTL2) & 697 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 698 "Power well 2 on.\n"); 699 drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), 700 "Interrupts not disabled yet.\n"); 701 702 /* 703 * TODO: check for the following to verify the conditions to enter DC9 704 * state are satisfied: 705 * 1] Check relevant display engine registers to verify if mode set 706 * disable sequence was followed. 707 * 2] Check if display uninitialize sequence is initialized. 708 */ 709 } 710 711 static void assert_can_disable_dc9(struct intel_display *display) 712 { 713 drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), 714 "Interrupts not disabled yet.\n"); 715 drm_WARN_ONCE(display->drm, 716 intel_de_read(display, DC_STATE_EN) & 717 DC_STATE_EN_UPTO_DC5, 718 "DC5 still not disabled.\n"); 719 720 /* 721 * TODO: check for the following to verify DC9 state was indeed 722 * entered before programming to disable it: 723 * 1] Check relevant display engine registers to verify if mode 724 * set disable sequence was followed. 725 * 2] Check if display uninitialize sequence is initialized. 726 */ 727 } 728 729 static u32 dc_state_ro_mask(struct intel_display *display) 730 { 731 if (DISPLAY_VER(display) >= 20) 732 return DC_STATE_EN_CSR_MASK_CMTG_1 | DC_STATE_EN_CSR_MASK_CMTG_0; 733 else if (DISPLAY_VER(display) >= 13 && !display->platform.dg2) 734 return DC_STATE_EN_CSR_MASK_CMTG_0; 735 736 return 0; 737 } 738 739 static void gen9_write_dc_state(struct intel_display *display, 740 u32 state) 741 { 742 int rewrites = 0; 743 int rereads = 0; 744 u32 v; 745 /* 746 * Mask out RO status bits from read-back comparison. 747 * HW may set these bits independently, so exclude them 748 * to prevent the verify loop from retrying due to RO bits mismatch. 749 */ 750 u32 ro_mask = dc_state_ro_mask(display); 751 752 intel_de_write(display, DC_STATE_EN, state); 753 754 /* It has been observed that disabling the dc6 state sometimes 755 * doesn't stick and dmc keeps returning old value. Make sure 756 * the write really sticks enough times and also force rewrite until 757 * we are confident that state is exactly what we want. 758 */ 759 do { 760 v = intel_de_read(display, DC_STATE_EN); 761 762 if ((v & ~ro_mask) != (state & ~ro_mask)) { 763 intel_de_write(display, DC_STATE_EN, state); 764 rewrites++; 765 rereads = 0; 766 } else if (rereads++ > 5) { 767 break; 768 } 769 770 } while (rewrites < 100); 771 772 if ((v & ~ro_mask) != (state & ~ro_mask)) 773 drm_err(display->drm, 774 "Writing dc state to 0x%x failed, now 0x%x (ro_mask=0x%x)\n", 775 state, v, ro_mask); 776 777 /* Most of the times we need one retry, avoid spam */ 778 if (rewrites > 1) 779 drm_dbg_kms(display->drm, 780 "Rewrote dc state to 0x%x %d times\n", 781 state, rewrites); 782 } 783 784 static u32 gen9_dc_mask(struct intel_display *display) 785 { 786 u32 mask; 787 788 mask = DC_STATE_EN_UPTO_DC5; 789 790 if (DISPLAY_VER(display) >= 12) 791 mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6 792 | DC_STATE_EN_DC9; 793 else if (DISPLAY_VER(display) == 11) 794 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; 795 else if (display->platform.geminilake || display->platform.broxton) 796 mask |= DC_STATE_EN_DC9; 797 else 798 mask |= DC_STATE_EN_UPTO_DC6; 799 800 return mask; 801 } 802 803 void gen9_sanitize_dc_state(struct intel_display *display) 804 { 805 struct i915_power_domains *power_domains = &display->power.domains; 806 u32 val; 807 808 if (!HAS_DISPLAY(display)) 809 return; 810 811 val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display); 812 813 drm_dbg_kms(display->drm, 814 "Resetting DC state tracking from %02x to %02x\n", 815 power_domains->dc_state, val); 816 power_domains->dc_state = val; 817 } 818 819 /** 820 * gen9_set_dc_state - set target display C power state 821 * @display: display instance 822 * @state: target DC power state 823 * - DC_STATE_DISABLE 824 * - DC_STATE_EN_UPTO_DC5 825 * - DC_STATE_EN_UPTO_DC6 826 * - DC_STATE_EN_DC9 827 * 828 * Signal to DMC firmware/HW the target DC power state passed in @state. 829 * DMC/HW can turn off individual display clocks and power rails when entering 830 * a deeper DC power state (higher in number) and turns these back when exiting 831 * that state to a shallower power state (lower in number). The HW will decide 832 * when to actually enter a given state on an on-demand basis, for instance 833 * depending on the active state of display pipes. The state of display 834 * registers backed by affected power rails are saved/restored as needed. 835 * 836 * Based on the above enabling a deeper DC power state is asynchronous wrt. 837 * enabling it. Disabling a deeper power state is synchronous: for instance 838 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 839 * back on and register state is restored. This is guaranteed by the MMIO write 840 * to DC_STATE_EN blocking until the state is restored. 841 */ 842 void gen9_set_dc_state(struct intel_display *display, u32 state) 843 { 844 struct i915_power_domains *power_domains = &display->power.domains; 845 bool dc6_was_enabled, enable_dc6; 846 u32 mask; 847 u32 val; 848 849 if (!HAS_DISPLAY(display)) 850 return; 851 852 if (drm_WARN_ON_ONCE(display->drm, 853 state & ~power_domains->allowed_dc_mask)) 854 state &= power_domains->allowed_dc_mask; 855 856 if (!power_domains->initializing) 857 intel_psr_notify_dc5_dc6(display); 858 859 val = intel_de_read(display, DC_STATE_EN); 860 mask = gen9_dc_mask(display); 861 drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", 862 val & mask, state); 863 864 /* Check if DMC is ignoring our DC state requests */ 865 if ((val & mask) != power_domains->dc_state) 866 drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n", 867 power_domains->dc_state, val & mask); 868 869 enable_dc6 = state & DC_STATE_EN_UPTO_DC6; 870 dc6_was_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6; 871 if (!dc6_was_enabled && enable_dc6) 872 intel_dmc_update_dc6_allowed_count(display, true); 873 874 val &= ~mask; 875 val |= state; 876 877 gen9_write_dc_state(display, val); 878 879 if (!enable_dc6 && dc6_was_enabled) 880 intel_dmc_update_dc6_allowed_count(display, false); 881 882 power_domains->dc_state = val & mask; 883 } 884 885 void xe3lpd_enable_dc_count(struct intel_display *display) 886 { 887 if (DISPLAY_VER(display) < 35) 888 return; 889 890 intel_de_write(display, DC_COUNT_EN, DC_COUNT_EN_COUNTER_ENABLE); 891 } 892 893 static void assert_can_enable_dc3co(struct intel_display *display) 894 { 895 drm_WARN_ONCE(display->drm, 896 (intel_de_read(display, DC_STATE_EN) & 897 DC_STATE_EN_UPTO_DC3CO), 898 "DC3CO already programmed to be enabled.\n"); 899 900 assert_main_dmc_loaded(display); 901 } 902 903 static void xe3lpd_enable_dc3co(struct intel_display *display) 904 { 905 assert_can_enable_dc3co(display); 906 drm_dbg_kms(display->drm, "Enabling DC3CO\n"); 907 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC3CO); 908 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC3CO); 909 } 910 911 static void assert_can_enable_dc5(struct intel_display *display) 912 { 913 enum i915_power_well_id high_pg; 914 915 /* Power wells at this level and above must be disabled for DC5 entry */ 916 if (DISPLAY_VER(display) == 12) 917 high_pg = ICL_DISP_PW_3; 918 else 919 high_pg = SKL_DISP_PW_2; 920 921 drm_WARN_ONCE(display->drm, 922 intel_display_power_well_is_enabled(display, high_pg), 923 "Power wells above platform's DC5 limit still enabled.\n"); 924 925 drm_WARN_ONCE(display->drm, 926 (intel_de_read(display, DC_STATE_EN) & 927 DC_STATE_EN_UPTO_DC5), 928 "DC5 already programmed to be enabled.\n"); 929 930 assert_display_rpm_held(display); 931 932 assert_main_dmc_loaded(display); 933 } 934 935 void gen9_enable_dc5(struct intel_display *display) 936 { 937 assert_can_enable_dc5(display); 938 939 drm_dbg_kms(display->drm, "Enabling DC5\n"); 940 941 /* Wa Display #1183: skl,kbl,cfl */ 942 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 943 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 944 0, SKL_SELECT_ALTERNATE_DC_EXIT); 945 946 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5); 947 948 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); 949 } 950 951 static void assert_can_enable_dc6(struct intel_display *display) 952 { 953 drm_WARN_ONCE(display->drm, 954 (intel_de_read(display, UTIL_PIN_CTL) & 955 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == 956 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 957 "Utility pin enabled in PWM mode\n"); 958 drm_WARN_ONCE(display->drm, 959 (intel_de_read(display, DC_STATE_EN) & 960 DC_STATE_EN_UPTO_DC6), 961 "DC6 already programmed to be enabled.\n"); 962 963 assert_main_dmc_loaded(display); 964 } 965 966 void skl_enable_dc6(struct intel_display *display) 967 { 968 assert_can_enable_dc6(display); 969 970 drm_dbg_kms(display->drm, "Enabling DC6\n"); 971 972 /* Wa Display #1183: skl,kbl,cfl */ 973 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 974 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 975 0, SKL_SELECT_ALTERNATE_DC_EXIT); 976 977 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6); 978 979 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); 980 } 981 982 void bxt_enable_dc9(struct intel_display *display) 983 { 984 assert_can_enable_dc9(display); 985 986 drm_dbg_kms(display->drm, "Enabling DC9\n"); 987 /* 988 * Power sequencer reset is needed on BXT/GLK, because the PPS registers 989 * aren't always on, unlike with South Display Engine on PCH. 990 */ 991 if (display->platform.broxton || display->platform.geminilake) 992 bxt_pps_reset_all(display); 993 gen9_set_dc_state(display, DC_STATE_EN_DC9); 994 } 995 996 void bxt_disable_dc9(struct intel_display *display) 997 { 998 assert_can_disable_dc9(display); 999 1000 drm_dbg_kms(display->drm, "Disabling DC9\n"); 1001 1002 gen9_set_dc_state(display, DC_STATE_DISABLE); 1003 1004 intel_pps_unlock_regs_wa(display); 1005 } 1006 1007 static void hsw_power_well_sync_hw(struct intel_display *display, 1008 struct i915_power_well *power_well) 1009 { 1010 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 1011 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 1012 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 1013 u32 bios_req = intel_de_read(display, regs->bios); 1014 1015 /* Take over the request bit if set by BIOS. */ 1016 if (bios_req & mask) { 1017 u32 drv_req = intel_de_read(display, regs->driver); 1018 1019 if (!(drv_req & mask)) 1020 intel_de_write(display, regs->driver, drv_req | mask); 1021 intel_de_write(display, regs->bios, bios_req & ~mask); 1022 } 1023 } 1024 1025 static void bxt_dpio_cmn_power_well_enable(struct intel_display *display, 1026 struct i915_power_well *power_well) 1027 { 1028 bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy); 1029 } 1030 1031 static void bxt_dpio_cmn_power_well_disable(struct intel_display *display, 1032 struct i915_power_well *power_well) 1033 { 1034 bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy); 1035 } 1036 1037 static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display, 1038 struct i915_power_well *power_well) 1039 { 1040 return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy); 1041 } 1042 1043 static void bxt_verify_dpio_phy_power_wells(struct intel_display *display) 1044 { 1045 struct i915_power_well *power_well; 1046 1047 power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A); 1048 if (intel_power_well_refcount(power_well) > 0) 1049 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 1050 1051 power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1052 if (intel_power_well_refcount(power_well) > 0) 1053 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 1054 1055 if (display->platform.geminilake) { 1056 power_well = lookup_power_well(display, 1057 GLK_DISP_PW_DPIO_CMN_C); 1058 if (intel_power_well_refcount(power_well) > 0) 1059 bxt_dpio_phy_verify_state(display, 1060 i915_power_well_instance(power_well)->bxt.phy); 1061 } 1062 } 1063 1064 static bool gen9_dc_off_power_well_enabled(struct intel_display *display, 1065 struct i915_power_well *power_well) 1066 { 1067 return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC3CO) == 0 && 1068 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC3CO_DC5_DC6_MASK) == 0); 1069 } 1070 1071 static void gen9_assert_dbuf_enabled(struct intel_display *display) 1072 { 1073 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display); 1074 u8 enabled_dbuf_slices = display->dbuf.enabled_slices; 1075 1076 drm_WARN(display->drm, 1077 hw_enabled_dbuf_slices != enabled_dbuf_slices, 1078 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 1079 hw_enabled_dbuf_slices, 1080 enabled_dbuf_slices); 1081 } 1082 1083 void gen9_disable_dc_states(struct intel_display *display) 1084 { 1085 struct i915_power_domains *power_domains = &display->power.domains; 1086 struct intel_cdclk_config cdclk_config = {}; 1087 u32 old_state = power_domains->dc_state; 1088 1089 if (HAS_DISPLAY(display)) { 1090 intel_dmc_wl_get_noreg(display); 1091 gen9_set_dc_state(display, DC_STATE_DISABLE); 1092 intel_dmc_wl_put_noreg(display); 1093 } else { 1094 gen9_set_dc_state(display, DC_STATE_DISABLE); 1095 return; 1096 } 1097 1098 if (old_state == DC_STATE_EN_UPTO_DC5 || 1099 old_state == DC_STATE_EN_UPTO_DC6 || 1100 old_state == DC_STATE_EN_UPTO_DC3CO) 1101 intel_dmc_wl_disable(display); 1102 1103 if (old_state == DC_STATE_EN_UPTO_DC3CO) 1104 return; 1105 1106 intel_cdclk_get_cdclk(display, &cdclk_config); 1107 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 1108 drm_WARN_ON(display->drm, 1109 intel_cdclk_clock_changed(&display->cdclk.hw, 1110 &cdclk_config)); 1111 1112 gen9_assert_dbuf_enabled(display); 1113 1114 if (display->platform.geminilake || display->platform.broxton) 1115 bxt_verify_dpio_phy_power_wells(display); 1116 1117 if (DISPLAY_VER(display) >= 11) 1118 /* 1119 * DMC retains HW context only for port A, the other combo 1120 * PHY's HW context for port B is lost after DC transitions, 1121 * so we need to restore it manually. 1122 */ 1123 intel_combo_phy_init(display); 1124 } 1125 1126 static void gen9_dc_off_power_well_enable(struct intel_display *display, 1127 struct i915_power_well *power_well) 1128 { 1129 gen9_disable_dc_states(display); 1130 } 1131 1132 static void gen9_dc_off_power_well_disable(struct intel_display *display, 1133 struct i915_power_well *power_well) 1134 { 1135 struct i915_power_domains *power_domains = &display->power.domains; 1136 1137 if (!intel_dmc_has_payload(display)) 1138 return; 1139 1140 switch (power_domains->target_dc_state) { 1141 case DC_STATE_EN_UPTO_DC3CO: 1142 xe3lpd_enable_dc3co(display); 1143 break; 1144 case DC_STATE_EN_UPTO_DC6: 1145 skl_enable_dc6(display); 1146 break; 1147 case DC_STATE_EN_UPTO_DC5: 1148 gen9_enable_dc5(display); 1149 break; 1150 } 1151 } 1152 1153 static void i9xx_power_well_sync_hw_noop(struct intel_display *display, 1154 struct i915_power_well *power_well) 1155 { 1156 } 1157 1158 static void i9xx_always_on_power_well_noop(struct intel_display *display, 1159 struct i915_power_well *power_well) 1160 { 1161 } 1162 1163 static bool i9xx_always_on_power_well_enabled(struct intel_display *display, 1164 struct i915_power_well *power_well) 1165 { 1166 return true; 1167 } 1168 1169 static void i830_pipes_power_well_enable(struct intel_display *display, 1170 struct i915_power_well *power_well) 1171 { 1172 if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) 1173 i830_enable_pipe(display, PIPE_A); 1174 if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0) 1175 i830_enable_pipe(display, PIPE_B); 1176 } 1177 1178 static void i830_pipes_power_well_disable(struct intel_display *display, 1179 struct i915_power_well *power_well) 1180 { 1181 i830_disable_pipe(display, PIPE_B); 1182 i830_disable_pipe(display, PIPE_A); 1183 } 1184 1185 static bool i830_pipes_power_well_enabled(struct intel_display *display, 1186 struct i915_power_well *power_well) 1187 { 1188 return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && 1189 intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; 1190 } 1191 1192 static void i830_pipes_power_well_sync_hw(struct intel_display *display, 1193 struct i915_power_well *power_well) 1194 { 1195 if (intel_power_well_refcount(power_well) > 0) 1196 i830_pipes_power_well_enable(display, power_well); 1197 else 1198 i830_pipes_power_well_disable(display, power_well); 1199 } 1200 1201 static void vlv_set_power_well(struct intel_display *display, 1202 struct i915_power_well *power_well, bool enable) 1203 { 1204 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1205 u32 mask; 1206 u32 state; 1207 u32 ctrl; 1208 u32 val; 1209 int ret; 1210 1211 mask = PUNIT_PWRGT_MASK(pw_idx); 1212 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : 1213 PUNIT_PWRGT_PWR_GATE(pw_idx); 1214 1215 vlv_punit_get(display); 1216 1217 val = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS); 1218 if ((val & mask) == state) 1219 goto out; 1220 1221 ctrl = vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL); 1222 ctrl &= ~mask; 1223 ctrl |= state; 1224 vlv_punit_write(display, PUNIT_REG_PWRGT_CTRL, ctrl); 1225 1226 ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS), 1227 (val & mask) == state, 1228 500, 100 * 1000, false); 1229 if (ret) 1230 drm_err(display->drm, 1231 "timeout setting power well state %08x (%08x)\n", 1232 state, 1233 vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL)); 1234 1235 out: 1236 vlv_punit_put(display); 1237 } 1238 1239 static void vlv_power_well_enable(struct intel_display *display, 1240 struct i915_power_well *power_well) 1241 { 1242 vlv_set_power_well(display, power_well, true); 1243 } 1244 1245 static void vlv_power_well_disable(struct intel_display *display, 1246 struct i915_power_well *power_well) 1247 { 1248 vlv_set_power_well(display, power_well, false); 1249 } 1250 1251 static bool vlv_power_well_enabled(struct intel_display *display, 1252 struct i915_power_well *power_well) 1253 { 1254 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1255 bool enabled = false; 1256 u32 mask; 1257 u32 state; 1258 u32 ctrl; 1259 1260 mask = PUNIT_PWRGT_MASK(pw_idx); 1261 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); 1262 1263 vlv_punit_get(display); 1264 1265 state = vlv_punit_read(display, PUNIT_REG_PWRGT_STATUS) & mask; 1266 /* 1267 * We only ever set the power-on and power-gate states, anything 1268 * else is unexpected. 1269 */ 1270 drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1271 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 1272 if (state == ctrl) 1273 enabled = true; 1274 1275 /* 1276 * A transient state at this point would mean some unexpected party 1277 * is poking at the power controls too. 1278 */ 1279 ctrl = vlv_punit_read(display, PUNIT_REG_PWRGT_CTRL) & mask; 1280 drm_WARN_ON(display->drm, ctrl != state); 1281 1282 vlv_punit_put(display); 1283 1284 return enabled; 1285 } 1286 1287 static void vlv_init_display_clock_gating(struct intel_display *display) 1288 { 1289 /* 1290 * On driver load, a pipe may be active and driving a DSI display. 1291 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1292 * (and never recovering) in this case. intel_dsi_post_disable() will 1293 * clear it when we turn off the display. 1294 */ 1295 intel_de_rmw(display, VLV_DSPCLK_GATE_D, 1296 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE); 1297 1298 /* 1299 * Disable trickle feed and enable pnd deadline calculation 1300 */ 1301 intel_de_write(display, MI_ARB_VLV, 1302 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE_VLV); 1303 intel_de_write(display, CBR1_VLV, 0); 1304 1305 drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0); 1306 intel_de_write(display, RAWCLK_FREQ_VLV, 1307 DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 1308 1000)); 1309 } 1310 1311 static void vlv_display_power_well_init(struct intel_display *display) 1312 { 1313 struct intel_encoder *encoder; 1314 enum pipe pipe; 1315 1316 /* 1317 * Enable the CRI clock source so we can get at the 1318 * display and the reference clock for VGA 1319 * hotplug / manual detection. Supposedly DSI also 1320 * needs the ref clock up and running. 1321 * 1322 * CHV DPLL B/C have some issues if VGA mode is enabled. 1323 */ 1324 for_each_pipe(display, pipe) { 1325 u32 val = intel_de_read(display, DPLL(display, pipe)); 1326 1327 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1328 if (pipe != PIPE_A) 1329 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1330 1331 intel_de_write(display, DPLL(display, pipe), val); 1332 } 1333 1334 vlv_init_display_clock_gating(display); 1335 1336 valleyview_enable_display_irqs(display); 1337 1338 /* 1339 * During driver initialization/resume we can avoid restoring the 1340 * part of the HW/SW state that will be inited anyway explicitly. 1341 */ 1342 if (display->power.domains.initializing) 1343 return; 1344 1345 intel_hpd_init(display); 1346 intel_hpd_poll_disable(display); 1347 1348 /* Re-enable the ADPA, if we have one */ 1349 for_each_intel_encoder(display->drm, encoder) { 1350 if (encoder->type == INTEL_OUTPUT_ANALOG) 1351 intel_crt_reset(&encoder->base); 1352 } 1353 1354 intel_vga_disable(display); 1355 1356 intel_pps_unlock_regs_wa(display); 1357 } 1358 1359 static void vlv_display_power_well_deinit(struct intel_display *display) 1360 { 1361 valleyview_disable_display_irqs(display); 1362 1363 /* make sure we're done processing display irqs */ 1364 intel_parent_irq_synchronize(display); 1365 1366 vlv_pps_reset_all(display); 1367 1368 /* Prevent us from re-enabling polling on accident in late suspend */ 1369 if (!display->drm->dev->power.is_suspended) 1370 intel_hpd_poll_enable(display); 1371 } 1372 1373 static void vlv_display_power_well_enable(struct intel_display *display, 1374 struct i915_power_well *power_well) 1375 { 1376 vlv_set_power_well(display, power_well, true); 1377 1378 vlv_display_power_well_init(display); 1379 } 1380 1381 static void vlv_display_power_well_disable(struct intel_display *display, 1382 struct i915_power_well *power_well) 1383 { 1384 vlv_display_power_well_deinit(display); 1385 1386 vlv_set_power_well(display, power_well, false); 1387 } 1388 1389 static void vlv_dpio_cmn_power_well_enable(struct intel_display *display, 1390 struct i915_power_well *power_well) 1391 { 1392 /* since ref/cri clock was enabled */ 1393 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1394 1395 vlv_set_power_well(display, power_well, true); 1396 1397 /* 1398 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1399 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1400 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1401 * b. The other bits such as sfr settings / modesel may all 1402 * be set to 0. 1403 * 1404 * This should only be done on init and resume from S3 with 1405 * both PLLs disabled, or we risk losing DPIO and PLL 1406 * synchronization. 1407 */ 1408 intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST); 1409 } 1410 1411 static void vlv_dpio_cmn_power_well_disable(struct intel_display *display, 1412 struct i915_power_well *power_well) 1413 { 1414 enum pipe pipe; 1415 1416 for_each_pipe(display, pipe) 1417 assert_pll_disabled(display, pipe); 1418 1419 /* Assert common reset */ 1420 intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); 1421 1422 vlv_set_power_well(display, power_well, false); 1423 } 1424 1425 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1426 1427 static void assert_chv_phy_status(struct intel_display *display) 1428 { 1429 struct i915_power_well *cmn_bc = 1430 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1431 struct i915_power_well *cmn_d = 1432 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1433 u32 phy_control = display->power.chv_phy_control; 1434 u32 phy_status = 0; 1435 u32 phy_status_mask = 0xffffffff; 1436 u32 val; 1437 1438 /* 1439 * The BIOS can leave the PHY is some weird state 1440 * where it doesn't fully power down some parts. 1441 * Disable the asserts until the PHY has been fully 1442 * reset (ie. the power well has been disabled at 1443 * least once). 1444 */ 1445 if (!display->power.chv_phy_assert[DPIO_PHY0]) 1446 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1447 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1448 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1449 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1450 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1451 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1452 1453 if (!display->power.chv_phy_assert[DPIO_PHY1]) 1454 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1455 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1456 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1457 1458 if (intel_power_well_is_enabled(display, cmn_bc)) { 1459 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1460 1461 /* this assumes override is only used to enable lanes */ 1462 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1463 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1464 1465 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1466 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1467 1468 /* CL1 is on whenever anything is on in either channel */ 1469 if (BITS_SET(phy_control, 1470 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1471 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1472 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1473 1474 /* 1475 * The DPLLB check accounts for the pipe B + port A usage 1476 * with CL2 powered up but all the lanes in the second channel 1477 * powered down. 1478 */ 1479 if (BITS_SET(phy_control, 1480 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1481 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1482 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1483 1484 if (BITS_SET(phy_control, 1485 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1486 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1487 if (BITS_SET(phy_control, 1488 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1489 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1490 1491 if (BITS_SET(phy_control, 1492 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1493 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1494 if (BITS_SET(phy_control, 1495 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1496 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1497 } 1498 1499 if (intel_power_well_is_enabled(display, cmn_d)) { 1500 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1501 1502 /* this assumes override is only used to enable lanes */ 1503 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1504 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1505 1506 if (BITS_SET(phy_control, 1507 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1508 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1509 1510 if (BITS_SET(phy_control, 1511 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1512 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1513 if (BITS_SET(phy_control, 1514 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1515 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1516 } 1517 1518 phy_status &= phy_status_mask; 1519 1520 /* 1521 * The PHY may be busy with some initial calibration and whatnot, 1522 * so the power state can take a while to actually change. 1523 */ 1524 if (intel_de_wait_ms(display, DISPLAY_PHY_STATUS, 1525 phy_status_mask, phy_status, 10, &val)) 1526 drm_err(display->drm, 1527 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1528 val & phy_status_mask, phy_status, display->power.chv_phy_control); 1529 } 1530 1531 #undef BITS_SET 1532 1533 static void chv_dpio_cmn_power_well_enable(struct intel_display *display, 1534 struct i915_power_well *power_well) 1535 { 1536 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1537 enum dpio_phy phy; 1538 u32 tmp; 1539 1540 drm_WARN_ON_ONCE(display->drm, 1541 id != VLV_DISP_PW_DPIO_CMN_BC && 1542 id != CHV_DISP_PW_DPIO_CMN_D); 1543 1544 if (id == VLV_DISP_PW_DPIO_CMN_BC) 1545 phy = DPIO_PHY0; 1546 else 1547 phy = DPIO_PHY1; 1548 1549 /* since ref/cri clock was enabled */ 1550 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1551 vlv_set_power_well(display, power_well, true); 1552 1553 /* Poll for phypwrgood signal */ 1554 if (intel_de_wait_for_set_ms(display, DISPLAY_PHY_STATUS, 1555 PHY_POWERGOOD(phy), 1)) 1556 drm_err(display->drm, "Display PHY %d is not power up\n", 1557 phy); 1558 1559 vlv_dpio_get(display); 1560 1561 /* Enable dynamic power down */ 1562 tmp = vlv_dpio_read(display, phy, CHV_CMN_DW28); 1563 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1564 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1565 vlv_dpio_write(display, phy, CHV_CMN_DW28, tmp); 1566 1567 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1568 tmp = vlv_dpio_read(display, phy, CHV_CMN_DW6_CH1); 1569 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1570 vlv_dpio_write(display, phy, CHV_CMN_DW6_CH1, tmp); 1571 } else { 1572 /* 1573 * Force the non-existing CL2 off. BXT does this 1574 * too, so maybe it saves some power even though 1575 * CL2 doesn't exist? 1576 */ 1577 tmp = vlv_dpio_read(display, phy, CHV_CMN_DW30); 1578 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1579 vlv_dpio_write(display, phy, CHV_CMN_DW30, tmp); 1580 } 1581 1582 vlv_dpio_put(display); 1583 1584 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1585 intel_de_write(display, DISPLAY_PHY_CONTROL, 1586 display->power.chv_phy_control); 1587 1588 drm_dbg_kms(display->drm, 1589 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1590 phy, display->power.chv_phy_control); 1591 1592 assert_chv_phy_status(display); 1593 } 1594 1595 static void chv_dpio_cmn_power_well_disable(struct intel_display *display, 1596 struct i915_power_well *power_well) 1597 { 1598 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1599 enum dpio_phy phy; 1600 1601 drm_WARN_ON_ONCE(display->drm, 1602 id != VLV_DISP_PW_DPIO_CMN_BC && 1603 id != CHV_DISP_PW_DPIO_CMN_D); 1604 1605 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1606 phy = DPIO_PHY0; 1607 assert_pll_disabled(display, PIPE_A); 1608 assert_pll_disabled(display, PIPE_B); 1609 } else { 1610 phy = DPIO_PHY1; 1611 assert_pll_disabled(display, PIPE_C); 1612 } 1613 1614 display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1615 intel_de_write(display, DISPLAY_PHY_CONTROL, 1616 display->power.chv_phy_control); 1617 1618 vlv_set_power_well(display, power_well, false); 1619 1620 drm_dbg_kms(display->drm, 1621 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1622 phy, display->power.chv_phy_control); 1623 1624 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1625 display->power.chv_phy_assert[phy] = true; 1626 1627 assert_chv_phy_status(display); 1628 } 1629 1630 static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy, 1631 enum dpio_channel ch, bool override, unsigned int mask) 1632 { 1633 u32 reg, val, expected, actual; 1634 1635 /* 1636 * The BIOS can leave the PHY is some weird state 1637 * where it doesn't fully power down some parts. 1638 * Disable the asserts until the PHY has been fully 1639 * reset (ie. the power well has been disabled at 1640 * least once). 1641 */ 1642 if (!display->power.chv_phy_assert[phy]) 1643 return; 1644 1645 if (ch == DPIO_CH0) 1646 reg = CHV_CMN_DW0_CH0; 1647 else 1648 reg = CHV_CMN_DW6_CH1; 1649 1650 vlv_dpio_get(display); 1651 val = vlv_dpio_read(display, phy, reg); 1652 vlv_dpio_put(display); 1653 1654 /* 1655 * This assumes !override is only used when the port is disabled. 1656 * All lanes should power down even without the override when 1657 * the port is disabled. 1658 */ 1659 if (!override || mask == 0xf) { 1660 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1661 /* 1662 * If CH1 common lane is not active anymore 1663 * (eg. for pipe B DPLL) the entire channel will 1664 * shut down, which causes the common lane registers 1665 * to read as 0. That means we can't actually check 1666 * the lane power down status bits, but as the entire 1667 * register reads as 0 it's a good indication that the 1668 * channel is indeed entirely powered down. 1669 */ 1670 if (ch == DPIO_CH1 && val == 0) 1671 expected = 0; 1672 } else if (mask != 0x0) { 1673 expected = DPIO_ANYDL_POWERDOWN; 1674 } else { 1675 expected = 0; 1676 } 1677 1678 if (ch == DPIO_CH0) 1679 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 | 1680 DPIO_ALLDL_POWERDOWN_CH0, val); 1681 else 1682 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 | 1683 DPIO_ALLDL_POWERDOWN_CH1, val); 1684 1685 drm_WARN(display->drm, actual != expected, 1686 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1687 !!(actual & DPIO_ALLDL_POWERDOWN), 1688 !!(actual & DPIO_ANYDL_POWERDOWN), 1689 !!(expected & DPIO_ALLDL_POWERDOWN), 1690 !!(expected & DPIO_ANYDL_POWERDOWN), 1691 reg, val); 1692 } 1693 1694 bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy, 1695 enum dpio_channel ch, bool override) 1696 { 1697 struct i915_power_domains *power_domains = &display->power.domains; 1698 bool was_override; 1699 1700 mutex_lock(&power_domains->lock); 1701 1702 was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1703 1704 if (override == was_override) 1705 goto out; 1706 1707 if (override) 1708 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1709 else 1710 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1711 1712 intel_de_write(display, DISPLAY_PHY_CONTROL, 1713 display->power.chv_phy_control); 1714 1715 drm_dbg_kms(display->drm, 1716 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1717 phy, ch, display->power.chv_phy_control); 1718 1719 assert_chv_phy_status(display); 1720 1721 out: 1722 mutex_unlock(&power_domains->lock); 1723 1724 return was_override; 1725 } 1726 1727 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1728 bool override, unsigned int mask) 1729 { 1730 struct intel_display *display = to_intel_display(encoder); 1731 struct i915_power_domains *power_domains = &display->power.domains; 1732 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1733 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 1734 1735 mutex_lock(&power_domains->lock); 1736 1737 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1738 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1739 1740 if (override) 1741 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1742 else 1743 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1744 1745 intel_de_write(display, DISPLAY_PHY_CONTROL, 1746 display->power.chv_phy_control); 1747 1748 drm_dbg_kms(display->drm, 1749 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1750 phy, ch, mask, display->power.chv_phy_control); 1751 1752 assert_chv_phy_status(display); 1753 1754 assert_chv_phy_powergate(display, phy, ch, override, mask); 1755 1756 mutex_unlock(&power_domains->lock); 1757 } 1758 1759 static bool chv_pipe_power_well_enabled(struct intel_display *display, 1760 struct i915_power_well *power_well) 1761 { 1762 enum pipe pipe = PIPE_A; 1763 bool enabled; 1764 u32 state, ctrl; 1765 1766 vlv_punit_get(display); 1767 1768 state = vlv_punit_read(display, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); 1769 /* 1770 * We only ever set the power-on and power-gate states, anything 1771 * else is unexpected. 1772 */ 1773 drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) && 1774 state != DP_SSS_PWR_GATE(pipe)); 1775 enabled = state == DP_SSS_PWR_ON(pipe); 1776 1777 /* 1778 * A transient state at this point would mean some unexpected party 1779 * is poking at the power controls too. 1780 */ 1781 ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); 1782 drm_WARN_ON(display->drm, ctrl << 16 != state); 1783 1784 vlv_punit_put(display); 1785 1786 return enabled; 1787 } 1788 1789 static void chv_set_pipe_power_well(struct intel_display *display, 1790 struct i915_power_well *power_well, 1791 bool enable) 1792 { 1793 enum pipe pipe = PIPE_A; 1794 u32 state; 1795 u32 ctrl; 1796 int ret; 1797 1798 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1799 1800 vlv_punit_get(display); 1801 1802 ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM); 1803 if ((ctrl & DP_SSS_MASK(pipe)) == state) 1804 goto out; 1805 1806 ctrl &= ~DP_SSC_MASK(pipe); 1807 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1808 vlv_punit_write(display, PUNIT_REG_DSPSSPM, ctrl); 1809 1810 ret = poll_timeout_us(ctrl = vlv_punit_read(display, PUNIT_REG_DSPSSPM), 1811 (ctrl & DP_SSS_MASK(pipe)) == state, 1812 500, 100 * 1000, false); 1813 if (ret) 1814 drm_err(display->drm, 1815 "timeout setting power well state %08x (%08x)\n", 1816 state, 1817 vlv_punit_read(display, PUNIT_REG_DSPSSPM)); 1818 1819 #undef COND 1820 1821 out: 1822 vlv_punit_put(display); 1823 } 1824 1825 static void chv_pipe_power_well_sync_hw(struct intel_display *display, 1826 struct i915_power_well *power_well) 1827 { 1828 intel_de_write(display, DISPLAY_PHY_CONTROL, 1829 display->power.chv_phy_control); 1830 } 1831 1832 static void chv_pipe_power_well_enable(struct intel_display *display, 1833 struct i915_power_well *power_well) 1834 { 1835 chv_set_pipe_power_well(display, power_well, true); 1836 1837 vlv_display_power_well_init(display); 1838 } 1839 1840 static void chv_pipe_power_well_disable(struct intel_display *display, 1841 struct i915_power_well *power_well) 1842 { 1843 vlv_display_power_well_deinit(display); 1844 1845 chv_set_pipe_power_well(display, power_well, false); 1846 } 1847 1848 static void 1849 tgl_tc_cold_request(struct intel_display *display, bool block) 1850 { 1851 u8 tries = 0; 1852 int ret; 1853 1854 while (1) { 1855 u32 low_val; 1856 u32 high_val = 0; 1857 1858 if (block) 1859 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ; 1860 else 1861 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ; 1862 1863 /* 1864 * Spec states that we should timeout the request after 200us 1865 * but the function below will timeout after 500us 1866 */ 1867 ret = intel_parent_pcode_read(display, TGL_PCODE_TCCOLD, &low_val, &high_val); 1868 if (ret == 0) { 1869 if (block && 1870 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED)) 1871 ret = -EIO; 1872 else 1873 break; 1874 } 1875 1876 if (++tries == 3) 1877 break; 1878 1879 msleep(1); 1880 } 1881 1882 if (ret) 1883 drm_err(display->drm, "TC cold %sblock failed\n", block ? "" : "un"); 1884 else 1885 drm_dbg_kms(display->drm, "TC cold %sblock succeeded\n", 1886 block ? "" : "un"); 1887 } 1888 1889 static void 1890 tgl_tc_cold_off_power_well_enable(struct intel_display *display, 1891 struct i915_power_well *power_well) 1892 { 1893 tgl_tc_cold_request(display, true); 1894 } 1895 1896 static void 1897 tgl_tc_cold_off_power_well_disable(struct intel_display *display, 1898 struct i915_power_well *power_well) 1899 { 1900 tgl_tc_cold_request(display, false); 1901 } 1902 1903 static void 1904 tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display, 1905 struct i915_power_well *power_well) 1906 { 1907 if (intel_power_well_refcount(power_well) > 0) 1908 tgl_tc_cold_off_power_well_enable(display, power_well); 1909 else 1910 tgl_tc_cold_off_power_well_disable(display, power_well); 1911 } 1912 1913 static bool 1914 tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display, 1915 struct i915_power_well *power_well) 1916 { 1917 /* 1918 * Not the correctly implementation but there is no way to just read it 1919 * from PCODE, so returning count to avoid state mismatch errors 1920 */ 1921 return intel_power_well_refcount(power_well); 1922 } 1923 1924 static void xelpdp_aux_power_well_enable(struct intel_display *display, 1925 struct i915_power_well *power_well) 1926 { 1927 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1928 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1929 1930 if (icl_aux_pw_is_tc_phy(display, power_well)) 1931 icl_tc_port_assert_ref_held(display, power_well, 1932 aux_ch_to_digital_port(display, aux_ch)); 1933 1934 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1935 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1936 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1937 1938 if (HAS_LT_PHY(display)) { 1939 if (intel_de_wait_for_set_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1940 XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2)) 1941 drm_warn(display->drm, 1942 "Timeout waiting for PHY %c AUX channel power to be up\n", 1943 phy_name(phy)); 1944 } else { 1945 /* 1946 * The power status flag cannot be used to determine whether aux 1947 * power wells have finished powering up. Instead we're 1948 * expected to just wait a fixed 600us after raising the request 1949 * bit. 1950 */ 1951 usleep_range(600, 1200); 1952 } 1953 } 1954 1955 static void xelpdp_aux_power_well_disable(struct intel_display *display, 1956 struct i915_power_well *power_well) 1957 { 1958 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1959 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1960 1961 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1962 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1963 0); 1964 1965 if (HAS_LT_PHY(display)) { 1966 if (intel_de_wait_for_clear_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1967 XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1)) 1968 drm_warn(display->drm, 1969 "Timeout waiting for PHY %c AUX channel to powerdown\n", 1970 phy_name(phy)); 1971 } else { 1972 usleep_range(10, 30); 1973 } 1974 } 1975 1976 static bool xelpdp_aux_power_well_enabled(struct intel_display *display, 1977 struct i915_power_well *power_well) 1978 { 1979 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1980 1981 return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) & 1982 XELPDP_DP_AUX_CH_CTL_POWER_STATUS; 1983 } 1984 1985 static void xe2lpd_pica_power_well_enable(struct intel_display *display, 1986 struct i915_power_well *power_well) 1987 { 1988 intel_de_write(display, XE2LPD_PICA_PW_CTL, 1989 XE2LPD_PICA_CTL_POWER_REQUEST); 1990 1991 if (intel_de_wait_for_set_ms(display, XE2LPD_PICA_PW_CTL, 1992 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1993 drm_dbg_kms(display->drm, "pica power well enable timeout\n"); 1994 1995 drm_WARN(display->drm, 1, "Power well PICA timeout when enabled"); 1996 } 1997 } 1998 1999 static void xe2lpd_pica_power_well_disable(struct intel_display *display, 2000 struct i915_power_well *power_well) 2001 { 2002 intel_de_write(display, XE2LPD_PICA_PW_CTL, 0); 2003 2004 if (intel_de_wait_for_clear_ms(display, XE2LPD_PICA_PW_CTL, 2005 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 2006 drm_dbg_kms(display->drm, "pica power well disable timeout\n"); 2007 2008 drm_WARN(display->drm, 1, "Power well PICA timeout when disabled"); 2009 } 2010 } 2011 2012 static bool xe2lpd_pica_power_well_enabled(struct intel_display *display, 2013 struct i915_power_well *power_well) 2014 { 2015 return intel_de_read(display, XE2LPD_PICA_PW_CTL) & 2016 XE2LPD_PICA_CTL_POWER_STATUS; 2017 } 2018 2019 const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 2020 .sync_hw = i9xx_power_well_sync_hw_noop, 2021 .enable = i9xx_always_on_power_well_noop, 2022 .disable = i9xx_always_on_power_well_noop, 2023 .is_enabled = i9xx_always_on_power_well_enabled, 2024 }; 2025 2026 const struct i915_power_well_ops chv_pipe_power_well_ops = { 2027 .sync_hw = chv_pipe_power_well_sync_hw, 2028 .enable = chv_pipe_power_well_enable, 2029 .disable = chv_pipe_power_well_disable, 2030 .is_enabled = chv_pipe_power_well_enabled, 2031 }; 2032 2033 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 2034 .sync_hw = i9xx_power_well_sync_hw_noop, 2035 .enable = chv_dpio_cmn_power_well_enable, 2036 .disable = chv_dpio_cmn_power_well_disable, 2037 .is_enabled = vlv_power_well_enabled, 2038 }; 2039 2040 const struct i915_power_well_ops i830_pipes_power_well_ops = { 2041 .sync_hw = i830_pipes_power_well_sync_hw, 2042 .enable = i830_pipes_power_well_enable, 2043 .disable = i830_pipes_power_well_disable, 2044 .is_enabled = i830_pipes_power_well_enabled, 2045 }; 2046 2047 static const struct i915_power_well_regs hsw_power_well_regs = { 2048 .bios = HSW_PWR_WELL_CTL1, 2049 .driver = HSW_PWR_WELL_CTL2, 2050 .kvmr = HSW_PWR_WELL_CTL3, 2051 .debug = HSW_PWR_WELL_CTL4, 2052 }; 2053 2054 const struct i915_power_well_ops hsw_power_well_ops = { 2055 .regs = &hsw_power_well_regs, 2056 .sync_hw = hsw_power_well_sync_hw, 2057 .enable = hsw_power_well_enable, 2058 .disable = hsw_power_well_disable, 2059 .is_enabled = hsw_power_well_enabled, 2060 }; 2061 2062 const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 2063 .sync_hw = i9xx_power_well_sync_hw_noop, 2064 .enable = gen9_dc_off_power_well_enable, 2065 .disable = gen9_dc_off_power_well_disable, 2066 .is_enabled = gen9_dc_off_power_well_enabled, 2067 }; 2068 2069 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 2070 .sync_hw = i9xx_power_well_sync_hw_noop, 2071 .enable = bxt_dpio_cmn_power_well_enable, 2072 .disable = bxt_dpio_cmn_power_well_disable, 2073 .is_enabled = bxt_dpio_cmn_power_well_enabled, 2074 }; 2075 2076 const struct i915_power_well_ops vlv_display_power_well_ops = { 2077 .sync_hw = i9xx_power_well_sync_hw_noop, 2078 .enable = vlv_display_power_well_enable, 2079 .disable = vlv_display_power_well_disable, 2080 .is_enabled = vlv_power_well_enabled, 2081 }; 2082 2083 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 2084 .sync_hw = i9xx_power_well_sync_hw_noop, 2085 .enable = vlv_dpio_cmn_power_well_enable, 2086 .disable = vlv_dpio_cmn_power_well_disable, 2087 .is_enabled = vlv_power_well_enabled, 2088 }; 2089 2090 const struct i915_power_well_ops vlv_dpio_power_well_ops = { 2091 .sync_hw = i9xx_power_well_sync_hw_noop, 2092 .enable = vlv_power_well_enable, 2093 .disable = vlv_power_well_disable, 2094 .is_enabled = vlv_power_well_enabled, 2095 }; 2096 2097 static const struct i915_power_well_regs icl_aux_power_well_regs = { 2098 .bios = ICL_PWR_WELL_CTL_AUX1, 2099 .driver = ICL_PWR_WELL_CTL_AUX2, 2100 .debug = ICL_PWR_WELL_CTL_AUX4, 2101 }; 2102 2103 const struct i915_power_well_ops icl_aux_power_well_ops = { 2104 .regs = &icl_aux_power_well_regs, 2105 .sync_hw = hsw_power_well_sync_hw, 2106 .enable = icl_aux_power_well_enable, 2107 .disable = icl_aux_power_well_disable, 2108 .is_enabled = hsw_power_well_enabled, 2109 }; 2110 2111 static const struct i915_power_well_regs icl_ddi_power_well_regs = { 2112 .bios = ICL_PWR_WELL_CTL_DDI1, 2113 .driver = ICL_PWR_WELL_CTL_DDI2, 2114 .debug = ICL_PWR_WELL_CTL_DDI4, 2115 }; 2116 2117 const struct i915_power_well_ops icl_ddi_power_well_ops = { 2118 .regs = &icl_ddi_power_well_regs, 2119 .sync_hw = hsw_power_well_sync_hw, 2120 .enable = hsw_power_well_enable, 2121 .disable = hsw_power_well_disable, 2122 .is_enabled = hsw_power_well_enabled, 2123 }; 2124 2125 const struct i915_power_well_ops tgl_tc_cold_off_ops = { 2126 .sync_hw = tgl_tc_cold_off_power_well_sync_hw, 2127 .enable = tgl_tc_cold_off_power_well_enable, 2128 .disable = tgl_tc_cold_off_power_well_disable, 2129 .is_enabled = tgl_tc_cold_off_power_well_is_enabled, 2130 }; 2131 2132 const struct i915_power_well_ops xelpdp_aux_power_well_ops = { 2133 .sync_hw = i9xx_power_well_sync_hw_noop, 2134 .enable = xelpdp_aux_power_well_enable, 2135 .disable = xelpdp_aux_power_well_disable, 2136 .is_enabled = xelpdp_aux_power_well_enabled, 2137 }; 2138 2139 const struct i915_power_well_ops xe2lpd_pica_power_well_ops = { 2140 .sync_hw = i9xx_power_well_sync_hw_noop, 2141 .enable = xe2lpd_pica_power_well_enable, 2142 .disable = xe2lpd_pica_power_well_disable, 2143 .is_enabled = xe2lpd_pica_power_well_enabled, 2144 }; 2145