1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <linux/iopoll.h> 7 8 #include <drm/drm_print.h> 9 10 #include "i915_reg.h" 11 #include "intel_backlight_regs.h" 12 #include "intel_combo_phy.h" 13 #include "intel_combo_phy_regs.h" 14 #include "intel_crt.h" 15 #include "intel_de.h" 16 #include "intel_display_irq.h" 17 #include "intel_display_power_well.h" 18 #include "intel_display_regs.h" 19 #include "intel_display_rpm.h" 20 #include "intel_display_types.h" 21 #include "intel_dkl_phy.h" 22 #include "intel_dkl_phy_regs.h" 23 #include "intel_dmc.h" 24 #include "intel_dmc_wl.h" 25 #include "intel_dp_aux_regs.h" 26 #include "intel_dpio_phy.h" 27 #include "intel_dpll.h" 28 #include "intel_hotplug.h" 29 #include "intel_parent.h" 30 #include "intel_pcode.h" 31 #include "intel_pps.h" 32 #include "intel_psr.h" 33 #include "intel_tc.h" 34 #include "intel_vga.h" 35 #include "skl_watermark.h" 36 #include "vlv_dpio_phy_regs.h" 37 #include "vlv_iosf_sb_reg.h" 38 #include "vlv_sideband.h" 39 40 /* 41 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 42 * 43 * {ICL,SKL}_DISP_PW1_IDX..{ICL,SKL}_DISP_PW4_IDX -> PG1..PG4 44 */ 45 static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx) 46 { 47 int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1; 48 49 return pw_idx - pw1_idx + SKL_PG1; 50 } 51 52 struct i915_power_well_regs { 53 i915_reg_t bios; 54 i915_reg_t driver; 55 i915_reg_t kvmr; 56 i915_reg_t debug; 57 }; 58 59 struct i915_power_well_ops { 60 const struct i915_power_well_regs *regs; 61 /* 62 * Synchronize the well's hw state to match the current sw state, for 63 * example enable/disable it based on the current refcount. Called 64 * during driver init and resume time, possibly after first calling 65 * the enable/disable handlers. 66 */ 67 void (*sync_hw)(struct intel_display *display, 68 struct i915_power_well *power_well); 69 /* 70 * Enable the well and resources that depend on it (for example 71 * interrupts located on the well). Called after the 0->1 refcount 72 * transition. 73 */ 74 void (*enable)(struct intel_display *display, 75 struct i915_power_well *power_well); 76 /* 77 * Disable the well and resources that depend on it. Called after 78 * the 1->0 refcount transition. 79 */ 80 void (*disable)(struct intel_display *display, 81 struct i915_power_well *power_well); 82 /* Returns the hw enabled state. */ 83 bool (*is_enabled)(struct intel_display *display, 84 struct i915_power_well *power_well); 85 }; 86 87 static const struct i915_power_well_instance * 88 i915_power_well_instance(const struct i915_power_well *power_well) 89 { 90 return &power_well->desc->instances->list[power_well->instance_idx]; 91 } 92 93 struct i915_power_well * 94 lookup_power_well(struct intel_display *display, 95 enum i915_power_well_id power_well_id) 96 { 97 struct i915_power_well *power_well; 98 99 for_each_power_well(display, power_well) 100 if (i915_power_well_instance(power_well)->id == power_well_id) 101 return power_well; 102 103 /* 104 * It's not feasible to add error checking code to the callers since 105 * this condition really shouldn't happen and it doesn't even make sense 106 * to abort things like display initialization sequences. Just return 107 * the first power well and hope the WARN gets reported so we can fix 108 * our driver. 109 */ 110 drm_WARN(display->drm, 1, 111 "Power well %d not defined for this platform\n", 112 power_well_id); 113 return &display->power.domains.power_wells[0]; 114 } 115 116 void intel_power_well_enable(struct intel_display *display, 117 struct i915_power_well *power_well) 118 { 119 drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well)); 120 power_well->desc->ops->enable(display, power_well); 121 power_well->hw_enabled = true; 122 } 123 124 void intel_power_well_disable(struct intel_display *display, 125 struct i915_power_well *power_well) 126 { 127 drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well)); 128 power_well->hw_enabled = false; 129 power_well->desc->ops->disable(display, power_well); 130 } 131 132 void intel_power_well_sync_hw(struct intel_display *display, 133 struct i915_power_well *power_well) 134 { 135 power_well->desc->ops->sync_hw(display, power_well); 136 power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well); 137 } 138 139 void intel_power_well_get(struct intel_display *display, 140 struct i915_power_well *power_well) 141 { 142 if (!power_well->count++) 143 intel_power_well_enable(display, power_well); 144 } 145 146 void intel_power_well_put(struct intel_display *display, 147 struct i915_power_well *power_well) 148 { 149 drm_WARN(display->drm, !power_well->count, 150 "Use count on power well %s is already zero", 151 i915_power_well_instance(power_well)->name); 152 153 if (!--power_well->count) 154 intel_power_well_disable(display, power_well); 155 } 156 157 bool intel_power_well_is_enabled(struct intel_display *display, 158 struct i915_power_well *power_well) 159 { 160 return power_well->desc->ops->is_enabled(display, power_well); 161 } 162 163 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well) 164 { 165 return power_well->hw_enabled; 166 } 167 168 bool intel_display_power_well_is_enabled(struct intel_display *display, 169 enum i915_power_well_id power_well_id) 170 { 171 struct i915_power_well *power_well; 172 173 power_well = lookup_power_well(display, power_well_id); 174 175 return intel_power_well_is_enabled(display, power_well); 176 } 177 178 bool intel_power_well_is_always_on(struct i915_power_well *power_well) 179 { 180 return power_well->desc->always_on; 181 } 182 183 const char *intel_power_well_name(struct i915_power_well *power_well) 184 { 185 return i915_power_well_instance(power_well)->name; 186 } 187 188 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well) 189 { 190 return &power_well->domains; 191 } 192 193 int intel_power_well_refcount(struct i915_power_well *power_well) 194 { 195 return power_well->count; 196 } 197 198 /* 199 * Starting with Haswell, we have a "Power Down Well" that can be turned off 200 * when not needed anymore. We have 4 registers that can request the power well 201 * to be enabled, and it will only be disabled if none of the registers is 202 * requesting it to be enabled. 203 */ 204 static void hsw_power_well_post_enable(struct intel_display *display, 205 u8 irq_pipe_mask, bool has_vga) 206 { 207 if (has_vga) 208 intel_vga_reset_io_mem(display); 209 210 if (irq_pipe_mask) 211 gen8_irq_power_well_post_enable(display, irq_pipe_mask); 212 } 213 214 static void hsw_power_well_pre_disable(struct intel_display *display, 215 u8 irq_pipe_mask) 216 { 217 if (irq_pipe_mask) 218 gen8_irq_power_well_pre_disable(display, irq_pipe_mask); 219 } 220 221 #define ICL_AUX_PW_TO_PHY(pw_idx) \ 222 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + PHY_A) 223 224 #define ICL_AUX_PW_TO_CH(pw_idx) \ 225 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) 226 227 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ 228 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) 229 230 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well) 231 { 232 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 233 234 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : 235 ICL_AUX_PW_TO_CH(pw_idx); 236 } 237 238 static struct intel_digital_port * 239 aux_ch_to_digital_port(struct intel_display *display, 240 enum aux_ch aux_ch) 241 { 242 struct intel_encoder *encoder; 243 244 for_each_intel_encoder(display->drm, encoder) { 245 struct intel_digital_port *dig_port; 246 247 /* We'll check the MST primary port */ 248 if (encoder->type == INTEL_OUTPUT_DP_MST) 249 continue; 250 251 dig_port = enc_to_dig_port(encoder); 252 253 if (dig_port && dig_port->aux_ch == aux_ch) 254 return dig_port; 255 } 256 257 return NULL; 258 } 259 260 static enum phy icl_aux_pw_to_phy(struct intel_display *display, 261 const struct i915_power_well *power_well) 262 { 263 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 264 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 265 266 /* 267 * FIXME should we care about the (VBT defined) dig_port->aux_ch 268 * relationship or should this be purely defined by the hardware layout? 269 * Currently if the port doesn't appear in the VBT, or if it's declared 270 * as HDMI-only and routed to a combo PHY, the encoder either won't be 271 * present at all or it will not have an aux_ch assigned. 272 */ 273 return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE; 274 } 275 276 static void hsw_wait_for_power_well_enable(struct intel_display *display, 277 struct i915_power_well *power_well, 278 bool timeout_expected) 279 { 280 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 281 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 282 int timeout = power_well->desc->enable_timeout ? : 1; 283 284 /* 285 * For some power wells we're not supposed to watch the status bit for 286 * an ack, but rather just wait a fixed amount of time and then 287 * proceed. This is only used on DG2. 288 */ 289 if (display->platform.dg2 && power_well->desc->fixed_enable_delay) { 290 usleep_range(600, 1200); 291 return; 292 } 293 294 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 295 if (intel_de_wait_for_set_ms(display, regs->driver, 296 HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) { 297 drm_dbg_kms(display->drm, "%s power well enable timeout\n", 298 intel_power_well_name(power_well)); 299 300 drm_WARN_ON(display->drm, !timeout_expected); 301 302 } 303 } 304 305 static u32 hsw_power_well_requesters(struct intel_display *display, 306 const struct i915_power_well_regs *regs, 307 int pw_idx) 308 { 309 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 310 u32 ret; 311 312 ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0; 313 ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0; 314 if (regs->kvmr.reg) 315 ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0; 316 ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0; 317 318 return ret; 319 } 320 321 static void hsw_wait_for_power_well_disable(struct intel_display *display, 322 struct i915_power_well *power_well) 323 { 324 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 325 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 326 u32 reqs; 327 int ret; 328 329 /* 330 * Bspec doesn't require waiting for PWs to get disabled, but still do 331 * this for paranoia. The known cases where a PW will be forced on: 332 * - a KVMR request on any power well via the KVMR request register 333 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 334 * DEBUG request registers 335 * Skip the wait in case any of the request bits are set and print a 336 * diagnostic message. 337 */ 338 reqs = hsw_power_well_requesters(display, regs, pw_idx); 339 340 ret = intel_de_wait_for_clear_ms(display, regs->driver, 341 HSW_PWR_WELL_CTL_STATE(pw_idx), 342 reqs ? 0 : 1); 343 if (!ret) 344 return; 345 346 /* Refresh requesters in case they popped up during the wait. */ 347 if (!reqs) 348 reqs = hsw_power_well_requesters(display, regs, pw_idx); 349 350 drm_dbg_kms(display->drm, 351 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 352 intel_power_well_name(power_well), 353 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 354 } 355 356 static void gen9_wait_for_power_well_fuses(struct intel_display *display, 357 enum skl_power_gate pg) 358 { 359 /* Timeout 5us for PG#0, for other PGs 1us */ 360 drm_WARN_ON(display->drm, 361 intel_de_wait_for_set_ms(display, SKL_FUSE_STATUS, 362 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 363 } 364 365 static void hsw_power_well_enable(struct intel_display *display, 366 struct i915_power_well *power_well) 367 { 368 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 369 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 370 371 if (power_well->desc->has_fuses) { 372 enum skl_power_gate pg; 373 374 pg = pw_idx_to_pg(display, pw_idx); 375 376 /* Wa_16013190616:adlp */ 377 if (display->platform.alderlake_p && pg == SKL_PG1) 378 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 379 380 /* 381 * For PW1 we have to wait both for the PW0/PG0 fuse state 382 * before enabling the power well and PW1/PG1's own fuse 383 * state after the enabling. For all other power wells with 384 * fuses we only have to wait for that PW/PG's fuse state 385 * after the enabling. 386 */ 387 if (pg == SKL_PG1) 388 gen9_wait_for_power_well_fuses(display, SKL_PG0); 389 } 390 391 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 392 393 hsw_wait_for_power_well_enable(display, power_well, false); 394 395 if (power_well->desc->has_fuses) { 396 enum skl_power_gate pg; 397 398 pg = pw_idx_to_pg(display, pw_idx); 399 400 gen9_wait_for_power_well_fuses(display, pg); 401 } 402 403 hsw_power_well_post_enable(display, 404 power_well->desc->irq_pipe_mask, 405 power_well->desc->has_vga); 406 } 407 408 static void hsw_power_well_disable(struct intel_display *display, 409 struct i915_power_well *power_well) 410 { 411 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 412 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 413 414 hsw_power_well_pre_disable(display, 415 power_well->desc->irq_pipe_mask); 416 417 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 418 hsw_wait_for_power_well_disable(display, power_well); 419 } 420 421 static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch) 422 { 423 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 424 425 return dig_port && dig_port->base.type == INTEL_OUTPUT_EDP; 426 } 427 428 static void 429 icl_combo_phy_aux_power_well_enable(struct intel_display *display, 430 struct i915_power_well *power_well) 431 { 432 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 433 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 434 435 drm_WARN_ON(display->drm, !display->platform.icelake); 436 437 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 438 439 /* 440 * FIXME not sure if we should derive the PHY from the pw_idx, or 441 * from the VBT defined AUX_CH->DDI->PHY mapping. 442 */ 443 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 444 0, ICL_LANE_ENABLE_AUX); 445 446 hsw_wait_for_power_well_enable(display, power_well, false); 447 448 /* Display WA #1178: icl */ 449 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && 450 !intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx))) 451 intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), 452 0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI); 453 } 454 455 static void 456 icl_combo_phy_aux_power_well_disable(struct intel_display *display, 457 struct i915_power_well *power_well) 458 { 459 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 460 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 461 462 drm_WARN_ON(display->drm, !display->platform.icelake); 463 464 /* 465 * FIXME not sure if we should derive the PHY from the pw_idx, or 466 * from the VBT defined AUX_CH->DDI->PHY mapping. 467 */ 468 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 469 ICL_LANE_ENABLE_AUX, 0); 470 471 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 472 473 hsw_wait_for_power_well_disable(display, power_well); 474 } 475 476 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 477 478 static void icl_tc_port_assert_ref_held(struct intel_display *display, 479 struct i915_power_well *power_well, 480 struct intel_digital_port *dig_port) 481 { 482 if (drm_WARN_ON(display->drm, !dig_port)) 483 return; 484 485 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 486 return; 487 488 drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port)); 489 } 490 491 #else 492 493 static void icl_tc_port_assert_ref_held(struct intel_display *display, 494 struct i915_power_well *power_well, 495 struct intel_digital_port *dig_port) 496 { 497 } 498 499 #endif 500 501 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1) 502 503 static void icl_tc_cold_exit(struct intel_display *display) 504 { 505 int ret, tries = 0; 506 507 while (1) { 508 ret = intel_pcode_write(display->drm, ICL_PCODE_EXIT_TCCOLD, 0); 509 if (ret != -EAGAIN || ++tries == 3) 510 break; 511 msleep(1); 512 } 513 514 /* Spec states that TC cold exit can take up to 1ms to complete */ 515 if (!ret) 516 msleep(1); 517 518 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */ 519 drm_dbg_kms(display->drm, "TC cold block %s\n", ret ? "failed" : 520 "succeeded"); 521 } 522 523 static void 524 icl_tc_phy_aux_power_well_enable(struct intel_display *display, 525 struct i915_power_well *power_well) 526 { 527 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 528 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 529 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 530 bool is_tbt = power_well->desc->is_tc_tbt; 531 bool timeout_expected; 532 u32 val; 533 int ret; 534 535 icl_tc_port_assert_ref_held(display, power_well, dig_port); 536 537 intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), 538 DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0); 539 540 intel_de_rmw(display, regs->driver, 541 0, 542 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); 543 544 /* 545 * An AUX timeout is expected if the TBT DP tunnel is down, 546 * or need to enable AUX on a legacy TypeC port as part of the TC-cold 547 * exit sequence. 548 */ 549 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port); 550 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 551 icl_tc_cold_exit(display); 552 553 hsw_wait_for_power_well_enable(display, power_well, timeout_expected); 554 555 if (DISPLAY_VER(display) >= 12 && !is_tbt) { 556 enum tc_port tc_port; 557 558 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); 559 560 ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)), 561 val & DKL_CMN_UC_DW27_UC_HEALTH, 562 100, 1000, false); 563 if (ret) 564 drm_warn(display->drm, "Timeout waiting TC uC health\n"); 565 } 566 } 567 568 static void 569 icl_aux_power_well_enable(struct intel_display *display, 570 struct i915_power_well *power_well) 571 { 572 enum phy phy = icl_aux_pw_to_phy(display, power_well); 573 574 if (intel_phy_is_tc(display, phy)) 575 return icl_tc_phy_aux_power_well_enable(display, power_well); 576 else if (display->platform.icelake) 577 return icl_combo_phy_aux_power_well_enable(display, 578 power_well); 579 else 580 return hsw_power_well_enable(display, power_well); 581 } 582 583 static void 584 icl_aux_power_well_disable(struct intel_display *display, 585 struct i915_power_well *power_well) 586 { 587 enum phy phy = icl_aux_pw_to_phy(display, power_well); 588 589 if (intel_phy_is_tc(display, phy)) 590 return hsw_power_well_disable(display, power_well); 591 else if (display->platform.icelake) 592 return icl_combo_phy_aux_power_well_disable(display, 593 power_well); 594 else 595 return hsw_power_well_disable(display, power_well); 596 } 597 598 /* 599 * We should only use the power well if we explicitly asked the hardware to 600 * enable it, so check if it's enabled and also check if we've requested it to 601 * be enabled. 602 */ 603 static bool hsw_power_well_enabled(struct intel_display *display, 604 struct i915_power_well *power_well) 605 { 606 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 607 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 608 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 609 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | 610 HSW_PWR_WELL_CTL_STATE(pw_idx); 611 u32 val; 612 613 val = intel_de_read(display, regs->driver); 614 615 /* 616 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 617 * and the MISC_IO PW will be not restored, so check instead for the 618 * BIOS's own request bits, which are forced-on for these power wells 619 * when exiting DC5/6. 620 */ 621 if (DISPLAY_VER(display) == 9 && !display->platform.broxton && 622 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 623 val |= intel_de_read(display, regs->bios); 624 625 return (val & mask) == mask; 626 } 627 628 static void assert_can_enable_dc9(struct intel_display *display) 629 { 630 drm_WARN_ONCE(display->drm, 631 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), 632 "DC9 already programmed to be enabled.\n"); 633 drm_WARN_ONCE(display->drm, 634 intel_de_read(display, DC_STATE_EN) & 635 DC_STATE_EN_UPTO_DC5, 636 "DC5 still not disabled to enable DC9.\n"); 637 drm_WARN_ONCE(display->drm, 638 intel_de_read(display, HSW_PWR_WELL_CTL2) & 639 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 640 "Power well 2 on.\n"); 641 drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), 642 "Interrupts not disabled yet.\n"); 643 644 /* 645 * TODO: check for the following to verify the conditions to enter DC9 646 * state are satisfied: 647 * 1] Check relevant display engine registers to verify if mode set 648 * disable sequence was followed. 649 * 2] Check if display uninitialize sequence is initialized. 650 */ 651 } 652 653 static void assert_can_disable_dc9(struct intel_display *display) 654 { 655 drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), 656 "Interrupts not disabled yet.\n"); 657 drm_WARN_ONCE(display->drm, 658 intel_de_read(display, DC_STATE_EN) & 659 DC_STATE_EN_UPTO_DC5, 660 "DC5 still not disabled.\n"); 661 662 /* 663 * TODO: check for the following to verify DC9 state was indeed 664 * entered before programming to disable it: 665 * 1] Check relevant display engine registers to verify if mode 666 * set disable sequence was followed. 667 * 2] Check if display uninitialize sequence is initialized. 668 */ 669 } 670 671 static void gen9_write_dc_state(struct intel_display *display, 672 u32 state) 673 { 674 int rewrites = 0; 675 int rereads = 0; 676 u32 v; 677 678 intel_de_write(display, DC_STATE_EN, state); 679 680 /* It has been observed that disabling the dc6 state sometimes 681 * doesn't stick and dmc keeps returning old value. Make sure 682 * the write really sticks enough times and also force rewrite until 683 * we are confident that state is exactly what we want. 684 */ 685 do { 686 v = intel_de_read(display, DC_STATE_EN); 687 688 if (v != state) { 689 intel_de_write(display, DC_STATE_EN, state); 690 rewrites++; 691 rereads = 0; 692 } else if (rereads++ > 5) { 693 break; 694 } 695 696 } while (rewrites < 100); 697 698 if (v != state) 699 drm_err(display->drm, 700 "Writing dc state to 0x%x failed, now 0x%x\n", 701 state, v); 702 703 /* Most of the times we need one retry, avoid spam */ 704 if (rewrites > 1) 705 drm_dbg_kms(display->drm, 706 "Rewrote dc state to 0x%x %d times\n", 707 state, rewrites); 708 } 709 710 static u32 gen9_dc_mask(struct intel_display *display) 711 { 712 u32 mask; 713 714 mask = DC_STATE_EN_UPTO_DC5; 715 716 if (DISPLAY_VER(display) >= 12) 717 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 718 | DC_STATE_EN_DC9; 719 else if (DISPLAY_VER(display) == 11) 720 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; 721 else if (display->platform.geminilake || display->platform.broxton) 722 mask |= DC_STATE_EN_DC9; 723 else 724 mask |= DC_STATE_EN_UPTO_DC6; 725 726 return mask; 727 } 728 729 void gen9_sanitize_dc_state(struct intel_display *display) 730 { 731 struct i915_power_domains *power_domains = &display->power.domains; 732 u32 val; 733 734 if (!HAS_DISPLAY(display)) 735 return; 736 737 val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display); 738 739 drm_dbg_kms(display->drm, 740 "Resetting DC state tracking from %02x to %02x\n", 741 power_domains->dc_state, val); 742 power_domains->dc_state = val; 743 } 744 745 /** 746 * gen9_set_dc_state - set target display C power state 747 * @display: display instance 748 * @state: target DC power state 749 * - DC_STATE_DISABLE 750 * - DC_STATE_EN_UPTO_DC5 751 * - DC_STATE_EN_UPTO_DC6 752 * - DC_STATE_EN_DC9 753 * 754 * Signal to DMC firmware/HW the target DC power state passed in @state. 755 * DMC/HW can turn off individual display clocks and power rails when entering 756 * a deeper DC power state (higher in number) and turns these back when exiting 757 * that state to a shallower power state (lower in number). The HW will decide 758 * when to actually enter a given state on an on-demand basis, for instance 759 * depending on the active state of display pipes. The state of display 760 * registers backed by affected power rails are saved/restored as needed. 761 * 762 * Based on the above enabling a deeper DC power state is asynchronous wrt. 763 * enabling it. Disabling a deeper power state is synchronous: for instance 764 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 765 * back on and register state is restored. This is guaranteed by the MMIO write 766 * to DC_STATE_EN blocking until the state is restored. 767 */ 768 void gen9_set_dc_state(struct intel_display *display, u32 state) 769 { 770 struct i915_power_domains *power_domains = &display->power.domains; 771 bool dc6_was_enabled, enable_dc6; 772 u32 mask; 773 u32 val; 774 775 if (!HAS_DISPLAY(display)) 776 return; 777 778 if (drm_WARN_ON_ONCE(display->drm, 779 state & ~power_domains->allowed_dc_mask)) 780 state &= power_domains->allowed_dc_mask; 781 782 if (!power_domains->initializing) 783 intel_psr_notify_dc5_dc6(display); 784 785 val = intel_de_read(display, DC_STATE_EN); 786 mask = gen9_dc_mask(display); 787 drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", 788 val & mask, state); 789 790 /* Check if DMC is ignoring our DC state requests */ 791 if ((val & mask) != power_domains->dc_state) 792 drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n", 793 power_domains->dc_state, val & mask); 794 795 enable_dc6 = state & DC_STATE_EN_UPTO_DC6; 796 dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6; 797 if (!dc6_was_enabled && enable_dc6) 798 intel_dmc_update_dc6_allowed_count(display, true); 799 800 val &= ~mask; 801 val |= state; 802 803 gen9_write_dc_state(display, val); 804 805 if (!enable_dc6 && dc6_was_enabled) 806 intel_dmc_update_dc6_allowed_count(display, false); 807 808 power_domains->dc_state = val & mask; 809 } 810 811 static void tgl_enable_dc3co(struct intel_display *display) 812 { 813 drm_dbg_kms(display->drm, "Enabling DC3CO\n"); 814 gen9_set_dc_state(display, DC_STATE_EN_DC3CO); 815 } 816 817 static void tgl_disable_dc3co(struct intel_display *display) 818 { 819 drm_dbg_kms(display->drm, "Disabling DC3CO\n"); 820 intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); 821 gen9_set_dc_state(display, DC_STATE_DISABLE); 822 /* 823 * Delay of 200us DC3CO Exit time B.Spec 49196 824 */ 825 usleep_range(200, 210); 826 } 827 828 static void assert_can_enable_dc5(struct intel_display *display) 829 { 830 enum i915_power_well_id high_pg; 831 832 /* Power wells at this level and above must be disabled for DC5 entry */ 833 if (DISPLAY_VER(display) == 12) 834 high_pg = ICL_DISP_PW_3; 835 else 836 high_pg = SKL_DISP_PW_2; 837 838 drm_WARN_ONCE(display->drm, 839 intel_display_power_well_is_enabled(display, high_pg), 840 "Power wells above platform's DC5 limit still enabled.\n"); 841 842 drm_WARN_ONCE(display->drm, 843 (intel_de_read(display, DC_STATE_EN) & 844 DC_STATE_EN_UPTO_DC5), 845 "DC5 already programmed to be enabled.\n"); 846 847 assert_display_rpm_held(display); 848 849 assert_main_dmc_loaded(display); 850 } 851 852 void gen9_enable_dc5(struct intel_display *display) 853 { 854 assert_can_enable_dc5(display); 855 856 drm_dbg_kms(display->drm, "Enabling DC5\n"); 857 858 /* Wa Display #1183: skl,kbl,cfl */ 859 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 860 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 861 0, SKL_SELECT_ALTERNATE_DC_EXIT); 862 863 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5); 864 865 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); 866 } 867 868 static void assert_can_enable_dc6(struct intel_display *display) 869 { 870 drm_WARN_ONCE(display->drm, 871 (intel_de_read(display, UTIL_PIN_CTL) & 872 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == 873 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 874 "Utility pin enabled in PWM mode\n"); 875 drm_WARN_ONCE(display->drm, 876 (intel_de_read(display, DC_STATE_EN) & 877 DC_STATE_EN_UPTO_DC6), 878 "DC6 already programmed to be enabled.\n"); 879 880 assert_main_dmc_loaded(display); 881 } 882 883 void skl_enable_dc6(struct intel_display *display) 884 { 885 assert_can_enable_dc6(display); 886 887 drm_dbg_kms(display->drm, "Enabling DC6\n"); 888 889 /* Wa Display #1183: skl,kbl,cfl */ 890 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 891 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 892 0, SKL_SELECT_ALTERNATE_DC_EXIT); 893 894 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6); 895 896 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); 897 } 898 899 void bxt_enable_dc9(struct intel_display *display) 900 { 901 assert_can_enable_dc9(display); 902 903 drm_dbg_kms(display->drm, "Enabling DC9\n"); 904 /* 905 * Power sequencer reset is needed on BXT/GLK, because the PPS registers 906 * aren't always on, unlike with South Display Engine on PCH. 907 */ 908 if (display->platform.broxton || display->platform.geminilake) 909 bxt_pps_reset_all(display); 910 gen9_set_dc_state(display, DC_STATE_EN_DC9); 911 } 912 913 void bxt_disable_dc9(struct intel_display *display) 914 { 915 assert_can_disable_dc9(display); 916 917 drm_dbg_kms(display->drm, "Disabling DC9\n"); 918 919 gen9_set_dc_state(display, DC_STATE_DISABLE); 920 921 intel_pps_unlock_regs_wa(display); 922 } 923 924 static void hsw_power_well_sync_hw(struct intel_display *display, 925 struct i915_power_well *power_well) 926 { 927 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 928 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 929 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 930 u32 bios_req = intel_de_read(display, regs->bios); 931 932 /* Take over the request bit if set by BIOS. */ 933 if (bios_req & mask) { 934 u32 drv_req = intel_de_read(display, regs->driver); 935 936 if (!(drv_req & mask)) 937 intel_de_write(display, regs->driver, drv_req | mask); 938 intel_de_write(display, regs->bios, bios_req & ~mask); 939 } 940 } 941 942 static void bxt_dpio_cmn_power_well_enable(struct intel_display *display, 943 struct i915_power_well *power_well) 944 { 945 bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy); 946 } 947 948 static void bxt_dpio_cmn_power_well_disable(struct intel_display *display, 949 struct i915_power_well *power_well) 950 { 951 bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy); 952 } 953 954 static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display, 955 struct i915_power_well *power_well) 956 { 957 return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy); 958 } 959 960 static void bxt_verify_dpio_phy_power_wells(struct intel_display *display) 961 { 962 struct i915_power_well *power_well; 963 964 power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A); 965 if (intel_power_well_refcount(power_well) > 0) 966 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 967 968 power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 969 if (intel_power_well_refcount(power_well) > 0) 970 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 971 972 if (display->platform.geminilake) { 973 power_well = lookup_power_well(display, 974 GLK_DISP_PW_DPIO_CMN_C); 975 if (intel_power_well_refcount(power_well) > 0) 976 bxt_dpio_phy_verify_state(display, 977 i915_power_well_instance(power_well)->bxt.phy); 978 } 979 } 980 981 static bool gen9_dc_off_power_well_enabled(struct intel_display *display, 982 struct i915_power_well *power_well) 983 { 984 return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && 985 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); 986 } 987 988 static void gen9_assert_dbuf_enabled(struct intel_display *display) 989 { 990 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display); 991 u8 enabled_dbuf_slices = display->dbuf.enabled_slices; 992 993 drm_WARN(display->drm, 994 hw_enabled_dbuf_slices != enabled_dbuf_slices, 995 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 996 hw_enabled_dbuf_slices, 997 enabled_dbuf_slices); 998 } 999 1000 void gen9_disable_dc_states(struct intel_display *display) 1001 { 1002 struct i915_power_domains *power_domains = &display->power.domains; 1003 struct intel_cdclk_config cdclk_config = {}; 1004 u32 old_state = power_domains->dc_state; 1005 1006 if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { 1007 tgl_disable_dc3co(display); 1008 return; 1009 } 1010 1011 if (HAS_DISPLAY(display)) { 1012 intel_dmc_wl_get_noreg(display); 1013 gen9_set_dc_state(display, DC_STATE_DISABLE); 1014 intel_dmc_wl_put_noreg(display); 1015 } else { 1016 gen9_set_dc_state(display, DC_STATE_DISABLE); 1017 return; 1018 } 1019 1020 if (old_state == DC_STATE_EN_UPTO_DC5 || 1021 old_state == DC_STATE_EN_UPTO_DC6) 1022 intel_dmc_wl_disable(display); 1023 1024 intel_cdclk_get_cdclk(display, &cdclk_config); 1025 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 1026 drm_WARN_ON(display->drm, 1027 intel_cdclk_clock_changed(&display->cdclk.hw, 1028 &cdclk_config)); 1029 1030 gen9_assert_dbuf_enabled(display); 1031 1032 if (display->platform.geminilake || display->platform.broxton) 1033 bxt_verify_dpio_phy_power_wells(display); 1034 1035 if (DISPLAY_VER(display) >= 11) 1036 /* 1037 * DMC retains HW context only for port A, the other combo 1038 * PHY's HW context for port B is lost after DC transitions, 1039 * so we need to restore it manually. 1040 */ 1041 intel_combo_phy_init(display); 1042 } 1043 1044 static void gen9_dc_off_power_well_enable(struct intel_display *display, 1045 struct i915_power_well *power_well) 1046 { 1047 gen9_disable_dc_states(display); 1048 } 1049 1050 static void gen9_dc_off_power_well_disable(struct intel_display *display, 1051 struct i915_power_well *power_well) 1052 { 1053 struct i915_power_domains *power_domains = &display->power.domains; 1054 1055 if (!intel_dmc_has_payload(display)) 1056 return; 1057 1058 switch (power_domains->target_dc_state) { 1059 case DC_STATE_EN_DC3CO: 1060 tgl_enable_dc3co(display); 1061 break; 1062 case DC_STATE_EN_UPTO_DC6: 1063 skl_enable_dc6(display); 1064 break; 1065 case DC_STATE_EN_UPTO_DC5: 1066 gen9_enable_dc5(display); 1067 break; 1068 } 1069 } 1070 1071 static void i9xx_power_well_sync_hw_noop(struct intel_display *display, 1072 struct i915_power_well *power_well) 1073 { 1074 } 1075 1076 static void i9xx_always_on_power_well_noop(struct intel_display *display, 1077 struct i915_power_well *power_well) 1078 { 1079 } 1080 1081 static bool i9xx_always_on_power_well_enabled(struct intel_display *display, 1082 struct i915_power_well *power_well) 1083 { 1084 return true; 1085 } 1086 1087 static void i830_pipes_power_well_enable(struct intel_display *display, 1088 struct i915_power_well *power_well) 1089 { 1090 if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) 1091 i830_enable_pipe(display, PIPE_A); 1092 if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0) 1093 i830_enable_pipe(display, PIPE_B); 1094 } 1095 1096 static void i830_pipes_power_well_disable(struct intel_display *display, 1097 struct i915_power_well *power_well) 1098 { 1099 i830_disable_pipe(display, PIPE_B); 1100 i830_disable_pipe(display, PIPE_A); 1101 } 1102 1103 static bool i830_pipes_power_well_enabled(struct intel_display *display, 1104 struct i915_power_well *power_well) 1105 { 1106 return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && 1107 intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; 1108 } 1109 1110 static void i830_pipes_power_well_sync_hw(struct intel_display *display, 1111 struct i915_power_well *power_well) 1112 { 1113 if (intel_power_well_refcount(power_well) > 0) 1114 i830_pipes_power_well_enable(display, power_well); 1115 else 1116 i830_pipes_power_well_disable(display, power_well); 1117 } 1118 1119 static void vlv_set_power_well(struct intel_display *display, 1120 struct i915_power_well *power_well, bool enable) 1121 { 1122 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1123 u32 mask; 1124 u32 state; 1125 u32 ctrl; 1126 u32 val; 1127 int ret; 1128 1129 mask = PUNIT_PWRGT_MASK(pw_idx); 1130 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : 1131 PUNIT_PWRGT_PWR_GATE(pw_idx); 1132 1133 vlv_punit_get(display->drm); 1134 1135 val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS); 1136 if ((val & mask) == state) 1137 goto out; 1138 1139 ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL); 1140 ctrl &= ~mask; 1141 ctrl |= state; 1142 vlv_punit_write(display->drm, PUNIT_REG_PWRGT_CTRL, ctrl); 1143 1144 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS), 1145 (val & mask) == state, 1146 500, 100 * 1000, false); 1147 if (ret) 1148 drm_err(display->drm, 1149 "timeout setting power well state %08x (%08x)\n", 1150 state, 1151 vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL)); 1152 1153 out: 1154 vlv_punit_put(display->drm); 1155 } 1156 1157 static void vlv_power_well_enable(struct intel_display *display, 1158 struct i915_power_well *power_well) 1159 { 1160 vlv_set_power_well(display, power_well, true); 1161 } 1162 1163 static void vlv_power_well_disable(struct intel_display *display, 1164 struct i915_power_well *power_well) 1165 { 1166 vlv_set_power_well(display, power_well, false); 1167 } 1168 1169 static bool vlv_power_well_enabled(struct intel_display *display, 1170 struct i915_power_well *power_well) 1171 { 1172 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1173 bool enabled = false; 1174 u32 mask; 1175 u32 state; 1176 u32 ctrl; 1177 1178 mask = PUNIT_PWRGT_MASK(pw_idx); 1179 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); 1180 1181 vlv_punit_get(display->drm); 1182 1183 state = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask; 1184 /* 1185 * We only ever set the power-on and power-gate states, anything 1186 * else is unexpected. 1187 */ 1188 drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1189 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 1190 if (state == ctrl) 1191 enabled = true; 1192 1193 /* 1194 * A transient state at this point would mean some unexpected party 1195 * is poking at the power controls too. 1196 */ 1197 ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL) & mask; 1198 drm_WARN_ON(display->drm, ctrl != state); 1199 1200 vlv_punit_put(display->drm); 1201 1202 return enabled; 1203 } 1204 1205 static void vlv_init_display_clock_gating(struct intel_display *display) 1206 { 1207 /* 1208 * On driver load, a pipe may be active and driving a DSI display. 1209 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1210 * (and never recovering) in this case. intel_dsi_post_disable() will 1211 * clear it when we turn off the display. 1212 */ 1213 intel_de_rmw(display, VLV_DSPCLK_GATE_D, 1214 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE); 1215 1216 /* 1217 * Disable trickle feed and enable pnd deadline calculation 1218 */ 1219 intel_de_write(display, MI_ARB_VLV, 1220 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1221 intel_de_write(display, CBR1_VLV, 0); 1222 1223 drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0); 1224 intel_de_write(display, RAWCLK_FREQ_VLV, 1225 DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 1226 1000)); 1227 } 1228 1229 static void vlv_display_power_well_init(struct intel_display *display) 1230 { 1231 struct intel_encoder *encoder; 1232 enum pipe pipe; 1233 1234 /* 1235 * Enable the CRI clock source so we can get at the 1236 * display and the reference clock for VGA 1237 * hotplug / manual detection. Supposedly DSI also 1238 * needs the ref clock up and running. 1239 * 1240 * CHV DPLL B/C have some issues if VGA mode is enabled. 1241 */ 1242 for_each_pipe(display, pipe) { 1243 u32 val = intel_de_read(display, DPLL(display, pipe)); 1244 1245 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1246 if (pipe != PIPE_A) 1247 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1248 1249 intel_de_write(display, DPLL(display, pipe), val); 1250 } 1251 1252 vlv_init_display_clock_gating(display); 1253 1254 valleyview_enable_display_irqs(display); 1255 1256 /* 1257 * During driver initialization/resume we can avoid restoring the 1258 * part of the HW/SW state that will be inited anyway explicitly. 1259 */ 1260 if (display->power.domains.initializing) 1261 return; 1262 1263 intel_hpd_init(display); 1264 intel_hpd_poll_disable(display); 1265 1266 /* Re-enable the ADPA, if we have one */ 1267 for_each_intel_encoder(display->drm, encoder) { 1268 if (encoder->type == INTEL_OUTPUT_ANALOG) 1269 intel_crt_reset(&encoder->base); 1270 } 1271 1272 intel_vga_disable(display); 1273 1274 intel_pps_unlock_regs_wa(display); 1275 } 1276 1277 static void vlv_display_power_well_deinit(struct intel_display *display) 1278 { 1279 valleyview_disable_display_irqs(display); 1280 1281 /* make sure we're done processing display irqs */ 1282 intel_parent_irq_synchronize(display); 1283 1284 vlv_pps_reset_all(display); 1285 1286 /* Prevent us from re-enabling polling on accident in late suspend */ 1287 if (!display->drm->dev->power.is_suspended) 1288 intel_hpd_poll_enable(display); 1289 } 1290 1291 static void vlv_display_power_well_enable(struct intel_display *display, 1292 struct i915_power_well *power_well) 1293 { 1294 vlv_set_power_well(display, power_well, true); 1295 1296 vlv_display_power_well_init(display); 1297 } 1298 1299 static void vlv_display_power_well_disable(struct intel_display *display, 1300 struct i915_power_well *power_well) 1301 { 1302 vlv_display_power_well_deinit(display); 1303 1304 vlv_set_power_well(display, power_well, false); 1305 } 1306 1307 static void vlv_dpio_cmn_power_well_enable(struct intel_display *display, 1308 struct i915_power_well *power_well) 1309 { 1310 /* since ref/cri clock was enabled */ 1311 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1312 1313 vlv_set_power_well(display, power_well, true); 1314 1315 /* 1316 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1317 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1318 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1319 * b. The other bits such as sfr settings / modesel may all 1320 * be set to 0. 1321 * 1322 * This should only be done on init and resume from S3 with 1323 * both PLLs disabled, or we risk losing DPIO and PLL 1324 * synchronization. 1325 */ 1326 intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST); 1327 } 1328 1329 static void vlv_dpio_cmn_power_well_disable(struct intel_display *display, 1330 struct i915_power_well *power_well) 1331 { 1332 enum pipe pipe; 1333 1334 for_each_pipe(display, pipe) 1335 assert_pll_disabled(display, pipe); 1336 1337 /* Assert common reset */ 1338 intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); 1339 1340 vlv_set_power_well(display, power_well, false); 1341 } 1342 1343 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1344 1345 static void assert_chv_phy_status(struct intel_display *display) 1346 { 1347 struct i915_power_well *cmn_bc = 1348 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1349 struct i915_power_well *cmn_d = 1350 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1351 u32 phy_control = display->power.chv_phy_control; 1352 u32 phy_status = 0; 1353 u32 phy_status_mask = 0xffffffff; 1354 u32 val; 1355 1356 /* 1357 * The BIOS can leave the PHY is some weird state 1358 * where it doesn't fully power down some parts. 1359 * Disable the asserts until the PHY has been fully 1360 * reset (ie. the power well has been disabled at 1361 * least once). 1362 */ 1363 if (!display->power.chv_phy_assert[DPIO_PHY0]) 1364 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1365 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1366 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1367 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1368 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1369 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1370 1371 if (!display->power.chv_phy_assert[DPIO_PHY1]) 1372 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1373 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1374 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1375 1376 if (intel_power_well_is_enabled(display, cmn_bc)) { 1377 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1378 1379 /* this assumes override is only used to enable lanes */ 1380 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1381 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1382 1383 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1384 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1385 1386 /* CL1 is on whenever anything is on in either channel */ 1387 if (BITS_SET(phy_control, 1388 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1389 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1390 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1391 1392 /* 1393 * The DPLLB check accounts for the pipe B + port A usage 1394 * with CL2 powered up but all the lanes in the second channel 1395 * powered down. 1396 */ 1397 if (BITS_SET(phy_control, 1398 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1399 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1400 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1401 1402 if (BITS_SET(phy_control, 1403 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1404 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1405 if (BITS_SET(phy_control, 1406 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1407 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1408 1409 if (BITS_SET(phy_control, 1410 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1411 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1412 if (BITS_SET(phy_control, 1413 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1414 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1415 } 1416 1417 if (intel_power_well_is_enabled(display, cmn_d)) { 1418 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1419 1420 /* this assumes override is only used to enable lanes */ 1421 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1422 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1423 1424 if (BITS_SET(phy_control, 1425 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1426 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1427 1428 if (BITS_SET(phy_control, 1429 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1430 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1431 if (BITS_SET(phy_control, 1432 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1433 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1434 } 1435 1436 phy_status &= phy_status_mask; 1437 1438 /* 1439 * The PHY may be busy with some initial calibration and whatnot, 1440 * so the power state can take a while to actually change. 1441 */ 1442 if (intel_de_wait_ms(display, DISPLAY_PHY_STATUS, 1443 phy_status_mask, phy_status, 10, &val)) 1444 drm_err(display->drm, 1445 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1446 val & phy_status_mask, phy_status, display->power.chv_phy_control); 1447 } 1448 1449 #undef BITS_SET 1450 1451 static void chv_dpio_cmn_power_well_enable(struct intel_display *display, 1452 struct i915_power_well *power_well) 1453 { 1454 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1455 enum dpio_phy phy; 1456 u32 tmp; 1457 1458 drm_WARN_ON_ONCE(display->drm, 1459 id != VLV_DISP_PW_DPIO_CMN_BC && 1460 id != CHV_DISP_PW_DPIO_CMN_D); 1461 1462 if (id == VLV_DISP_PW_DPIO_CMN_BC) 1463 phy = DPIO_PHY0; 1464 else 1465 phy = DPIO_PHY1; 1466 1467 /* since ref/cri clock was enabled */ 1468 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1469 vlv_set_power_well(display, power_well, true); 1470 1471 /* Poll for phypwrgood signal */ 1472 if (intel_de_wait_for_set_ms(display, DISPLAY_PHY_STATUS, 1473 PHY_POWERGOOD(phy), 1)) 1474 drm_err(display->drm, "Display PHY %d is not power up\n", 1475 phy); 1476 1477 vlv_dpio_get(display->drm); 1478 1479 /* Enable dynamic power down */ 1480 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW28); 1481 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1482 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1483 vlv_dpio_write(display->drm, phy, CHV_CMN_DW28, tmp); 1484 1485 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1486 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW6_CH1); 1487 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1488 vlv_dpio_write(display->drm, phy, CHV_CMN_DW6_CH1, tmp); 1489 } else { 1490 /* 1491 * Force the non-existing CL2 off. BXT does this 1492 * too, so maybe it saves some power even though 1493 * CL2 doesn't exist? 1494 */ 1495 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW30); 1496 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1497 vlv_dpio_write(display->drm, phy, CHV_CMN_DW30, tmp); 1498 } 1499 1500 vlv_dpio_put(display->drm); 1501 1502 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1503 intel_de_write(display, DISPLAY_PHY_CONTROL, 1504 display->power.chv_phy_control); 1505 1506 drm_dbg_kms(display->drm, 1507 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1508 phy, display->power.chv_phy_control); 1509 1510 assert_chv_phy_status(display); 1511 } 1512 1513 static void chv_dpio_cmn_power_well_disable(struct intel_display *display, 1514 struct i915_power_well *power_well) 1515 { 1516 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1517 enum dpio_phy phy; 1518 1519 drm_WARN_ON_ONCE(display->drm, 1520 id != VLV_DISP_PW_DPIO_CMN_BC && 1521 id != CHV_DISP_PW_DPIO_CMN_D); 1522 1523 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1524 phy = DPIO_PHY0; 1525 assert_pll_disabled(display, PIPE_A); 1526 assert_pll_disabled(display, PIPE_B); 1527 } else { 1528 phy = DPIO_PHY1; 1529 assert_pll_disabled(display, PIPE_C); 1530 } 1531 1532 display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1533 intel_de_write(display, DISPLAY_PHY_CONTROL, 1534 display->power.chv_phy_control); 1535 1536 vlv_set_power_well(display, power_well, false); 1537 1538 drm_dbg_kms(display->drm, 1539 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1540 phy, display->power.chv_phy_control); 1541 1542 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1543 display->power.chv_phy_assert[phy] = true; 1544 1545 assert_chv_phy_status(display); 1546 } 1547 1548 static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy, 1549 enum dpio_channel ch, bool override, unsigned int mask) 1550 { 1551 u32 reg, val, expected, actual; 1552 1553 /* 1554 * The BIOS can leave the PHY is some weird state 1555 * where it doesn't fully power down some parts. 1556 * Disable the asserts until the PHY has been fully 1557 * reset (ie. the power well has been disabled at 1558 * least once). 1559 */ 1560 if (!display->power.chv_phy_assert[phy]) 1561 return; 1562 1563 if (ch == DPIO_CH0) 1564 reg = CHV_CMN_DW0_CH0; 1565 else 1566 reg = CHV_CMN_DW6_CH1; 1567 1568 vlv_dpio_get(display->drm); 1569 val = vlv_dpio_read(display->drm, phy, reg); 1570 vlv_dpio_put(display->drm); 1571 1572 /* 1573 * This assumes !override is only used when the port is disabled. 1574 * All lanes should power down even without the override when 1575 * the port is disabled. 1576 */ 1577 if (!override || mask == 0xf) { 1578 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1579 /* 1580 * If CH1 common lane is not active anymore 1581 * (eg. for pipe B DPLL) the entire channel will 1582 * shut down, which causes the common lane registers 1583 * to read as 0. That means we can't actually check 1584 * the lane power down status bits, but as the entire 1585 * register reads as 0 it's a good indication that the 1586 * channel is indeed entirely powered down. 1587 */ 1588 if (ch == DPIO_CH1 && val == 0) 1589 expected = 0; 1590 } else if (mask != 0x0) { 1591 expected = DPIO_ANYDL_POWERDOWN; 1592 } else { 1593 expected = 0; 1594 } 1595 1596 if (ch == DPIO_CH0) 1597 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 | 1598 DPIO_ALLDL_POWERDOWN_CH0, val); 1599 else 1600 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 | 1601 DPIO_ALLDL_POWERDOWN_CH1, val); 1602 1603 drm_WARN(display->drm, actual != expected, 1604 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1605 !!(actual & DPIO_ALLDL_POWERDOWN), 1606 !!(actual & DPIO_ANYDL_POWERDOWN), 1607 !!(expected & DPIO_ALLDL_POWERDOWN), 1608 !!(expected & DPIO_ANYDL_POWERDOWN), 1609 reg, val); 1610 } 1611 1612 bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy, 1613 enum dpio_channel ch, bool override) 1614 { 1615 struct i915_power_domains *power_domains = &display->power.domains; 1616 bool was_override; 1617 1618 mutex_lock(&power_domains->lock); 1619 1620 was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1621 1622 if (override == was_override) 1623 goto out; 1624 1625 if (override) 1626 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1627 else 1628 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1629 1630 intel_de_write(display, DISPLAY_PHY_CONTROL, 1631 display->power.chv_phy_control); 1632 1633 drm_dbg_kms(display->drm, 1634 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1635 phy, ch, display->power.chv_phy_control); 1636 1637 assert_chv_phy_status(display); 1638 1639 out: 1640 mutex_unlock(&power_domains->lock); 1641 1642 return was_override; 1643 } 1644 1645 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1646 bool override, unsigned int mask) 1647 { 1648 struct intel_display *display = to_intel_display(encoder); 1649 struct i915_power_domains *power_domains = &display->power.domains; 1650 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1651 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 1652 1653 mutex_lock(&power_domains->lock); 1654 1655 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1656 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1657 1658 if (override) 1659 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1660 else 1661 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1662 1663 intel_de_write(display, DISPLAY_PHY_CONTROL, 1664 display->power.chv_phy_control); 1665 1666 drm_dbg_kms(display->drm, 1667 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1668 phy, ch, mask, display->power.chv_phy_control); 1669 1670 assert_chv_phy_status(display); 1671 1672 assert_chv_phy_powergate(display, phy, ch, override, mask); 1673 1674 mutex_unlock(&power_domains->lock); 1675 } 1676 1677 static bool chv_pipe_power_well_enabled(struct intel_display *display, 1678 struct i915_power_well *power_well) 1679 { 1680 enum pipe pipe = PIPE_A; 1681 bool enabled; 1682 u32 state, ctrl; 1683 1684 vlv_punit_get(display->drm); 1685 1686 state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); 1687 /* 1688 * We only ever set the power-on and power-gate states, anything 1689 * else is unexpected. 1690 */ 1691 drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) && 1692 state != DP_SSS_PWR_GATE(pipe)); 1693 enabled = state == DP_SSS_PWR_ON(pipe); 1694 1695 /* 1696 * A transient state at this point would mean some unexpected party 1697 * is poking at the power controls too. 1698 */ 1699 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); 1700 drm_WARN_ON(display->drm, ctrl << 16 != state); 1701 1702 vlv_punit_put(display->drm); 1703 1704 return enabled; 1705 } 1706 1707 static void chv_set_pipe_power_well(struct intel_display *display, 1708 struct i915_power_well *power_well, 1709 bool enable) 1710 { 1711 enum pipe pipe = PIPE_A; 1712 u32 state; 1713 u32 ctrl; 1714 int ret; 1715 1716 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1717 1718 vlv_punit_get(display->drm); 1719 1720 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 1721 if ((ctrl & DP_SSS_MASK(pipe)) == state) 1722 goto out; 1723 1724 ctrl &= ~DP_SSC_MASK(pipe); 1725 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1726 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, ctrl); 1727 1728 ret = poll_timeout_us(ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), 1729 (ctrl & DP_SSS_MASK(pipe)) == state, 1730 500, 100 * 1000, false); 1731 if (ret) 1732 drm_err(display->drm, 1733 "timeout setting power well state %08x (%08x)\n", 1734 state, 1735 vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM)); 1736 1737 #undef COND 1738 1739 out: 1740 vlv_punit_put(display->drm); 1741 } 1742 1743 static void chv_pipe_power_well_sync_hw(struct intel_display *display, 1744 struct i915_power_well *power_well) 1745 { 1746 intel_de_write(display, DISPLAY_PHY_CONTROL, 1747 display->power.chv_phy_control); 1748 } 1749 1750 static void chv_pipe_power_well_enable(struct intel_display *display, 1751 struct i915_power_well *power_well) 1752 { 1753 chv_set_pipe_power_well(display, power_well, true); 1754 1755 vlv_display_power_well_init(display); 1756 } 1757 1758 static void chv_pipe_power_well_disable(struct intel_display *display, 1759 struct i915_power_well *power_well) 1760 { 1761 vlv_display_power_well_deinit(display); 1762 1763 chv_set_pipe_power_well(display, power_well, false); 1764 } 1765 1766 static void 1767 tgl_tc_cold_request(struct intel_display *display, bool block) 1768 { 1769 u8 tries = 0; 1770 int ret; 1771 1772 while (1) { 1773 u32 low_val; 1774 u32 high_val = 0; 1775 1776 if (block) 1777 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ; 1778 else 1779 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ; 1780 1781 /* 1782 * Spec states that we should timeout the request after 200us 1783 * but the function below will timeout after 500us 1784 */ 1785 ret = intel_pcode_read(display->drm, TGL_PCODE_TCCOLD, &low_val, &high_val); 1786 if (ret == 0) { 1787 if (block && 1788 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED)) 1789 ret = -EIO; 1790 else 1791 break; 1792 } 1793 1794 if (++tries == 3) 1795 break; 1796 1797 msleep(1); 1798 } 1799 1800 if (ret) 1801 drm_err(display->drm, "TC cold %sblock failed\n", block ? "" : "un"); 1802 else 1803 drm_dbg_kms(display->drm, "TC cold %sblock succeeded\n", 1804 block ? "" : "un"); 1805 } 1806 1807 static void 1808 tgl_tc_cold_off_power_well_enable(struct intel_display *display, 1809 struct i915_power_well *power_well) 1810 { 1811 tgl_tc_cold_request(display, true); 1812 } 1813 1814 static void 1815 tgl_tc_cold_off_power_well_disable(struct intel_display *display, 1816 struct i915_power_well *power_well) 1817 { 1818 tgl_tc_cold_request(display, false); 1819 } 1820 1821 static void 1822 tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display, 1823 struct i915_power_well *power_well) 1824 { 1825 if (intel_power_well_refcount(power_well) > 0) 1826 tgl_tc_cold_off_power_well_enable(display, power_well); 1827 else 1828 tgl_tc_cold_off_power_well_disable(display, power_well); 1829 } 1830 1831 static bool 1832 tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display, 1833 struct i915_power_well *power_well) 1834 { 1835 /* 1836 * Not the correctly implementation but there is no way to just read it 1837 * from PCODE, so returning count to avoid state mismatch errors 1838 */ 1839 return intel_power_well_refcount(power_well); 1840 } 1841 1842 static void xelpdp_aux_power_well_enable(struct intel_display *display, 1843 struct i915_power_well *power_well) 1844 { 1845 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1846 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1847 1848 if (intel_phy_is_tc(display, phy)) 1849 icl_tc_port_assert_ref_held(display, power_well, 1850 aux_ch_to_digital_port(display, aux_ch)); 1851 1852 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1853 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1854 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1855 1856 /* 1857 * The power status flag cannot be used to determine whether aux 1858 * power wells have finished powering up. Instead we're 1859 * expected to just wait a fixed 600us after raising the request 1860 * bit. 1861 */ 1862 if (DISPLAY_VER(display) >= 35) { 1863 if (intel_de_wait_for_set_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1864 XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2)) 1865 drm_warn(display->drm, 1866 "Timeout waiting for PHY %c AUX channel power to be up\n", 1867 phy_name(phy)); 1868 } else { 1869 usleep_range(600, 1200); 1870 } 1871 } 1872 1873 static void xelpdp_aux_power_well_disable(struct intel_display *display, 1874 struct i915_power_well *power_well) 1875 { 1876 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1877 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1878 1879 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1880 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1881 0); 1882 1883 if (DISPLAY_VER(display) >= 35) { 1884 if (intel_de_wait_for_clear_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1885 XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1)) 1886 drm_warn(display->drm, 1887 "Timeout waiting for PHY %c AUX channel to powerdown\n", 1888 phy_name(phy)); 1889 } else { 1890 usleep_range(10, 30); 1891 } 1892 } 1893 1894 static bool xelpdp_aux_power_well_enabled(struct intel_display *display, 1895 struct i915_power_well *power_well) 1896 { 1897 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1898 1899 return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) & 1900 XELPDP_DP_AUX_CH_CTL_POWER_STATUS; 1901 } 1902 1903 static void xe2lpd_pica_power_well_enable(struct intel_display *display, 1904 struct i915_power_well *power_well) 1905 { 1906 intel_de_write(display, XE2LPD_PICA_PW_CTL, 1907 XE2LPD_PICA_CTL_POWER_REQUEST); 1908 1909 if (intel_de_wait_for_set_ms(display, XE2LPD_PICA_PW_CTL, 1910 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1911 drm_dbg_kms(display->drm, "pica power well enable timeout\n"); 1912 1913 drm_WARN(display->drm, 1, "Power well PICA timeout when enabled"); 1914 } 1915 } 1916 1917 static void xe2lpd_pica_power_well_disable(struct intel_display *display, 1918 struct i915_power_well *power_well) 1919 { 1920 intel_de_write(display, XE2LPD_PICA_PW_CTL, 0); 1921 1922 if (intel_de_wait_for_clear_ms(display, XE2LPD_PICA_PW_CTL, 1923 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1924 drm_dbg_kms(display->drm, "pica power well disable timeout\n"); 1925 1926 drm_WARN(display->drm, 1, "Power well PICA timeout when disabled"); 1927 } 1928 } 1929 1930 static bool xe2lpd_pica_power_well_enabled(struct intel_display *display, 1931 struct i915_power_well *power_well) 1932 { 1933 return intel_de_read(display, XE2LPD_PICA_PW_CTL) & 1934 XE2LPD_PICA_CTL_POWER_STATUS; 1935 } 1936 1937 const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1938 .sync_hw = i9xx_power_well_sync_hw_noop, 1939 .enable = i9xx_always_on_power_well_noop, 1940 .disable = i9xx_always_on_power_well_noop, 1941 .is_enabled = i9xx_always_on_power_well_enabled, 1942 }; 1943 1944 const struct i915_power_well_ops chv_pipe_power_well_ops = { 1945 .sync_hw = chv_pipe_power_well_sync_hw, 1946 .enable = chv_pipe_power_well_enable, 1947 .disable = chv_pipe_power_well_disable, 1948 .is_enabled = chv_pipe_power_well_enabled, 1949 }; 1950 1951 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1952 .sync_hw = i9xx_power_well_sync_hw_noop, 1953 .enable = chv_dpio_cmn_power_well_enable, 1954 .disable = chv_dpio_cmn_power_well_disable, 1955 .is_enabled = vlv_power_well_enabled, 1956 }; 1957 1958 const struct i915_power_well_ops i830_pipes_power_well_ops = { 1959 .sync_hw = i830_pipes_power_well_sync_hw, 1960 .enable = i830_pipes_power_well_enable, 1961 .disable = i830_pipes_power_well_disable, 1962 .is_enabled = i830_pipes_power_well_enabled, 1963 }; 1964 1965 static const struct i915_power_well_regs hsw_power_well_regs = { 1966 .bios = HSW_PWR_WELL_CTL1, 1967 .driver = HSW_PWR_WELL_CTL2, 1968 .kvmr = HSW_PWR_WELL_CTL3, 1969 .debug = HSW_PWR_WELL_CTL4, 1970 }; 1971 1972 const struct i915_power_well_ops hsw_power_well_ops = { 1973 .regs = &hsw_power_well_regs, 1974 .sync_hw = hsw_power_well_sync_hw, 1975 .enable = hsw_power_well_enable, 1976 .disable = hsw_power_well_disable, 1977 .is_enabled = hsw_power_well_enabled, 1978 }; 1979 1980 const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1981 .sync_hw = i9xx_power_well_sync_hw_noop, 1982 .enable = gen9_dc_off_power_well_enable, 1983 .disable = gen9_dc_off_power_well_disable, 1984 .is_enabled = gen9_dc_off_power_well_enabled, 1985 }; 1986 1987 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1988 .sync_hw = i9xx_power_well_sync_hw_noop, 1989 .enable = bxt_dpio_cmn_power_well_enable, 1990 .disable = bxt_dpio_cmn_power_well_disable, 1991 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1992 }; 1993 1994 const struct i915_power_well_ops vlv_display_power_well_ops = { 1995 .sync_hw = i9xx_power_well_sync_hw_noop, 1996 .enable = vlv_display_power_well_enable, 1997 .disable = vlv_display_power_well_disable, 1998 .is_enabled = vlv_power_well_enabled, 1999 }; 2000 2001 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 2002 .sync_hw = i9xx_power_well_sync_hw_noop, 2003 .enable = vlv_dpio_cmn_power_well_enable, 2004 .disable = vlv_dpio_cmn_power_well_disable, 2005 .is_enabled = vlv_power_well_enabled, 2006 }; 2007 2008 const struct i915_power_well_ops vlv_dpio_power_well_ops = { 2009 .sync_hw = i9xx_power_well_sync_hw_noop, 2010 .enable = vlv_power_well_enable, 2011 .disable = vlv_power_well_disable, 2012 .is_enabled = vlv_power_well_enabled, 2013 }; 2014 2015 static const struct i915_power_well_regs icl_aux_power_well_regs = { 2016 .bios = ICL_PWR_WELL_CTL_AUX1, 2017 .driver = ICL_PWR_WELL_CTL_AUX2, 2018 .debug = ICL_PWR_WELL_CTL_AUX4, 2019 }; 2020 2021 const struct i915_power_well_ops icl_aux_power_well_ops = { 2022 .regs = &icl_aux_power_well_regs, 2023 .sync_hw = hsw_power_well_sync_hw, 2024 .enable = icl_aux_power_well_enable, 2025 .disable = icl_aux_power_well_disable, 2026 .is_enabled = hsw_power_well_enabled, 2027 }; 2028 2029 static const struct i915_power_well_regs icl_ddi_power_well_regs = { 2030 .bios = ICL_PWR_WELL_CTL_DDI1, 2031 .driver = ICL_PWR_WELL_CTL_DDI2, 2032 .debug = ICL_PWR_WELL_CTL_DDI4, 2033 }; 2034 2035 const struct i915_power_well_ops icl_ddi_power_well_ops = { 2036 .regs = &icl_ddi_power_well_regs, 2037 .sync_hw = hsw_power_well_sync_hw, 2038 .enable = hsw_power_well_enable, 2039 .disable = hsw_power_well_disable, 2040 .is_enabled = hsw_power_well_enabled, 2041 }; 2042 2043 const struct i915_power_well_ops tgl_tc_cold_off_ops = { 2044 .sync_hw = tgl_tc_cold_off_power_well_sync_hw, 2045 .enable = tgl_tc_cold_off_power_well_enable, 2046 .disable = tgl_tc_cold_off_power_well_disable, 2047 .is_enabled = tgl_tc_cold_off_power_well_is_enabled, 2048 }; 2049 2050 const struct i915_power_well_ops xelpdp_aux_power_well_ops = { 2051 .sync_hw = i9xx_power_well_sync_hw_noop, 2052 .enable = xelpdp_aux_power_well_enable, 2053 .disable = xelpdp_aux_power_well_disable, 2054 .is_enabled = xelpdp_aux_power_well_enabled, 2055 }; 2056 2057 const struct i915_power_well_ops xe2lpd_pica_power_well_ops = { 2058 .sync_hw = i9xx_power_well_sync_hw_noop, 2059 .enable = xe2lpd_pica_power_well_enable, 2060 .disable = xe2lpd_pica_power_well_disable, 2061 .is_enabled = xe2lpd_pica_power_well_enabled, 2062 }; 2063