1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_irq.h" 8 #include "i915_reg.h" 9 #include "intel_backlight_regs.h" 10 #include "intel_combo_phy.h" 11 #include "intel_combo_phy_regs.h" 12 #include "intel_crt.h" 13 #include "intel_de.h" 14 #include "intel_display_irq.h" 15 #include "intel_display_power_well.h" 16 #include "intel_display_rpm.h" 17 #include "intel_display_types.h" 18 #include "intel_dkl_phy.h" 19 #include "intel_dkl_phy_regs.h" 20 #include "intel_dmc.h" 21 #include "intel_dmc_wl.h" 22 #include "intel_dp_aux_regs.h" 23 #include "intel_dpio_phy.h" 24 #include "intel_dpll.h" 25 #include "intel_hotplug.h" 26 #include "intel_pcode.h" 27 #include "intel_pps.h" 28 #include "intel_psr.h" 29 #include "intel_tc.h" 30 #include "intel_vga.h" 31 #include "skl_watermark.h" 32 #include "vlv_dpio_phy_regs.h" 33 #include "vlv_sideband.h" 34 #include "vlv_sideband_reg.h" 35 36 struct i915_power_well_regs { 37 i915_reg_t bios; 38 i915_reg_t driver; 39 i915_reg_t kvmr; 40 i915_reg_t debug; 41 }; 42 43 struct i915_power_well_ops { 44 const struct i915_power_well_regs *regs; 45 /* 46 * Synchronize the well's hw state to match the current sw state, for 47 * example enable/disable it based on the current refcount. Called 48 * during driver init and resume time, possibly after first calling 49 * the enable/disable handlers. 50 */ 51 void (*sync_hw)(struct intel_display *display, 52 struct i915_power_well *power_well); 53 /* 54 * Enable the well and resources that depend on it (for example 55 * interrupts located on the well). Called after the 0->1 refcount 56 * transition. 57 */ 58 void (*enable)(struct intel_display *display, 59 struct i915_power_well *power_well); 60 /* 61 * Disable the well and resources that depend on it. Called after 62 * the 1->0 refcount transition. 63 */ 64 void (*disable)(struct intel_display *display, 65 struct i915_power_well *power_well); 66 /* Returns the hw enabled state. */ 67 bool (*is_enabled)(struct intel_display *display, 68 struct i915_power_well *power_well); 69 }; 70 71 static const struct i915_power_well_instance * 72 i915_power_well_instance(const struct i915_power_well *power_well) 73 { 74 return &power_well->desc->instances->list[power_well->instance_idx]; 75 } 76 77 struct i915_power_well * 78 lookup_power_well(struct intel_display *display, 79 enum i915_power_well_id power_well_id) 80 { 81 struct i915_power_well *power_well; 82 83 for_each_power_well(display, power_well) 84 if (i915_power_well_instance(power_well)->id == power_well_id) 85 return power_well; 86 87 /* 88 * It's not feasible to add error checking code to the callers since 89 * this condition really shouldn't happen and it doesn't even make sense 90 * to abort things like display initialization sequences. Just return 91 * the first power well and hope the WARN gets reported so we can fix 92 * our driver. 93 */ 94 drm_WARN(display->drm, 1, 95 "Power well %d not defined for this platform\n", 96 power_well_id); 97 return &display->power.domains.power_wells[0]; 98 } 99 100 void intel_power_well_enable(struct intel_display *display, 101 struct i915_power_well *power_well) 102 { 103 drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well)); 104 power_well->desc->ops->enable(display, power_well); 105 power_well->hw_enabled = true; 106 } 107 108 void intel_power_well_disable(struct intel_display *display, 109 struct i915_power_well *power_well) 110 { 111 drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well)); 112 power_well->hw_enabled = false; 113 power_well->desc->ops->disable(display, power_well); 114 } 115 116 void intel_power_well_sync_hw(struct intel_display *display, 117 struct i915_power_well *power_well) 118 { 119 power_well->desc->ops->sync_hw(display, power_well); 120 power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well); 121 } 122 123 void intel_power_well_get(struct intel_display *display, 124 struct i915_power_well *power_well) 125 { 126 if (!power_well->count++) 127 intel_power_well_enable(display, power_well); 128 } 129 130 void intel_power_well_put(struct intel_display *display, 131 struct i915_power_well *power_well) 132 { 133 drm_WARN(display->drm, !power_well->count, 134 "Use count on power well %s is already zero", 135 i915_power_well_instance(power_well)->name); 136 137 if (!--power_well->count) 138 intel_power_well_disable(display, power_well); 139 } 140 141 bool intel_power_well_is_enabled(struct intel_display *display, 142 struct i915_power_well *power_well) 143 { 144 return power_well->desc->ops->is_enabled(display, power_well); 145 } 146 147 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well) 148 { 149 return power_well->hw_enabled; 150 } 151 152 bool intel_display_power_well_is_enabled(struct intel_display *display, 153 enum i915_power_well_id power_well_id) 154 { 155 struct i915_power_well *power_well; 156 157 power_well = lookup_power_well(display, power_well_id); 158 159 return intel_power_well_is_enabled(display, power_well); 160 } 161 162 bool intel_power_well_is_always_on(struct i915_power_well *power_well) 163 { 164 return power_well->desc->always_on; 165 } 166 167 const char *intel_power_well_name(struct i915_power_well *power_well) 168 { 169 return i915_power_well_instance(power_well)->name; 170 } 171 172 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well) 173 { 174 return &power_well->domains; 175 } 176 177 int intel_power_well_refcount(struct i915_power_well *power_well) 178 { 179 return power_well->count; 180 } 181 182 /* 183 * Starting with Haswell, we have a "Power Down Well" that can be turned off 184 * when not needed anymore. We have 4 registers that can request the power well 185 * to be enabled, and it will only be disabled if none of the registers is 186 * requesting it to be enabled. 187 */ 188 static void hsw_power_well_post_enable(struct intel_display *display, 189 u8 irq_pipe_mask, bool has_vga) 190 { 191 if (has_vga) 192 intel_vga_reset_io_mem(display); 193 194 if (irq_pipe_mask) 195 gen8_irq_power_well_post_enable(display, irq_pipe_mask); 196 } 197 198 static void hsw_power_well_pre_disable(struct intel_display *display, 199 u8 irq_pipe_mask) 200 { 201 if (irq_pipe_mask) 202 gen8_irq_power_well_pre_disable(display, irq_pipe_mask); 203 } 204 205 #define ICL_AUX_PW_TO_PHY(pw_idx) \ 206 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + PHY_A) 207 208 #define ICL_AUX_PW_TO_CH(pw_idx) \ 209 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) 210 211 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ 212 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) 213 214 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well) 215 { 216 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 217 218 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : 219 ICL_AUX_PW_TO_CH(pw_idx); 220 } 221 222 static struct intel_digital_port * 223 aux_ch_to_digital_port(struct intel_display *display, 224 enum aux_ch aux_ch) 225 { 226 struct intel_encoder *encoder; 227 228 for_each_intel_encoder(display->drm, encoder) { 229 struct intel_digital_port *dig_port; 230 231 /* We'll check the MST primary port */ 232 if (encoder->type == INTEL_OUTPUT_DP_MST) 233 continue; 234 235 dig_port = enc_to_dig_port(encoder); 236 237 if (dig_port && dig_port->aux_ch == aux_ch) 238 return dig_port; 239 } 240 241 return NULL; 242 } 243 244 static enum phy icl_aux_pw_to_phy(struct intel_display *display, 245 const struct i915_power_well *power_well) 246 { 247 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 248 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 249 250 /* 251 * FIXME should we care about the (VBT defined) dig_port->aux_ch 252 * relationship or should this be purely defined by the hardware layout? 253 * Currently if the port doesn't appear in the VBT, or if it's declared 254 * as HDMI-only and routed to a combo PHY, the encoder either won't be 255 * present at all or it will not have an aux_ch assigned. 256 */ 257 return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE; 258 } 259 260 static void hsw_wait_for_power_well_enable(struct intel_display *display, 261 struct i915_power_well *power_well, 262 bool timeout_expected) 263 { 264 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 265 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 266 int timeout = power_well->desc->enable_timeout ? : 1; 267 268 /* 269 * For some power wells we're not supposed to watch the status bit for 270 * an ack, but rather just wait a fixed amount of time and then 271 * proceed. This is only used on DG2. 272 */ 273 if (display->platform.dg2 && power_well->desc->fixed_enable_delay) { 274 usleep_range(600, 1200); 275 return; 276 } 277 278 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 279 if (intel_de_wait_for_set(display, regs->driver, 280 HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) { 281 drm_dbg_kms(display->drm, "%s power well enable timeout\n", 282 intel_power_well_name(power_well)); 283 284 drm_WARN_ON(display->drm, !timeout_expected); 285 286 } 287 } 288 289 static u32 hsw_power_well_requesters(struct intel_display *display, 290 const struct i915_power_well_regs *regs, 291 int pw_idx) 292 { 293 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 294 u32 ret; 295 296 ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0; 297 ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0; 298 if (regs->kvmr.reg) 299 ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0; 300 ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0; 301 302 return ret; 303 } 304 305 static void hsw_wait_for_power_well_disable(struct intel_display *display, 306 struct i915_power_well *power_well) 307 { 308 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 309 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 310 bool disabled; 311 u32 reqs; 312 313 /* 314 * Bspec doesn't require waiting for PWs to get disabled, but still do 315 * this for paranoia. The known cases where a PW will be forced on: 316 * - a KVMR request on any power well via the KVMR request register 317 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 318 * DEBUG request registers 319 * Skip the wait in case any of the request bits are set and print a 320 * diagnostic message. 321 */ 322 wait_for((disabled = !(intel_de_read(display, regs->driver) & 323 HSW_PWR_WELL_CTL_STATE(pw_idx))) || 324 (reqs = hsw_power_well_requesters(display, regs, pw_idx)), 1); 325 if (disabled) 326 return; 327 328 drm_dbg_kms(display->drm, 329 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 330 intel_power_well_name(power_well), 331 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 332 } 333 334 static void gen9_wait_for_power_well_fuses(struct intel_display *display, 335 enum skl_power_gate pg) 336 { 337 /* Timeout 5us for PG#0, for other PGs 1us */ 338 drm_WARN_ON(display->drm, 339 intel_de_wait_for_set(display, SKL_FUSE_STATUS, 340 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 341 } 342 343 static void hsw_power_well_enable(struct intel_display *display, 344 struct i915_power_well *power_well) 345 { 346 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 347 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 348 349 if (power_well->desc->has_fuses) { 350 enum skl_power_gate pg; 351 352 pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 353 SKL_PW_CTL_IDX_TO_PG(pw_idx); 354 355 /* Wa_16013190616:adlp */ 356 if (display->platform.alderlake_p && pg == SKL_PG1) 357 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 358 359 /* 360 * For PW1 we have to wait both for the PW0/PG0 fuse state 361 * before enabling the power well and PW1/PG1's own fuse 362 * state after the enabling. For all other power wells with 363 * fuses we only have to wait for that PW/PG's fuse state 364 * after the enabling. 365 */ 366 if (pg == SKL_PG1) 367 gen9_wait_for_power_well_fuses(display, SKL_PG0); 368 } 369 370 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 371 372 hsw_wait_for_power_well_enable(display, power_well, false); 373 374 if (power_well->desc->has_fuses) { 375 enum skl_power_gate pg; 376 377 pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 378 SKL_PW_CTL_IDX_TO_PG(pw_idx); 379 gen9_wait_for_power_well_fuses(display, pg); 380 } 381 382 hsw_power_well_post_enable(display, 383 power_well->desc->irq_pipe_mask, 384 power_well->desc->has_vga); 385 } 386 387 static void hsw_power_well_disable(struct intel_display *display, 388 struct i915_power_well *power_well) 389 { 390 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 391 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 392 393 hsw_power_well_pre_disable(display, 394 power_well->desc->irq_pipe_mask); 395 396 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 397 hsw_wait_for_power_well_disable(display, power_well); 398 } 399 400 static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch) 401 { 402 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 403 404 return dig_port && dig_port->base.type == INTEL_OUTPUT_EDP; 405 } 406 407 static void 408 icl_combo_phy_aux_power_well_enable(struct intel_display *display, 409 struct i915_power_well *power_well) 410 { 411 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 412 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 413 414 drm_WARN_ON(display->drm, !display->platform.icelake); 415 416 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 417 418 /* 419 * FIXME not sure if we should derive the PHY from the pw_idx, or 420 * from the VBT defined AUX_CH->DDI->PHY mapping. 421 */ 422 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 423 0, ICL_LANE_ENABLE_AUX); 424 425 hsw_wait_for_power_well_enable(display, power_well, false); 426 427 /* Display WA #1178: icl */ 428 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && 429 !intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx))) 430 intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), 431 0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI); 432 } 433 434 static void 435 icl_combo_phy_aux_power_well_disable(struct intel_display *display, 436 struct i915_power_well *power_well) 437 { 438 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 439 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 440 441 drm_WARN_ON(display->drm, !display->platform.icelake); 442 443 /* 444 * FIXME not sure if we should derive the PHY from the pw_idx, or 445 * from the VBT defined AUX_CH->DDI->PHY mapping. 446 */ 447 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 448 ICL_LANE_ENABLE_AUX, 0); 449 450 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 451 452 hsw_wait_for_power_well_disable(display, power_well); 453 } 454 455 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 456 457 static void icl_tc_port_assert_ref_held(struct intel_display *display, 458 struct i915_power_well *power_well, 459 struct intel_digital_port *dig_port) 460 { 461 if (drm_WARN_ON(display->drm, !dig_port)) 462 return; 463 464 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 465 return; 466 467 drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port)); 468 } 469 470 #else 471 472 static void icl_tc_port_assert_ref_held(struct intel_display *display, 473 struct i915_power_well *power_well, 474 struct intel_digital_port *dig_port) 475 { 476 } 477 478 #endif 479 480 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1) 481 482 static void icl_tc_cold_exit(struct intel_display *display) 483 { 484 struct drm_i915_private *i915 = to_i915(display->drm); 485 int ret, tries = 0; 486 487 while (1) { 488 ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0, 489 250, 1); 490 if (ret != -EAGAIN || ++tries == 3) 491 break; 492 msleep(1); 493 } 494 495 /* Spec states that TC cold exit can take up to 1ms to complete */ 496 if (!ret) 497 msleep(1); 498 499 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */ 500 drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" : 501 "succeeded"); 502 } 503 504 static void 505 icl_tc_phy_aux_power_well_enable(struct intel_display *display, 506 struct i915_power_well *power_well) 507 { 508 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 509 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 510 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 511 bool is_tbt = power_well->desc->is_tc_tbt; 512 bool timeout_expected; 513 514 icl_tc_port_assert_ref_held(display, power_well, dig_port); 515 516 intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), 517 DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0); 518 519 intel_de_rmw(display, regs->driver, 520 0, 521 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); 522 523 /* 524 * An AUX timeout is expected if the TBT DP tunnel is down, 525 * or need to enable AUX on a legacy TypeC port as part of the TC-cold 526 * exit sequence. 527 */ 528 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port); 529 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 530 icl_tc_cold_exit(display); 531 532 hsw_wait_for_power_well_enable(display, power_well, timeout_expected); 533 534 if (DISPLAY_VER(display) >= 12 && !is_tbt) { 535 enum tc_port tc_port; 536 537 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); 538 539 if (wait_for(intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)) & 540 DKL_CMN_UC_DW27_UC_HEALTH, 1)) 541 drm_warn(display->drm, 542 "Timeout waiting TC uC health\n"); 543 } 544 } 545 546 static void 547 icl_aux_power_well_enable(struct intel_display *display, 548 struct i915_power_well *power_well) 549 { 550 enum phy phy = icl_aux_pw_to_phy(display, power_well); 551 552 if (intel_phy_is_tc(display, phy)) 553 return icl_tc_phy_aux_power_well_enable(display, power_well); 554 else if (display->platform.icelake) 555 return icl_combo_phy_aux_power_well_enable(display, 556 power_well); 557 else 558 return hsw_power_well_enable(display, power_well); 559 } 560 561 static void 562 icl_aux_power_well_disable(struct intel_display *display, 563 struct i915_power_well *power_well) 564 { 565 enum phy phy = icl_aux_pw_to_phy(display, power_well); 566 567 if (intel_phy_is_tc(display, phy)) 568 return hsw_power_well_disable(display, power_well); 569 else if (display->platform.icelake) 570 return icl_combo_phy_aux_power_well_disable(display, 571 power_well); 572 else 573 return hsw_power_well_disable(display, power_well); 574 } 575 576 /* 577 * We should only use the power well if we explicitly asked the hardware to 578 * enable it, so check if it's enabled and also check if we've requested it to 579 * be enabled. 580 */ 581 static bool hsw_power_well_enabled(struct intel_display *display, 582 struct i915_power_well *power_well) 583 { 584 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 585 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 586 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 587 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | 588 HSW_PWR_WELL_CTL_STATE(pw_idx); 589 u32 val; 590 591 val = intel_de_read(display, regs->driver); 592 593 /* 594 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 595 * and the MISC_IO PW will be not restored, so check instead for the 596 * BIOS's own request bits, which are forced-on for these power wells 597 * when exiting DC5/6. 598 */ 599 if (DISPLAY_VER(display) == 9 && !display->platform.broxton && 600 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 601 val |= intel_de_read(display, regs->bios); 602 603 return (val & mask) == mask; 604 } 605 606 static void assert_can_enable_dc9(struct intel_display *display) 607 { 608 struct drm_i915_private *dev_priv = to_i915(display->drm); 609 610 drm_WARN_ONCE(display->drm, 611 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), 612 "DC9 already programmed to be enabled.\n"); 613 drm_WARN_ONCE(display->drm, 614 intel_de_read(display, DC_STATE_EN) & 615 DC_STATE_EN_UPTO_DC5, 616 "DC5 still not disabled to enable DC9.\n"); 617 drm_WARN_ONCE(display->drm, 618 intel_de_read(display, HSW_PWR_WELL_CTL2) & 619 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 620 "Power well 2 on.\n"); 621 drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), 622 "Interrupts not disabled yet.\n"); 623 624 /* 625 * TODO: check for the following to verify the conditions to enter DC9 626 * state are satisfied: 627 * 1] Check relevant display engine registers to verify if mode set 628 * disable sequence was followed. 629 * 2] Check if display uninitialize sequence is initialized. 630 */ 631 } 632 633 static void assert_can_disable_dc9(struct intel_display *display) 634 { 635 struct drm_i915_private *dev_priv = to_i915(display->drm); 636 637 drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), 638 "Interrupts not disabled yet.\n"); 639 drm_WARN_ONCE(display->drm, 640 intel_de_read(display, DC_STATE_EN) & 641 DC_STATE_EN_UPTO_DC5, 642 "DC5 still not disabled.\n"); 643 644 /* 645 * TODO: check for the following to verify DC9 state was indeed 646 * entered before programming to disable it: 647 * 1] Check relevant display engine registers to verify if mode 648 * set disable sequence was followed. 649 * 2] Check if display uninitialize sequence is initialized. 650 */ 651 } 652 653 static void gen9_write_dc_state(struct intel_display *display, 654 u32 state) 655 { 656 int rewrites = 0; 657 int rereads = 0; 658 u32 v; 659 660 intel_de_write(display, DC_STATE_EN, state); 661 662 /* It has been observed that disabling the dc6 state sometimes 663 * doesn't stick and dmc keeps returning old value. Make sure 664 * the write really sticks enough times and also force rewrite until 665 * we are confident that state is exactly what we want. 666 */ 667 do { 668 v = intel_de_read(display, DC_STATE_EN); 669 670 if (v != state) { 671 intel_de_write(display, DC_STATE_EN, state); 672 rewrites++; 673 rereads = 0; 674 } else if (rereads++ > 5) { 675 break; 676 } 677 678 } while (rewrites < 100); 679 680 if (v != state) 681 drm_err(display->drm, 682 "Writing dc state to 0x%x failed, now 0x%x\n", 683 state, v); 684 685 /* Most of the times we need one retry, avoid spam */ 686 if (rewrites > 1) 687 drm_dbg_kms(display->drm, 688 "Rewrote dc state to 0x%x %d times\n", 689 state, rewrites); 690 } 691 692 static u32 gen9_dc_mask(struct intel_display *display) 693 { 694 u32 mask; 695 696 mask = DC_STATE_EN_UPTO_DC5; 697 698 if (DISPLAY_VER(display) >= 12) 699 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 700 | DC_STATE_EN_DC9; 701 else if (DISPLAY_VER(display) == 11) 702 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; 703 else if (display->platform.geminilake || display->platform.broxton) 704 mask |= DC_STATE_EN_DC9; 705 else 706 mask |= DC_STATE_EN_UPTO_DC6; 707 708 return mask; 709 } 710 711 void gen9_sanitize_dc_state(struct intel_display *display) 712 { 713 struct i915_power_domains *power_domains = &display->power.domains; 714 u32 val; 715 716 if (!HAS_DISPLAY(display)) 717 return; 718 719 val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display); 720 721 drm_dbg_kms(display->drm, 722 "Resetting DC state tracking from %02x to %02x\n", 723 power_domains->dc_state, val); 724 power_domains->dc_state = val; 725 } 726 727 /** 728 * gen9_set_dc_state - set target display C power state 729 * @display: display instance 730 * @state: target DC power state 731 * - DC_STATE_DISABLE 732 * - DC_STATE_EN_UPTO_DC5 733 * - DC_STATE_EN_UPTO_DC6 734 * - DC_STATE_EN_DC9 735 * 736 * Signal to DMC firmware/HW the target DC power state passed in @state. 737 * DMC/HW can turn off individual display clocks and power rails when entering 738 * a deeper DC power state (higher in number) and turns these back when exiting 739 * that state to a shallower power state (lower in number). The HW will decide 740 * when to actually enter a given state on an on-demand basis, for instance 741 * depending on the active state of display pipes. The state of display 742 * registers backed by affected power rails are saved/restored as needed. 743 * 744 * Based on the above enabling a deeper DC power state is asynchronous wrt. 745 * enabling it. Disabling a deeper power state is synchronous: for instance 746 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 747 * back on and register state is restored. This is guaranteed by the MMIO write 748 * to DC_STATE_EN blocking until the state is restored. 749 */ 750 void gen9_set_dc_state(struct intel_display *display, u32 state) 751 { 752 struct i915_power_domains *power_domains = &display->power.domains; 753 bool dc6_was_enabled, enable_dc6; 754 u32 mask; 755 u32 val; 756 757 if (!HAS_DISPLAY(display)) 758 return; 759 760 if (drm_WARN_ON_ONCE(display->drm, 761 state & ~power_domains->allowed_dc_mask)) 762 state &= power_domains->allowed_dc_mask; 763 764 if (!power_domains->initializing) 765 intel_psr_notify_dc5_dc6(display); 766 767 val = intel_de_read(display, DC_STATE_EN); 768 mask = gen9_dc_mask(display); 769 drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", 770 val & mask, state); 771 772 /* Check if DMC is ignoring our DC state requests */ 773 if ((val & mask) != power_domains->dc_state) 774 drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n", 775 power_domains->dc_state, val & mask); 776 777 enable_dc6 = state & DC_STATE_EN_UPTO_DC6; 778 dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6; 779 if (!dc6_was_enabled && enable_dc6) 780 intel_dmc_update_dc6_allowed_count(display, true); 781 782 val &= ~mask; 783 val |= state; 784 785 gen9_write_dc_state(display, val); 786 787 if (!enable_dc6 && dc6_was_enabled) 788 intel_dmc_update_dc6_allowed_count(display, false); 789 790 power_domains->dc_state = val & mask; 791 } 792 793 static void tgl_enable_dc3co(struct intel_display *display) 794 { 795 drm_dbg_kms(display->drm, "Enabling DC3CO\n"); 796 gen9_set_dc_state(display, DC_STATE_EN_DC3CO); 797 } 798 799 static void tgl_disable_dc3co(struct intel_display *display) 800 { 801 drm_dbg_kms(display->drm, "Disabling DC3CO\n"); 802 intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); 803 gen9_set_dc_state(display, DC_STATE_DISABLE); 804 /* 805 * Delay of 200us DC3CO Exit time B.Spec 49196 806 */ 807 usleep_range(200, 210); 808 } 809 810 static void assert_can_enable_dc5(struct intel_display *display) 811 { 812 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); 813 enum i915_power_well_id high_pg; 814 815 /* Power wells at this level and above must be disabled for DC5 entry */ 816 if (DISPLAY_VER(display) == 12) 817 high_pg = ICL_DISP_PW_3; 818 else 819 high_pg = SKL_DISP_PW_2; 820 821 drm_WARN_ONCE(display->drm, 822 intel_display_power_well_is_enabled(display, high_pg), 823 "Power wells above platform's DC5 limit still enabled.\n"); 824 825 drm_WARN_ONCE(display->drm, 826 (intel_de_read(display, DC_STATE_EN) & 827 DC_STATE_EN_UPTO_DC5), 828 "DC5 already programmed to be enabled.\n"); 829 830 assert_display_rpm_held(display); 831 832 assert_dmc_loaded(display); 833 } 834 835 void gen9_enable_dc5(struct intel_display *display) 836 { 837 assert_can_enable_dc5(display); 838 839 drm_dbg_kms(display->drm, "Enabling DC5\n"); 840 841 /* Wa Display #1183: skl,kbl,cfl */ 842 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 843 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 844 0, SKL_SELECT_ALTERNATE_DC_EXIT); 845 846 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5); 847 848 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); 849 } 850 851 static void assert_can_enable_dc6(struct intel_display *display) 852 { 853 drm_WARN_ONCE(display->drm, 854 (intel_de_read(display, UTIL_PIN_CTL) & 855 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == 856 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 857 "Utility pin enabled in PWM mode\n"); 858 drm_WARN_ONCE(display->drm, 859 (intel_de_read(display, DC_STATE_EN) & 860 DC_STATE_EN_UPTO_DC6), 861 "DC6 already programmed to be enabled.\n"); 862 863 assert_dmc_loaded(display); 864 } 865 866 void skl_enable_dc6(struct intel_display *display) 867 { 868 assert_can_enable_dc6(display); 869 870 drm_dbg_kms(display->drm, "Enabling DC6\n"); 871 872 /* Wa Display #1183: skl,kbl,cfl */ 873 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 874 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 875 0, SKL_SELECT_ALTERNATE_DC_EXIT); 876 877 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6); 878 879 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); 880 } 881 882 void bxt_enable_dc9(struct intel_display *display) 883 { 884 assert_can_enable_dc9(display); 885 886 drm_dbg_kms(display->drm, "Enabling DC9\n"); 887 /* 888 * Power sequencer reset is needed on BXT/GLK, because the PPS registers 889 * aren't always on, unlike with South Display Engine on PCH. 890 */ 891 if (display->platform.broxton || display->platform.geminilake) 892 bxt_pps_reset_all(display); 893 gen9_set_dc_state(display, DC_STATE_EN_DC9); 894 } 895 896 void bxt_disable_dc9(struct intel_display *display) 897 { 898 assert_can_disable_dc9(display); 899 900 drm_dbg_kms(display->drm, "Disabling DC9\n"); 901 902 gen9_set_dc_state(display, DC_STATE_DISABLE); 903 904 intel_pps_unlock_regs_wa(display); 905 } 906 907 static void hsw_power_well_sync_hw(struct intel_display *display, 908 struct i915_power_well *power_well) 909 { 910 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 911 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 912 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 913 u32 bios_req = intel_de_read(display, regs->bios); 914 915 /* Take over the request bit if set by BIOS. */ 916 if (bios_req & mask) { 917 u32 drv_req = intel_de_read(display, regs->driver); 918 919 if (!(drv_req & mask)) 920 intel_de_write(display, regs->driver, drv_req | mask); 921 intel_de_write(display, regs->bios, bios_req & ~mask); 922 } 923 } 924 925 static void bxt_dpio_cmn_power_well_enable(struct intel_display *display, 926 struct i915_power_well *power_well) 927 { 928 bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy); 929 } 930 931 static void bxt_dpio_cmn_power_well_disable(struct intel_display *display, 932 struct i915_power_well *power_well) 933 { 934 bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy); 935 } 936 937 static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display, 938 struct i915_power_well *power_well) 939 { 940 return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy); 941 } 942 943 static void bxt_verify_dpio_phy_power_wells(struct intel_display *display) 944 { 945 struct i915_power_well *power_well; 946 947 power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A); 948 if (intel_power_well_refcount(power_well) > 0) 949 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 950 951 power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 952 if (intel_power_well_refcount(power_well) > 0) 953 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 954 955 if (display->platform.geminilake) { 956 power_well = lookup_power_well(display, 957 GLK_DISP_PW_DPIO_CMN_C); 958 if (intel_power_well_refcount(power_well) > 0) 959 bxt_dpio_phy_verify_state(display, 960 i915_power_well_instance(power_well)->bxt.phy); 961 } 962 } 963 964 static bool gen9_dc_off_power_well_enabled(struct intel_display *display, 965 struct i915_power_well *power_well) 966 { 967 return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && 968 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); 969 } 970 971 static void gen9_assert_dbuf_enabled(struct intel_display *display) 972 { 973 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display); 974 u8 enabled_dbuf_slices = display->dbuf.enabled_slices; 975 976 drm_WARN(display->drm, 977 hw_enabled_dbuf_slices != enabled_dbuf_slices, 978 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 979 hw_enabled_dbuf_slices, 980 enabled_dbuf_slices); 981 } 982 983 void gen9_disable_dc_states(struct intel_display *display) 984 { 985 struct i915_power_domains *power_domains = &display->power.domains; 986 struct intel_cdclk_config cdclk_config = {}; 987 u32 old_state = power_domains->dc_state; 988 989 if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { 990 tgl_disable_dc3co(display); 991 return; 992 } 993 994 if (HAS_DISPLAY(display)) { 995 intel_dmc_wl_get_noreg(display); 996 gen9_set_dc_state(display, DC_STATE_DISABLE); 997 intel_dmc_wl_put_noreg(display); 998 } else { 999 gen9_set_dc_state(display, DC_STATE_DISABLE); 1000 return; 1001 } 1002 1003 if (old_state == DC_STATE_EN_UPTO_DC5 || 1004 old_state == DC_STATE_EN_UPTO_DC6) 1005 intel_dmc_wl_disable(display); 1006 1007 intel_cdclk_get_cdclk(display, &cdclk_config); 1008 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 1009 drm_WARN_ON(display->drm, 1010 intel_cdclk_clock_changed(&display->cdclk.hw, 1011 &cdclk_config)); 1012 1013 gen9_assert_dbuf_enabled(display); 1014 1015 if (display->platform.geminilake || display->platform.broxton) 1016 bxt_verify_dpio_phy_power_wells(display); 1017 1018 if (DISPLAY_VER(display) >= 11) 1019 /* 1020 * DMC retains HW context only for port A, the other combo 1021 * PHY's HW context for port B is lost after DC transitions, 1022 * so we need to restore it manually. 1023 */ 1024 intel_combo_phy_init(display); 1025 } 1026 1027 static void gen9_dc_off_power_well_enable(struct intel_display *display, 1028 struct i915_power_well *power_well) 1029 { 1030 gen9_disable_dc_states(display); 1031 } 1032 1033 static void gen9_dc_off_power_well_disable(struct intel_display *display, 1034 struct i915_power_well *power_well) 1035 { 1036 struct i915_power_domains *power_domains = &display->power.domains; 1037 1038 if (!intel_dmc_has_payload(display)) 1039 return; 1040 1041 switch (power_domains->target_dc_state) { 1042 case DC_STATE_EN_DC3CO: 1043 tgl_enable_dc3co(display); 1044 break; 1045 case DC_STATE_EN_UPTO_DC6: 1046 skl_enable_dc6(display); 1047 break; 1048 case DC_STATE_EN_UPTO_DC5: 1049 gen9_enable_dc5(display); 1050 break; 1051 } 1052 } 1053 1054 static void i9xx_power_well_sync_hw_noop(struct intel_display *display, 1055 struct i915_power_well *power_well) 1056 { 1057 } 1058 1059 static void i9xx_always_on_power_well_noop(struct intel_display *display, 1060 struct i915_power_well *power_well) 1061 { 1062 } 1063 1064 static bool i9xx_always_on_power_well_enabled(struct intel_display *display, 1065 struct i915_power_well *power_well) 1066 { 1067 return true; 1068 } 1069 1070 static void i830_pipes_power_well_enable(struct intel_display *display, 1071 struct i915_power_well *power_well) 1072 { 1073 if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) 1074 i830_enable_pipe(display, PIPE_A); 1075 if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0) 1076 i830_enable_pipe(display, PIPE_B); 1077 } 1078 1079 static void i830_pipes_power_well_disable(struct intel_display *display, 1080 struct i915_power_well *power_well) 1081 { 1082 i830_disable_pipe(display, PIPE_B); 1083 i830_disable_pipe(display, PIPE_A); 1084 } 1085 1086 static bool i830_pipes_power_well_enabled(struct intel_display *display, 1087 struct i915_power_well *power_well) 1088 { 1089 return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && 1090 intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; 1091 } 1092 1093 static void i830_pipes_power_well_sync_hw(struct intel_display *display, 1094 struct i915_power_well *power_well) 1095 { 1096 if (intel_power_well_refcount(power_well) > 0) 1097 i830_pipes_power_well_enable(display, power_well); 1098 else 1099 i830_pipes_power_well_disable(display, power_well); 1100 } 1101 1102 static void vlv_set_power_well(struct intel_display *display, 1103 struct i915_power_well *power_well, bool enable) 1104 { 1105 struct drm_i915_private *dev_priv = to_i915(display->drm); 1106 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1107 u32 mask; 1108 u32 state; 1109 u32 ctrl; 1110 1111 mask = PUNIT_PWRGT_MASK(pw_idx); 1112 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : 1113 PUNIT_PWRGT_PWR_GATE(pw_idx); 1114 1115 vlv_punit_get(dev_priv); 1116 1117 #define COND \ 1118 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 1119 1120 if (COND) 1121 goto out; 1122 1123 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 1124 ctrl &= ~mask; 1125 ctrl |= state; 1126 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 1127 1128 if (wait_for(COND, 100)) 1129 drm_err(display->drm, 1130 "timeout setting power well state %08x (%08x)\n", 1131 state, 1132 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 1133 1134 #undef COND 1135 1136 out: 1137 vlv_punit_put(dev_priv); 1138 } 1139 1140 static void vlv_power_well_enable(struct intel_display *display, 1141 struct i915_power_well *power_well) 1142 { 1143 vlv_set_power_well(display, power_well, true); 1144 } 1145 1146 static void vlv_power_well_disable(struct intel_display *display, 1147 struct i915_power_well *power_well) 1148 { 1149 vlv_set_power_well(display, power_well, false); 1150 } 1151 1152 static bool vlv_power_well_enabled(struct intel_display *display, 1153 struct i915_power_well *power_well) 1154 { 1155 struct drm_i915_private *dev_priv = to_i915(display->drm); 1156 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1157 bool enabled = false; 1158 u32 mask; 1159 u32 state; 1160 u32 ctrl; 1161 1162 mask = PUNIT_PWRGT_MASK(pw_idx); 1163 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); 1164 1165 vlv_punit_get(dev_priv); 1166 1167 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 1168 /* 1169 * We only ever set the power-on and power-gate states, anything 1170 * else is unexpected. 1171 */ 1172 drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1173 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 1174 if (state == ctrl) 1175 enabled = true; 1176 1177 /* 1178 * A transient state at this point would mean some unexpected party 1179 * is poking at the power controls too. 1180 */ 1181 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 1182 drm_WARN_ON(display->drm, ctrl != state); 1183 1184 vlv_punit_put(dev_priv); 1185 1186 return enabled; 1187 } 1188 1189 static void vlv_init_display_clock_gating(struct intel_display *display) 1190 { 1191 /* 1192 * On driver load, a pipe may be active and driving a DSI display. 1193 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1194 * (and never recovering) in this case. intel_dsi_post_disable() will 1195 * clear it when we turn off the display. 1196 */ 1197 intel_de_rmw(display, DSPCLK_GATE_D(display), 1198 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE); 1199 1200 /* 1201 * Disable trickle feed and enable pnd deadline calculation 1202 */ 1203 intel_de_write(display, MI_ARB_VLV, 1204 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1205 intel_de_write(display, CBR1_VLV, 0); 1206 1207 drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0); 1208 intel_de_write(display, RAWCLK_FREQ_VLV, 1209 DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 1210 1000)); 1211 } 1212 1213 static void vlv_display_power_well_init(struct intel_display *display) 1214 { 1215 struct intel_encoder *encoder; 1216 enum pipe pipe; 1217 1218 /* 1219 * Enable the CRI clock source so we can get at the 1220 * display and the reference clock for VGA 1221 * hotplug / manual detection. Supposedly DSI also 1222 * needs the ref clock up and running. 1223 * 1224 * CHV DPLL B/C have some issues if VGA mode is enabled. 1225 */ 1226 for_each_pipe(display, pipe) { 1227 u32 val = intel_de_read(display, DPLL(display, pipe)); 1228 1229 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1230 if (pipe != PIPE_A) 1231 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1232 1233 intel_de_write(display, DPLL(display, pipe), val); 1234 } 1235 1236 vlv_init_display_clock_gating(display); 1237 1238 valleyview_enable_display_irqs(display); 1239 1240 /* 1241 * During driver initialization/resume we can avoid restoring the 1242 * part of the HW/SW state that will be inited anyway explicitly. 1243 */ 1244 if (display->power.domains.initializing) 1245 return; 1246 1247 intel_hpd_init(display); 1248 intel_hpd_poll_disable(display); 1249 1250 /* Re-enable the ADPA, if we have one */ 1251 for_each_intel_encoder(display->drm, encoder) { 1252 if (encoder->type == INTEL_OUTPUT_ANALOG) 1253 intel_crt_reset(&encoder->base); 1254 } 1255 1256 intel_vga_disable(display); 1257 1258 intel_pps_unlock_regs_wa(display); 1259 } 1260 1261 static void vlv_display_power_well_deinit(struct intel_display *display) 1262 { 1263 struct drm_i915_private *dev_priv = to_i915(display->drm); 1264 1265 valleyview_disable_display_irqs(display); 1266 1267 /* make sure we're done processing display irqs */ 1268 intel_synchronize_irq(dev_priv); 1269 1270 vlv_pps_reset_all(display); 1271 1272 /* Prevent us from re-enabling polling on accident in late suspend */ 1273 if (!display->drm->dev->power.is_suspended) 1274 intel_hpd_poll_enable(display); 1275 } 1276 1277 static void vlv_display_power_well_enable(struct intel_display *display, 1278 struct i915_power_well *power_well) 1279 { 1280 vlv_set_power_well(display, power_well, true); 1281 1282 vlv_display_power_well_init(display); 1283 } 1284 1285 static void vlv_display_power_well_disable(struct intel_display *display, 1286 struct i915_power_well *power_well) 1287 { 1288 vlv_display_power_well_deinit(display); 1289 1290 vlv_set_power_well(display, power_well, false); 1291 } 1292 1293 static void vlv_dpio_cmn_power_well_enable(struct intel_display *display, 1294 struct i915_power_well *power_well) 1295 { 1296 /* since ref/cri clock was enabled */ 1297 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1298 1299 vlv_set_power_well(display, power_well, true); 1300 1301 /* 1302 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1303 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1304 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1305 * b. The other bits such as sfr settings / modesel may all 1306 * be set to 0. 1307 * 1308 * This should only be done on init and resume from S3 with 1309 * both PLLs disabled, or we risk losing DPIO and PLL 1310 * synchronization. 1311 */ 1312 intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST); 1313 } 1314 1315 static void vlv_dpio_cmn_power_well_disable(struct intel_display *display, 1316 struct i915_power_well *power_well) 1317 { 1318 enum pipe pipe; 1319 1320 for_each_pipe(display, pipe) 1321 assert_pll_disabled(display, pipe); 1322 1323 /* Assert common reset */ 1324 intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); 1325 1326 vlv_set_power_well(display, power_well, false); 1327 } 1328 1329 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1330 1331 static void assert_chv_phy_status(struct intel_display *display) 1332 { 1333 struct i915_power_well *cmn_bc = 1334 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1335 struct i915_power_well *cmn_d = 1336 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1337 u32 phy_control = display->power.chv_phy_control; 1338 u32 phy_status = 0; 1339 u32 phy_status_mask = 0xffffffff; 1340 1341 /* 1342 * The BIOS can leave the PHY is some weird state 1343 * where it doesn't fully power down some parts. 1344 * Disable the asserts until the PHY has been fully 1345 * reset (ie. the power well has been disabled at 1346 * least once). 1347 */ 1348 if (!display->power.chv_phy_assert[DPIO_PHY0]) 1349 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1350 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1351 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1352 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1353 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1354 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1355 1356 if (!display->power.chv_phy_assert[DPIO_PHY1]) 1357 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1358 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1359 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1360 1361 if (intel_power_well_is_enabled(display, cmn_bc)) { 1362 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1363 1364 /* this assumes override is only used to enable lanes */ 1365 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1366 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1367 1368 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1369 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1370 1371 /* CL1 is on whenever anything is on in either channel */ 1372 if (BITS_SET(phy_control, 1373 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1374 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1375 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1376 1377 /* 1378 * The DPLLB check accounts for the pipe B + port A usage 1379 * with CL2 powered up but all the lanes in the second channel 1380 * powered down. 1381 */ 1382 if (BITS_SET(phy_control, 1383 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1384 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1385 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1386 1387 if (BITS_SET(phy_control, 1388 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1389 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1390 if (BITS_SET(phy_control, 1391 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1392 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1393 1394 if (BITS_SET(phy_control, 1395 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1396 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1397 if (BITS_SET(phy_control, 1398 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1399 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1400 } 1401 1402 if (intel_power_well_is_enabled(display, cmn_d)) { 1403 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1404 1405 /* this assumes override is only used to enable lanes */ 1406 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1407 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1408 1409 if (BITS_SET(phy_control, 1410 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1411 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1412 1413 if (BITS_SET(phy_control, 1414 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1415 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1416 if (BITS_SET(phy_control, 1417 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1418 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1419 } 1420 1421 phy_status &= phy_status_mask; 1422 1423 /* 1424 * The PHY may be busy with some initial calibration and whatnot, 1425 * so the power state can take a while to actually change. 1426 */ 1427 if (intel_de_wait(display, DISPLAY_PHY_STATUS, 1428 phy_status_mask, phy_status, 10)) 1429 drm_err(display->drm, 1430 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1431 intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask, 1432 phy_status, display->power.chv_phy_control); 1433 } 1434 1435 #undef BITS_SET 1436 1437 static void chv_dpio_cmn_power_well_enable(struct intel_display *display, 1438 struct i915_power_well *power_well) 1439 { 1440 struct drm_i915_private *dev_priv = to_i915(display->drm); 1441 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1442 enum dpio_phy phy; 1443 u32 tmp; 1444 1445 drm_WARN_ON_ONCE(display->drm, 1446 id != VLV_DISP_PW_DPIO_CMN_BC && 1447 id != CHV_DISP_PW_DPIO_CMN_D); 1448 1449 if (id == VLV_DISP_PW_DPIO_CMN_BC) 1450 phy = DPIO_PHY0; 1451 else 1452 phy = DPIO_PHY1; 1453 1454 /* since ref/cri clock was enabled */ 1455 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1456 vlv_set_power_well(display, power_well, true); 1457 1458 /* Poll for phypwrgood signal */ 1459 if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS, 1460 PHY_POWERGOOD(phy), 1)) 1461 drm_err(display->drm, "Display PHY %d is not power up\n", 1462 phy); 1463 1464 vlv_dpio_get(dev_priv); 1465 1466 /* Enable dynamic power down */ 1467 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW28); 1468 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1469 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1470 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp); 1471 1472 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1473 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1); 1474 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1475 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW6_CH1, tmp); 1476 } else { 1477 /* 1478 * Force the non-existing CL2 off. BXT does this 1479 * too, so maybe it saves some power even though 1480 * CL2 doesn't exist? 1481 */ 1482 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW30); 1483 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1484 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW30, tmp); 1485 } 1486 1487 vlv_dpio_put(dev_priv); 1488 1489 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1490 intel_de_write(display, DISPLAY_PHY_CONTROL, 1491 display->power.chv_phy_control); 1492 1493 drm_dbg_kms(display->drm, 1494 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1495 phy, display->power.chv_phy_control); 1496 1497 assert_chv_phy_status(display); 1498 } 1499 1500 static void chv_dpio_cmn_power_well_disable(struct intel_display *display, 1501 struct i915_power_well *power_well) 1502 { 1503 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1504 enum dpio_phy phy; 1505 1506 drm_WARN_ON_ONCE(display->drm, 1507 id != VLV_DISP_PW_DPIO_CMN_BC && 1508 id != CHV_DISP_PW_DPIO_CMN_D); 1509 1510 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1511 phy = DPIO_PHY0; 1512 assert_pll_disabled(display, PIPE_A); 1513 assert_pll_disabled(display, PIPE_B); 1514 } else { 1515 phy = DPIO_PHY1; 1516 assert_pll_disabled(display, PIPE_C); 1517 } 1518 1519 display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1520 intel_de_write(display, DISPLAY_PHY_CONTROL, 1521 display->power.chv_phy_control); 1522 1523 vlv_set_power_well(display, power_well, false); 1524 1525 drm_dbg_kms(display->drm, 1526 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1527 phy, display->power.chv_phy_control); 1528 1529 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1530 display->power.chv_phy_assert[phy] = true; 1531 1532 assert_chv_phy_status(display); 1533 } 1534 1535 static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy, 1536 enum dpio_channel ch, bool override, unsigned int mask) 1537 { 1538 struct drm_i915_private *dev_priv = to_i915(display->drm); 1539 u32 reg, val, expected, actual; 1540 1541 /* 1542 * The BIOS can leave the PHY is some weird state 1543 * where it doesn't fully power down some parts. 1544 * Disable the asserts until the PHY has been fully 1545 * reset (ie. the power well has been disabled at 1546 * least once). 1547 */ 1548 if (!display->power.chv_phy_assert[phy]) 1549 return; 1550 1551 if (ch == DPIO_CH0) 1552 reg = CHV_CMN_DW0_CH0; 1553 else 1554 reg = CHV_CMN_DW6_CH1; 1555 1556 vlv_dpio_get(dev_priv); 1557 val = vlv_dpio_read(dev_priv, phy, reg); 1558 vlv_dpio_put(dev_priv); 1559 1560 /* 1561 * This assumes !override is only used when the port is disabled. 1562 * All lanes should power down even without the override when 1563 * the port is disabled. 1564 */ 1565 if (!override || mask == 0xf) { 1566 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1567 /* 1568 * If CH1 common lane is not active anymore 1569 * (eg. for pipe B DPLL) the entire channel will 1570 * shut down, which causes the common lane registers 1571 * to read as 0. That means we can't actually check 1572 * the lane power down status bits, but as the entire 1573 * register reads as 0 it's a good indication that the 1574 * channel is indeed entirely powered down. 1575 */ 1576 if (ch == DPIO_CH1 && val == 0) 1577 expected = 0; 1578 } else if (mask != 0x0) { 1579 expected = DPIO_ANYDL_POWERDOWN; 1580 } else { 1581 expected = 0; 1582 } 1583 1584 if (ch == DPIO_CH0) 1585 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 | 1586 DPIO_ALLDL_POWERDOWN_CH0, val); 1587 else 1588 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 | 1589 DPIO_ALLDL_POWERDOWN_CH1, val); 1590 1591 drm_WARN(display->drm, actual != expected, 1592 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1593 !!(actual & DPIO_ALLDL_POWERDOWN), 1594 !!(actual & DPIO_ANYDL_POWERDOWN), 1595 !!(expected & DPIO_ALLDL_POWERDOWN), 1596 !!(expected & DPIO_ANYDL_POWERDOWN), 1597 reg, val); 1598 } 1599 1600 bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy, 1601 enum dpio_channel ch, bool override) 1602 { 1603 struct i915_power_domains *power_domains = &display->power.domains; 1604 bool was_override; 1605 1606 mutex_lock(&power_domains->lock); 1607 1608 was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1609 1610 if (override == was_override) 1611 goto out; 1612 1613 if (override) 1614 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1615 else 1616 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1617 1618 intel_de_write(display, DISPLAY_PHY_CONTROL, 1619 display->power.chv_phy_control); 1620 1621 drm_dbg_kms(display->drm, 1622 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1623 phy, ch, display->power.chv_phy_control); 1624 1625 assert_chv_phy_status(display); 1626 1627 out: 1628 mutex_unlock(&power_domains->lock); 1629 1630 return was_override; 1631 } 1632 1633 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1634 bool override, unsigned int mask) 1635 { 1636 struct intel_display *display = to_intel_display(encoder); 1637 struct i915_power_domains *power_domains = &display->power.domains; 1638 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1639 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 1640 1641 mutex_lock(&power_domains->lock); 1642 1643 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1644 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1645 1646 if (override) 1647 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1648 else 1649 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1650 1651 intel_de_write(display, DISPLAY_PHY_CONTROL, 1652 display->power.chv_phy_control); 1653 1654 drm_dbg_kms(display->drm, 1655 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1656 phy, ch, mask, display->power.chv_phy_control); 1657 1658 assert_chv_phy_status(display); 1659 1660 assert_chv_phy_powergate(display, phy, ch, override, mask); 1661 1662 mutex_unlock(&power_domains->lock); 1663 } 1664 1665 static bool chv_pipe_power_well_enabled(struct intel_display *display, 1666 struct i915_power_well *power_well) 1667 { 1668 struct drm_i915_private *dev_priv = to_i915(display->drm); 1669 enum pipe pipe = PIPE_A; 1670 bool enabled; 1671 u32 state, ctrl; 1672 1673 vlv_punit_get(dev_priv); 1674 1675 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); 1676 /* 1677 * We only ever set the power-on and power-gate states, anything 1678 * else is unexpected. 1679 */ 1680 drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) && 1681 state != DP_SSS_PWR_GATE(pipe)); 1682 enabled = state == DP_SSS_PWR_ON(pipe); 1683 1684 /* 1685 * A transient state at this point would mean some unexpected party 1686 * is poking at the power controls too. 1687 */ 1688 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); 1689 drm_WARN_ON(display->drm, ctrl << 16 != state); 1690 1691 vlv_punit_put(dev_priv); 1692 1693 return enabled; 1694 } 1695 1696 static void chv_set_pipe_power_well(struct intel_display *display, 1697 struct i915_power_well *power_well, 1698 bool enable) 1699 { 1700 struct drm_i915_private *dev_priv = to_i915(display->drm); 1701 enum pipe pipe = PIPE_A; 1702 u32 state; 1703 u32 ctrl; 1704 1705 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1706 1707 vlv_punit_get(dev_priv); 1708 1709 #define COND \ 1710 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) 1711 1712 if (COND) 1713 goto out; 1714 1715 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 1716 ctrl &= ~DP_SSC_MASK(pipe); 1717 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1718 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl); 1719 1720 if (wait_for(COND, 100)) 1721 drm_err(display->drm, 1722 "timeout setting power well state %08x (%08x)\n", 1723 state, 1724 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); 1725 1726 #undef COND 1727 1728 out: 1729 vlv_punit_put(dev_priv); 1730 } 1731 1732 static void chv_pipe_power_well_sync_hw(struct intel_display *display, 1733 struct i915_power_well *power_well) 1734 { 1735 intel_de_write(display, DISPLAY_PHY_CONTROL, 1736 display->power.chv_phy_control); 1737 } 1738 1739 static void chv_pipe_power_well_enable(struct intel_display *display, 1740 struct i915_power_well *power_well) 1741 { 1742 chv_set_pipe_power_well(display, power_well, true); 1743 1744 vlv_display_power_well_init(display); 1745 } 1746 1747 static void chv_pipe_power_well_disable(struct intel_display *display, 1748 struct i915_power_well *power_well) 1749 { 1750 vlv_display_power_well_deinit(display); 1751 1752 chv_set_pipe_power_well(display, power_well, false); 1753 } 1754 1755 static void 1756 tgl_tc_cold_request(struct intel_display *display, bool block) 1757 { 1758 struct drm_i915_private *i915 = to_i915(display->drm); 1759 u8 tries = 0; 1760 int ret; 1761 1762 while (1) { 1763 u32 low_val; 1764 u32 high_val = 0; 1765 1766 if (block) 1767 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ; 1768 else 1769 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ; 1770 1771 /* 1772 * Spec states that we should timeout the request after 200us 1773 * but the function below will timeout after 500us 1774 */ 1775 ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val); 1776 if (ret == 0) { 1777 if (block && 1778 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED)) 1779 ret = -EIO; 1780 else 1781 break; 1782 } 1783 1784 if (++tries == 3) 1785 break; 1786 1787 msleep(1); 1788 } 1789 1790 if (ret) 1791 drm_err(&i915->drm, "TC cold %sblock failed\n", 1792 block ? "" : "un"); 1793 else 1794 drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n", 1795 block ? "" : "un"); 1796 } 1797 1798 static void 1799 tgl_tc_cold_off_power_well_enable(struct intel_display *display, 1800 struct i915_power_well *power_well) 1801 { 1802 tgl_tc_cold_request(display, true); 1803 } 1804 1805 static void 1806 tgl_tc_cold_off_power_well_disable(struct intel_display *display, 1807 struct i915_power_well *power_well) 1808 { 1809 tgl_tc_cold_request(display, false); 1810 } 1811 1812 static void 1813 tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display, 1814 struct i915_power_well *power_well) 1815 { 1816 if (intel_power_well_refcount(power_well) > 0) 1817 tgl_tc_cold_off_power_well_enable(display, power_well); 1818 else 1819 tgl_tc_cold_off_power_well_disable(display, power_well); 1820 } 1821 1822 static bool 1823 tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display, 1824 struct i915_power_well *power_well) 1825 { 1826 /* 1827 * Not the correctly implementation but there is no way to just read it 1828 * from PCODE, so returning count to avoid state mismatch errors 1829 */ 1830 return intel_power_well_refcount(power_well); 1831 } 1832 1833 static void xelpdp_aux_power_well_enable(struct intel_display *display, 1834 struct i915_power_well *power_well) 1835 { 1836 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1837 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1838 1839 if (intel_phy_is_tc(display, phy)) 1840 icl_tc_port_assert_ref_held(display, power_well, 1841 aux_ch_to_digital_port(display, aux_ch)); 1842 1843 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1844 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1845 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1846 1847 /* 1848 * The power status flag cannot be used to determine whether aux 1849 * power wells have finished powering up. Instead we're 1850 * expected to just wait a fixed 600us after raising the request 1851 * bit. 1852 */ 1853 usleep_range(600, 1200); 1854 } 1855 1856 static void xelpdp_aux_power_well_disable(struct intel_display *display, 1857 struct i915_power_well *power_well) 1858 { 1859 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1860 1861 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1862 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1863 0); 1864 usleep_range(10, 30); 1865 } 1866 1867 static bool xelpdp_aux_power_well_enabled(struct intel_display *display, 1868 struct i915_power_well *power_well) 1869 { 1870 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1871 1872 return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) & 1873 XELPDP_DP_AUX_CH_CTL_POWER_STATUS; 1874 } 1875 1876 static void xe2lpd_pica_power_well_enable(struct intel_display *display, 1877 struct i915_power_well *power_well) 1878 { 1879 intel_de_write(display, XE2LPD_PICA_PW_CTL, 1880 XE2LPD_PICA_CTL_POWER_REQUEST); 1881 1882 if (intel_de_wait_for_set(display, XE2LPD_PICA_PW_CTL, 1883 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1884 drm_dbg_kms(display->drm, "pica power well enable timeout\n"); 1885 1886 drm_WARN(display->drm, 1, "Power well PICA timeout when enabled"); 1887 } 1888 } 1889 1890 static void xe2lpd_pica_power_well_disable(struct intel_display *display, 1891 struct i915_power_well *power_well) 1892 { 1893 intel_de_write(display, XE2LPD_PICA_PW_CTL, 0); 1894 1895 if (intel_de_wait_for_clear(display, XE2LPD_PICA_PW_CTL, 1896 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1897 drm_dbg_kms(display->drm, "pica power well disable timeout\n"); 1898 1899 drm_WARN(display->drm, 1, "Power well PICA timeout when disabled"); 1900 } 1901 } 1902 1903 static bool xe2lpd_pica_power_well_enabled(struct intel_display *display, 1904 struct i915_power_well *power_well) 1905 { 1906 return intel_de_read(display, XE2LPD_PICA_PW_CTL) & 1907 XE2LPD_PICA_CTL_POWER_STATUS; 1908 } 1909 1910 const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1911 .sync_hw = i9xx_power_well_sync_hw_noop, 1912 .enable = i9xx_always_on_power_well_noop, 1913 .disable = i9xx_always_on_power_well_noop, 1914 .is_enabled = i9xx_always_on_power_well_enabled, 1915 }; 1916 1917 const struct i915_power_well_ops chv_pipe_power_well_ops = { 1918 .sync_hw = chv_pipe_power_well_sync_hw, 1919 .enable = chv_pipe_power_well_enable, 1920 .disable = chv_pipe_power_well_disable, 1921 .is_enabled = chv_pipe_power_well_enabled, 1922 }; 1923 1924 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1925 .sync_hw = i9xx_power_well_sync_hw_noop, 1926 .enable = chv_dpio_cmn_power_well_enable, 1927 .disable = chv_dpio_cmn_power_well_disable, 1928 .is_enabled = vlv_power_well_enabled, 1929 }; 1930 1931 const struct i915_power_well_ops i830_pipes_power_well_ops = { 1932 .sync_hw = i830_pipes_power_well_sync_hw, 1933 .enable = i830_pipes_power_well_enable, 1934 .disable = i830_pipes_power_well_disable, 1935 .is_enabled = i830_pipes_power_well_enabled, 1936 }; 1937 1938 static const struct i915_power_well_regs hsw_power_well_regs = { 1939 .bios = HSW_PWR_WELL_CTL1, 1940 .driver = HSW_PWR_WELL_CTL2, 1941 .kvmr = HSW_PWR_WELL_CTL3, 1942 .debug = HSW_PWR_WELL_CTL4, 1943 }; 1944 1945 const struct i915_power_well_ops hsw_power_well_ops = { 1946 .regs = &hsw_power_well_regs, 1947 .sync_hw = hsw_power_well_sync_hw, 1948 .enable = hsw_power_well_enable, 1949 .disable = hsw_power_well_disable, 1950 .is_enabled = hsw_power_well_enabled, 1951 }; 1952 1953 const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1954 .sync_hw = i9xx_power_well_sync_hw_noop, 1955 .enable = gen9_dc_off_power_well_enable, 1956 .disable = gen9_dc_off_power_well_disable, 1957 .is_enabled = gen9_dc_off_power_well_enabled, 1958 }; 1959 1960 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1961 .sync_hw = i9xx_power_well_sync_hw_noop, 1962 .enable = bxt_dpio_cmn_power_well_enable, 1963 .disable = bxt_dpio_cmn_power_well_disable, 1964 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1965 }; 1966 1967 const struct i915_power_well_ops vlv_display_power_well_ops = { 1968 .sync_hw = i9xx_power_well_sync_hw_noop, 1969 .enable = vlv_display_power_well_enable, 1970 .disable = vlv_display_power_well_disable, 1971 .is_enabled = vlv_power_well_enabled, 1972 }; 1973 1974 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1975 .sync_hw = i9xx_power_well_sync_hw_noop, 1976 .enable = vlv_dpio_cmn_power_well_enable, 1977 .disable = vlv_dpio_cmn_power_well_disable, 1978 .is_enabled = vlv_power_well_enabled, 1979 }; 1980 1981 const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1982 .sync_hw = i9xx_power_well_sync_hw_noop, 1983 .enable = vlv_power_well_enable, 1984 .disable = vlv_power_well_disable, 1985 .is_enabled = vlv_power_well_enabled, 1986 }; 1987 1988 static const struct i915_power_well_regs icl_aux_power_well_regs = { 1989 .bios = ICL_PWR_WELL_CTL_AUX1, 1990 .driver = ICL_PWR_WELL_CTL_AUX2, 1991 .debug = ICL_PWR_WELL_CTL_AUX4, 1992 }; 1993 1994 const struct i915_power_well_ops icl_aux_power_well_ops = { 1995 .regs = &icl_aux_power_well_regs, 1996 .sync_hw = hsw_power_well_sync_hw, 1997 .enable = icl_aux_power_well_enable, 1998 .disable = icl_aux_power_well_disable, 1999 .is_enabled = hsw_power_well_enabled, 2000 }; 2001 2002 static const struct i915_power_well_regs icl_ddi_power_well_regs = { 2003 .bios = ICL_PWR_WELL_CTL_DDI1, 2004 .driver = ICL_PWR_WELL_CTL_DDI2, 2005 .debug = ICL_PWR_WELL_CTL_DDI4, 2006 }; 2007 2008 const struct i915_power_well_ops icl_ddi_power_well_ops = { 2009 .regs = &icl_ddi_power_well_regs, 2010 .sync_hw = hsw_power_well_sync_hw, 2011 .enable = hsw_power_well_enable, 2012 .disable = hsw_power_well_disable, 2013 .is_enabled = hsw_power_well_enabled, 2014 }; 2015 2016 const struct i915_power_well_ops tgl_tc_cold_off_ops = { 2017 .sync_hw = tgl_tc_cold_off_power_well_sync_hw, 2018 .enable = tgl_tc_cold_off_power_well_enable, 2019 .disable = tgl_tc_cold_off_power_well_disable, 2020 .is_enabled = tgl_tc_cold_off_power_well_is_enabled, 2021 }; 2022 2023 const struct i915_power_well_ops xelpdp_aux_power_well_ops = { 2024 .sync_hw = i9xx_power_well_sync_hw_noop, 2025 .enable = xelpdp_aux_power_well_enable, 2026 .disable = xelpdp_aux_power_well_disable, 2027 .is_enabled = xelpdp_aux_power_well_enabled, 2028 }; 2029 2030 const struct i915_power_well_ops xe2lpd_pica_power_well_ops = { 2031 .sync_hw = i9xx_power_well_sync_hw_noop, 2032 .enable = xe2lpd_pica_power_well_enable, 2033 .disable = xe2lpd_pica_power_well_disable, 2034 .is_enabled = xe2lpd_pica_power_well_enabled, 2035 }; 2036