1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <linux/iopoll.h> 7 8 #include <drm/drm_print.h> 9 10 #include "i915_reg.h" 11 #include "intel_backlight_regs.h" 12 #include "intel_combo_phy.h" 13 #include "intel_combo_phy_regs.h" 14 #include "intel_crt.h" 15 #include "intel_de.h" 16 #include "intel_display_irq.h" 17 #include "intel_display_power_well.h" 18 #include "intel_display_regs.h" 19 #include "intel_display_rpm.h" 20 #include "intel_display_types.h" 21 #include "intel_dkl_phy.h" 22 #include "intel_dkl_phy_regs.h" 23 #include "intel_dmc.h" 24 #include "intel_dmc_wl.h" 25 #include "intel_dp_aux_regs.h" 26 #include "intel_dpio_phy.h" 27 #include "intel_dpll.h" 28 #include "intel_hotplug.h" 29 #include "intel_parent.h" 30 #include "intel_pcode.h" 31 #include "intel_pps.h" 32 #include "intel_psr.h" 33 #include "intel_tc.h" 34 #include "intel_vga.h" 35 #include "skl_watermark.h" 36 #include "vlv_dpio_phy_regs.h" 37 #include "vlv_iosf_sb_reg.h" 38 #include "vlv_sideband.h" 39 40 /* 41 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 42 * 43 * {ICL,SKL}_DISP_PW1_IDX..{ICL,SKL}_DISP_PW4_IDX -> PG1..PG4 44 */ 45 static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx) 46 { 47 int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1; 48 49 return pw_idx - pw1_idx + SKL_PG1; 50 } 51 52 struct i915_power_well_regs { 53 i915_reg_t bios; 54 i915_reg_t driver; 55 i915_reg_t kvmr; 56 i915_reg_t debug; 57 }; 58 59 struct i915_power_well_ops { 60 const struct i915_power_well_regs *regs; 61 /* 62 * Synchronize the well's hw state to match the current sw state, for 63 * example enable/disable it based on the current refcount. Called 64 * during driver init and resume time, possibly after first calling 65 * the enable/disable handlers. 66 */ 67 void (*sync_hw)(struct intel_display *display, 68 struct i915_power_well *power_well); 69 /* 70 * Enable the well and resources that depend on it (for example 71 * interrupts located on the well). Called after the 0->1 refcount 72 * transition. 73 */ 74 void (*enable)(struct intel_display *display, 75 struct i915_power_well *power_well); 76 /* 77 * Disable the well and resources that depend on it. Called after 78 * the 1->0 refcount transition. 79 */ 80 void (*disable)(struct intel_display *display, 81 struct i915_power_well *power_well); 82 /* Returns the hw enabled state. */ 83 bool (*is_enabled)(struct intel_display *display, 84 struct i915_power_well *power_well); 85 }; 86 87 static const struct i915_power_well_instance * 88 i915_power_well_instance(const struct i915_power_well *power_well) 89 { 90 return &power_well->desc->instances->list[power_well->instance_idx]; 91 } 92 93 struct i915_power_well * 94 lookup_power_well(struct intel_display *display, 95 enum i915_power_well_id power_well_id) 96 { 97 struct i915_power_well *power_well; 98 99 for_each_power_well(display, power_well) 100 if (i915_power_well_instance(power_well)->id == power_well_id) 101 return power_well; 102 103 /* 104 * It's not feasible to add error checking code to the callers since 105 * this condition really shouldn't happen and it doesn't even make sense 106 * to abort things like display initialization sequences. Just return 107 * the first power well and hope the WARN gets reported so we can fix 108 * our driver. 109 */ 110 drm_WARN(display->drm, 1, 111 "Power well %d not defined for this platform\n", 112 power_well_id); 113 return &display->power.domains.power_wells[0]; 114 } 115 116 void intel_power_well_enable(struct intel_display *display, 117 struct i915_power_well *power_well) 118 { 119 drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well)); 120 power_well->desc->ops->enable(display, power_well); 121 power_well->hw_enabled = true; 122 } 123 124 void intel_power_well_disable(struct intel_display *display, 125 struct i915_power_well *power_well) 126 { 127 drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well)); 128 power_well->hw_enabled = false; 129 power_well->desc->ops->disable(display, power_well); 130 } 131 132 void intel_power_well_sync_hw(struct intel_display *display, 133 struct i915_power_well *power_well) 134 { 135 power_well->desc->ops->sync_hw(display, power_well); 136 power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well); 137 } 138 139 void intel_power_well_get(struct intel_display *display, 140 struct i915_power_well *power_well) 141 { 142 if (!power_well->count++) 143 intel_power_well_enable(display, power_well); 144 } 145 146 void intel_power_well_put(struct intel_display *display, 147 struct i915_power_well *power_well) 148 { 149 drm_WARN(display->drm, !power_well->count, 150 "Use count on power well %s is already zero", 151 i915_power_well_instance(power_well)->name); 152 153 if (!--power_well->count) 154 intel_power_well_disable(display, power_well); 155 } 156 157 bool intel_power_well_is_enabled(struct intel_display *display, 158 struct i915_power_well *power_well) 159 { 160 return power_well->desc->ops->is_enabled(display, power_well); 161 } 162 163 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well) 164 { 165 return power_well->hw_enabled; 166 } 167 168 bool intel_display_power_well_is_enabled(struct intel_display *display, 169 enum i915_power_well_id power_well_id) 170 { 171 struct i915_power_well *power_well; 172 173 power_well = lookup_power_well(display, power_well_id); 174 175 return intel_power_well_is_enabled(display, power_well); 176 } 177 178 bool intel_power_well_is_always_on(struct i915_power_well *power_well) 179 { 180 return power_well->desc->always_on; 181 } 182 183 const char *intel_power_well_name(struct i915_power_well *power_well) 184 { 185 return i915_power_well_instance(power_well)->name; 186 } 187 188 struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well) 189 { 190 return &power_well->domains; 191 } 192 193 int intel_power_well_refcount(struct i915_power_well *power_well) 194 { 195 return power_well->count; 196 } 197 198 /* 199 * Starting with Haswell, we have a "Power Down Well" that can be turned off 200 * when not needed anymore. We have 4 registers that can request the power well 201 * to be enabled, and it will only be disabled if none of the registers is 202 * requesting it to be enabled. 203 */ 204 static void hsw_power_well_post_enable(struct intel_display *display, 205 u8 irq_pipe_mask, bool has_vga) 206 { 207 if (has_vga) 208 intel_vga_reset_io_mem(display); 209 210 if (irq_pipe_mask) 211 gen8_irq_power_well_post_enable(display, irq_pipe_mask); 212 } 213 214 static void hsw_power_well_pre_disable(struct intel_display *display, 215 u8 irq_pipe_mask) 216 { 217 if (irq_pipe_mask) 218 gen8_irq_power_well_pre_disable(display, irq_pipe_mask); 219 } 220 221 #define ICL_AUX_PW_TO_PHY(pw_idx) \ 222 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + PHY_A) 223 224 #define ICL_AUX_PW_TO_CH(pw_idx) \ 225 ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) 226 227 #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ 228 ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) 229 230 static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well) 231 { 232 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 233 234 return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : 235 ICL_AUX_PW_TO_CH(pw_idx); 236 } 237 238 static struct intel_digital_port * 239 aux_ch_to_digital_port(struct intel_display *display, 240 enum aux_ch aux_ch) 241 { 242 struct intel_encoder *encoder; 243 244 for_each_intel_encoder(display->drm, encoder) { 245 struct intel_digital_port *dig_port; 246 247 /* We'll check the MST primary port */ 248 if (encoder->type == INTEL_OUTPUT_DP_MST) 249 continue; 250 251 dig_port = enc_to_dig_port(encoder); 252 253 if (dig_port && dig_port->aux_ch == aux_ch) 254 return dig_port; 255 } 256 257 return NULL; 258 } 259 260 static struct intel_encoder * 261 icl_aux_pw_to_encoder(struct intel_display *display, 262 const struct i915_power_well *power_well) 263 { 264 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 265 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 266 267 /* 268 * FIXME should we care about the (VBT defined) dig_port->aux_ch 269 * relationship or should this be purely defined by the hardware layout? 270 * Currently if the port doesn't appear in the VBT, or if it's declared 271 * as HDMI-only and routed to a combo PHY, the encoder either won't be 272 * present at all or it will not have an aux_ch assigned. 273 */ 274 return dig_port ? &dig_port->base : NULL; 275 } 276 277 static enum phy icl_aux_pw_to_phy(struct intel_display *display, 278 const struct i915_power_well *power_well) 279 { 280 struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well); 281 282 return encoder ? intel_encoder_to_phy(encoder) : PHY_NONE; 283 } 284 285 static bool icl_aux_pw_is_tc_phy(struct intel_display *display, 286 const struct i915_power_well *power_well) 287 { 288 struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well); 289 290 return encoder && intel_encoder_is_tc(encoder); 291 } 292 293 static void hsw_wait_for_power_well_enable(struct intel_display *display, 294 struct i915_power_well *power_well, 295 bool timeout_expected) 296 { 297 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 298 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 299 int timeout = power_well->desc->enable_timeout ? : 1; 300 301 /* 302 * For some power wells we're not supposed to watch the status bit for 303 * an ack, but rather just wait a fixed amount of time and then 304 * proceed. This is only used on DG2. 305 */ 306 if (display->platform.dg2 && power_well->desc->fixed_enable_delay) { 307 usleep_range(600, 1200); 308 return; 309 } 310 311 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 312 if (intel_de_wait_for_set_ms(display, regs->driver, 313 HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) { 314 drm_dbg_kms(display->drm, "%s power well enable timeout\n", 315 intel_power_well_name(power_well)); 316 317 drm_WARN_ON(display->drm, !timeout_expected); 318 319 } 320 } 321 322 static u32 hsw_power_well_requesters(struct intel_display *display, 323 const struct i915_power_well_regs *regs, 324 int pw_idx) 325 { 326 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 327 u32 ret; 328 329 ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0; 330 ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0; 331 if (regs->kvmr.reg) 332 ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0; 333 ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0; 334 335 return ret; 336 } 337 338 static void hsw_wait_for_power_well_disable(struct intel_display *display, 339 struct i915_power_well *power_well) 340 { 341 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 342 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 343 u32 reqs; 344 int ret; 345 346 /* 347 * Bspec doesn't require waiting for PWs to get disabled, but still do 348 * this for paranoia. The known cases where a PW will be forced on: 349 * - a KVMR request on any power well via the KVMR request register 350 * - a DMC request on PW1 and MISC_IO power wells via the BIOS and 351 * DEBUG request registers 352 * Skip the wait in case any of the request bits are set and print a 353 * diagnostic message. 354 */ 355 reqs = hsw_power_well_requesters(display, regs, pw_idx); 356 357 ret = intel_de_wait_for_clear_ms(display, regs->driver, 358 HSW_PWR_WELL_CTL_STATE(pw_idx), 359 reqs ? 0 : 1); 360 if (!ret) 361 return; 362 363 /* Refresh requesters in case they popped up during the wait. */ 364 if (!reqs) 365 reqs = hsw_power_well_requesters(display, regs, pw_idx); 366 367 drm_dbg_kms(display->drm, 368 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 369 intel_power_well_name(power_well), 370 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 371 } 372 373 static void gen9_wait_for_power_well_fuses(struct intel_display *display, 374 enum skl_power_gate pg) 375 { 376 /* Timeout 5us for PG#0, for other PGs 1us */ 377 drm_WARN_ON(display->drm, 378 intel_de_wait_for_set_ms(display, SKL_FUSE_STATUS, 379 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 380 } 381 382 static void hsw_power_well_enable(struct intel_display *display, 383 struct i915_power_well *power_well) 384 { 385 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 386 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 387 388 if (power_well->desc->has_fuses) { 389 enum skl_power_gate pg; 390 391 pg = pw_idx_to_pg(display, pw_idx); 392 393 /* Wa_16013190616:adlp */ 394 if (display->platform.alderlake_p && pg == SKL_PG1) 395 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 396 397 /* 398 * For PW1 we have to wait both for the PW0/PG0 fuse state 399 * before enabling the power well and PW1/PG1's own fuse 400 * state after the enabling. For all other power wells with 401 * fuses we only have to wait for that PW/PG's fuse state 402 * after the enabling. 403 */ 404 if (pg == SKL_PG1) 405 gen9_wait_for_power_well_fuses(display, SKL_PG0); 406 } 407 408 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 409 410 hsw_wait_for_power_well_enable(display, power_well, false); 411 412 if (power_well->desc->has_fuses) { 413 enum skl_power_gate pg; 414 415 pg = pw_idx_to_pg(display, pw_idx); 416 417 gen9_wait_for_power_well_fuses(display, pg); 418 } 419 420 hsw_power_well_post_enable(display, 421 power_well->desc->irq_pipe_mask, 422 power_well->desc->has_vga); 423 } 424 425 static void hsw_power_well_disable(struct intel_display *display, 426 struct i915_power_well *power_well) 427 { 428 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 429 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 430 431 hsw_power_well_pre_disable(display, 432 power_well->desc->irq_pipe_mask); 433 434 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 435 hsw_wait_for_power_well_disable(display, power_well); 436 } 437 438 static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch) 439 { 440 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 441 442 return dig_port && dig_port->base.type == INTEL_OUTPUT_EDP; 443 } 444 445 static void 446 icl_combo_phy_aux_power_well_enable(struct intel_display *display, 447 struct i915_power_well *power_well) 448 { 449 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 450 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 451 452 drm_WARN_ON(display->drm, !display->platform.icelake); 453 454 intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 455 456 /* 457 * FIXME not sure if we should derive the PHY from the pw_idx, or 458 * from the VBT defined AUX_CH->DDI->PHY mapping. 459 */ 460 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 461 0, ICL_LANE_ENABLE_AUX); 462 463 hsw_wait_for_power_well_enable(display, power_well, false); 464 465 /* Display WA #1178: icl */ 466 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && 467 !intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx))) 468 intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), 469 0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI); 470 } 471 472 static void 473 icl_combo_phy_aux_power_well_disable(struct intel_display *display, 474 struct i915_power_well *power_well) 475 { 476 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 477 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 478 479 drm_WARN_ON(display->drm, !display->platform.icelake); 480 481 /* 482 * FIXME not sure if we should derive the PHY from the pw_idx, or 483 * from the VBT defined AUX_CH->DDI->PHY mapping. 484 */ 485 intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 486 ICL_LANE_ENABLE_AUX, 0); 487 488 intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 489 490 hsw_wait_for_power_well_disable(display, power_well); 491 } 492 493 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 494 495 static void icl_tc_port_assert_ref_held(struct intel_display *display, 496 struct i915_power_well *power_well, 497 struct intel_digital_port *dig_port) 498 { 499 if (drm_WARN_ON(display->drm, !dig_port)) 500 return; 501 502 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 503 return; 504 505 drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port)); 506 } 507 508 #else 509 510 static void icl_tc_port_assert_ref_held(struct intel_display *display, 511 struct i915_power_well *power_well, 512 struct intel_digital_port *dig_port) 513 { 514 } 515 516 #endif 517 518 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1) 519 520 static void icl_tc_cold_exit(struct intel_display *display) 521 { 522 int ret, tries = 0; 523 524 while (1) { 525 ret = intel_pcode_write(display->drm, ICL_PCODE_EXIT_TCCOLD, 0); 526 if (ret != -EAGAIN || ++tries == 3) 527 break; 528 msleep(1); 529 } 530 531 /* Spec states that TC cold exit can take up to 1ms to complete */ 532 if (!ret) 533 msleep(1); 534 535 /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */ 536 drm_dbg_kms(display->drm, "TC cold block %s\n", ret ? "failed" : 537 "succeeded"); 538 } 539 540 static void 541 icl_tc_phy_aux_power_well_enable(struct intel_display *display, 542 struct i915_power_well *power_well) 543 { 544 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 545 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 546 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 547 bool is_tbt = power_well->desc->is_tc_tbt; 548 bool timeout_expected; 549 u32 val; 550 int ret; 551 552 icl_tc_port_assert_ref_held(display, power_well, dig_port); 553 554 intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), 555 DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0); 556 557 intel_de_rmw(display, regs->driver, 558 0, 559 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); 560 561 /* 562 * An AUX timeout is expected if the TBT DP tunnel is down, 563 * or need to enable AUX on a legacy TypeC port as part of the TC-cold 564 * exit sequence. 565 */ 566 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port); 567 if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 568 icl_tc_cold_exit(display); 569 570 hsw_wait_for_power_well_enable(display, power_well, timeout_expected); 571 572 if (DISPLAY_VER(display) >= 12 && !is_tbt) { 573 enum tc_port tc_port; 574 575 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); 576 577 ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)), 578 val & DKL_CMN_UC_DW27_UC_HEALTH, 579 100, 1000, false); 580 if (ret) 581 drm_warn(display->drm, "Timeout waiting TC uC health\n"); 582 } 583 } 584 585 static void 586 icl_aux_power_well_enable(struct intel_display *display, 587 struct i915_power_well *power_well) 588 { 589 if (icl_aux_pw_is_tc_phy(display, power_well)) 590 return icl_tc_phy_aux_power_well_enable(display, power_well); 591 else if (display->platform.icelake) 592 return icl_combo_phy_aux_power_well_enable(display, 593 power_well); 594 else 595 return hsw_power_well_enable(display, power_well); 596 } 597 598 static void 599 icl_aux_power_well_disable(struct intel_display *display, 600 struct i915_power_well *power_well) 601 { 602 if (icl_aux_pw_is_tc_phy(display, power_well)) 603 return hsw_power_well_disable(display, power_well); 604 else if (display->platform.icelake) 605 return icl_combo_phy_aux_power_well_disable(display, 606 power_well); 607 else 608 return hsw_power_well_disable(display, power_well); 609 } 610 611 /* 612 * We should only use the power well if we explicitly asked the hardware to 613 * enable it, so check if it's enabled and also check if we've requested it to 614 * be enabled. 615 */ 616 static bool hsw_power_well_enabled(struct intel_display *display, 617 struct i915_power_well *power_well) 618 { 619 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 620 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 621 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 622 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | 623 HSW_PWR_WELL_CTL_STATE(pw_idx); 624 u32 val; 625 626 val = intel_de_read(display, regs->driver); 627 628 /* 629 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 630 * and the MISC_IO PW will be not restored, so check instead for the 631 * BIOS's own request bits, which are forced-on for these power wells 632 * when exiting DC5/6. 633 */ 634 if (DISPLAY_VER(display) == 9 && !display->platform.broxton && 635 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 636 val |= intel_de_read(display, regs->bios); 637 638 return (val & mask) == mask; 639 } 640 641 static void assert_can_enable_dc9(struct intel_display *display) 642 { 643 drm_WARN_ONCE(display->drm, 644 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), 645 "DC9 already programmed to be enabled.\n"); 646 drm_WARN_ONCE(display->drm, 647 intel_de_read(display, DC_STATE_EN) & 648 DC_STATE_EN_UPTO_DC5, 649 "DC5 still not disabled to enable DC9.\n"); 650 drm_WARN_ONCE(display->drm, 651 intel_de_read(display, HSW_PWR_WELL_CTL2) & 652 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 653 "Power well 2 on.\n"); 654 drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), 655 "Interrupts not disabled yet.\n"); 656 657 /* 658 * TODO: check for the following to verify the conditions to enter DC9 659 * state are satisfied: 660 * 1] Check relevant display engine registers to verify if mode set 661 * disable sequence was followed. 662 * 2] Check if display uninitialize sequence is initialized. 663 */ 664 } 665 666 static void assert_can_disable_dc9(struct intel_display *display) 667 { 668 drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), 669 "Interrupts not disabled yet.\n"); 670 drm_WARN_ONCE(display->drm, 671 intel_de_read(display, DC_STATE_EN) & 672 DC_STATE_EN_UPTO_DC5, 673 "DC5 still not disabled.\n"); 674 675 /* 676 * TODO: check for the following to verify DC9 state was indeed 677 * entered before programming to disable it: 678 * 1] Check relevant display engine registers to verify if mode 679 * set disable sequence was followed. 680 * 2] Check if display uninitialize sequence is initialized. 681 */ 682 } 683 684 static void gen9_write_dc_state(struct intel_display *display, 685 u32 state) 686 { 687 int rewrites = 0; 688 int rereads = 0; 689 u32 v; 690 691 intel_de_write(display, DC_STATE_EN, state); 692 693 /* It has been observed that disabling the dc6 state sometimes 694 * doesn't stick and dmc keeps returning old value. Make sure 695 * the write really sticks enough times and also force rewrite until 696 * we are confident that state is exactly what we want. 697 */ 698 do { 699 v = intel_de_read(display, DC_STATE_EN); 700 701 if (v != state) { 702 intel_de_write(display, DC_STATE_EN, state); 703 rewrites++; 704 rereads = 0; 705 } else if (rereads++ > 5) { 706 break; 707 } 708 709 } while (rewrites < 100); 710 711 if (v != state) 712 drm_err(display->drm, 713 "Writing dc state to 0x%x failed, now 0x%x\n", 714 state, v); 715 716 /* Most of the times we need one retry, avoid spam */ 717 if (rewrites > 1) 718 drm_dbg_kms(display->drm, 719 "Rewrote dc state to 0x%x %d times\n", 720 state, rewrites); 721 } 722 723 static u32 gen9_dc_mask(struct intel_display *display) 724 { 725 u32 mask; 726 727 mask = DC_STATE_EN_UPTO_DC5; 728 729 if (DISPLAY_VER(display) >= 12) 730 mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 731 | DC_STATE_EN_DC9; 732 else if (DISPLAY_VER(display) == 11) 733 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; 734 else if (display->platform.geminilake || display->platform.broxton) 735 mask |= DC_STATE_EN_DC9; 736 else 737 mask |= DC_STATE_EN_UPTO_DC6; 738 739 return mask; 740 } 741 742 void gen9_sanitize_dc_state(struct intel_display *display) 743 { 744 struct i915_power_domains *power_domains = &display->power.domains; 745 u32 val; 746 747 if (!HAS_DISPLAY(display)) 748 return; 749 750 val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display); 751 752 drm_dbg_kms(display->drm, 753 "Resetting DC state tracking from %02x to %02x\n", 754 power_domains->dc_state, val); 755 power_domains->dc_state = val; 756 } 757 758 /** 759 * gen9_set_dc_state - set target display C power state 760 * @display: display instance 761 * @state: target DC power state 762 * - DC_STATE_DISABLE 763 * - DC_STATE_EN_UPTO_DC5 764 * - DC_STATE_EN_UPTO_DC6 765 * - DC_STATE_EN_DC9 766 * 767 * Signal to DMC firmware/HW the target DC power state passed in @state. 768 * DMC/HW can turn off individual display clocks and power rails when entering 769 * a deeper DC power state (higher in number) and turns these back when exiting 770 * that state to a shallower power state (lower in number). The HW will decide 771 * when to actually enter a given state on an on-demand basis, for instance 772 * depending on the active state of display pipes. The state of display 773 * registers backed by affected power rails are saved/restored as needed. 774 * 775 * Based on the above enabling a deeper DC power state is asynchronous wrt. 776 * enabling it. Disabling a deeper power state is synchronous: for instance 777 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned 778 * back on and register state is restored. This is guaranteed by the MMIO write 779 * to DC_STATE_EN blocking until the state is restored. 780 */ 781 void gen9_set_dc_state(struct intel_display *display, u32 state) 782 { 783 struct i915_power_domains *power_domains = &display->power.domains; 784 bool dc6_was_enabled, enable_dc6; 785 u32 mask; 786 u32 val; 787 788 if (!HAS_DISPLAY(display)) 789 return; 790 791 if (drm_WARN_ON_ONCE(display->drm, 792 state & ~power_domains->allowed_dc_mask)) 793 state &= power_domains->allowed_dc_mask; 794 795 if (!power_domains->initializing) 796 intel_psr_notify_dc5_dc6(display); 797 798 val = intel_de_read(display, DC_STATE_EN); 799 mask = gen9_dc_mask(display); 800 drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", 801 val & mask, state); 802 803 /* Check if DMC is ignoring our DC state requests */ 804 if ((val & mask) != power_domains->dc_state) 805 drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n", 806 power_domains->dc_state, val & mask); 807 808 enable_dc6 = state & DC_STATE_EN_UPTO_DC6; 809 dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6; 810 if (!dc6_was_enabled && enable_dc6) 811 intel_dmc_update_dc6_allowed_count(display, true); 812 813 val &= ~mask; 814 val |= state; 815 816 gen9_write_dc_state(display, val); 817 818 if (!enable_dc6 && dc6_was_enabled) 819 intel_dmc_update_dc6_allowed_count(display, false); 820 821 power_domains->dc_state = val & mask; 822 } 823 824 static void tgl_enable_dc3co(struct intel_display *display) 825 { 826 drm_dbg_kms(display->drm, "Enabling DC3CO\n"); 827 gen9_set_dc_state(display, DC_STATE_EN_DC3CO); 828 } 829 830 static void tgl_disable_dc3co(struct intel_display *display) 831 { 832 drm_dbg_kms(display->drm, "Disabling DC3CO\n"); 833 intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); 834 gen9_set_dc_state(display, DC_STATE_DISABLE); 835 /* 836 * Delay of 200us DC3CO Exit time B.Spec 49196 837 */ 838 usleep_range(200, 210); 839 } 840 841 static void assert_can_enable_dc5(struct intel_display *display) 842 { 843 enum i915_power_well_id high_pg; 844 845 /* Power wells at this level and above must be disabled for DC5 entry */ 846 if (DISPLAY_VER(display) == 12) 847 high_pg = ICL_DISP_PW_3; 848 else 849 high_pg = SKL_DISP_PW_2; 850 851 drm_WARN_ONCE(display->drm, 852 intel_display_power_well_is_enabled(display, high_pg), 853 "Power wells above platform's DC5 limit still enabled.\n"); 854 855 drm_WARN_ONCE(display->drm, 856 (intel_de_read(display, DC_STATE_EN) & 857 DC_STATE_EN_UPTO_DC5), 858 "DC5 already programmed to be enabled.\n"); 859 860 assert_display_rpm_held(display); 861 862 assert_main_dmc_loaded(display); 863 } 864 865 void gen9_enable_dc5(struct intel_display *display) 866 { 867 assert_can_enable_dc5(display); 868 869 drm_dbg_kms(display->drm, "Enabling DC5\n"); 870 871 /* Wa Display #1183: skl,kbl,cfl */ 872 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 873 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 874 0, SKL_SELECT_ALTERNATE_DC_EXIT); 875 876 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5); 877 878 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); 879 } 880 881 static void assert_can_enable_dc6(struct intel_display *display) 882 { 883 drm_WARN_ONCE(display->drm, 884 (intel_de_read(display, UTIL_PIN_CTL) & 885 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == 886 (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), 887 "Utility pin enabled in PWM mode\n"); 888 drm_WARN_ONCE(display->drm, 889 (intel_de_read(display, DC_STATE_EN) & 890 DC_STATE_EN_UPTO_DC6), 891 "DC6 already programmed to be enabled.\n"); 892 893 assert_main_dmc_loaded(display); 894 } 895 896 void skl_enable_dc6(struct intel_display *display) 897 { 898 assert_can_enable_dc6(display); 899 900 drm_dbg_kms(display->drm, "Enabling DC6\n"); 901 902 /* Wa Display #1183: skl,kbl,cfl */ 903 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 904 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 905 0, SKL_SELECT_ALTERNATE_DC_EXIT); 906 907 intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6); 908 909 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); 910 } 911 912 void bxt_enable_dc9(struct intel_display *display) 913 { 914 assert_can_enable_dc9(display); 915 916 drm_dbg_kms(display->drm, "Enabling DC9\n"); 917 /* 918 * Power sequencer reset is needed on BXT/GLK, because the PPS registers 919 * aren't always on, unlike with South Display Engine on PCH. 920 */ 921 if (display->platform.broxton || display->platform.geminilake) 922 bxt_pps_reset_all(display); 923 gen9_set_dc_state(display, DC_STATE_EN_DC9); 924 } 925 926 void bxt_disable_dc9(struct intel_display *display) 927 { 928 assert_can_disable_dc9(display); 929 930 drm_dbg_kms(display->drm, "Disabling DC9\n"); 931 932 gen9_set_dc_state(display, DC_STATE_DISABLE); 933 934 intel_pps_unlock_regs_wa(display); 935 } 936 937 static void hsw_power_well_sync_hw(struct intel_display *display, 938 struct i915_power_well *power_well) 939 { 940 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 941 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 942 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 943 u32 bios_req = intel_de_read(display, regs->bios); 944 945 /* Take over the request bit if set by BIOS. */ 946 if (bios_req & mask) { 947 u32 drv_req = intel_de_read(display, regs->driver); 948 949 if (!(drv_req & mask)) 950 intel_de_write(display, regs->driver, drv_req | mask); 951 intel_de_write(display, regs->bios, bios_req & ~mask); 952 } 953 } 954 955 static void bxt_dpio_cmn_power_well_enable(struct intel_display *display, 956 struct i915_power_well *power_well) 957 { 958 bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy); 959 } 960 961 static void bxt_dpio_cmn_power_well_disable(struct intel_display *display, 962 struct i915_power_well *power_well) 963 { 964 bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy); 965 } 966 967 static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display, 968 struct i915_power_well *power_well) 969 { 970 return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy); 971 } 972 973 static void bxt_verify_dpio_phy_power_wells(struct intel_display *display) 974 { 975 struct i915_power_well *power_well; 976 977 power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A); 978 if (intel_power_well_refcount(power_well) > 0) 979 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 980 981 power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 982 if (intel_power_well_refcount(power_well) > 0) 983 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 984 985 if (display->platform.geminilake) { 986 power_well = lookup_power_well(display, 987 GLK_DISP_PW_DPIO_CMN_C); 988 if (intel_power_well_refcount(power_well) > 0) 989 bxt_dpio_phy_verify_state(display, 990 i915_power_well_instance(power_well)->bxt.phy); 991 } 992 } 993 994 static bool gen9_dc_off_power_well_enabled(struct intel_display *display, 995 struct i915_power_well *power_well) 996 { 997 return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && 998 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); 999 } 1000 1001 static void gen9_assert_dbuf_enabled(struct intel_display *display) 1002 { 1003 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display); 1004 u8 enabled_dbuf_slices = display->dbuf.enabled_slices; 1005 1006 drm_WARN(display->drm, 1007 hw_enabled_dbuf_slices != enabled_dbuf_slices, 1008 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 1009 hw_enabled_dbuf_slices, 1010 enabled_dbuf_slices); 1011 } 1012 1013 void gen9_disable_dc_states(struct intel_display *display) 1014 { 1015 struct i915_power_domains *power_domains = &display->power.domains; 1016 struct intel_cdclk_config cdclk_config = {}; 1017 u32 old_state = power_domains->dc_state; 1018 1019 if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { 1020 tgl_disable_dc3co(display); 1021 return; 1022 } 1023 1024 if (HAS_DISPLAY(display)) { 1025 intel_dmc_wl_get_noreg(display); 1026 gen9_set_dc_state(display, DC_STATE_DISABLE); 1027 intel_dmc_wl_put_noreg(display); 1028 } else { 1029 gen9_set_dc_state(display, DC_STATE_DISABLE); 1030 return; 1031 } 1032 1033 if (old_state == DC_STATE_EN_UPTO_DC5 || 1034 old_state == DC_STATE_EN_UPTO_DC6) 1035 intel_dmc_wl_disable(display); 1036 1037 intel_cdclk_get_cdclk(display, &cdclk_config); 1038 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ 1039 drm_WARN_ON(display->drm, 1040 intel_cdclk_clock_changed(&display->cdclk.hw, 1041 &cdclk_config)); 1042 1043 gen9_assert_dbuf_enabled(display); 1044 1045 if (display->platform.geminilake || display->platform.broxton) 1046 bxt_verify_dpio_phy_power_wells(display); 1047 1048 if (DISPLAY_VER(display) >= 11) 1049 /* 1050 * DMC retains HW context only for port A, the other combo 1051 * PHY's HW context for port B is lost after DC transitions, 1052 * so we need to restore it manually. 1053 */ 1054 intel_combo_phy_init(display); 1055 } 1056 1057 static void gen9_dc_off_power_well_enable(struct intel_display *display, 1058 struct i915_power_well *power_well) 1059 { 1060 gen9_disable_dc_states(display); 1061 } 1062 1063 static void gen9_dc_off_power_well_disable(struct intel_display *display, 1064 struct i915_power_well *power_well) 1065 { 1066 struct i915_power_domains *power_domains = &display->power.domains; 1067 1068 if (!intel_dmc_has_payload(display)) 1069 return; 1070 1071 switch (power_domains->target_dc_state) { 1072 case DC_STATE_EN_DC3CO: 1073 tgl_enable_dc3co(display); 1074 break; 1075 case DC_STATE_EN_UPTO_DC6: 1076 skl_enable_dc6(display); 1077 break; 1078 case DC_STATE_EN_UPTO_DC5: 1079 gen9_enable_dc5(display); 1080 break; 1081 } 1082 } 1083 1084 static void i9xx_power_well_sync_hw_noop(struct intel_display *display, 1085 struct i915_power_well *power_well) 1086 { 1087 } 1088 1089 static void i9xx_always_on_power_well_noop(struct intel_display *display, 1090 struct i915_power_well *power_well) 1091 { 1092 } 1093 1094 static bool i9xx_always_on_power_well_enabled(struct intel_display *display, 1095 struct i915_power_well *power_well) 1096 { 1097 return true; 1098 } 1099 1100 static void i830_pipes_power_well_enable(struct intel_display *display, 1101 struct i915_power_well *power_well) 1102 { 1103 if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) 1104 i830_enable_pipe(display, PIPE_A); 1105 if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0) 1106 i830_enable_pipe(display, PIPE_B); 1107 } 1108 1109 static void i830_pipes_power_well_disable(struct intel_display *display, 1110 struct i915_power_well *power_well) 1111 { 1112 i830_disable_pipe(display, PIPE_B); 1113 i830_disable_pipe(display, PIPE_A); 1114 } 1115 1116 static bool i830_pipes_power_well_enabled(struct intel_display *display, 1117 struct i915_power_well *power_well) 1118 { 1119 return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && 1120 intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; 1121 } 1122 1123 static void i830_pipes_power_well_sync_hw(struct intel_display *display, 1124 struct i915_power_well *power_well) 1125 { 1126 if (intel_power_well_refcount(power_well) > 0) 1127 i830_pipes_power_well_enable(display, power_well); 1128 else 1129 i830_pipes_power_well_disable(display, power_well); 1130 } 1131 1132 static void vlv_set_power_well(struct intel_display *display, 1133 struct i915_power_well *power_well, bool enable) 1134 { 1135 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1136 u32 mask; 1137 u32 state; 1138 u32 ctrl; 1139 u32 val; 1140 int ret; 1141 1142 mask = PUNIT_PWRGT_MASK(pw_idx); 1143 state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : 1144 PUNIT_PWRGT_PWR_GATE(pw_idx); 1145 1146 vlv_punit_get(display->drm); 1147 1148 val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS); 1149 if ((val & mask) == state) 1150 goto out; 1151 1152 ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL); 1153 ctrl &= ~mask; 1154 ctrl |= state; 1155 vlv_punit_write(display->drm, PUNIT_REG_PWRGT_CTRL, ctrl); 1156 1157 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS), 1158 (val & mask) == state, 1159 500, 100 * 1000, false); 1160 if (ret) 1161 drm_err(display->drm, 1162 "timeout setting power well state %08x (%08x)\n", 1163 state, 1164 vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL)); 1165 1166 out: 1167 vlv_punit_put(display->drm); 1168 } 1169 1170 static void vlv_power_well_enable(struct intel_display *display, 1171 struct i915_power_well *power_well) 1172 { 1173 vlv_set_power_well(display, power_well, true); 1174 } 1175 1176 static void vlv_power_well_disable(struct intel_display *display, 1177 struct i915_power_well *power_well) 1178 { 1179 vlv_set_power_well(display, power_well, false); 1180 } 1181 1182 static bool vlv_power_well_enabled(struct intel_display *display, 1183 struct i915_power_well *power_well) 1184 { 1185 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1186 bool enabled = false; 1187 u32 mask; 1188 u32 state; 1189 u32 ctrl; 1190 1191 mask = PUNIT_PWRGT_MASK(pw_idx); 1192 ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); 1193 1194 vlv_punit_get(display->drm); 1195 1196 state = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask; 1197 /* 1198 * We only ever set the power-on and power-gate states, anything 1199 * else is unexpected. 1200 */ 1201 drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1202 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 1203 if (state == ctrl) 1204 enabled = true; 1205 1206 /* 1207 * A transient state at this point would mean some unexpected party 1208 * is poking at the power controls too. 1209 */ 1210 ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL) & mask; 1211 drm_WARN_ON(display->drm, ctrl != state); 1212 1213 vlv_punit_put(display->drm); 1214 1215 return enabled; 1216 } 1217 1218 static void vlv_init_display_clock_gating(struct intel_display *display) 1219 { 1220 /* 1221 * On driver load, a pipe may be active and driving a DSI display. 1222 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1223 * (and never recovering) in this case. intel_dsi_post_disable() will 1224 * clear it when we turn off the display. 1225 */ 1226 intel_de_rmw(display, VLV_DSPCLK_GATE_D, 1227 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE); 1228 1229 /* 1230 * Disable trickle feed and enable pnd deadline calculation 1231 */ 1232 intel_de_write(display, MI_ARB_VLV, 1233 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1234 intel_de_write(display, CBR1_VLV, 0); 1235 1236 drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0); 1237 intel_de_write(display, RAWCLK_FREQ_VLV, 1238 DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 1239 1000)); 1240 } 1241 1242 static void vlv_display_power_well_init(struct intel_display *display) 1243 { 1244 struct intel_encoder *encoder; 1245 enum pipe pipe; 1246 1247 /* 1248 * Enable the CRI clock source so we can get at the 1249 * display and the reference clock for VGA 1250 * hotplug / manual detection. Supposedly DSI also 1251 * needs the ref clock up and running. 1252 * 1253 * CHV DPLL B/C have some issues if VGA mode is enabled. 1254 */ 1255 for_each_pipe(display, pipe) { 1256 u32 val = intel_de_read(display, DPLL(display, pipe)); 1257 1258 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1259 if (pipe != PIPE_A) 1260 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1261 1262 intel_de_write(display, DPLL(display, pipe), val); 1263 } 1264 1265 vlv_init_display_clock_gating(display); 1266 1267 valleyview_enable_display_irqs(display); 1268 1269 /* 1270 * During driver initialization/resume we can avoid restoring the 1271 * part of the HW/SW state that will be inited anyway explicitly. 1272 */ 1273 if (display->power.domains.initializing) 1274 return; 1275 1276 intel_hpd_init(display); 1277 intel_hpd_poll_disable(display); 1278 1279 /* Re-enable the ADPA, if we have one */ 1280 for_each_intel_encoder(display->drm, encoder) { 1281 if (encoder->type == INTEL_OUTPUT_ANALOG) 1282 intel_crt_reset(&encoder->base); 1283 } 1284 1285 intel_vga_disable(display); 1286 1287 intel_pps_unlock_regs_wa(display); 1288 } 1289 1290 static void vlv_display_power_well_deinit(struct intel_display *display) 1291 { 1292 valleyview_disable_display_irqs(display); 1293 1294 /* make sure we're done processing display irqs */ 1295 intel_parent_irq_synchronize(display); 1296 1297 vlv_pps_reset_all(display); 1298 1299 /* Prevent us from re-enabling polling on accident in late suspend */ 1300 if (!display->drm->dev->power.is_suspended) 1301 intel_hpd_poll_enable(display); 1302 } 1303 1304 static void vlv_display_power_well_enable(struct intel_display *display, 1305 struct i915_power_well *power_well) 1306 { 1307 vlv_set_power_well(display, power_well, true); 1308 1309 vlv_display_power_well_init(display); 1310 } 1311 1312 static void vlv_display_power_well_disable(struct intel_display *display, 1313 struct i915_power_well *power_well) 1314 { 1315 vlv_display_power_well_deinit(display); 1316 1317 vlv_set_power_well(display, power_well, false); 1318 } 1319 1320 static void vlv_dpio_cmn_power_well_enable(struct intel_display *display, 1321 struct i915_power_well *power_well) 1322 { 1323 /* since ref/cri clock was enabled */ 1324 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1325 1326 vlv_set_power_well(display, power_well, true); 1327 1328 /* 1329 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1330 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1331 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1332 * b. The other bits such as sfr settings / modesel may all 1333 * be set to 0. 1334 * 1335 * This should only be done on init and resume from S3 with 1336 * both PLLs disabled, or we risk losing DPIO and PLL 1337 * synchronization. 1338 */ 1339 intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST); 1340 } 1341 1342 static void vlv_dpio_cmn_power_well_disable(struct intel_display *display, 1343 struct i915_power_well *power_well) 1344 { 1345 enum pipe pipe; 1346 1347 for_each_pipe(display, pipe) 1348 assert_pll_disabled(display, pipe); 1349 1350 /* Assert common reset */ 1351 intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); 1352 1353 vlv_set_power_well(display, power_well, false); 1354 } 1355 1356 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1357 1358 static void assert_chv_phy_status(struct intel_display *display) 1359 { 1360 struct i915_power_well *cmn_bc = 1361 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1362 struct i915_power_well *cmn_d = 1363 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1364 u32 phy_control = display->power.chv_phy_control; 1365 u32 phy_status = 0; 1366 u32 phy_status_mask = 0xffffffff; 1367 u32 val; 1368 1369 /* 1370 * The BIOS can leave the PHY is some weird state 1371 * where it doesn't fully power down some parts. 1372 * Disable the asserts until the PHY has been fully 1373 * reset (ie. the power well has been disabled at 1374 * least once). 1375 */ 1376 if (!display->power.chv_phy_assert[DPIO_PHY0]) 1377 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1378 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1379 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1380 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1381 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1382 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1383 1384 if (!display->power.chv_phy_assert[DPIO_PHY1]) 1385 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1386 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1387 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1388 1389 if (intel_power_well_is_enabled(display, cmn_bc)) { 1390 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1391 1392 /* this assumes override is only used to enable lanes */ 1393 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1394 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1395 1396 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1397 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1398 1399 /* CL1 is on whenever anything is on in either channel */ 1400 if (BITS_SET(phy_control, 1401 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1402 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1403 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1404 1405 /* 1406 * The DPLLB check accounts for the pipe B + port A usage 1407 * with CL2 powered up but all the lanes in the second channel 1408 * powered down. 1409 */ 1410 if (BITS_SET(phy_control, 1411 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1412 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1413 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1414 1415 if (BITS_SET(phy_control, 1416 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1417 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1418 if (BITS_SET(phy_control, 1419 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1420 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1421 1422 if (BITS_SET(phy_control, 1423 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1424 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1425 if (BITS_SET(phy_control, 1426 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1427 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1428 } 1429 1430 if (intel_power_well_is_enabled(display, cmn_d)) { 1431 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1432 1433 /* this assumes override is only used to enable lanes */ 1434 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1435 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1436 1437 if (BITS_SET(phy_control, 1438 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1439 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1440 1441 if (BITS_SET(phy_control, 1442 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1443 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1444 if (BITS_SET(phy_control, 1445 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1446 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1447 } 1448 1449 phy_status &= phy_status_mask; 1450 1451 /* 1452 * The PHY may be busy with some initial calibration and whatnot, 1453 * so the power state can take a while to actually change. 1454 */ 1455 if (intel_de_wait_ms(display, DISPLAY_PHY_STATUS, 1456 phy_status_mask, phy_status, 10, &val)) 1457 drm_err(display->drm, 1458 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1459 val & phy_status_mask, phy_status, display->power.chv_phy_control); 1460 } 1461 1462 #undef BITS_SET 1463 1464 static void chv_dpio_cmn_power_well_enable(struct intel_display *display, 1465 struct i915_power_well *power_well) 1466 { 1467 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1468 enum dpio_phy phy; 1469 u32 tmp; 1470 1471 drm_WARN_ON_ONCE(display->drm, 1472 id != VLV_DISP_PW_DPIO_CMN_BC && 1473 id != CHV_DISP_PW_DPIO_CMN_D); 1474 1475 if (id == VLV_DISP_PW_DPIO_CMN_BC) 1476 phy = DPIO_PHY0; 1477 else 1478 phy = DPIO_PHY1; 1479 1480 /* since ref/cri clock was enabled */ 1481 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1482 vlv_set_power_well(display, power_well, true); 1483 1484 /* Poll for phypwrgood signal */ 1485 if (intel_de_wait_for_set_ms(display, DISPLAY_PHY_STATUS, 1486 PHY_POWERGOOD(phy), 1)) 1487 drm_err(display->drm, "Display PHY %d is not power up\n", 1488 phy); 1489 1490 vlv_dpio_get(display->drm); 1491 1492 /* Enable dynamic power down */ 1493 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW28); 1494 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1495 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1496 vlv_dpio_write(display->drm, phy, CHV_CMN_DW28, tmp); 1497 1498 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1499 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW6_CH1); 1500 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1501 vlv_dpio_write(display->drm, phy, CHV_CMN_DW6_CH1, tmp); 1502 } else { 1503 /* 1504 * Force the non-existing CL2 off. BXT does this 1505 * too, so maybe it saves some power even though 1506 * CL2 doesn't exist? 1507 */ 1508 tmp = vlv_dpio_read(display->drm, phy, CHV_CMN_DW30); 1509 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1510 vlv_dpio_write(display->drm, phy, CHV_CMN_DW30, tmp); 1511 } 1512 1513 vlv_dpio_put(display->drm); 1514 1515 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1516 intel_de_write(display, DISPLAY_PHY_CONTROL, 1517 display->power.chv_phy_control); 1518 1519 drm_dbg_kms(display->drm, 1520 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1521 phy, display->power.chv_phy_control); 1522 1523 assert_chv_phy_status(display); 1524 } 1525 1526 static void chv_dpio_cmn_power_well_disable(struct intel_display *display, 1527 struct i915_power_well *power_well) 1528 { 1529 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1530 enum dpio_phy phy; 1531 1532 drm_WARN_ON_ONCE(display->drm, 1533 id != VLV_DISP_PW_DPIO_CMN_BC && 1534 id != CHV_DISP_PW_DPIO_CMN_D); 1535 1536 if (id == VLV_DISP_PW_DPIO_CMN_BC) { 1537 phy = DPIO_PHY0; 1538 assert_pll_disabled(display, PIPE_A); 1539 assert_pll_disabled(display, PIPE_B); 1540 } else { 1541 phy = DPIO_PHY1; 1542 assert_pll_disabled(display, PIPE_C); 1543 } 1544 1545 display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1546 intel_de_write(display, DISPLAY_PHY_CONTROL, 1547 display->power.chv_phy_control); 1548 1549 vlv_set_power_well(display, power_well, false); 1550 1551 drm_dbg_kms(display->drm, 1552 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1553 phy, display->power.chv_phy_control); 1554 1555 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1556 display->power.chv_phy_assert[phy] = true; 1557 1558 assert_chv_phy_status(display); 1559 } 1560 1561 static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy, 1562 enum dpio_channel ch, bool override, unsigned int mask) 1563 { 1564 u32 reg, val, expected, actual; 1565 1566 /* 1567 * The BIOS can leave the PHY is some weird state 1568 * where it doesn't fully power down some parts. 1569 * Disable the asserts until the PHY has been fully 1570 * reset (ie. the power well has been disabled at 1571 * least once). 1572 */ 1573 if (!display->power.chv_phy_assert[phy]) 1574 return; 1575 1576 if (ch == DPIO_CH0) 1577 reg = CHV_CMN_DW0_CH0; 1578 else 1579 reg = CHV_CMN_DW6_CH1; 1580 1581 vlv_dpio_get(display->drm); 1582 val = vlv_dpio_read(display->drm, phy, reg); 1583 vlv_dpio_put(display->drm); 1584 1585 /* 1586 * This assumes !override is only used when the port is disabled. 1587 * All lanes should power down even without the override when 1588 * the port is disabled. 1589 */ 1590 if (!override || mask == 0xf) { 1591 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1592 /* 1593 * If CH1 common lane is not active anymore 1594 * (eg. for pipe B DPLL) the entire channel will 1595 * shut down, which causes the common lane registers 1596 * to read as 0. That means we can't actually check 1597 * the lane power down status bits, but as the entire 1598 * register reads as 0 it's a good indication that the 1599 * channel is indeed entirely powered down. 1600 */ 1601 if (ch == DPIO_CH1 && val == 0) 1602 expected = 0; 1603 } else if (mask != 0x0) { 1604 expected = DPIO_ANYDL_POWERDOWN; 1605 } else { 1606 expected = 0; 1607 } 1608 1609 if (ch == DPIO_CH0) 1610 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 | 1611 DPIO_ALLDL_POWERDOWN_CH0, val); 1612 else 1613 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 | 1614 DPIO_ALLDL_POWERDOWN_CH1, val); 1615 1616 drm_WARN(display->drm, actual != expected, 1617 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1618 !!(actual & DPIO_ALLDL_POWERDOWN), 1619 !!(actual & DPIO_ANYDL_POWERDOWN), 1620 !!(expected & DPIO_ALLDL_POWERDOWN), 1621 !!(expected & DPIO_ANYDL_POWERDOWN), 1622 reg, val); 1623 } 1624 1625 bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy, 1626 enum dpio_channel ch, bool override) 1627 { 1628 struct i915_power_domains *power_domains = &display->power.domains; 1629 bool was_override; 1630 1631 mutex_lock(&power_domains->lock); 1632 1633 was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1634 1635 if (override == was_override) 1636 goto out; 1637 1638 if (override) 1639 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1640 else 1641 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1642 1643 intel_de_write(display, DISPLAY_PHY_CONTROL, 1644 display->power.chv_phy_control); 1645 1646 drm_dbg_kms(display->drm, 1647 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1648 phy, ch, display->power.chv_phy_control); 1649 1650 assert_chv_phy_status(display); 1651 1652 out: 1653 mutex_unlock(&power_domains->lock); 1654 1655 return was_override; 1656 } 1657 1658 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1659 bool override, unsigned int mask) 1660 { 1661 struct intel_display *display = to_intel_display(encoder); 1662 struct i915_power_domains *power_domains = &display->power.domains; 1663 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1664 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 1665 1666 mutex_lock(&power_domains->lock); 1667 1668 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1669 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1670 1671 if (override) 1672 display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1673 else 1674 display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1675 1676 intel_de_write(display, DISPLAY_PHY_CONTROL, 1677 display->power.chv_phy_control); 1678 1679 drm_dbg_kms(display->drm, 1680 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1681 phy, ch, mask, display->power.chv_phy_control); 1682 1683 assert_chv_phy_status(display); 1684 1685 assert_chv_phy_powergate(display, phy, ch, override, mask); 1686 1687 mutex_unlock(&power_domains->lock); 1688 } 1689 1690 static bool chv_pipe_power_well_enabled(struct intel_display *display, 1691 struct i915_power_well *power_well) 1692 { 1693 enum pipe pipe = PIPE_A; 1694 bool enabled; 1695 u32 state, ctrl; 1696 1697 vlv_punit_get(display->drm); 1698 1699 state = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); 1700 /* 1701 * We only ever set the power-on and power-gate states, anything 1702 * else is unexpected. 1703 */ 1704 drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) && 1705 state != DP_SSS_PWR_GATE(pipe)); 1706 enabled = state == DP_SSS_PWR_ON(pipe); 1707 1708 /* 1709 * A transient state at this point would mean some unexpected party 1710 * is poking at the power controls too. 1711 */ 1712 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); 1713 drm_WARN_ON(display->drm, ctrl << 16 != state); 1714 1715 vlv_punit_put(display->drm); 1716 1717 return enabled; 1718 } 1719 1720 static void chv_set_pipe_power_well(struct intel_display *display, 1721 struct i915_power_well *power_well, 1722 bool enable) 1723 { 1724 enum pipe pipe = PIPE_A; 1725 u32 state; 1726 u32 ctrl; 1727 int ret; 1728 1729 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1730 1731 vlv_punit_get(display->drm); 1732 1733 ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 1734 if ((ctrl & DP_SSS_MASK(pipe)) == state) 1735 goto out; 1736 1737 ctrl &= ~DP_SSC_MASK(pipe); 1738 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1739 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, ctrl); 1740 1741 ret = poll_timeout_us(ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), 1742 (ctrl & DP_SSS_MASK(pipe)) == state, 1743 500, 100 * 1000, false); 1744 if (ret) 1745 drm_err(display->drm, 1746 "timeout setting power well state %08x (%08x)\n", 1747 state, 1748 vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM)); 1749 1750 #undef COND 1751 1752 out: 1753 vlv_punit_put(display->drm); 1754 } 1755 1756 static void chv_pipe_power_well_sync_hw(struct intel_display *display, 1757 struct i915_power_well *power_well) 1758 { 1759 intel_de_write(display, DISPLAY_PHY_CONTROL, 1760 display->power.chv_phy_control); 1761 } 1762 1763 static void chv_pipe_power_well_enable(struct intel_display *display, 1764 struct i915_power_well *power_well) 1765 { 1766 chv_set_pipe_power_well(display, power_well, true); 1767 1768 vlv_display_power_well_init(display); 1769 } 1770 1771 static void chv_pipe_power_well_disable(struct intel_display *display, 1772 struct i915_power_well *power_well) 1773 { 1774 vlv_display_power_well_deinit(display); 1775 1776 chv_set_pipe_power_well(display, power_well, false); 1777 } 1778 1779 static void 1780 tgl_tc_cold_request(struct intel_display *display, bool block) 1781 { 1782 u8 tries = 0; 1783 int ret; 1784 1785 while (1) { 1786 u32 low_val; 1787 u32 high_val = 0; 1788 1789 if (block) 1790 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ; 1791 else 1792 low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ; 1793 1794 /* 1795 * Spec states that we should timeout the request after 200us 1796 * but the function below will timeout after 500us 1797 */ 1798 ret = intel_pcode_read(display->drm, TGL_PCODE_TCCOLD, &low_val, &high_val); 1799 if (ret == 0) { 1800 if (block && 1801 (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED)) 1802 ret = -EIO; 1803 else 1804 break; 1805 } 1806 1807 if (++tries == 3) 1808 break; 1809 1810 msleep(1); 1811 } 1812 1813 if (ret) 1814 drm_err(display->drm, "TC cold %sblock failed\n", block ? "" : "un"); 1815 else 1816 drm_dbg_kms(display->drm, "TC cold %sblock succeeded\n", 1817 block ? "" : "un"); 1818 } 1819 1820 static void 1821 tgl_tc_cold_off_power_well_enable(struct intel_display *display, 1822 struct i915_power_well *power_well) 1823 { 1824 tgl_tc_cold_request(display, true); 1825 } 1826 1827 static void 1828 tgl_tc_cold_off_power_well_disable(struct intel_display *display, 1829 struct i915_power_well *power_well) 1830 { 1831 tgl_tc_cold_request(display, false); 1832 } 1833 1834 static void 1835 tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display, 1836 struct i915_power_well *power_well) 1837 { 1838 if (intel_power_well_refcount(power_well) > 0) 1839 tgl_tc_cold_off_power_well_enable(display, power_well); 1840 else 1841 tgl_tc_cold_off_power_well_disable(display, power_well); 1842 } 1843 1844 static bool 1845 tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display, 1846 struct i915_power_well *power_well) 1847 { 1848 /* 1849 * Not the correctly implementation but there is no way to just read it 1850 * from PCODE, so returning count to avoid state mismatch errors 1851 */ 1852 return intel_power_well_refcount(power_well); 1853 } 1854 1855 static void xelpdp_aux_power_well_enable(struct intel_display *display, 1856 struct i915_power_well *power_well) 1857 { 1858 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1859 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1860 1861 if (icl_aux_pw_is_tc_phy(display, power_well)) 1862 icl_tc_port_assert_ref_held(display, power_well, 1863 aux_ch_to_digital_port(display, aux_ch)); 1864 1865 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1866 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1867 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1868 1869 if (HAS_LT_PHY(display)) { 1870 if (intel_de_wait_for_set_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1871 XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2)) 1872 drm_warn(display->drm, 1873 "Timeout waiting for PHY %c AUX channel power to be up\n", 1874 phy_name(phy)); 1875 } else { 1876 /* 1877 * The power status flag cannot be used to determine whether aux 1878 * power wells have finished powering up. Instead we're 1879 * expected to just wait a fixed 600us after raising the request 1880 * bit. 1881 */ 1882 usleep_range(600, 1200); 1883 } 1884 } 1885 1886 static void xelpdp_aux_power_well_disable(struct intel_display *display, 1887 struct i915_power_well *power_well) 1888 { 1889 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1890 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1891 1892 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1893 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1894 0); 1895 1896 if (HAS_LT_PHY(display)) { 1897 if (intel_de_wait_for_clear_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1898 XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1)) 1899 drm_warn(display->drm, 1900 "Timeout waiting for PHY %c AUX channel to powerdown\n", 1901 phy_name(phy)); 1902 } else { 1903 usleep_range(10, 30); 1904 } 1905 } 1906 1907 static bool xelpdp_aux_power_well_enabled(struct intel_display *display, 1908 struct i915_power_well *power_well) 1909 { 1910 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1911 1912 return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) & 1913 XELPDP_DP_AUX_CH_CTL_POWER_STATUS; 1914 } 1915 1916 static void xe2lpd_pica_power_well_enable(struct intel_display *display, 1917 struct i915_power_well *power_well) 1918 { 1919 intel_de_write(display, XE2LPD_PICA_PW_CTL, 1920 XE2LPD_PICA_CTL_POWER_REQUEST); 1921 1922 if (intel_de_wait_for_set_ms(display, XE2LPD_PICA_PW_CTL, 1923 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1924 drm_dbg_kms(display->drm, "pica power well enable timeout\n"); 1925 1926 drm_WARN(display->drm, 1, "Power well PICA timeout when enabled"); 1927 } 1928 } 1929 1930 static void xe2lpd_pica_power_well_disable(struct intel_display *display, 1931 struct i915_power_well *power_well) 1932 { 1933 intel_de_write(display, XE2LPD_PICA_PW_CTL, 0); 1934 1935 if (intel_de_wait_for_clear_ms(display, XE2LPD_PICA_PW_CTL, 1936 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1937 drm_dbg_kms(display->drm, "pica power well disable timeout\n"); 1938 1939 drm_WARN(display->drm, 1, "Power well PICA timeout when disabled"); 1940 } 1941 } 1942 1943 static bool xe2lpd_pica_power_well_enabled(struct intel_display *display, 1944 struct i915_power_well *power_well) 1945 { 1946 return intel_de_read(display, XE2LPD_PICA_PW_CTL) & 1947 XE2LPD_PICA_CTL_POWER_STATUS; 1948 } 1949 1950 const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1951 .sync_hw = i9xx_power_well_sync_hw_noop, 1952 .enable = i9xx_always_on_power_well_noop, 1953 .disable = i9xx_always_on_power_well_noop, 1954 .is_enabled = i9xx_always_on_power_well_enabled, 1955 }; 1956 1957 const struct i915_power_well_ops chv_pipe_power_well_ops = { 1958 .sync_hw = chv_pipe_power_well_sync_hw, 1959 .enable = chv_pipe_power_well_enable, 1960 .disable = chv_pipe_power_well_disable, 1961 .is_enabled = chv_pipe_power_well_enabled, 1962 }; 1963 1964 const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1965 .sync_hw = i9xx_power_well_sync_hw_noop, 1966 .enable = chv_dpio_cmn_power_well_enable, 1967 .disable = chv_dpio_cmn_power_well_disable, 1968 .is_enabled = vlv_power_well_enabled, 1969 }; 1970 1971 const struct i915_power_well_ops i830_pipes_power_well_ops = { 1972 .sync_hw = i830_pipes_power_well_sync_hw, 1973 .enable = i830_pipes_power_well_enable, 1974 .disable = i830_pipes_power_well_disable, 1975 .is_enabled = i830_pipes_power_well_enabled, 1976 }; 1977 1978 static const struct i915_power_well_regs hsw_power_well_regs = { 1979 .bios = HSW_PWR_WELL_CTL1, 1980 .driver = HSW_PWR_WELL_CTL2, 1981 .kvmr = HSW_PWR_WELL_CTL3, 1982 .debug = HSW_PWR_WELL_CTL4, 1983 }; 1984 1985 const struct i915_power_well_ops hsw_power_well_ops = { 1986 .regs = &hsw_power_well_regs, 1987 .sync_hw = hsw_power_well_sync_hw, 1988 .enable = hsw_power_well_enable, 1989 .disable = hsw_power_well_disable, 1990 .is_enabled = hsw_power_well_enabled, 1991 }; 1992 1993 const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1994 .sync_hw = i9xx_power_well_sync_hw_noop, 1995 .enable = gen9_dc_off_power_well_enable, 1996 .disable = gen9_dc_off_power_well_disable, 1997 .is_enabled = gen9_dc_off_power_well_enabled, 1998 }; 1999 2000 const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 2001 .sync_hw = i9xx_power_well_sync_hw_noop, 2002 .enable = bxt_dpio_cmn_power_well_enable, 2003 .disable = bxt_dpio_cmn_power_well_disable, 2004 .is_enabled = bxt_dpio_cmn_power_well_enabled, 2005 }; 2006 2007 const struct i915_power_well_ops vlv_display_power_well_ops = { 2008 .sync_hw = i9xx_power_well_sync_hw_noop, 2009 .enable = vlv_display_power_well_enable, 2010 .disable = vlv_display_power_well_disable, 2011 .is_enabled = vlv_power_well_enabled, 2012 }; 2013 2014 const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 2015 .sync_hw = i9xx_power_well_sync_hw_noop, 2016 .enable = vlv_dpio_cmn_power_well_enable, 2017 .disable = vlv_dpio_cmn_power_well_disable, 2018 .is_enabled = vlv_power_well_enabled, 2019 }; 2020 2021 const struct i915_power_well_ops vlv_dpio_power_well_ops = { 2022 .sync_hw = i9xx_power_well_sync_hw_noop, 2023 .enable = vlv_power_well_enable, 2024 .disable = vlv_power_well_disable, 2025 .is_enabled = vlv_power_well_enabled, 2026 }; 2027 2028 static const struct i915_power_well_regs icl_aux_power_well_regs = { 2029 .bios = ICL_PWR_WELL_CTL_AUX1, 2030 .driver = ICL_PWR_WELL_CTL_AUX2, 2031 .debug = ICL_PWR_WELL_CTL_AUX4, 2032 }; 2033 2034 const struct i915_power_well_ops icl_aux_power_well_ops = { 2035 .regs = &icl_aux_power_well_regs, 2036 .sync_hw = hsw_power_well_sync_hw, 2037 .enable = icl_aux_power_well_enable, 2038 .disable = icl_aux_power_well_disable, 2039 .is_enabled = hsw_power_well_enabled, 2040 }; 2041 2042 static const struct i915_power_well_regs icl_ddi_power_well_regs = { 2043 .bios = ICL_PWR_WELL_CTL_DDI1, 2044 .driver = ICL_PWR_WELL_CTL_DDI2, 2045 .debug = ICL_PWR_WELL_CTL_DDI4, 2046 }; 2047 2048 const struct i915_power_well_ops icl_ddi_power_well_ops = { 2049 .regs = &icl_ddi_power_well_regs, 2050 .sync_hw = hsw_power_well_sync_hw, 2051 .enable = hsw_power_well_enable, 2052 .disable = hsw_power_well_disable, 2053 .is_enabled = hsw_power_well_enabled, 2054 }; 2055 2056 const struct i915_power_well_ops tgl_tc_cold_off_ops = { 2057 .sync_hw = tgl_tc_cold_off_power_well_sync_hw, 2058 .enable = tgl_tc_cold_off_power_well_enable, 2059 .disable = tgl_tc_cold_off_power_well_disable, 2060 .is_enabled = tgl_tc_cold_off_power_well_is_enabled, 2061 }; 2062 2063 const struct i915_power_well_ops xelpdp_aux_power_well_ops = { 2064 .sync_hw = i9xx_power_well_sync_hw_noop, 2065 .enable = xelpdp_aux_power_well_enable, 2066 .disable = xelpdp_aux_power_well_disable, 2067 .is_enabled = xelpdp_aux_power_well_enabled, 2068 }; 2069 2070 const struct i915_power_well_ops xe2lpd_pica_power_well_ops = { 2071 .sync_hw = i9xx_power_well_sync_hw_noop, 2072 .enable = xe2lpd_pica_power_well_enable, 2073 .disable = xe2lpd_pica_power_well_disable, 2074 .is_enabled = xe2lpd_pica_power_well_enabled, 2075 }; 2076