1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 9 #include "vlv_sideband_reg.h" 10 11 #include "intel_display_power_map.h" 12 #include "intel_display_power_well.h" 13 #include "intel_display_types.h" 14 15 #define __LIST_INLINE_ELEMS(__elem_type, ...) \ 16 ((__elem_type[]) { __VA_ARGS__ }) 17 18 #define __LIST(__elems) { \ 19 .list = __elems, \ 20 .count = ARRAY_SIZE(__elems), \ 21 } 22 23 #define I915_PW_DOMAINS(...) \ 24 (const struct i915_power_domain_list) \ 25 __LIST(__LIST_INLINE_ELEMS(const enum intel_display_power_domain, __VA_ARGS__)) 26 27 #define I915_DECL_PW_DOMAINS(__name, ...) \ 28 static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__) 29 30 /* Zero-length list assigns all power domains, a NULL list assigns none. */ 31 #define I915_PW_DOMAINS_NONE NULL 32 #define I915_PW_DOMAINS_ALL /* zero-length list */ 33 34 #define I915_PW_INSTANCES(...) \ 35 (const struct i915_power_well_instance_list) \ 36 __LIST(__LIST_INLINE_ELEMS(const struct i915_power_well_instance, __VA_ARGS__)) 37 38 #define I915_PW(_name, _domain_list, ...) \ 39 { .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ } 40 41 42 struct i915_power_well_desc_list { 43 const struct i915_power_well_desc *list; 44 u8 count; 45 }; 46 47 #define I915_PW_DESCRIPTORS(x) __LIST(x) 48 49 50 I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL); 51 52 static const struct i915_power_well_desc i9xx_power_wells_always_on[] = { 53 { 54 .instances = &I915_PW_INSTANCES( 55 I915_PW("always-on", &i9xx_pwdoms_always_on), 56 ), 57 .ops = &i9xx_always_on_power_well_ops, 58 .always_on = true, 59 }, 60 }; 61 62 static const struct i915_power_well_desc_list i9xx_power_wells[] = { 63 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 64 }; 65 66 I915_DECL_PW_DOMAINS(i830_pwdoms_pipes, 67 POWER_DOMAIN_PIPE_A, 68 POWER_DOMAIN_PIPE_B, 69 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 70 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 71 POWER_DOMAIN_TRANSCODER_A, 72 POWER_DOMAIN_TRANSCODER_B, 73 POWER_DOMAIN_INIT); 74 75 static const struct i915_power_well_desc i830_power_wells_main[] = { 76 { 77 .instances = &I915_PW_INSTANCES( 78 I915_PW("pipes", &i830_pwdoms_pipes), 79 ), 80 .ops = &i830_pipes_power_well_ops, 81 }, 82 }; 83 84 static const struct i915_power_well_desc_list i830_power_wells[] = { 85 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 86 I915_PW_DESCRIPTORS(i830_power_wells_main), 87 }; 88 89 I915_DECL_PW_DOMAINS(hsw_pwdoms_display, 90 POWER_DOMAIN_PIPE_B, 91 POWER_DOMAIN_PIPE_C, 92 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 93 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 94 POWER_DOMAIN_PIPE_PANEL_FITTER_C, 95 POWER_DOMAIN_TRANSCODER_A, 96 POWER_DOMAIN_TRANSCODER_B, 97 POWER_DOMAIN_TRANSCODER_C, 98 POWER_DOMAIN_PORT_DDI_LANES_B, 99 POWER_DOMAIN_PORT_DDI_LANES_C, 100 POWER_DOMAIN_PORT_DDI_LANES_D, 101 POWER_DOMAIN_PORT_CRT, /* DDI E */ 102 POWER_DOMAIN_VGA, 103 POWER_DOMAIN_AUDIO_MMIO, 104 POWER_DOMAIN_AUDIO_PLAYBACK, 105 POWER_DOMAIN_INIT); 106 107 static const struct i915_power_well_desc hsw_power_wells_main[] = { 108 { 109 .instances = &I915_PW_INSTANCES( 110 I915_PW("display", &hsw_pwdoms_display, 111 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, 112 .id = HSW_DISP_PW_GLOBAL), 113 ), 114 .ops = &hsw_power_well_ops, 115 .has_vga = true, 116 }, 117 }; 118 119 static const struct i915_power_well_desc_list hsw_power_wells[] = { 120 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 121 I915_PW_DESCRIPTORS(hsw_power_wells_main), 122 }; 123 124 I915_DECL_PW_DOMAINS(bdw_pwdoms_display, 125 POWER_DOMAIN_PIPE_B, 126 POWER_DOMAIN_PIPE_C, 127 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 128 POWER_DOMAIN_PIPE_PANEL_FITTER_C, 129 POWER_DOMAIN_TRANSCODER_A, 130 POWER_DOMAIN_TRANSCODER_B, 131 POWER_DOMAIN_TRANSCODER_C, 132 POWER_DOMAIN_PORT_DDI_LANES_B, 133 POWER_DOMAIN_PORT_DDI_LANES_C, 134 POWER_DOMAIN_PORT_DDI_LANES_D, 135 POWER_DOMAIN_PORT_CRT, /* DDI E */ 136 POWER_DOMAIN_VGA, 137 POWER_DOMAIN_AUDIO_MMIO, 138 POWER_DOMAIN_AUDIO_PLAYBACK, 139 POWER_DOMAIN_INIT); 140 141 static const struct i915_power_well_desc bdw_power_wells_main[] = { 142 { 143 .instances = &I915_PW_INSTANCES( 144 I915_PW("display", &bdw_pwdoms_display, 145 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, 146 .id = HSW_DISP_PW_GLOBAL), 147 ), 148 .ops = &hsw_power_well_ops, 149 .has_vga = true, 150 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 151 }, 152 }; 153 154 static const struct i915_power_well_desc_list bdw_power_wells[] = { 155 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 156 I915_PW_DESCRIPTORS(bdw_power_wells_main), 157 }; 158 159 I915_DECL_PW_DOMAINS(vlv_pwdoms_display, 160 POWER_DOMAIN_DISPLAY_CORE, 161 POWER_DOMAIN_PIPE_A, 162 POWER_DOMAIN_PIPE_B, 163 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 164 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 165 POWER_DOMAIN_TRANSCODER_A, 166 POWER_DOMAIN_TRANSCODER_B, 167 POWER_DOMAIN_PORT_DDI_LANES_B, 168 POWER_DOMAIN_PORT_DDI_LANES_C, 169 POWER_DOMAIN_PORT_DSI, 170 POWER_DOMAIN_PORT_CRT, 171 POWER_DOMAIN_VGA, 172 POWER_DOMAIN_AUDIO_MMIO, 173 POWER_DOMAIN_AUDIO_PLAYBACK, 174 POWER_DOMAIN_AUX_IO_B, 175 POWER_DOMAIN_AUX_IO_C, 176 POWER_DOMAIN_AUX_B, 177 POWER_DOMAIN_AUX_C, 178 POWER_DOMAIN_GMBUS, 179 POWER_DOMAIN_INIT); 180 181 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc, 182 POWER_DOMAIN_PORT_DDI_LANES_B, 183 POWER_DOMAIN_PORT_DDI_LANES_C, 184 POWER_DOMAIN_PORT_CRT, 185 POWER_DOMAIN_AUX_IO_B, 186 POWER_DOMAIN_AUX_IO_C, 187 POWER_DOMAIN_AUX_B, 188 POWER_DOMAIN_AUX_C, 189 POWER_DOMAIN_INIT); 190 191 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes, 192 POWER_DOMAIN_PORT_DDI_LANES_B, 193 POWER_DOMAIN_PORT_DDI_LANES_C, 194 POWER_DOMAIN_AUX_IO_B, 195 POWER_DOMAIN_AUX_IO_C, 196 POWER_DOMAIN_AUX_B, 197 POWER_DOMAIN_AUX_C, 198 POWER_DOMAIN_INIT); 199 200 static const struct i915_power_well_desc vlv_power_wells_main[] = { 201 { 202 .instances = &I915_PW_INSTANCES( 203 I915_PW("display", &vlv_pwdoms_display, 204 .vlv.idx = PUNIT_PWGT_IDX_DISP2D, 205 .id = VLV_DISP_PW_DISP2D), 206 ), 207 .ops = &vlv_display_power_well_ops, 208 }, { 209 .instances = &I915_PW_INSTANCES( 210 I915_PW("dpio-tx-b-01", &vlv_pwdoms_dpio_tx_bc_lanes, 211 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01), 212 I915_PW("dpio-tx-b-23", &vlv_pwdoms_dpio_tx_bc_lanes, 213 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23), 214 I915_PW("dpio-tx-c-01", &vlv_pwdoms_dpio_tx_bc_lanes, 215 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01), 216 I915_PW("dpio-tx-c-23", &vlv_pwdoms_dpio_tx_bc_lanes, 217 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23), 218 ), 219 .ops = &vlv_dpio_power_well_ops, 220 }, { 221 .instances = &I915_PW_INSTANCES( 222 I915_PW("dpio-common", &vlv_pwdoms_dpio_cmn_bc, 223 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, 224 .id = VLV_DISP_PW_DPIO_CMN_BC), 225 ), 226 .ops = &vlv_dpio_cmn_power_well_ops, 227 }, 228 }; 229 230 static const struct i915_power_well_desc_list vlv_power_wells[] = { 231 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 232 I915_PW_DESCRIPTORS(vlv_power_wells_main), 233 }; 234 235 I915_DECL_PW_DOMAINS(chv_pwdoms_display, 236 POWER_DOMAIN_DISPLAY_CORE, 237 POWER_DOMAIN_PIPE_A, 238 POWER_DOMAIN_PIPE_B, 239 POWER_DOMAIN_PIPE_C, 240 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 241 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 242 POWER_DOMAIN_PIPE_PANEL_FITTER_C, 243 POWER_DOMAIN_TRANSCODER_A, 244 POWER_DOMAIN_TRANSCODER_B, 245 POWER_DOMAIN_TRANSCODER_C, 246 POWER_DOMAIN_PORT_DDI_LANES_B, 247 POWER_DOMAIN_PORT_DDI_LANES_C, 248 POWER_DOMAIN_PORT_DDI_LANES_D, 249 POWER_DOMAIN_PORT_DSI, 250 POWER_DOMAIN_VGA, 251 POWER_DOMAIN_AUDIO_MMIO, 252 POWER_DOMAIN_AUDIO_PLAYBACK, 253 POWER_DOMAIN_AUX_IO_B, 254 POWER_DOMAIN_AUX_IO_C, 255 POWER_DOMAIN_AUX_IO_D, 256 POWER_DOMAIN_AUX_B, 257 POWER_DOMAIN_AUX_C, 258 POWER_DOMAIN_AUX_D, 259 POWER_DOMAIN_GMBUS, 260 POWER_DOMAIN_INIT); 261 262 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc, 263 POWER_DOMAIN_PORT_DDI_LANES_B, 264 POWER_DOMAIN_PORT_DDI_LANES_C, 265 POWER_DOMAIN_AUX_IO_B, 266 POWER_DOMAIN_AUX_IO_C, 267 POWER_DOMAIN_AUX_B, 268 POWER_DOMAIN_AUX_C, 269 POWER_DOMAIN_INIT); 270 271 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d, 272 POWER_DOMAIN_PORT_DDI_LANES_D, 273 POWER_DOMAIN_AUX_IO_D, 274 POWER_DOMAIN_AUX_D, 275 POWER_DOMAIN_INIT); 276 277 static const struct i915_power_well_desc chv_power_wells_main[] = { 278 { 279 /* 280 * Pipe A power well is the new disp2d well. Pipe B and C 281 * power wells don't actually exist. Pipe A power well is 282 * required for any pipe to work. 283 */ 284 .instances = &I915_PW_INSTANCES( 285 I915_PW("display", &chv_pwdoms_display), 286 ), 287 .ops = &chv_pipe_power_well_ops, 288 }, { 289 .instances = &I915_PW_INSTANCES( 290 I915_PW("dpio-common-bc", &chv_pwdoms_dpio_cmn_bc, 291 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, 292 .id = VLV_DISP_PW_DPIO_CMN_BC), 293 I915_PW("dpio-common-d", &chv_pwdoms_dpio_cmn_d, 294 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D, 295 .id = CHV_DISP_PW_DPIO_CMN_D), 296 ), 297 .ops = &chv_dpio_cmn_power_well_ops, 298 }, 299 }; 300 301 static const struct i915_power_well_desc_list chv_power_wells[] = { 302 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 303 I915_PW_DESCRIPTORS(chv_power_wells_main), 304 }; 305 306 #define SKL_PW_2_POWER_DOMAINS \ 307 POWER_DOMAIN_PIPE_B, \ 308 POWER_DOMAIN_PIPE_C, \ 309 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 310 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 311 POWER_DOMAIN_TRANSCODER_A, \ 312 POWER_DOMAIN_TRANSCODER_B, \ 313 POWER_DOMAIN_TRANSCODER_C, \ 314 POWER_DOMAIN_PORT_DDI_LANES_B, \ 315 POWER_DOMAIN_PORT_DDI_LANES_C, \ 316 POWER_DOMAIN_PORT_DDI_LANES_D, \ 317 POWER_DOMAIN_PORT_DDI_LANES_E, \ 318 POWER_DOMAIN_VGA, \ 319 POWER_DOMAIN_AUDIO_MMIO, \ 320 POWER_DOMAIN_AUDIO_PLAYBACK, \ 321 POWER_DOMAIN_AUX_IO_B, \ 322 POWER_DOMAIN_AUX_IO_C, \ 323 POWER_DOMAIN_AUX_IO_D, \ 324 POWER_DOMAIN_AUX_B, \ 325 POWER_DOMAIN_AUX_C, \ 326 POWER_DOMAIN_AUX_D 327 328 I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2, 329 SKL_PW_2_POWER_DOMAINS, 330 POWER_DOMAIN_INIT); 331 332 I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off, 333 SKL_PW_2_POWER_DOMAINS, 334 POWER_DOMAIN_AUX_A, 335 POWER_DOMAIN_MODESET, 336 POWER_DOMAIN_GT_IRQ, 337 POWER_DOMAIN_DC_OFF, 338 POWER_DOMAIN_INIT); 339 340 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e, 341 POWER_DOMAIN_PORT_DDI_IO_A, 342 POWER_DOMAIN_PORT_DDI_IO_E, 343 POWER_DOMAIN_INIT); 344 345 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b, 346 POWER_DOMAIN_PORT_DDI_IO_B, 347 POWER_DOMAIN_INIT); 348 349 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c, 350 POWER_DOMAIN_PORT_DDI_IO_C, 351 POWER_DOMAIN_INIT); 352 353 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d, 354 POWER_DOMAIN_PORT_DDI_IO_D, 355 POWER_DOMAIN_INIT); 356 357 static const struct i915_power_well_desc skl_power_wells_pw_1[] = { 358 { 359 /* Handled by the DMC firmware */ 360 .instances = &I915_PW_INSTANCES( 361 I915_PW("PW_1", I915_PW_DOMAINS_NONE, 362 .hsw.idx = SKL_PW_CTL_IDX_PW_1, 363 .id = SKL_DISP_PW_1), 364 ), 365 .ops = &hsw_power_well_ops, 366 .always_on = true, 367 .has_fuses = true, 368 }, 369 }; 370 371 static const struct i915_power_well_desc skl_power_wells_main[] = { 372 { 373 /* Handled by the DMC firmware */ 374 .instances = &I915_PW_INSTANCES( 375 I915_PW("MISC_IO", I915_PW_DOMAINS_NONE, 376 .hsw.idx = SKL_PW_CTL_IDX_MISC_IO, 377 .id = SKL_DISP_PW_MISC_IO), 378 ), 379 .ops = &hsw_power_well_ops, 380 .always_on = true, 381 }, { 382 .instances = &I915_PW_INSTANCES( 383 I915_PW("DC_off", &skl_pwdoms_dc_off, 384 .id = SKL_DISP_DC_OFF), 385 ), 386 .ops = &gen9_dc_off_power_well_ops, 387 }, { 388 .instances = &I915_PW_INSTANCES( 389 I915_PW("PW_2", &skl_pwdoms_pw_2, 390 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 391 .id = SKL_DISP_PW_2), 392 ), 393 .ops = &hsw_power_well_ops, 394 .has_vga = true, 395 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 396 .has_fuses = true, 397 }, { 398 .instances = &I915_PW_INSTANCES( 399 I915_PW("DDI_IO_A_E", &skl_pwdoms_ddi_io_a_e, .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E), 400 I915_PW("DDI_IO_B", &skl_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B), 401 I915_PW("DDI_IO_C", &skl_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C), 402 I915_PW("DDI_IO_D", &skl_pwdoms_ddi_io_d, .hsw.idx = SKL_PW_CTL_IDX_DDI_D), 403 ), 404 .ops = &hsw_power_well_ops, 405 }, 406 }; 407 408 static const struct i915_power_well_desc_list skl_power_wells[] = { 409 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 410 I915_PW_DESCRIPTORS(skl_power_wells_pw_1), 411 I915_PW_DESCRIPTORS(skl_power_wells_main), 412 }; 413 414 #define BXT_PW_2_POWER_DOMAINS \ 415 POWER_DOMAIN_PIPE_B, \ 416 POWER_DOMAIN_PIPE_C, \ 417 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 418 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 419 POWER_DOMAIN_TRANSCODER_A, \ 420 POWER_DOMAIN_TRANSCODER_B, \ 421 POWER_DOMAIN_TRANSCODER_C, \ 422 POWER_DOMAIN_PORT_DDI_LANES_B, \ 423 POWER_DOMAIN_PORT_DDI_LANES_C, \ 424 POWER_DOMAIN_VGA, \ 425 POWER_DOMAIN_AUDIO_MMIO, \ 426 POWER_DOMAIN_AUDIO_PLAYBACK, \ 427 POWER_DOMAIN_AUX_IO_B, \ 428 POWER_DOMAIN_AUX_IO_C, \ 429 POWER_DOMAIN_AUX_B, \ 430 POWER_DOMAIN_AUX_C 431 432 I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2, 433 BXT_PW_2_POWER_DOMAINS, 434 POWER_DOMAIN_INIT); 435 436 I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off, 437 BXT_PW_2_POWER_DOMAINS, 438 POWER_DOMAIN_AUX_A, 439 POWER_DOMAIN_GMBUS, 440 POWER_DOMAIN_MODESET, 441 POWER_DOMAIN_GT_IRQ, 442 POWER_DOMAIN_DC_OFF, 443 POWER_DOMAIN_INIT); 444 445 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a, 446 POWER_DOMAIN_PORT_DDI_LANES_A, 447 POWER_DOMAIN_AUX_IO_A, 448 POWER_DOMAIN_AUX_A, 449 POWER_DOMAIN_INIT); 450 451 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc, 452 POWER_DOMAIN_PORT_DDI_LANES_B, 453 POWER_DOMAIN_PORT_DDI_LANES_C, 454 POWER_DOMAIN_AUX_IO_B, 455 POWER_DOMAIN_AUX_IO_C, 456 POWER_DOMAIN_AUX_B, 457 POWER_DOMAIN_AUX_C, 458 POWER_DOMAIN_INIT); 459 460 static const struct i915_power_well_desc bxt_power_wells_main[] = { 461 { 462 .instances = &I915_PW_INSTANCES( 463 I915_PW("DC_off", &bxt_pwdoms_dc_off, 464 .id = SKL_DISP_DC_OFF), 465 ), 466 .ops = &gen9_dc_off_power_well_ops, 467 }, { 468 .instances = &I915_PW_INSTANCES( 469 I915_PW("PW_2", &bxt_pwdoms_pw_2, 470 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 471 .id = SKL_DISP_PW_2), 472 ), 473 .ops = &hsw_power_well_ops, 474 .has_vga = true, 475 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 476 .has_fuses = true, 477 }, { 478 .instances = &I915_PW_INSTANCES( 479 I915_PW("dpio-common-a", &bxt_pwdoms_dpio_cmn_a, 480 .bxt.phy = DPIO_PHY1, 481 .id = BXT_DISP_PW_DPIO_CMN_A), 482 I915_PW("dpio-common-bc", &bxt_pwdoms_dpio_cmn_bc, 483 .bxt.phy = DPIO_PHY0, 484 .id = VLV_DISP_PW_DPIO_CMN_BC), 485 ), 486 .ops = &bxt_dpio_cmn_power_well_ops, 487 }, 488 }; 489 490 static const struct i915_power_well_desc_list bxt_power_wells[] = { 491 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 492 I915_PW_DESCRIPTORS(skl_power_wells_pw_1), 493 I915_PW_DESCRIPTORS(bxt_power_wells_main), 494 }; 495 496 #define GLK_PW_2_POWER_DOMAINS \ 497 POWER_DOMAIN_PIPE_B, \ 498 POWER_DOMAIN_PIPE_C, \ 499 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 500 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 501 POWER_DOMAIN_TRANSCODER_A, \ 502 POWER_DOMAIN_TRANSCODER_B, \ 503 POWER_DOMAIN_TRANSCODER_C, \ 504 POWER_DOMAIN_PORT_DDI_LANES_B, \ 505 POWER_DOMAIN_PORT_DDI_LANES_C, \ 506 POWER_DOMAIN_VGA, \ 507 POWER_DOMAIN_AUDIO_MMIO, \ 508 POWER_DOMAIN_AUDIO_PLAYBACK, \ 509 POWER_DOMAIN_AUX_IO_B, \ 510 POWER_DOMAIN_AUX_IO_C, \ 511 POWER_DOMAIN_AUX_B, \ 512 POWER_DOMAIN_AUX_C 513 514 I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2, 515 GLK_PW_2_POWER_DOMAINS, 516 POWER_DOMAIN_INIT); 517 518 I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off, 519 GLK_PW_2_POWER_DOMAINS, 520 POWER_DOMAIN_AUX_A, 521 POWER_DOMAIN_GMBUS, 522 POWER_DOMAIN_MODESET, 523 POWER_DOMAIN_GT_IRQ, 524 POWER_DOMAIN_DC_OFF, 525 POWER_DOMAIN_INIT); 526 527 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A); 528 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B); 529 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C); 530 531 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a, 532 POWER_DOMAIN_PORT_DDI_LANES_A, 533 POWER_DOMAIN_AUX_IO_A, 534 POWER_DOMAIN_AUX_A, 535 POWER_DOMAIN_INIT); 536 537 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b, 538 POWER_DOMAIN_PORT_DDI_LANES_B, 539 POWER_DOMAIN_AUX_IO_B, 540 POWER_DOMAIN_AUX_B, 541 POWER_DOMAIN_INIT); 542 543 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c, 544 POWER_DOMAIN_PORT_DDI_LANES_C, 545 POWER_DOMAIN_AUX_IO_C, 546 POWER_DOMAIN_AUX_C, 547 POWER_DOMAIN_INIT); 548 549 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a, 550 POWER_DOMAIN_AUX_IO_A, 551 POWER_DOMAIN_AUX_A, 552 POWER_DOMAIN_INIT); 553 554 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b, 555 POWER_DOMAIN_AUX_IO_B, 556 POWER_DOMAIN_AUX_B, 557 POWER_DOMAIN_INIT); 558 559 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c, 560 POWER_DOMAIN_AUX_IO_C, 561 POWER_DOMAIN_AUX_C, 562 POWER_DOMAIN_INIT); 563 564 static const struct i915_power_well_desc glk_power_wells_main[] = { 565 { 566 .instances = &I915_PW_INSTANCES( 567 I915_PW("DC_off", &glk_pwdoms_dc_off, 568 .id = SKL_DISP_DC_OFF), 569 ), 570 .ops = &gen9_dc_off_power_well_ops, 571 }, { 572 .instances = &I915_PW_INSTANCES( 573 I915_PW("PW_2", &glk_pwdoms_pw_2, 574 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 575 .id = SKL_DISP_PW_2), 576 ), 577 .ops = &hsw_power_well_ops, 578 .has_vga = true, 579 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 580 .has_fuses = true, 581 }, { 582 .instances = &I915_PW_INSTANCES( 583 I915_PW("dpio-common-a", &glk_pwdoms_dpio_cmn_a, 584 .bxt.phy = DPIO_PHY1, 585 .id = BXT_DISP_PW_DPIO_CMN_A), 586 I915_PW("dpio-common-b", &glk_pwdoms_dpio_cmn_b, 587 .bxt.phy = DPIO_PHY0, 588 .id = VLV_DISP_PW_DPIO_CMN_BC), 589 I915_PW("dpio-common-c", &glk_pwdoms_dpio_cmn_c, 590 .bxt.phy = DPIO_PHY2, 591 .id = GLK_DISP_PW_DPIO_CMN_C), 592 ), 593 .ops = &bxt_dpio_cmn_power_well_ops, 594 }, { 595 .instances = &I915_PW_INSTANCES( 596 I915_PW("AUX_A", &glk_pwdoms_aux_a, .hsw.idx = GLK_PW_CTL_IDX_AUX_A), 597 I915_PW("AUX_B", &glk_pwdoms_aux_b, .hsw.idx = GLK_PW_CTL_IDX_AUX_B), 598 I915_PW("AUX_C", &glk_pwdoms_aux_c, .hsw.idx = GLK_PW_CTL_IDX_AUX_C), 599 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = GLK_PW_CTL_IDX_DDI_A), 600 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B), 601 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C), 602 ), 603 .ops = &hsw_power_well_ops, 604 }, 605 }; 606 607 static const struct i915_power_well_desc_list glk_power_wells[] = { 608 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 609 I915_PW_DESCRIPTORS(skl_power_wells_pw_1), 610 I915_PW_DESCRIPTORS(glk_power_wells_main), 611 }; 612 613 /* 614 * ICL PW_0/PG_0 domains (HW/DMC control): 615 * - PCI 616 * - clocks except port PLL 617 * - central power except FBC 618 * - shared functions except pipe interrupts, pipe MBUS, DBUF registers 619 * ICL PW_1/PG_1 domains (HW/DMC control): 620 * - DBUF function 621 * - PIPE_A and its planes, except VGA 622 * - transcoder EDP + PSR 623 * - transcoder DSI 624 * - DDI_A 625 * - FBC 626 */ 627 #define ICL_PW_4_POWER_DOMAINS \ 628 POWER_DOMAIN_PIPE_C, \ 629 POWER_DOMAIN_PIPE_PANEL_FITTER_C 630 631 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4, 632 ICL_PW_4_POWER_DOMAINS, 633 POWER_DOMAIN_INIT); 634 /* VDSC/joining */ 635 636 #define ICL_PW_3_POWER_DOMAINS \ 637 ICL_PW_4_POWER_DOMAINS, \ 638 POWER_DOMAIN_PIPE_B, \ 639 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 640 POWER_DOMAIN_TRANSCODER_A, \ 641 POWER_DOMAIN_TRANSCODER_B, \ 642 POWER_DOMAIN_TRANSCODER_C, \ 643 POWER_DOMAIN_PORT_DDI_LANES_B, \ 644 POWER_DOMAIN_PORT_DDI_LANES_C, \ 645 POWER_DOMAIN_PORT_DDI_LANES_D, \ 646 POWER_DOMAIN_PORT_DDI_LANES_E, \ 647 POWER_DOMAIN_PORT_DDI_LANES_F, \ 648 POWER_DOMAIN_VGA, \ 649 POWER_DOMAIN_AUDIO_MMIO, \ 650 POWER_DOMAIN_AUDIO_PLAYBACK, \ 651 POWER_DOMAIN_AUX_IO_B, \ 652 POWER_DOMAIN_AUX_IO_C, \ 653 POWER_DOMAIN_AUX_IO_D, \ 654 POWER_DOMAIN_AUX_IO_E, \ 655 POWER_DOMAIN_AUX_IO_F, \ 656 POWER_DOMAIN_AUX_B, \ 657 POWER_DOMAIN_AUX_C, \ 658 POWER_DOMAIN_AUX_D, \ 659 POWER_DOMAIN_AUX_E, \ 660 POWER_DOMAIN_AUX_F, \ 661 POWER_DOMAIN_AUX_TBT1, \ 662 POWER_DOMAIN_AUX_TBT2, \ 663 POWER_DOMAIN_AUX_TBT3, \ 664 POWER_DOMAIN_AUX_TBT4 665 666 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3, 667 ICL_PW_3_POWER_DOMAINS, 668 POWER_DOMAIN_INIT); 669 /* 670 * - transcoder WD 671 * - KVMR (HW control) 672 */ 673 674 #define ICL_PW_2_POWER_DOMAINS \ 675 ICL_PW_3_POWER_DOMAINS, \ 676 POWER_DOMAIN_TRANSCODER_VDSC_PW2 677 678 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2, 679 ICL_PW_2_POWER_DOMAINS, 680 POWER_DOMAIN_INIT); 681 /* 682 * - KVMR (HW control) 683 */ 684 685 I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off, 686 ICL_PW_2_POWER_DOMAINS, 687 POWER_DOMAIN_AUX_A, 688 POWER_DOMAIN_MODESET, 689 POWER_DOMAIN_DC_OFF, 690 POWER_DOMAIN_INIT); 691 692 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D); 693 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E); 694 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F); 695 696 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a, 697 POWER_DOMAIN_AUX_IO_A, 698 POWER_DOMAIN_AUX_A); 699 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b, 700 POWER_DOMAIN_AUX_IO_B, 701 POWER_DOMAIN_AUX_B); 702 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, 703 POWER_DOMAIN_AUX_IO_C, 704 POWER_DOMAIN_AUX_C); 705 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, 706 POWER_DOMAIN_AUX_IO_D, 707 POWER_DOMAIN_AUX_D); 708 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, 709 POWER_DOMAIN_AUX_IO_E, 710 POWER_DOMAIN_AUX_E); 711 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, 712 POWER_DOMAIN_AUX_IO_F, 713 POWER_DOMAIN_AUX_F); 714 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1); 715 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2); 716 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3); 717 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4); 718 719 static const struct i915_power_well_desc icl_power_wells_pw_1[] = { 720 { 721 /* Handled by the DMC firmware */ 722 .instances = &I915_PW_INSTANCES( 723 I915_PW("PW_1", I915_PW_DOMAINS_NONE, 724 .hsw.idx = ICL_PW_CTL_IDX_PW_1, 725 .id = SKL_DISP_PW_1), 726 ), 727 .ops = &hsw_power_well_ops, 728 .always_on = true, 729 .has_fuses = true, 730 }, 731 }; 732 733 static const struct i915_power_well_desc icl_power_wells_main[] = { 734 { 735 .instances = &I915_PW_INSTANCES( 736 I915_PW("DC_off", &icl_pwdoms_dc_off, 737 .id = SKL_DISP_DC_OFF), 738 ), 739 .ops = &gen9_dc_off_power_well_ops, 740 }, { 741 .instances = &I915_PW_INSTANCES( 742 I915_PW("PW_2", &icl_pwdoms_pw_2, 743 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 744 .id = SKL_DISP_PW_2), 745 ), 746 .ops = &hsw_power_well_ops, 747 .has_fuses = true, 748 }, { 749 .instances = &I915_PW_INSTANCES( 750 I915_PW("PW_3", &icl_pwdoms_pw_3, 751 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 752 .id = ICL_DISP_PW_3), 753 ), 754 .ops = &hsw_power_well_ops, 755 .has_vga = true, 756 .irq_pipe_mask = BIT(PIPE_B), 757 .has_fuses = true, 758 }, { 759 .instances = &I915_PW_INSTANCES( 760 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 761 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 762 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), 763 I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = ICL_PW_CTL_IDX_DDI_D), 764 I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = ICL_PW_CTL_IDX_DDI_E), 765 I915_PW("DDI_IO_F", &icl_pwdoms_ddi_io_f, .hsw.idx = ICL_PW_CTL_IDX_DDI_F), 766 ), 767 .ops = &icl_ddi_power_well_ops, 768 }, { 769 .instances = &I915_PW_INSTANCES( 770 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 771 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 772 I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), 773 I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = ICL_PW_CTL_IDX_AUX_D), 774 I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = ICL_PW_CTL_IDX_AUX_E), 775 I915_PW("AUX_F", &icl_pwdoms_aux_f, .hsw.idx = ICL_PW_CTL_IDX_AUX_F), 776 ), 777 .ops = &icl_aux_power_well_ops, 778 }, { 779 .instances = &I915_PW_INSTANCES( 780 I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1), 781 I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2), 782 I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3), 783 I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4), 784 ), 785 .ops = &icl_aux_power_well_ops, 786 .is_tc_tbt = true, 787 }, { 788 .instances = &I915_PW_INSTANCES( 789 I915_PW("PW_4", &icl_pwdoms_pw_4, 790 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 791 ), 792 .ops = &hsw_power_well_ops, 793 .irq_pipe_mask = BIT(PIPE_C), 794 .has_fuses = true, 795 }, 796 }; 797 798 static const struct i915_power_well_desc_list icl_power_wells[] = { 799 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 800 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 801 I915_PW_DESCRIPTORS(icl_power_wells_main), 802 }; 803 804 #define TGL_PW_5_POWER_DOMAINS \ 805 POWER_DOMAIN_PIPE_D, \ 806 POWER_DOMAIN_PIPE_PANEL_FITTER_D, \ 807 POWER_DOMAIN_TRANSCODER_D 808 809 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5, 810 TGL_PW_5_POWER_DOMAINS, 811 POWER_DOMAIN_INIT); 812 813 #define TGL_PW_4_POWER_DOMAINS \ 814 TGL_PW_5_POWER_DOMAINS, \ 815 POWER_DOMAIN_PIPE_C, \ 816 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 817 POWER_DOMAIN_TRANSCODER_C 818 819 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4, 820 TGL_PW_4_POWER_DOMAINS, 821 POWER_DOMAIN_INIT); 822 823 #define TGL_PW_3_POWER_DOMAINS \ 824 TGL_PW_4_POWER_DOMAINS, \ 825 POWER_DOMAIN_PIPE_B, \ 826 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 827 POWER_DOMAIN_TRANSCODER_B, \ 828 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 829 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 830 POWER_DOMAIN_PORT_DDI_LANES_TC3, \ 831 POWER_DOMAIN_PORT_DDI_LANES_TC4, \ 832 POWER_DOMAIN_PORT_DDI_LANES_TC5, \ 833 POWER_DOMAIN_PORT_DDI_LANES_TC6, \ 834 POWER_DOMAIN_VGA, \ 835 POWER_DOMAIN_AUDIO_MMIO, \ 836 POWER_DOMAIN_AUDIO_PLAYBACK, \ 837 POWER_DOMAIN_AUX_USBC1, \ 838 POWER_DOMAIN_AUX_USBC2, \ 839 POWER_DOMAIN_AUX_USBC3, \ 840 POWER_DOMAIN_AUX_USBC4, \ 841 POWER_DOMAIN_AUX_USBC5, \ 842 POWER_DOMAIN_AUX_USBC6, \ 843 POWER_DOMAIN_AUX_TBT1, \ 844 POWER_DOMAIN_AUX_TBT2, \ 845 POWER_DOMAIN_AUX_TBT3, \ 846 POWER_DOMAIN_AUX_TBT4, \ 847 POWER_DOMAIN_AUX_TBT5, \ 848 POWER_DOMAIN_AUX_TBT6 849 850 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3, 851 TGL_PW_3_POWER_DOMAINS, 852 POWER_DOMAIN_INIT); 853 854 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2, 855 TGL_PW_3_POWER_DOMAINS, 856 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 857 POWER_DOMAIN_INIT); 858 859 I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off, 860 TGL_PW_3_POWER_DOMAINS, 861 POWER_DOMAIN_AUX_A, 862 POWER_DOMAIN_AUX_B, 863 POWER_DOMAIN_AUX_C, 864 POWER_DOMAIN_MODESET, 865 POWER_DOMAIN_DC_OFF, 866 POWER_DOMAIN_INIT); 867 868 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1); 869 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2); 870 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3); 871 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4); 872 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5); 873 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6); 874 875 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1); 876 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2); 877 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3); 878 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4); 879 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5); 880 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6); 881 882 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5); 883 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6); 884 885 I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off, 886 POWER_DOMAIN_AUX_USBC1, 887 POWER_DOMAIN_AUX_USBC2, 888 POWER_DOMAIN_AUX_USBC3, 889 POWER_DOMAIN_AUX_USBC4, 890 POWER_DOMAIN_AUX_USBC5, 891 POWER_DOMAIN_AUX_USBC6, 892 POWER_DOMAIN_AUX_TBT1, 893 POWER_DOMAIN_AUX_TBT2, 894 POWER_DOMAIN_AUX_TBT3, 895 POWER_DOMAIN_AUX_TBT4, 896 POWER_DOMAIN_AUX_TBT5, 897 POWER_DOMAIN_AUX_TBT6, 898 POWER_DOMAIN_TC_COLD_OFF); 899 900 static const struct i915_power_well_desc tgl_power_wells_main[] = { 901 { 902 .instances = &I915_PW_INSTANCES( 903 I915_PW("DC_off", &tgl_pwdoms_dc_off, 904 .id = SKL_DISP_DC_OFF), 905 ), 906 .ops = &gen9_dc_off_power_well_ops, 907 }, { 908 .instances = &I915_PW_INSTANCES( 909 I915_PW("PW_2", &tgl_pwdoms_pw_2, 910 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 911 .id = SKL_DISP_PW_2), 912 ), 913 .ops = &hsw_power_well_ops, 914 .has_fuses = true, 915 }, { 916 .instances = &I915_PW_INSTANCES( 917 I915_PW("PW_3", &tgl_pwdoms_pw_3, 918 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 919 .id = ICL_DISP_PW_3), 920 ), 921 .ops = &hsw_power_well_ops, 922 .has_vga = true, 923 .irq_pipe_mask = BIT(PIPE_B), 924 .has_fuses = true, 925 }, { 926 .instances = &I915_PW_INSTANCES( 927 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 928 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 929 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), 930 I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), 931 I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), 932 I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3), 933 I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4), 934 I915_PW("DDI_IO_TC5", &tgl_pwdoms_ddi_io_tc5, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5), 935 I915_PW("DDI_IO_TC6", &tgl_pwdoms_ddi_io_tc6, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6), 936 ), 937 .ops = &icl_ddi_power_well_ops, 938 }, { 939 .instances = &I915_PW_INSTANCES( 940 I915_PW("PW_4", &tgl_pwdoms_pw_4, 941 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 942 ), 943 .ops = &hsw_power_well_ops, 944 .has_fuses = true, 945 .irq_pipe_mask = BIT(PIPE_C), 946 }, { 947 .instances = &I915_PW_INSTANCES( 948 I915_PW("PW_5", &tgl_pwdoms_pw_5, 949 .hsw.idx = TGL_PW_CTL_IDX_PW_5), 950 ), 951 .ops = &hsw_power_well_ops, 952 .has_fuses = true, 953 .irq_pipe_mask = BIT(PIPE_D), 954 }, 955 }; 956 957 static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = { 958 { 959 .instances = &I915_PW_INSTANCES( 960 I915_PW("TC_cold_off", &tgl_pwdoms_tc_cold_off, 961 .id = TGL_DISP_PW_TC_COLD_OFF), 962 ), 963 .ops = &tgl_tc_cold_off_ops, 964 }, 965 }; 966 967 static const struct i915_power_well_desc tgl_power_wells_aux[] = { 968 { 969 .instances = &I915_PW_INSTANCES( 970 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 971 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 972 I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), 973 I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), 974 I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), 975 I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3), 976 I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4), 977 I915_PW("AUX_USBC5", &tgl_pwdoms_aux_usbc5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5), 978 I915_PW("AUX_USBC6", &tgl_pwdoms_aux_usbc6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6), 979 ), 980 .ops = &icl_aux_power_well_ops, 981 }, { 982 .instances = &I915_PW_INSTANCES( 983 I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1), 984 I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2), 985 I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3), 986 I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4), 987 I915_PW("AUX_TBT5", &tgl_pwdoms_aux_tbt5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5), 988 I915_PW("AUX_TBT6", &tgl_pwdoms_aux_tbt6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6), 989 ), 990 .ops = &icl_aux_power_well_ops, 991 .is_tc_tbt = true, 992 }, 993 }; 994 995 static const struct i915_power_well_desc_list tgl_power_wells[] = { 996 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 997 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 998 I915_PW_DESCRIPTORS(tgl_power_wells_main), 999 I915_PW_DESCRIPTORS(tgl_power_wells_tc_cold_off), 1000 I915_PW_DESCRIPTORS(tgl_power_wells_aux), 1001 }; 1002 1003 static const struct i915_power_well_desc_list adls_power_wells[] = { 1004 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1005 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1006 I915_PW_DESCRIPTORS(tgl_power_wells_main), 1007 I915_PW_DESCRIPTORS(tgl_power_wells_aux), 1008 }; 1009 1010 #define RKL_PW_4_POWER_DOMAINS \ 1011 POWER_DOMAIN_PIPE_C, \ 1012 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 1013 POWER_DOMAIN_TRANSCODER_C 1014 1015 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4, 1016 RKL_PW_4_POWER_DOMAINS, 1017 POWER_DOMAIN_INIT); 1018 1019 #define RKL_PW_3_POWER_DOMAINS \ 1020 RKL_PW_4_POWER_DOMAINS, \ 1021 POWER_DOMAIN_PIPE_B, \ 1022 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 1023 POWER_DOMAIN_TRANSCODER_B, \ 1024 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1025 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1026 POWER_DOMAIN_VGA, \ 1027 POWER_DOMAIN_AUDIO_MMIO, \ 1028 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1029 POWER_DOMAIN_AUX_USBC1, \ 1030 POWER_DOMAIN_AUX_USBC2 1031 1032 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3, 1033 RKL_PW_3_POWER_DOMAINS, 1034 POWER_DOMAIN_INIT); 1035 1036 /* 1037 * There is no PW_2/PG_2 on RKL. 1038 * 1039 * RKL PW_1/PG_1 domains (under HW/DMC control): 1040 * - DBUF function (note: registers are in PW0) 1041 * - PIPE_A and its planes and VDSC/joining, except VGA 1042 * - transcoder A 1043 * - DDI_A and DDI_B 1044 * - FBC 1045 * 1046 * RKL PW_0/PG_0 domains (under HW/DMC control): 1047 * - PCI 1048 * - clocks except port PLL 1049 * - shared functions: 1050 * * interrupts except pipe interrupts 1051 * * MBus except PIPE_MBUS_DBOX_CTL 1052 * * DBUF registers 1053 * - central power except FBC 1054 * - top-level GTC (DDI-level GTC is in the well associated with the DDI) 1055 */ 1056 1057 I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off, 1058 RKL_PW_3_POWER_DOMAINS, 1059 POWER_DOMAIN_AUX_A, 1060 POWER_DOMAIN_AUX_B, 1061 POWER_DOMAIN_MODESET, 1062 POWER_DOMAIN_DC_OFF, 1063 POWER_DOMAIN_INIT); 1064 1065 static const struct i915_power_well_desc rkl_power_wells_main[] = { 1066 { 1067 .instances = &I915_PW_INSTANCES( 1068 I915_PW("DC_off", &rkl_pwdoms_dc_off, 1069 .id = SKL_DISP_DC_OFF), 1070 ), 1071 .ops = &gen9_dc_off_power_well_ops, 1072 }, { 1073 .instances = &I915_PW_INSTANCES( 1074 I915_PW("PW_3", &rkl_pwdoms_pw_3, 1075 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 1076 .id = ICL_DISP_PW_3), 1077 ), 1078 .ops = &hsw_power_well_ops, 1079 .irq_pipe_mask = BIT(PIPE_B), 1080 .has_vga = true, 1081 .has_fuses = true, 1082 }, { 1083 .instances = &I915_PW_INSTANCES( 1084 I915_PW("PW_4", &rkl_pwdoms_pw_4, 1085 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 1086 ), 1087 .ops = &hsw_power_well_ops, 1088 .has_fuses = true, 1089 .irq_pipe_mask = BIT(PIPE_C), 1090 }, 1091 }; 1092 1093 static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = { 1094 { 1095 .instances = &I915_PW_INSTANCES( 1096 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 1097 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 1098 I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), 1099 I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), 1100 ), 1101 .ops = &icl_ddi_power_well_ops, 1102 }, { 1103 .instances = &I915_PW_INSTANCES( 1104 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 1105 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 1106 I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), 1107 I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), 1108 ), 1109 .ops = &icl_aux_power_well_ops, 1110 }, 1111 }; 1112 1113 static const struct i915_power_well_desc_list rkl_power_wells[] = { 1114 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1115 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1116 I915_PW_DESCRIPTORS(rkl_power_wells_main), 1117 I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux), 1118 }; 1119 1120 /* 1121 * DG1 onwards Audio MMIO/VERBS lies in PG0 power well. 1122 */ 1123 #define DG1_PW_3_POWER_DOMAINS \ 1124 TGL_PW_4_POWER_DOMAINS, \ 1125 POWER_DOMAIN_PIPE_B, \ 1126 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 1127 POWER_DOMAIN_TRANSCODER_B, \ 1128 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1129 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1130 POWER_DOMAIN_VGA, \ 1131 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1132 POWER_DOMAIN_AUX_USBC1, \ 1133 POWER_DOMAIN_AUX_USBC2 1134 1135 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3, 1136 DG1_PW_3_POWER_DOMAINS, 1137 POWER_DOMAIN_INIT); 1138 1139 I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off, 1140 DG1_PW_3_POWER_DOMAINS, 1141 POWER_DOMAIN_AUDIO_MMIO, 1142 POWER_DOMAIN_AUX_A, 1143 POWER_DOMAIN_AUX_B, 1144 POWER_DOMAIN_MODESET, 1145 POWER_DOMAIN_DC_OFF, 1146 POWER_DOMAIN_INIT); 1147 1148 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2, 1149 DG1_PW_3_POWER_DOMAINS, 1150 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 1151 POWER_DOMAIN_INIT); 1152 1153 static const struct i915_power_well_desc dg1_power_wells_main[] = { 1154 { 1155 .instances = &I915_PW_INSTANCES( 1156 I915_PW("DC_off", &dg1_pwdoms_dc_off, 1157 .id = SKL_DISP_DC_OFF), 1158 ), 1159 .ops = &gen9_dc_off_power_well_ops, 1160 }, { 1161 .instances = &I915_PW_INSTANCES( 1162 I915_PW("PW_2", &dg1_pwdoms_pw_2, 1163 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 1164 .id = SKL_DISP_PW_2), 1165 ), 1166 .ops = &hsw_power_well_ops, 1167 .has_fuses = true, 1168 }, { 1169 .instances = &I915_PW_INSTANCES( 1170 I915_PW("PW_3", &dg1_pwdoms_pw_3, 1171 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 1172 .id = ICL_DISP_PW_3), 1173 ), 1174 .ops = &hsw_power_well_ops, 1175 .irq_pipe_mask = BIT(PIPE_B), 1176 .has_vga = true, 1177 .has_fuses = true, 1178 }, { 1179 .instances = &I915_PW_INSTANCES( 1180 I915_PW("PW_4", &tgl_pwdoms_pw_4, 1181 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 1182 ), 1183 .ops = &hsw_power_well_ops, 1184 .has_fuses = true, 1185 .irq_pipe_mask = BIT(PIPE_C), 1186 }, { 1187 .instances = &I915_PW_INSTANCES( 1188 I915_PW("PW_5", &tgl_pwdoms_pw_5, 1189 .hsw.idx = TGL_PW_CTL_IDX_PW_5), 1190 ), 1191 .ops = &hsw_power_well_ops, 1192 .has_fuses = true, 1193 .irq_pipe_mask = BIT(PIPE_D), 1194 }, 1195 }; 1196 1197 static const struct i915_power_well_desc_list dg1_power_wells[] = { 1198 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1199 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1200 I915_PW_DESCRIPTORS(dg1_power_wells_main), 1201 I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux), 1202 }; 1203 1204 /* 1205 * XE_LPD Power Domains 1206 * 1207 * Previous platforms required that PG(n-1) be enabled before PG(n). That 1208 * dependency chain turns into a dependency tree on XE_LPD: 1209 * 1210 * PG0 1211 * | 1212 * --PG1-- 1213 * / \ 1214 * PGA --PG2-- 1215 * / | \ 1216 * PGB PGC PGD 1217 * 1218 * Power wells must be enabled from top to bottom and disabled from bottom 1219 * to top. This allows pipes to be power gated independently. 1220 */ 1221 1222 #define XELPD_PW_D_POWER_DOMAINS \ 1223 POWER_DOMAIN_PIPE_D, \ 1224 POWER_DOMAIN_PIPE_PANEL_FITTER_D, \ 1225 POWER_DOMAIN_TRANSCODER_D 1226 1227 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d, 1228 XELPD_PW_D_POWER_DOMAINS, 1229 POWER_DOMAIN_INIT); 1230 1231 #define XELPD_PW_C_POWER_DOMAINS \ 1232 POWER_DOMAIN_PIPE_C, \ 1233 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 1234 POWER_DOMAIN_TRANSCODER_C 1235 1236 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c, 1237 XELPD_PW_C_POWER_DOMAINS, 1238 POWER_DOMAIN_INIT); 1239 1240 #define XELPD_PW_B_POWER_DOMAINS \ 1241 POWER_DOMAIN_PIPE_B, \ 1242 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 1243 POWER_DOMAIN_TRANSCODER_B 1244 1245 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b, 1246 XELPD_PW_B_POWER_DOMAINS, 1247 POWER_DOMAIN_INIT); 1248 1249 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a, 1250 POWER_DOMAIN_PIPE_A, 1251 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 1252 POWER_DOMAIN_INIT); 1253 1254 #define XELPD_DC_OFF_PORT_POWER_DOMAINS \ 1255 POWER_DOMAIN_PORT_DDI_LANES_C, \ 1256 POWER_DOMAIN_PORT_DDI_LANES_D, \ 1257 POWER_DOMAIN_PORT_DDI_LANES_E, \ 1258 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1259 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1260 POWER_DOMAIN_PORT_DDI_LANES_TC3, \ 1261 POWER_DOMAIN_PORT_DDI_LANES_TC4, \ 1262 POWER_DOMAIN_VGA, \ 1263 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1264 POWER_DOMAIN_AUX_IO_C, \ 1265 POWER_DOMAIN_AUX_IO_D, \ 1266 POWER_DOMAIN_AUX_IO_E, \ 1267 POWER_DOMAIN_AUX_C, \ 1268 POWER_DOMAIN_AUX_D, \ 1269 POWER_DOMAIN_AUX_E, \ 1270 POWER_DOMAIN_AUX_USBC1, \ 1271 POWER_DOMAIN_AUX_USBC2, \ 1272 POWER_DOMAIN_AUX_USBC3, \ 1273 POWER_DOMAIN_AUX_USBC4, \ 1274 POWER_DOMAIN_AUX_TBT1, \ 1275 POWER_DOMAIN_AUX_TBT2, \ 1276 POWER_DOMAIN_AUX_TBT3, \ 1277 POWER_DOMAIN_AUX_TBT4 1278 1279 #define XELPD_PW_2_POWER_DOMAINS \ 1280 XELPD_PW_B_POWER_DOMAINS, \ 1281 XELPD_PW_C_POWER_DOMAINS, \ 1282 XELPD_PW_D_POWER_DOMAINS, \ 1283 XELPD_DC_OFF_PORT_POWER_DOMAINS 1284 1285 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2, 1286 XELPD_PW_2_POWER_DOMAINS, 1287 POWER_DOMAIN_INIT); 1288 1289 /* 1290 * XELPD PW_1/PG_1 domains (under HW/DMC control): 1291 * - DBUF function (registers are in PW0) 1292 * - Transcoder A 1293 * - DDI_A and DDI_B 1294 * 1295 * XELPD PW_0/PW_1 domains (under HW/DMC control): 1296 * - PCI 1297 * - Clocks except port PLL 1298 * - Shared functions: 1299 * * interrupts except pipe interrupts 1300 * * MBus except PIPE_MBUS_DBOX_CTL 1301 * * DBUF registers 1302 * - Central power except FBC 1303 * - Top-level GTC (DDI-level GTC is in the well associated with the DDI) 1304 */ 1305 1306 I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off, 1307 XELPD_DC_OFF_PORT_POWER_DOMAINS, 1308 XELPD_PW_C_POWER_DOMAINS, 1309 XELPD_PW_D_POWER_DOMAINS, 1310 POWER_DOMAIN_PORT_DSI, 1311 POWER_DOMAIN_AUDIO_MMIO, 1312 POWER_DOMAIN_AUX_A, 1313 POWER_DOMAIN_AUX_B, 1314 POWER_DOMAIN_MODESET, 1315 POWER_DOMAIN_DC_OFF, 1316 POWER_DOMAIN_INIT); 1317 1318 static const struct i915_power_well_desc xelpd_power_wells_dc_off[] = { 1319 { 1320 .instances = &I915_PW_INSTANCES( 1321 I915_PW("DC_off", &xelpd_pwdoms_dc_off, 1322 .id = SKL_DISP_DC_OFF), 1323 ), 1324 .ops = &gen9_dc_off_power_well_ops, 1325 } 1326 }; 1327 1328 static const struct i915_power_well_desc xelpd_power_wells_main[] = { 1329 { 1330 .instances = &I915_PW_INSTANCES( 1331 I915_PW("PW_2", &xelpd_pwdoms_pw_2, 1332 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 1333 .id = SKL_DISP_PW_2), 1334 ), 1335 .ops = &hsw_power_well_ops, 1336 .has_vga = true, 1337 .has_fuses = true, 1338 }, { 1339 .instances = &I915_PW_INSTANCES( 1340 I915_PW("PW_A", &xelpd_pwdoms_pw_a, 1341 .hsw.idx = XELPD_PW_CTL_IDX_PW_A), 1342 ), 1343 .ops = &hsw_power_well_ops, 1344 .irq_pipe_mask = BIT(PIPE_A), 1345 .has_fuses = true, 1346 }, { 1347 .instances = &I915_PW_INSTANCES( 1348 I915_PW("PW_B", &xelpd_pwdoms_pw_b, 1349 .hsw.idx = XELPD_PW_CTL_IDX_PW_B), 1350 ), 1351 .ops = &hsw_power_well_ops, 1352 .irq_pipe_mask = BIT(PIPE_B), 1353 .has_fuses = true, 1354 }, { 1355 .instances = &I915_PW_INSTANCES( 1356 I915_PW("PW_C", &xelpd_pwdoms_pw_c, 1357 .hsw.idx = XELPD_PW_CTL_IDX_PW_C), 1358 ), 1359 .ops = &hsw_power_well_ops, 1360 .irq_pipe_mask = BIT(PIPE_C), 1361 .has_fuses = true, 1362 }, { 1363 .instances = &I915_PW_INSTANCES( 1364 I915_PW("PW_D", &xelpd_pwdoms_pw_d, 1365 .hsw.idx = XELPD_PW_CTL_IDX_PW_D), 1366 ), 1367 .ops = &hsw_power_well_ops, 1368 .irq_pipe_mask = BIT(PIPE_D), 1369 .has_fuses = true, 1370 }, { 1371 .instances = &I915_PW_INSTANCES( 1372 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 1373 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 1374 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), 1375 I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D), 1376 I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E), 1377 I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), 1378 I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), 1379 I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3), 1380 I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4), 1381 ), 1382 .ops = &icl_ddi_power_well_ops, 1383 }, { 1384 .instances = &I915_PW_INSTANCES( 1385 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 1386 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 1387 I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), 1388 I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D), 1389 I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E), 1390 ), 1391 .ops = &icl_aux_power_well_ops, 1392 .fixed_enable_delay = true, 1393 }, { 1394 .instances = &I915_PW_INSTANCES( 1395 I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), 1396 I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), 1397 I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3), 1398 I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4), 1399 ), 1400 .ops = &icl_aux_power_well_ops, 1401 .fixed_enable_delay = true, 1402 /* WA_14017248603: adlp */ 1403 .enable_timeout = 500, 1404 }, { 1405 .instances = &I915_PW_INSTANCES( 1406 I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1), 1407 I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2), 1408 I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3), 1409 I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4), 1410 ), 1411 .ops = &icl_aux_power_well_ops, 1412 .is_tc_tbt = true, 1413 }, 1414 }; 1415 1416 static const struct i915_power_well_desc_list xelpd_power_wells[] = { 1417 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1418 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1419 I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off), 1420 I915_PW_DESCRIPTORS(xelpd_power_wells_main), 1421 }; 1422 1423 I915_DECL_PW_DOMAINS(xehpd_pwdoms_dc_off, 1424 XELPD_PW_2_POWER_DOMAINS, 1425 POWER_DOMAIN_PORT_DSI, 1426 POWER_DOMAIN_AUDIO_MMIO, 1427 POWER_DOMAIN_AUX_A, 1428 POWER_DOMAIN_AUX_B, 1429 POWER_DOMAIN_MODESET, 1430 POWER_DOMAIN_DC_OFF, 1431 POWER_DOMAIN_INIT); 1432 1433 static const struct i915_power_well_desc xehpd_power_wells_dc_off[] = { 1434 { 1435 .instances = &I915_PW_INSTANCES( 1436 I915_PW("DC_off", &xehpd_pwdoms_dc_off, 1437 .id = SKL_DISP_DC_OFF), 1438 ), 1439 .ops = &gen9_dc_off_power_well_ops, 1440 } 1441 }; 1442 1443 static const struct i915_power_well_desc_list xehpd_power_wells[] = { 1444 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1445 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1446 I915_PW_DESCRIPTORS(xehpd_power_wells_dc_off), 1447 I915_PW_DESCRIPTORS(xelpd_power_wells_main), 1448 }; 1449 1450 /* 1451 * MTL is based on XELPD power domains with the exception of power gating for: 1452 * - DDI_IO (moved to PLL logic) 1453 * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA always-on) 1454 */ 1455 #define XELPDP_PW_2_POWER_DOMAINS \ 1456 XELPD_PW_B_POWER_DOMAINS, \ 1457 XELPD_PW_C_POWER_DOMAINS, \ 1458 XELPD_PW_D_POWER_DOMAINS, \ 1459 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1460 POWER_DOMAIN_VGA, \ 1461 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1462 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1463 POWER_DOMAIN_PORT_DDI_LANES_TC3, \ 1464 POWER_DOMAIN_PORT_DDI_LANES_TC4 1465 1466 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2, 1467 XELPDP_PW_2_POWER_DOMAINS, 1468 POWER_DOMAIN_INIT); 1469 1470 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1, 1471 POWER_DOMAIN_AUX_USBC1, 1472 POWER_DOMAIN_AUX_TBT1); 1473 1474 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2, 1475 POWER_DOMAIN_AUX_USBC2, 1476 POWER_DOMAIN_AUX_TBT2); 1477 1478 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3, 1479 POWER_DOMAIN_AUX_USBC3, 1480 POWER_DOMAIN_AUX_TBT3); 1481 1482 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4, 1483 POWER_DOMAIN_AUX_USBC4, 1484 POWER_DOMAIN_AUX_TBT4); 1485 1486 static const struct i915_power_well_desc xelpdp_power_wells_main[] = { 1487 { 1488 .instances = &I915_PW_INSTANCES( 1489 I915_PW("PW_2", &xelpdp_pwdoms_pw_2, 1490 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 1491 .id = SKL_DISP_PW_2), 1492 ), 1493 .ops = &hsw_power_well_ops, 1494 .has_vga = true, 1495 .has_fuses = true, 1496 }, { 1497 .instances = &I915_PW_INSTANCES( 1498 I915_PW("PW_A", &xelpd_pwdoms_pw_a, 1499 .hsw.idx = XELPD_PW_CTL_IDX_PW_A), 1500 ), 1501 .ops = &hsw_power_well_ops, 1502 .irq_pipe_mask = BIT(PIPE_A), 1503 .has_fuses = true, 1504 }, { 1505 .instances = &I915_PW_INSTANCES( 1506 I915_PW("PW_B", &xelpd_pwdoms_pw_b, 1507 .hsw.idx = XELPD_PW_CTL_IDX_PW_B), 1508 ), 1509 .ops = &hsw_power_well_ops, 1510 .irq_pipe_mask = BIT(PIPE_B), 1511 .has_fuses = true, 1512 }, { 1513 .instances = &I915_PW_INSTANCES( 1514 I915_PW("PW_C", &xelpd_pwdoms_pw_c, 1515 .hsw.idx = XELPD_PW_CTL_IDX_PW_C), 1516 ), 1517 .ops = &hsw_power_well_ops, 1518 .irq_pipe_mask = BIT(PIPE_C), 1519 .has_fuses = true, 1520 }, { 1521 .instances = &I915_PW_INSTANCES( 1522 I915_PW("PW_D", &xelpd_pwdoms_pw_d, 1523 .hsw.idx = XELPD_PW_CTL_IDX_PW_D), 1524 ), 1525 .ops = &hsw_power_well_ops, 1526 .irq_pipe_mask = BIT(PIPE_D), 1527 .has_fuses = true, 1528 }, { 1529 .instances = &I915_PW_INSTANCES( 1530 I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A), 1531 I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B), 1532 I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1), 1533 I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2), 1534 I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3), 1535 I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4), 1536 ), 1537 .ops = &xelpdp_aux_power_well_ops, 1538 }, 1539 }; 1540 1541 static const struct i915_power_well_desc_list xelpdp_power_wells[] = { 1542 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1543 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1544 I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off), 1545 I915_PW_DESCRIPTORS(xelpdp_power_wells_main), 1546 }; 1547 1548 static void init_power_well_domains(const struct i915_power_well_instance *inst, 1549 struct i915_power_well *power_well) 1550 { 1551 int j; 1552 1553 if (!inst->domain_list) 1554 return; 1555 1556 if (inst->domain_list->count == 0) { 1557 bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM); 1558 1559 return; 1560 } 1561 1562 for (j = 0; j < inst->domain_list->count; j++) 1563 set_bit(inst->domain_list->list[j], power_well->domains.bits); 1564 } 1565 1566 #define for_each_power_well_instance_in_desc_list(_desc_list, _desc_count, _desc, _inst) \ 1567 for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \ 1568 for ((_inst) = (_desc)->instances->list; \ 1569 (_inst) - (_desc)->instances->list < (_desc)->instances->count; \ 1570 (_inst)++) 1571 1572 #define for_each_power_well_instance(_desc_list, _desc_count, _descs, _desc, _inst) \ 1573 for ((_descs) = (_desc_list); \ 1574 (_descs) - (_desc_list) < (_desc_count); \ 1575 (_descs)++) \ 1576 for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ 1577 (_desc), (_inst)) 1578 1579 static int 1580 __set_power_wells(struct i915_power_domains *power_domains, 1581 const struct i915_power_well_desc_list *power_well_descs, 1582 int power_well_descs_sz) 1583 { 1584 struct drm_i915_private *i915 = container_of(power_domains, 1585 struct drm_i915_private, 1586 display.power.domains); 1587 u64 power_well_ids = 0; 1588 const struct i915_power_well_desc_list *desc_list; 1589 const struct i915_power_well_desc *desc; 1590 const struct i915_power_well_instance *inst; 1591 int power_well_count = 0; 1592 int plt_idx = 0; 1593 1594 for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) 1595 power_well_count++; 1596 1597 power_domains->power_well_count = power_well_count; 1598 power_domains->power_wells = 1599 kcalloc(power_well_count, 1600 sizeof(*power_domains->power_wells), 1601 GFP_KERNEL); 1602 if (!power_domains->power_wells) 1603 return -ENOMEM; 1604 1605 for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { 1606 struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; 1607 enum i915_power_well_id id = inst->id; 1608 1609 pw->desc = desc; 1610 drm_WARN_ON(&i915->drm, 1611 overflows_type(inst - desc->instances->list, pw->instance_idx)); 1612 pw->instance_idx = inst - desc->instances->list; 1613 1614 init_power_well_domains(inst, pw); 1615 1616 plt_idx++; 1617 1618 if (id == DISP_PW_ID_NONE) 1619 continue; 1620 1621 drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8); 1622 drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id)); 1623 power_well_ids |= BIT_ULL(id); 1624 } 1625 1626 return 0; 1627 } 1628 1629 #define set_power_wells(power_domains, __power_well_descs) \ 1630 __set_power_wells(power_domains, __power_well_descs, \ 1631 ARRAY_SIZE(__power_well_descs)) 1632 1633 /** 1634 * intel_display_power_map_init - initialize power domain -> power well mappings 1635 * @power_domains: power domain state 1636 * 1637 * Creates all the power wells for the current platform, initializes the 1638 * dynamic state for them and initializes the mapping of each power well to 1639 * all the power domains the power well belongs to. 1640 */ 1641 int intel_display_power_map_init(struct i915_power_domains *power_domains) 1642 { 1643 struct drm_i915_private *i915 = container_of(power_domains, 1644 struct drm_i915_private, 1645 display.power.domains); 1646 /* 1647 * The enabling order will be from lower to higher indexed wells, 1648 * the disabling order is reversed. 1649 */ 1650 if (!HAS_DISPLAY(i915)) { 1651 power_domains->power_well_count = 0; 1652 return 0; 1653 } 1654 1655 if (DISPLAY_VER(i915) >= 14) 1656 return set_power_wells(power_domains, xelpdp_power_wells); 1657 else if (IS_DG2(i915)) 1658 return set_power_wells(power_domains, xehpd_power_wells); 1659 else if (DISPLAY_VER(i915) >= 13) 1660 return set_power_wells(power_domains, xelpd_power_wells); 1661 else if (IS_DG1(i915)) 1662 return set_power_wells(power_domains, dg1_power_wells); 1663 else if (IS_ALDERLAKE_S(i915)) 1664 return set_power_wells(power_domains, adls_power_wells); 1665 else if (IS_ROCKETLAKE(i915)) 1666 return set_power_wells(power_domains, rkl_power_wells); 1667 else if (DISPLAY_VER(i915) == 12) 1668 return set_power_wells(power_domains, tgl_power_wells); 1669 else if (DISPLAY_VER(i915) == 11) 1670 return set_power_wells(power_domains, icl_power_wells); 1671 else if (IS_GEMINILAKE(i915)) 1672 return set_power_wells(power_domains, glk_power_wells); 1673 else if (IS_BROXTON(i915)) 1674 return set_power_wells(power_domains, bxt_power_wells); 1675 else if (DISPLAY_VER(i915) == 9) 1676 return set_power_wells(power_domains, skl_power_wells); 1677 else if (IS_CHERRYVIEW(i915)) 1678 return set_power_wells(power_domains, chv_power_wells); 1679 else if (IS_BROADWELL(i915)) 1680 return set_power_wells(power_domains, bdw_power_wells); 1681 else if (IS_HASWELL(i915)) 1682 return set_power_wells(power_domains, hsw_power_wells); 1683 else if (IS_VALLEYVIEW(i915)) 1684 return set_power_wells(power_domains, vlv_power_wells); 1685 else if (IS_I830(i915)) 1686 return set_power_wells(power_domains, i830_power_wells); 1687 else 1688 return set_power_wells(power_domains, i9xx_power_wells); 1689 } 1690 1691 /** 1692 * intel_display_power_map_cleanup - clean up power domain -> power well mappings 1693 * @power_domains: power domain state 1694 * 1695 * Cleans up all the state that was initialized by intel_display_power_map_init(). 1696 */ 1697 void intel_display_power_map_cleanup(struct i915_power_domains *power_domains) 1698 { 1699 kfree(power_domains->power_wells); 1700 } 1701