1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "intel_display_core.h" 9 #include "intel_display_power_map.h" 10 #include "intel_display_power_well.h" 11 #include "intel_display_regs.h" 12 #include "intel_display_types.h" 13 #include "vlv_iosf_sb_reg.h" 14 15 #define __LIST_INLINE_ELEMS(__elem_type, ...) \ 16 ((__elem_type[]) { __VA_ARGS__ }) 17 18 #define __LIST(__elems) { \ 19 .list = __elems, \ 20 .count = ARRAY_SIZE(__elems), \ 21 } 22 23 #define I915_PW_DOMAINS(...) \ 24 (const struct i915_power_domain_list) \ 25 __LIST(__LIST_INLINE_ELEMS(const enum intel_display_power_domain, __VA_ARGS__)) 26 27 #define I915_DECL_PW_DOMAINS(__name, ...) \ 28 static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__) 29 30 /* Zero-length list assigns all power domains, a NULL list assigns none. */ 31 #define I915_PW_DOMAINS_NONE NULL 32 #define I915_PW_DOMAINS_ALL /* zero-length list */ 33 34 #define I915_PW_INSTANCES(...) \ 35 (const struct i915_power_well_instance_list) \ 36 __LIST(__LIST_INLINE_ELEMS(const struct i915_power_well_instance, __VA_ARGS__)) 37 38 #define I915_PW(_name, _domain_list, ...) \ 39 { .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ } 40 41 42 struct i915_power_well_desc_list { 43 const struct i915_power_well_desc *list; 44 u8 count; 45 }; 46 47 #define I915_PW_DESCRIPTORS(x) __LIST(x) 48 49 50 I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL); 51 52 static const struct i915_power_well_desc i9xx_power_wells_always_on[] = { 53 { 54 .instances = &I915_PW_INSTANCES( 55 I915_PW("always-on", &i9xx_pwdoms_always_on), 56 ), 57 .ops = &i9xx_always_on_power_well_ops, 58 .always_on = true, 59 }, 60 }; 61 62 static const struct i915_power_well_desc_list i9xx_power_wells[] = { 63 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 64 }; 65 66 I915_DECL_PW_DOMAINS(i830_pwdoms_pipes, 67 POWER_DOMAIN_PIPE_A, 68 POWER_DOMAIN_PIPE_B, 69 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 70 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 71 POWER_DOMAIN_TRANSCODER_A, 72 POWER_DOMAIN_TRANSCODER_B, 73 POWER_DOMAIN_INIT); 74 75 static const struct i915_power_well_desc i830_power_wells_main[] = { 76 { 77 .instances = &I915_PW_INSTANCES( 78 I915_PW("pipes", &i830_pwdoms_pipes), 79 ), 80 .ops = &i830_pipes_power_well_ops, 81 }, 82 }; 83 84 static const struct i915_power_well_desc_list i830_power_wells[] = { 85 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 86 I915_PW_DESCRIPTORS(i830_power_wells_main), 87 }; 88 89 I915_DECL_PW_DOMAINS(hsw_pwdoms_display, 90 POWER_DOMAIN_PIPE_B, 91 POWER_DOMAIN_PIPE_C, 92 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 93 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 94 POWER_DOMAIN_PIPE_PANEL_FITTER_C, 95 POWER_DOMAIN_TRANSCODER_A, 96 POWER_DOMAIN_TRANSCODER_B, 97 POWER_DOMAIN_TRANSCODER_C, 98 POWER_DOMAIN_PORT_DDI_LANES_B, 99 POWER_DOMAIN_PORT_DDI_LANES_C, 100 POWER_DOMAIN_PORT_DDI_LANES_D, 101 POWER_DOMAIN_PORT_CRT, /* DDI E */ 102 POWER_DOMAIN_VGA, 103 POWER_DOMAIN_AUDIO_MMIO, 104 POWER_DOMAIN_AUDIO_PLAYBACK, 105 POWER_DOMAIN_INIT); 106 107 static const struct i915_power_well_desc hsw_power_wells_main[] = { 108 { 109 .instances = &I915_PW_INSTANCES( 110 I915_PW("display", &hsw_pwdoms_display, 111 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, 112 .id = HSW_DISP_PW_GLOBAL), 113 ), 114 .ops = &hsw_power_well_ops, 115 }, 116 }; 117 118 static const struct i915_power_well_desc_list hsw_power_wells[] = { 119 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 120 I915_PW_DESCRIPTORS(hsw_power_wells_main), 121 }; 122 123 I915_DECL_PW_DOMAINS(bdw_pwdoms_display, 124 POWER_DOMAIN_PIPE_B, 125 POWER_DOMAIN_PIPE_C, 126 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 127 POWER_DOMAIN_PIPE_PANEL_FITTER_C, 128 POWER_DOMAIN_TRANSCODER_A, 129 POWER_DOMAIN_TRANSCODER_B, 130 POWER_DOMAIN_TRANSCODER_C, 131 POWER_DOMAIN_PORT_DDI_LANES_B, 132 POWER_DOMAIN_PORT_DDI_LANES_C, 133 POWER_DOMAIN_PORT_DDI_LANES_D, 134 POWER_DOMAIN_PORT_CRT, /* DDI E */ 135 POWER_DOMAIN_VGA, 136 POWER_DOMAIN_AUDIO_MMIO, 137 POWER_DOMAIN_AUDIO_PLAYBACK, 138 POWER_DOMAIN_INIT); 139 140 static const struct i915_power_well_desc bdw_power_wells_main[] = { 141 { 142 .instances = &I915_PW_INSTANCES( 143 I915_PW("display", &bdw_pwdoms_display, 144 .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, 145 .id = HSW_DISP_PW_GLOBAL), 146 ), 147 .ops = &hsw_power_well_ops, 148 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 149 }, 150 }; 151 152 static const struct i915_power_well_desc_list bdw_power_wells[] = { 153 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 154 I915_PW_DESCRIPTORS(bdw_power_wells_main), 155 }; 156 157 I915_DECL_PW_DOMAINS(vlv_pwdoms_display, 158 POWER_DOMAIN_DISPLAY_CORE, 159 POWER_DOMAIN_PIPE_A, 160 POWER_DOMAIN_PIPE_B, 161 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 162 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 163 POWER_DOMAIN_TRANSCODER_A, 164 POWER_DOMAIN_TRANSCODER_B, 165 POWER_DOMAIN_PORT_DDI_LANES_B, 166 POWER_DOMAIN_PORT_DDI_LANES_C, 167 POWER_DOMAIN_PORT_DSI, 168 POWER_DOMAIN_PORT_CRT, 169 POWER_DOMAIN_VGA, 170 POWER_DOMAIN_AUDIO_MMIO, 171 POWER_DOMAIN_AUDIO_PLAYBACK, 172 POWER_DOMAIN_AUX_IO_B, 173 POWER_DOMAIN_AUX_IO_C, 174 POWER_DOMAIN_AUX_B, 175 POWER_DOMAIN_AUX_C, 176 POWER_DOMAIN_GMBUS, 177 POWER_DOMAIN_INIT); 178 179 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc, 180 POWER_DOMAIN_PORT_DDI_LANES_B, 181 POWER_DOMAIN_PORT_DDI_LANES_C, 182 POWER_DOMAIN_PORT_CRT, 183 POWER_DOMAIN_AUX_IO_B, 184 POWER_DOMAIN_AUX_IO_C, 185 POWER_DOMAIN_AUX_B, 186 POWER_DOMAIN_AUX_C, 187 POWER_DOMAIN_INIT); 188 189 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes, 190 POWER_DOMAIN_PORT_DDI_LANES_B, 191 POWER_DOMAIN_PORT_DDI_LANES_C, 192 POWER_DOMAIN_AUX_IO_B, 193 POWER_DOMAIN_AUX_IO_C, 194 POWER_DOMAIN_AUX_B, 195 POWER_DOMAIN_AUX_C, 196 POWER_DOMAIN_INIT); 197 198 static const struct i915_power_well_desc vlv_power_wells_main[] = { 199 { 200 .instances = &I915_PW_INSTANCES( 201 I915_PW("display", &vlv_pwdoms_display, 202 .vlv.idx = PUNIT_PWGT_IDX_DISP2D, 203 .id = VLV_DISP_PW_DISP2D), 204 ), 205 .ops = &vlv_display_power_well_ops, 206 }, { 207 .instances = &I915_PW_INSTANCES( 208 I915_PW("dpio-tx-b-01", &vlv_pwdoms_dpio_tx_bc_lanes, 209 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01), 210 I915_PW("dpio-tx-b-23", &vlv_pwdoms_dpio_tx_bc_lanes, 211 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23), 212 I915_PW("dpio-tx-c-01", &vlv_pwdoms_dpio_tx_bc_lanes, 213 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01), 214 I915_PW("dpio-tx-c-23", &vlv_pwdoms_dpio_tx_bc_lanes, 215 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23), 216 ), 217 .ops = &vlv_dpio_power_well_ops, 218 }, { 219 .instances = &I915_PW_INSTANCES( 220 I915_PW("dpio-common", &vlv_pwdoms_dpio_cmn_bc, 221 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, 222 .id = VLV_DISP_PW_DPIO_CMN_BC), 223 ), 224 .ops = &vlv_dpio_cmn_power_well_ops, 225 }, 226 }; 227 228 static const struct i915_power_well_desc_list vlv_power_wells[] = { 229 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 230 I915_PW_DESCRIPTORS(vlv_power_wells_main), 231 }; 232 233 I915_DECL_PW_DOMAINS(chv_pwdoms_display, 234 POWER_DOMAIN_DISPLAY_CORE, 235 POWER_DOMAIN_PIPE_A, 236 POWER_DOMAIN_PIPE_B, 237 POWER_DOMAIN_PIPE_C, 238 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 239 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 240 POWER_DOMAIN_PIPE_PANEL_FITTER_C, 241 POWER_DOMAIN_TRANSCODER_A, 242 POWER_DOMAIN_TRANSCODER_B, 243 POWER_DOMAIN_TRANSCODER_C, 244 POWER_DOMAIN_PORT_DDI_LANES_B, 245 POWER_DOMAIN_PORT_DDI_LANES_C, 246 POWER_DOMAIN_PORT_DDI_LANES_D, 247 POWER_DOMAIN_PORT_DSI, 248 POWER_DOMAIN_VGA, 249 POWER_DOMAIN_AUDIO_MMIO, 250 POWER_DOMAIN_AUDIO_PLAYBACK, 251 POWER_DOMAIN_AUX_IO_B, 252 POWER_DOMAIN_AUX_IO_C, 253 POWER_DOMAIN_AUX_IO_D, 254 POWER_DOMAIN_AUX_B, 255 POWER_DOMAIN_AUX_C, 256 POWER_DOMAIN_AUX_D, 257 POWER_DOMAIN_GMBUS, 258 POWER_DOMAIN_INIT); 259 260 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc, 261 POWER_DOMAIN_PORT_DDI_LANES_B, 262 POWER_DOMAIN_PORT_DDI_LANES_C, 263 POWER_DOMAIN_AUX_IO_B, 264 POWER_DOMAIN_AUX_IO_C, 265 POWER_DOMAIN_AUX_B, 266 POWER_DOMAIN_AUX_C, 267 POWER_DOMAIN_INIT); 268 269 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d, 270 POWER_DOMAIN_PORT_DDI_LANES_D, 271 POWER_DOMAIN_AUX_IO_D, 272 POWER_DOMAIN_AUX_D, 273 POWER_DOMAIN_INIT); 274 275 static const struct i915_power_well_desc chv_power_wells_main[] = { 276 { 277 /* 278 * Pipe A power well is the new disp2d well. Pipe B and C 279 * power wells don't actually exist. Pipe A power well is 280 * required for any pipe to work. 281 */ 282 .instances = &I915_PW_INSTANCES( 283 I915_PW("display", &chv_pwdoms_display), 284 ), 285 .ops = &chv_pipe_power_well_ops, 286 }, { 287 .instances = &I915_PW_INSTANCES( 288 I915_PW("dpio-common-bc", &chv_pwdoms_dpio_cmn_bc, 289 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, 290 .id = VLV_DISP_PW_DPIO_CMN_BC), 291 I915_PW("dpio-common-d", &chv_pwdoms_dpio_cmn_d, 292 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D, 293 .id = CHV_DISP_PW_DPIO_CMN_D), 294 ), 295 .ops = &chv_dpio_cmn_power_well_ops, 296 }, 297 }; 298 299 static const struct i915_power_well_desc_list chv_power_wells[] = { 300 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 301 I915_PW_DESCRIPTORS(chv_power_wells_main), 302 }; 303 304 #define SKL_PW_2_POWER_DOMAINS \ 305 POWER_DOMAIN_PIPE_B, \ 306 POWER_DOMAIN_PIPE_C, \ 307 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 308 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 309 POWER_DOMAIN_TRANSCODER_A, \ 310 POWER_DOMAIN_TRANSCODER_B, \ 311 POWER_DOMAIN_TRANSCODER_C, \ 312 POWER_DOMAIN_PORT_DDI_LANES_B, \ 313 POWER_DOMAIN_PORT_DDI_LANES_C, \ 314 POWER_DOMAIN_PORT_DDI_LANES_D, \ 315 POWER_DOMAIN_PORT_DDI_LANES_E, \ 316 POWER_DOMAIN_VGA, \ 317 POWER_DOMAIN_AUDIO_MMIO, \ 318 POWER_DOMAIN_AUDIO_PLAYBACK, \ 319 POWER_DOMAIN_AUX_IO_B, \ 320 POWER_DOMAIN_AUX_IO_C, \ 321 POWER_DOMAIN_AUX_IO_D, \ 322 POWER_DOMAIN_AUX_B, \ 323 POWER_DOMAIN_AUX_C, \ 324 POWER_DOMAIN_AUX_D 325 326 I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2, 327 SKL_PW_2_POWER_DOMAINS, 328 POWER_DOMAIN_INIT); 329 330 I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off, 331 SKL_PW_2_POWER_DOMAINS, 332 POWER_DOMAIN_AUX_A, 333 POWER_DOMAIN_GT_IRQ, 334 POWER_DOMAIN_DC_OFF, 335 POWER_DOMAIN_INIT); 336 337 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e, 338 POWER_DOMAIN_PORT_DDI_IO_A, 339 POWER_DOMAIN_PORT_DDI_IO_E, 340 POWER_DOMAIN_INIT); 341 342 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b, 343 POWER_DOMAIN_PORT_DDI_IO_B, 344 POWER_DOMAIN_INIT); 345 346 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c, 347 POWER_DOMAIN_PORT_DDI_IO_C, 348 POWER_DOMAIN_INIT); 349 350 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d, 351 POWER_DOMAIN_PORT_DDI_IO_D, 352 POWER_DOMAIN_INIT); 353 354 static const struct i915_power_well_desc skl_power_wells_pw_1[] = { 355 { 356 /* Handled by the DMC firmware */ 357 .instances = &I915_PW_INSTANCES( 358 I915_PW("PW_1", I915_PW_DOMAINS_NONE, 359 .hsw.idx = SKL_PW_CTL_IDX_PW_1, 360 .id = SKL_DISP_PW_1), 361 ), 362 .ops = &hsw_power_well_ops, 363 .always_on = true, 364 .has_fuses = true, 365 }, 366 }; 367 368 static const struct i915_power_well_desc skl_power_wells_main[] = { 369 { 370 /* Handled by the DMC firmware */ 371 .instances = &I915_PW_INSTANCES( 372 I915_PW("MISC_IO", I915_PW_DOMAINS_NONE, 373 .hsw.idx = SKL_PW_CTL_IDX_MISC_IO, 374 .id = SKL_DISP_PW_MISC_IO), 375 ), 376 .ops = &hsw_power_well_ops, 377 .always_on = true, 378 }, { 379 .instances = &I915_PW_INSTANCES( 380 I915_PW("DC_off", &skl_pwdoms_dc_off, 381 .id = SKL_DISP_DC_OFF), 382 ), 383 .ops = &gen9_dc_off_power_well_ops, 384 }, { 385 .instances = &I915_PW_INSTANCES( 386 I915_PW("PW_2", &skl_pwdoms_pw_2, 387 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 388 .id = SKL_DISP_PW_2), 389 ), 390 .ops = &hsw_power_well_ops, 391 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 392 .has_fuses = true, 393 }, { 394 .instances = &I915_PW_INSTANCES( 395 I915_PW("DDI_IO_A_E", &skl_pwdoms_ddi_io_a_e, .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E), 396 I915_PW("DDI_IO_B", &skl_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B), 397 I915_PW("DDI_IO_C", &skl_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C), 398 I915_PW("DDI_IO_D", &skl_pwdoms_ddi_io_d, .hsw.idx = SKL_PW_CTL_IDX_DDI_D), 399 ), 400 .ops = &hsw_power_well_ops, 401 }, 402 }; 403 404 static const struct i915_power_well_desc_list skl_power_wells[] = { 405 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 406 I915_PW_DESCRIPTORS(skl_power_wells_pw_1), 407 I915_PW_DESCRIPTORS(skl_power_wells_main), 408 }; 409 410 #define BXT_PW_2_POWER_DOMAINS \ 411 POWER_DOMAIN_PIPE_B, \ 412 POWER_DOMAIN_PIPE_C, \ 413 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 414 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 415 POWER_DOMAIN_TRANSCODER_A, \ 416 POWER_DOMAIN_TRANSCODER_B, \ 417 POWER_DOMAIN_TRANSCODER_C, \ 418 POWER_DOMAIN_PORT_DDI_LANES_B, \ 419 POWER_DOMAIN_PORT_DDI_LANES_C, \ 420 POWER_DOMAIN_VGA, \ 421 POWER_DOMAIN_AUDIO_MMIO, \ 422 POWER_DOMAIN_AUDIO_PLAYBACK, \ 423 POWER_DOMAIN_AUX_IO_B, \ 424 POWER_DOMAIN_AUX_IO_C, \ 425 POWER_DOMAIN_AUX_B, \ 426 POWER_DOMAIN_AUX_C 427 428 I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2, 429 BXT_PW_2_POWER_DOMAINS, 430 POWER_DOMAIN_INIT); 431 432 I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off, 433 BXT_PW_2_POWER_DOMAINS, 434 POWER_DOMAIN_AUX_A, 435 POWER_DOMAIN_GMBUS, 436 POWER_DOMAIN_GT_IRQ, 437 POWER_DOMAIN_DC_OFF, 438 POWER_DOMAIN_INIT); 439 440 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a, 441 POWER_DOMAIN_PORT_DDI_LANES_A, 442 POWER_DOMAIN_AUX_IO_A, 443 POWER_DOMAIN_AUX_A, 444 POWER_DOMAIN_INIT); 445 446 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc, 447 POWER_DOMAIN_PORT_DDI_LANES_B, 448 POWER_DOMAIN_PORT_DDI_LANES_C, 449 POWER_DOMAIN_AUX_IO_B, 450 POWER_DOMAIN_AUX_IO_C, 451 POWER_DOMAIN_AUX_B, 452 POWER_DOMAIN_AUX_C, 453 POWER_DOMAIN_INIT); 454 455 static const struct i915_power_well_desc bxt_power_wells_main[] = { 456 { 457 .instances = &I915_PW_INSTANCES( 458 I915_PW("DC_off", &bxt_pwdoms_dc_off, 459 .id = SKL_DISP_DC_OFF), 460 ), 461 .ops = &gen9_dc_off_power_well_ops, 462 }, { 463 .instances = &I915_PW_INSTANCES( 464 I915_PW("PW_2", &bxt_pwdoms_pw_2, 465 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 466 .id = SKL_DISP_PW_2), 467 ), 468 .ops = &hsw_power_well_ops, 469 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 470 .has_fuses = true, 471 }, { 472 .instances = &I915_PW_INSTANCES( 473 I915_PW("dpio-common-a", &bxt_pwdoms_dpio_cmn_a, 474 .bxt.phy = DPIO_PHY1, 475 .id = BXT_DISP_PW_DPIO_CMN_A), 476 I915_PW("dpio-common-bc", &bxt_pwdoms_dpio_cmn_bc, 477 .bxt.phy = DPIO_PHY0, 478 .id = VLV_DISP_PW_DPIO_CMN_BC), 479 ), 480 .ops = &bxt_dpio_cmn_power_well_ops, 481 }, 482 }; 483 484 static const struct i915_power_well_desc_list bxt_power_wells[] = { 485 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 486 I915_PW_DESCRIPTORS(skl_power_wells_pw_1), 487 I915_PW_DESCRIPTORS(bxt_power_wells_main), 488 }; 489 490 #define GLK_PW_2_POWER_DOMAINS \ 491 POWER_DOMAIN_PIPE_B, \ 492 POWER_DOMAIN_PIPE_C, \ 493 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 494 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 495 POWER_DOMAIN_TRANSCODER_A, \ 496 POWER_DOMAIN_TRANSCODER_B, \ 497 POWER_DOMAIN_TRANSCODER_C, \ 498 POWER_DOMAIN_PORT_DDI_LANES_B, \ 499 POWER_DOMAIN_PORT_DDI_LANES_C, \ 500 POWER_DOMAIN_VGA, \ 501 POWER_DOMAIN_AUDIO_MMIO, \ 502 POWER_DOMAIN_AUDIO_PLAYBACK, \ 503 POWER_DOMAIN_AUX_IO_B, \ 504 POWER_DOMAIN_AUX_IO_C, \ 505 POWER_DOMAIN_AUX_B, \ 506 POWER_DOMAIN_AUX_C 507 508 I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2, 509 GLK_PW_2_POWER_DOMAINS, 510 POWER_DOMAIN_INIT); 511 512 I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off, 513 GLK_PW_2_POWER_DOMAINS, 514 POWER_DOMAIN_AUX_A, 515 POWER_DOMAIN_GMBUS, 516 POWER_DOMAIN_GT_IRQ, 517 POWER_DOMAIN_DC_OFF, 518 POWER_DOMAIN_INIT); 519 520 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A); 521 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B); 522 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C); 523 524 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a, 525 POWER_DOMAIN_PORT_DDI_LANES_A, 526 POWER_DOMAIN_AUX_IO_A, 527 POWER_DOMAIN_AUX_A, 528 POWER_DOMAIN_INIT); 529 530 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b, 531 POWER_DOMAIN_PORT_DDI_LANES_B, 532 POWER_DOMAIN_AUX_IO_B, 533 POWER_DOMAIN_AUX_B, 534 POWER_DOMAIN_INIT); 535 536 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c, 537 POWER_DOMAIN_PORT_DDI_LANES_C, 538 POWER_DOMAIN_AUX_IO_C, 539 POWER_DOMAIN_AUX_C, 540 POWER_DOMAIN_INIT); 541 542 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a, 543 POWER_DOMAIN_AUX_IO_A, 544 POWER_DOMAIN_AUX_A, 545 POWER_DOMAIN_INIT); 546 547 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b, 548 POWER_DOMAIN_AUX_IO_B, 549 POWER_DOMAIN_AUX_B, 550 POWER_DOMAIN_INIT); 551 552 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c, 553 POWER_DOMAIN_AUX_IO_C, 554 POWER_DOMAIN_AUX_C, 555 POWER_DOMAIN_INIT); 556 557 static const struct i915_power_well_desc glk_power_wells_main[] = { 558 { 559 .instances = &I915_PW_INSTANCES( 560 I915_PW("DC_off", &glk_pwdoms_dc_off, 561 .id = SKL_DISP_DC_OFF), 562 ), 563 .ops = &gen9_dc_off_power_well_ops, 564 }, { 565 .instances = &I915_PW_INSTANCES( 566 I915_PW("PW_2", &glk_pwdoms_pw_2, 567 .hsw.idx = SKL_PW_CTL_IDX_PW_2, 568 .id = SKL_DISP_PW_2), 569 ), 570 .ops = &hsw_power_well_ops, 571 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), 572 .has_fuses = true, 573 }, { 574 .instances = &I915_PW_INSTANCES( 575 I915_PW("dpio-common-a", &glk_pwdoms_dpio_cmn_a, 576 .bxt.phy = DPIO_PHY1, 577 .id = BXT_DISP_PW_DPIO_CMN_A), 578 I915_PW("dpio-common-b", &glk_pwdoms_dpio_cmn_b, 579 .bxt.phy = DPIO_PHY0, 580 .id = VLV_DISP_PW_DPIO_CMN_BC), 581 I915_PW("dpio-common-c", &glk_pwdoms_dpio_cmn_c, 582 .bxt.phy = DPIO_PHY2, 583 .id = GLK_DISP_PW_DPIO_CMN_C), 584 ), 585 .ops = &bxt_dpio_cmn_power_well_ops, 586 }, { 587 .instances = &I915_PW_INSTANCES( 588 I915_PW("AUX_A", &glk_pwdoms_aux_a, .hsw.idx = GLK_PW_CTL_IDX_AUX_A), 589 I915_PW("AUX_B", &glk_pwdoms_aux_b, .hsw.idx = GLK_PW_CTL_IDX_AUX_B), 590 I915_PW("AUX_C", &glk_pwdoms_aux_c, .hsw.idx = GLK_PW_CTL_IDX_AUX_C), 591 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = GLK_PW_CTL_IDX_DDI_A), 592 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B), 593 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C), 594 ), 595 .ops = &hsw_power_well_ops, 596 }, 597 }; 598 599 static const struct i915_power_well_desc_list glk_power_wells[] = { 600 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 601 I915_PW_DESCRIPTORS(skl_power_wells_pw_1), 602 I915_PW_DESCRIPTORS(glk_power_wells_main), 603 }; 604 605 /* 606 * ICL PW_0/PG_0 domains (HW/DMC control): 607 * - PCI 608 * - clocks except port PLL 609 * - central power except FBC 610 * - shared functions except pipe interrupts, pipe MBUS, DBUF registers 611 * ICL PW_1/PG_1 domains (HW/DMC control): 612 * - DBUF function 613 * - PIPE_A and its planes, except VGA 614 * - transcoder EDP + PSR 615 * - transcoder DSI 616 * - DDI_A 617 * - FBC 618 */ 619 #define ICL_PW_4_POWER_DOMAINS \ 620 POWER_DOMAIN_PIPE_C, \ 621 POWER_DOMAIN_PIPE_PANEL_FITTER_C 622 623 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4, 624 ICL_PW_4_POWER_DOMAINS, 625 POWER_DOMAIN_INIT); 626 /* VDSC/joining */ 627 628 #define ICL_PW_3_POWER_DOMAINS \ 629 ICL_PW_4_POWER_DOMAINS, \ 630 POWER_DOMAIN_PIPE_B, \ 631 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 632 POWER_DOMAIN_TRANSCODER_A, \ 633 POWER_DOMAIN_TRANSCODER_B, \ 634 POWER_DOMAIN_TRANSCODER_C, \ 635 POWER_DOMAIN_PORT_DDI_LANES_B, \ 636 POWER_DOMAIN_PORT_DDI_LANES_C, \ 637 POWER_DOMAIN_PORT_DDI_LANES_D, \ 638 POWER_DOMAIN_PORT_DDI_LANES_E, \ 639 POWER_DOMAIN_PORT_DDI_LANES_F, \ 640 POWER_DOMAIN_VGA, \ 641 POWER_DOMAIN_AUDIO_MMIO, \ 642 POWER_DOMAIN_AUDIO_PLAYBACK, \ 643 POWER_DOMAIN_AUX_IO_B, \ 644 POWER_DOMAIN_AUX_IO_C, \ 645 POWER_DOMAIN_AUX_IO_D, \ 646 POWER_DOMAIN_AUX_IO_E, \ 647 POWER_DOMAIN_AUX_IO_F, \ 648 POWER_DOMAIN_AUX_B, \ 649 POWER_DOMAIN_AUX_C, \ 650 POWER_DOMAIN_AUX_D, \ 651 POWER_DOMAIN_AUX_E, \ 652 POWER_DOMAIN_AUX_F, \ 653 POWER_DOMAIN_AUX_TBT1, \ 654 POWER_DOMAIN_AUX_TBT2, \ 655 POWER_DOMAIN_AUX_TBT3, \ 656 POWER_DOMAIN_AUX_TBT4 657 658 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3, 659 ICL_PW_3_POWER_DOMAINS, 660 POWER_DOMAIN_INIT); 661 /* 662 * - transcoder WD 663 * - KVMR (HW control) 664 */ 665 666 #define ICL_PW_2_POWER_DOMAINS \ 667 ICL_PW_3_POWER_DOMAINS, \ 668 POWER_DOMAIN_TRANSCODER_VDSC_PW2 669 670 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2, 671 ICL_PW_2_POWER_DOMAINS, 672 POWER_DOMAIN_INIT); 673 /* 674 * - KVMR (HW control) 675 */ 676 677 I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off, 678 ICL_PW_2_POWER_DOMAINS, 679 POWER_DOMAIN_AUX_A, 680 POWER_DOMAIN_DC_OFF, 681 POWER_DOMAIN_INIT); 682 683 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D); 684 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E); 685 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F); 686 687 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a, 688 POWER_DOMAIN_AUX_IO_A, 689 POWER_DOMAIN_AUX_A); 690 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b, 691 POWER_DOMAIN_AUX_IO_B, 692 POWER_DOMAIN_AUX_B); 693 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, 694 POWER_DOMAIN_AUX_IO_C, 695 POWER_DOMAIN_AUX_C); 696 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, 697 POWER_DOMAIN_AUX_IO_D, 698 POWER_DOMAIN_AUX_D); 699 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, 700 POWER_DOMAIN_AUX_IO_E, 701 POWER_DOMAIN_AUX_E); 702 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, 703 POWER_DOMAIN_AUX_IO_F, 704 POWER_DOMAIN_AUX_F); 705 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1); 706 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2); 707 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3); 708 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4); 709 710 static const struct i915_power_well_desc icl_power_wells_pw_1[] = { 711 { 712 /* Handled by the DMC firmware */ 713 .instances = &I915_PW_INSTANCES( 714 I915_PW("PW_1", I915_PW_DOMAINS_NONE, 715 .hsw.idx = ICL_PW_CTL_IDX_PW_1, 716 .id = SKL_DISP_PW_1), 717 ), 718 .ops = &hsw_power_well_ops, 719 .always_on = true, 720 .has_fuses = true, 721 }, 722 }; 723 724 static const struct i915_power_well_desc icl_power_wells_main[] = { 725 { 726 .instances = &I915_PW_INSTANCES( 727 I915_PW("DC_off", &icl_pwdoms_dc_off, 728 .id = SKL_DISP_DC_OFF), 729 ), 730 .ops = &gen9_dc_off_power_well_ops, 731 }, { 732 .instances = &I915_PW_INSTANCES( 733 I915_PW("PW_2", &icl_pwdoms_pw_2, 734 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 735 .id = SKL_DISP_PW_2), 736 ), 737 .ops = &hsw_power_well_ops, 738 .has_fuses = true, 739 }, { 740 .instances = &I915_PW_INSTANCES( 741 I915_PW("PW_3", &icl_pwdoms_pw_3, 742 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 743 .id = ICL_DISP_PW_3), 744 ), 745 .ops = &hsw_power_well_ops, 746 .irq_pipe_mask = BIT(PIPE_B), 747 .has_fuses = true, 748 }, { 749 .instances = &I915_PW_INSTANCES( 750 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 751 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 752 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), 753 I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = ICL_PW_CTL_IDX_DDI_D), 754 I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = ICL_PW_CTL_IDX_DDI_E), 755 I915_PW("DDI_IO_F", &icl_pwdoms_ddi_io_f, .hsw.idx = ICL_PW_CTL_IDX_DDI_F), 756 ), 757 .ops = &icl_ddi_power_well_ops, 758 }, { 759 .instances = &I915_PW_INSTANCES( 760 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 761 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 762 I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), 763 I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = ICL_PW_CTL_IDX_AUX_D), 764 I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = ICL_PW_CTL_IDX_AUX_E), 765 I915_PW("AUX_F", &icl_pwdoms_aux_f, .hsw.idx = ICL_PW_CTL_IDX_AUX_F), 766 ), 767 .ops = &icl_aux_power_well_ops, 768 }, { 769 .instances = &I915_PW_INSTANCES( 770 I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1), 771 I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2), 772 I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3), 773 I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4), 774 ), 775 .ops = &icl_aux_power_well_ops, 776 .is_tc_tbt = true, 777 }, { 778 .instances = &I915_PW_INSTANCES( 779 I915_PW("PW_4", &icl_pwdoms_pw_4, 780 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 781 ), 782 .ops = &hsw_power_well_ops, 783 .irq_pipe_mask = BIT(PIPE_C), 784 .has_fuses = true, 785 }, 786 }; 787 788 static const struct i915_power_well_desc_list icl_power_wells[] = { 789 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 790 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 791 I915_PW_DESCRIPTORS(icl_power_wells_main), 792 }; 793 794 #define TGL_PW_5_POWER_DOMAINS \ 795 POWER_DOMAIN_PIPE_D, \ 796 POWER_DOMAIN_PIPE_PANEL_FITTER_D, \ 797 POWER_DOMAIN_TRANSCODER_D 798 799 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5, 800 TGL_PW_5_POWER_DOMAINS, 801 POWER_DOMAIN_INIT); 802 803 #define TGL_PW_4_POWER_DOMAINS \ 804 TGL_PW_5_POWER_DOMAINS, \ 805 POWER_DOMAIN_PIPE_C, \ 806 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 807 POWER_DOMAIN_TRANSCODER_C 808 809 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4, 810 TGL_PW_4_POWER_DOMAINS, 811 POWER_DOMAIN_INIT); 812 813 #define TGL_PW_3_POWER_DOMAINS \ 814 TGL_PW_4_POWER_DOMAINS, \ 815 POWER_DOMAIN_PIPE_B, \ 816 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 817 POWER_DOMAIN_TRANSCODER_B, \ 818 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 819 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 820 POWER_DOMAIN_PORT_DDI_LANES_TC3, \ 821 POWER_DOMAIN_PORT_DDI_LANES_TC4, \ 822 POWER_DOMAIN_PORT_DDI_LANES_TC5, \ 823 POWER_DOMAIN_PORT_DDI_LANES_TC6, \ 824 POWER_DOMAIN_VGA, \ 825 POWER_DOMAIN_AUDIO_MMIO, \ 826 POWER_DOMAIN_AUDIO_PLAYBACK, \ 827 POWER_DOMAIN_AUX_USBC1, \ 828 POWER_DOMAIN_AUX_USBC2, \ 829 POWER_DOMAIN_AUX_USBC3, \ 830 POWER_DOMAIN_AUX_USBC4, \ 831 POWER_DOMAIN_AUX_USBC5, \ 832 POWER_DOMAIN_AUX_USBC6, \ 833 POWER_DOMAIN_AUX_TBT1, \ 834 POWER_DOMAIN_AUX_TBT2, \ 835 POWER_DOMAIN_AUX_TBT3, \ 836 POWER_DOMAIN_AUX_TBT4, \ 837 POWER_DOMAIN_AUX_TBT5, \ 838 POWER_DOMAIN_AUX_TBT6 839 840 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3, 841 TGL_PW_3_POWER_DOMAINS, 842 POWER_DOMAIN_INIT); 843 844 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2, 845 TGL_PW_3_POWER_DOMAINS, 846 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 847 POWER_DOMAIN_INIT); 848 849 I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off, 850 TGL_PW_3_POWER_DOMAINS, 851 POWER_DOMAIN_AUX_A, 852 POWER_DOMAIN_AUX_B, 853 POWER_DOMAIN_AUX_C, 854 POWER_DOMAIN_DC_OFF, 855 POWER_DOMAIN_INIT); 856 857 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1); 858 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2); 859 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3); 860 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4); 861 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5); 862 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6); 863 864 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1); 865 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2); 866 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3); 867 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4); 868 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5); 869 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6); 870 871 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5); 872 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6); 873 874 I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off, 875 POWER_DOMAIN_AUX_USBC1, 876 POWER_DOMAIN_AUX_USBC2, 877 POWER_DOMAIN_AUX_USBC3, 878 POWER_DOMAIN_AUX_USBC4, 879 POWER_DOMAIN_AUX_USBC5, 880 POWER_DOMAIN_AUX_USBC6, 881 POWER_DOMAIN_AUX_TBT1, 882 POWER_DOMAIN_AUX_TBT2, 883 POWER_DOMAIN_AUX_TBT3, 884 POWER_DOMAIN_AUX_TBT4, 885 POWER_DOMAIN_AUX_TBT5, 886 POWER_DOMAIN_AUX_TBT6, 887 POWER_DOMAIN_TC_COLD_OFF); 888 889 static const struct i915_power_well_desc tgl_power_wells_main[] = { 890 { 891 .instances = &I915_PW_INSTANCES( 892 I915_PW("DC_off", &tgl_pwdoms_dc_off, 893 .id = SKL_DISP_DC_OFF), 894 ), 895 .ops = &gen9_dc_off_power_well_ops, 896 }, { 897 .instances = &I915_PW_INSTANCES( 898 I915_PW("PW_2", &tgl_pwdoms_pw_2, 899 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 900 .id = SKL_DISP_PW_2), 901 ), 902 .ops = &hsw_power_well_ops, 903 .has_fuses = true, 904 }, { 905 .instances = &I915_PW_INSTANCES( 906 I915_PW("PW_3", &tgl_pwdoms_pw_3, 907 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 908 .id = ICL_DISP_PW_3), 909 ), 910 .ops = &hsw_power_well_ops, 911 .irq_pipe_mask = BIT(PIPE_B), 912 .has_fuses = true, 913 }, { 914 .instances = &I915_PW_INSTANCES( 915 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 916 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 917 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), 918 I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), 919 I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), 920 I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3), 921 I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4), 922 I915_PW("DDI_IO_TC5", &tgl_pwdoms_ddi_io_tc5, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5), 923 I915_PW("DDI_IO_TC6", &tgl_pwdoms_ddi_io_tc6, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6), 924 ), 925 .ops = &icl_ddi_power_well_ops, 926 }, { 927 .instances = &I915_PW_INSTANCES( 928 I915_PW("PW_4", &tgl_pwdoms_pw_4, 929 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 930 ), 931 .ops = &hsw_power_well_ops, 932 .has_fuses = true, 933 .irq_pipe_mask = BIT(PIPE_C), 934 }, { 935 .instances = &I915_PW_INSTANCES( 936 I915_PW("PW_5", &tgl_pwdoms_pw_5, 937 .hsw.idx = TGL_PW_CTL_IDX_PW_5), 938 ), 939 .ops = &hsw_power_well_ops, 940 .has_fuses = true, 941 .irq_pipe_mask = BIT(PIPE_D), 942 }, 943 }; 944 945 static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = { 946 { 947 .instances = &I915_PW_INSTANCES( 948 I915_PW("TC_cold_off", &tgl_pwdoms_tc_cold_off, 949 .id = TGL_DISP_PW_TC_COLD_OFF), 950 ), 951 .ops = &tgl_tc_cold_off_ops, 952 }, 953 }; 954 955 static const struct i915_power_well_desc tgl_power_wells_aux[] = { 956 { 957 .instances = &I915_PW_INSTANCES( 958 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 959 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 960 I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), 961 I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), 962 I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), 963 I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3), 964 I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4), 965 I915_PW("AUX_USBC5", &tgl_pwdoms_aux_usbc5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5), 966 I915_PW("AUX_USBC6", &tgl_pwdoms_aux_usbc6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6), 967 ), 968 .ops = &icl_aux_power_well_ops, 969 }, { 970 .instances = &I915_PW_INSTANCES( 971 I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1), 972 I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2), 973 I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3), 974 I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4), 975 I915_PW("AUX_TBT5", &tgl_pwdoms_aux_tbt5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5), 976 I915_PW("AUX_TBT6", &tgl_pwdoms_aux_tbt6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6), 977 ), 978 .ops = &icl_aux_power_well_ops, 979 .is_tc_tbt = true, 980 }, 981 }; 982 983 static const struct i915_power_well_desc_list tgl_power_wells[] = { 984 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 985 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 986 I915_PW_DESCRIPTORS(tgl_power_wells_main), 987 I915_PW_DESCRIPTORS(tgl_power_wells_tc_cold_off), 988 I915_PW_DESCRIPTORS(tgl_power_wells_aux), 989 }; 990 991 static const struct i915_power_well_desc_list adls_power_wells[] = { 992 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 993 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 994 I915_PW_DESCRIPTORS(tgl_power_wells_main), 995 I915_PW_DESCRIPTORS(tgl_power_wells_aux), 996 }; 997 998 #define RKL_PW_4_POWER_DOMAINS \ 999 POWER_DOMAIN_PIPE_C, \ 1000 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 1001 POWER_DOMAIN_TRANSCODER_C 1002 1003 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4, 1004 RKL_PW_4_POWER_DOMAINS, 1005 POWER_DOMAIN_INIT); 1006 1007 #define RKL_PW_3_POWER_DOMAINS \ 1008 RKL_PW_4_POWER_DOMAINS, \ 1009 POWER_DOMAIN_PIPE_B, \ 1010 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 1011 POWER_DOMAIN_TRANSCODER_B, \ 1012 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1013 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1014 POWER_DOMAIN_VGA, \ 1015 POWER_DOMAIN_AUDIO_MMIO, \ 1016 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1017 POWER_DOMAIN_AUX_USBC1, \ 1018 POWER_DOMAIN_AUX_USBC2 1019 1020 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3, 1021 RKL_PW_3_POWER_DOMAINS, 1022 POWER_DOMAIN_INIT); 1023 1024 /* 1025 * There is no PW_2/PG_2 on RKL. 1026 * 1027 * RKL PW_1/PG_1 domains (under HW/DMC control): 1028 * - DBUF function (note: registers are in PW0) 1029 * - PIPE_A and its planes and VDSC/joining, except VGA 1030 * - transcoder A 1031 * - DDI_A and DDI_B 1032 * - FBC 1033 * 1034 * RKL PW_0/PG_0 domains (under HW/DMC control): 1035 * - PCI 1036 * - clocks except port PLL 1037 * - shared functions: 1038 * * interrupts except pipe interrupts 1039 * * MBus except PIPE_MBUS_DBOX_CTL 1040 * * DBUF registers 1041 * - central power except FBC 1042 * - top-level GTC (DDI-level GTC is in the well associated with the DDI) 1043 */ 1044 1045 I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off, 1046 RKL_PW_3_POWER_DOMAINS, 1047 POWER_DOMAIN_AUX_A, 1048 POWER_DOMAIN_AUX_B, 1049 POWER_DOMAIN_DC_OFF, 1050 POWER_DOMAIN_INIT); 1051 1052 static const struct i915_power_well_desc rkl_power_wells_main[] = { 1053 { 1054 .instances = &I915_PW_INSTANCES( 1055 I915_PW("DC_off", &rkl_pwdoms_dc_off, 1056 .id = SKL_DISP_DC_OFF), 1057 ), 1058 .ops = &gen9_dc_off_power_well_ops, 1059 }, { 1060 .instances = &I915_PW_INSTANCES( 1061 I915_PW("PW_3", &rkl_pwdoms_pw_3, 1062 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 1063 .id = ICL_DISP_PW_3), 1064 ), 1065 .ops = &hsw_power_well_ops, 1066 .irq_pipe_mask = BIT(PIPE_B), 1067 .has_fuses = true, 1068 }, { 1069 .instances = &I915_PW_INSTANCES( 1070 I915_PW("PW_4", &rkl_pwdoms_pw_4, 1071 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 1072 ), 1073 .ops = &hsw_power_well_ops, 1074 .has_fuses = true, 1075 .irq_pipe_mask = BIT(PIPE_C), 1076 }, 1077 }; 1078 1079 static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = { 1080 { 1081 .instances = &I915_PW_INSTANCES( 1082 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 1083 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 1084 I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), 1085 I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), 1086 ), 1087 .ops = &icl_ddi_power_well_ops, 1088 }, { 1089 .instances = &I915_PW_INSTANCES( 1090 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 1091 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 1092 I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), 1093 I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), 1094 ), 1095 .ops = &icl_aux_power_well_ops, 1096 }, 1097 }; 1098 1099 static const struct i915_power_well_desc_list rkl_power_wells[] = { 1100 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1101 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1102 I915_PW_DESCRIPTORS(rkl_power_wells_main), 1103 I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux), 1104 }; 1105 1106 /* 1107 * DG1 onwards Audio MMIO/VERBS lies in PG0 power well. 1108 */ 1109 #define DG1_PW_3_POWER_DOMAINS \ 1110 TGL_PW_4_POWER_DOMAINS, \ 1111 POWER_DOMAIN_PIPE_B, \ 1112 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 1113 POWER_DOMAIN_TRANSCODER_B, \ 1114 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1115 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1116 POWER_DOMAIN_VGA, \ 1117 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1118 POWER_DOMAIN_AUX_USBC1, \ 1119 POWER_DOMAIN_AUX_USBC2 1120 1121 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3, 1122 DG1_PW_3_POWER_DOMAINS, 1123 POWER_DOMAIN_INIT); 1124 1125 I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off, 1126 DG1_PW_3_POWER_DOMAINS, 1127 POWER_DOMAIN_AUDIO_MMIO, 1128 POWER_DOMAIN_AUX_A, 1129 POWER_DOMAIN_AUX_B, 1130 POWER_DOMAIN_DC_OFF, 1131 POWER_DOMAIN_INIT); 1132 1133 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2, 1134 DG1_PW_3_POWER_DOMAINS, 1135 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 1136 POWER_DOMAIN_INIT); 1137 1138 static const struct i915_power_well_desc dg1_power_wells_main[] = { 1139 { 1140 .instances = &I915_PW_INSTANCES( 1141 I915_PW("DC_off", &dg1_pwdoms_dc_off, 1142 .id = SKL_DISP_DC_OFF), 1143 ), 1144 .ops = &gen9_dc_off_power_well_ops, 1145 }, { 1146 .instances = &I915_PW_INSTANCES( 1147 I915_PW("PW_2", &dg1_pwdoms_pw_2, 1148 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 1149 .id = SKL_DISP_PW_2), 1150 ), 1151 .ops = &hsw_power_well_ops, 1152 .has_fuses = true, 1153 }, { 1154 .instances = &I915_PW_INSTANCES( 1155 I915_PW("PW_3", &dg1_pwdoms_pw_3, 1156 .hsw.idx = ICL_PW_CTL_IDX_PW_3, 1157 .id = ICL_DISP_PW_3), 1158 ), 1159 .ops = &hsw_power_well_ops, 1160 .irq_pipe_mask = BIT(PIPE_B), 1161 .has_fuses = true, 1162 }, { 1163 .instances = &I915_PW_INSTANCES( 1164 I915_PW("PW_4", &tgl_pwdoms_pw_4, 1165 .hsw.idx = ICL_PW_CTL_IDX_PW_4), 1166 ), 1167 .ops = &hsw_power_well_ops, 1168 .has_fuses = true, 1169 .irq_pipe_mask = BIT(PIPE_C), 1170 }, { 1171 .instances = &I915_PW_INSTANCES( 1172 I915_PW("PW_5", &tgl_pwdoms_pw_5, 1173 .hsw.idx = TGL_PW_CTL_IDX_PW_5), 1174 ), 1175 .ops = &hsw_power_well_ops, 1176 .has_fuses = true, 1177 .irq_pipe_mask = BIT(PIPE_D), 1178 }, 1179 }; 1180 1181 static const struct i915_power_well_desc_list dg1_power_wells[] = { 1182 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1183 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1184 I915_PW_DESCRIPTORS(dg1_power_wells_main), 1185 I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux), 1186 }; 1187 1188 /* 1189 * XE_LPD Power Domains 1190 * 1191 * Previous platforms required that PG(n-1) be enabled before PG(n). That 1192 * dependency chain turns into a dependency tree on XE_LPD: 1193 * 1194 * PG0 1195 * | 1196 * --PG1-- 1197 * / \ 1198 * PGA --PG2-- 1199 * / | \ 1200 * PGB PGC PGD 1201 * 1202 * Power wells must be enabled from top to bottom and disabled from bottom 1203 * to top. This allows pipes to be power gated independently. 1204 */ 1205 1206 #define XELPD_PW_D_POWER_DOMAINS \ 1207 POWER_DOMAIN_PIPE_D, \ 1208 POWER_DOMAIN_PIPE_PANEL_FITTER_D, \ 1209 POWER_DOMAIN_TRANSCODER_D 1210 1211 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d, 1212 XELPD_PW_D_POWER_DOMAINS, 1213 POWER_DOMAIN_INIT); 1214 1215 #define XELPD_PW_C_POWER_DOMAINS \ 1216 POWER_DOMAIN_PIPE_C, \ 1217 POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ 1218 POWER_DOMAIN_TRANSCODER_C 1219 1220 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c, 1221 XELPD_PW_C_POWER_DOMAINS, 1222 POWER_DOMAIN_INIT); 1223 1224 #define XELPD_PW_B_POWER_DOMAINS \ 1225 POWER_DOMAIN_PIPE_B, \ 1226 POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ 1227 POWER_DOMAIN_TRANSCODER_B 1228 1229 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b, 1230 XELPD_PW_B_POWER_DOMAINS, 1231 POWER_DOMAIN_INIT); 1232 1233 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a, 1234 POWER_DOMAIN_PIPE_A, 1235 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 1236 POWER_DOMAIN_INIT); 1237 1238 #define XELPD_DC_OFF_PORT_POWER_DOMAINS \ 1239 POWER_DOMAIN_PORT_DDI_LANES_C, \ 1240 POWER_DOMAIN_PORT_DDI_LANES_D, \ 1241 POWER_DOMAIN_PORT_DDI_LANES_E, \ 1242 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1243 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1244 POWER_DOMAIN_PORT_DDI_LANES_TC3, \ 1245 POWER_DOMAIN_PORT_DDI_LANES_TC4, \ 1246 POWER_DOMAIN_VGA, \ 1247 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1248 POWER_DOMAIN_AUX_IO_C, \ 1249 POWER_DOMAIN_AUX_IO_D, \ 1250 POWER_DOMAIN_AUX_IO_E, \ 1251 POWER_DOMAIN_AUX_C, \ 1252 POWER_DOMAIN_AUX_D, \ 1253 POWER_DOMAIN_AUX_E, \ 1254 POWER_DOMAIN_AUX_USBC1, \ 1255 POWER_DOMAIN_AUX_USBC2, \ 1256 POWER_DOMAIN_AUX_USBC3, \ 1257 POWER_DOMAIN_AUX_USBC4, \ 1258 POWER_DOMAIN_AUX_TBT1, \ 1259 POWER_DOMAIN_AUX_TBT2, \ 1260 POWER_DOMAIN_AUX_TBT3, \ 1261 POWER_DOMAIN_AUX_TBT4 1262 1263 #define XELPD_PW_2_POWER_DOMAINS \ 1264 XELPD_PW_B_POWER_DOMAINS, \ 1265 XELPD_PW_C_POWER_DOMAINS, \ 1266 XELPD_PW_D_POWER_DOMAINS, \ 1267 XELPD_DC_OFF_PORT_POWER_DOMAINS 1268 1269 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2, 1270 XELPD_PW_2_POWER_DOMAINS, 1271 POWER_DOMAIN_INIT); 1272 1273 /* 1274 * XELPD PW_1/PG_1 domains (under HW/DMC control): 1275 * - DBUF function (registers are in PW0) 1276 * - Transcoder A 1277 * - DDI_A and DDI_B 1278 * 1279 * XELPD PW_0/PW_1 domains (under HW/DMC control): 1280 * - PCI 1281 * - Clocks except port PLL 1282 * - Shared functions: 1283 * * interrupts except pipe interrupts 1284 * * MBus except PIPE_MBUS_DBOX_CTL 1285 * * DBUF registers 1286 * - Central power except FBC 1287 * - Top-level GTC (DDI-level GTC is in the well associated with the DDI) 1288 */ 1289 1290 I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off, 1291 XELPD_DC_OFF_PORT_POWER_DOMAINS, 1292 XELPD_PW_C_POWER_DOMAINS, 1293 XELPD_PW_D_POWER_DOMAINS, 1294 POWER_DOMAIN_PORT_DSI, 1295 POWER_DOMAIN_AUDIO_MMIO, 1296 POWER_DOMAIN_AUX_A, 1297 POWER_DOMAIN_AUX_B, 1298 POWER_DOMAIN_DC_OFF, 1299 POWER_DOMAIN_INIT); 1300 1301 static const struct i915_power_well_desc xelpd_power_wells_dc_off[] = { 1302 { 1303 .instances = &I915_PW_INSTANCES( 1304 I915_PW("DC_off", &xelpd_pwdoms_dc_off, 1305 .id = SKL_DISP_DC_OFF), 1306 ), 1307 .ops = &gen9_dc_off_power_well_ops, 1308 } 1309 }; 1310 1311 static const struct i915_power_well_desc xelpd_power_wells_main[] = { 1312 { 1313 .instances = &I915_PW_INSTANCES( 1314 I915_PW("PW_2", &xelpd_pwdoms_pw_2, 1315 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 1316 .id = SKL_DISP_PW_2), 1317 ), 1318 .ops = &hsw_power_well_ops, 1319 .has_fuses = true, 1320 }, { 1321 .instances = &I915_PW_INSTANCES( 1322 I915_PW("PW_A", &xelpd_pwdoms_pw_a, 1323 .hsw.idx = XELPD_PW_CTL_IDX_PW_A), 1324 ), 1325 .ops = &hsw_power_well_ops, 1326 .irq_pipe_mask = BIT(PIPE_A), 1327 .has_fuses = true, 1328 }, { 1329 .instances = &I915_PW_INSTANCES( 1330 I915_PW("PW_B", &xelpd_pwdoms_pw_b, 1331 .hsw.idx = XELPD_PW_CTL_IDX_PW_B), 1332 ), 1333 .ops = &hsw_power_well_ops, 1334 .irq_pipe_mask = BIT(PIPE_B), 1335 .has_fuses = true, 1336 }, { 1337 .instances = &I915_PW_INSTANCES( 1338 I915_PW("PW_C", &xelpd_pwdoms_pw_c, 1339 .hsw.idx = XELPD_PW_CTL_IDX_PW_C), 1340 ), 1341 .ops = &hsw_power_well_ops, 1342 .irq_pipe_mask = BIT(PIPE_C), 1343 .has_fuses = true, 1344 }, { 1345 .instances = &I915_PW_INSTANCES( 1346 I915_PW("PW_D", &xelpd_pwdoms_pw_d, 1347 .hsw.idx = XELPD_PW_CTL_IDX_PW_D), 1348 ), 1349 .ops = &hsw_power_well_ops, 1350 .irq_pipe_mask = BIT(PIPE_D), 1351 .has_fuses = true, 1352 }, { 1353 .instances = &I915_PW_INSTANCES( 1354 I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), 1355 I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), 1356 I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), 1357 I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D), 1358 I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E), 1359 I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), 1360 I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), 1361 I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3), 1362 I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4), 1363 ), 1364 .ops = &icl_ddi_power_well_ops, 1365 }, { 1366 .instances = &I915_PW_INSTANCES( 1367 I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), 1368 I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), 1369 I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), 1370 I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D), 1371 I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E), 1372 ), 1373 .ops = &icl_aux_power_well_ops, 1374 .fixed_enable_delay = true, 1375 }, { 1376 .instances = &I915_PW_INSTANCES( 1377 I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), 1378 I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), 1379 I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3), 1380 I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4), 1381 ), 1382 .ops = &icl_aux_power_well_ops, 1383 .fixed_enable_delay = true, 1384 /* WA_14017248603: adlp */ 1385 .enable_timeout = 500, 1386 }, { 1387 .instances = &I915_PW_INSTANCES( 1388 I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1), 1389 I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2), 1390 I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3), 1391 I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4), 1392 ), 1393 .ops = &icl_aux_power_well_ops, 1394 .is_tc_tbt = true, 1395 }, 1396 }; 1397 1398 static const struct i915_power_well_desc_list xelpd_power_wells[] = { 1399 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1400 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1401 I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off), 1402 I915_PW_DESCRIPTORS(xelpd_power_wells_main), 1403 }; 1404 1405 I915_DECL_PW_DOMAINS(xehpd_pwdoms_dc_off, 1406 XELPD_PW_2_POWER_DOMAINS, 1407 POWER_DOMAIN_PORT_DSI, 1408 POWER_DOMAIN_AUDIO_MMIO, 1409 POWER_DOMAIN_AUX_A, 1410 POWER_DOMAIN_AUX_B, 1411 POWER_DOMAIN_DC_OFF, 1412 POWER_DOMAIN_INIT); 1413 1414 static const struct i915_power_well_desc xehpd_power_wells_dc_off[] = { 1415 { 1416 .instances = &I915_PW_INSTANCES( 1417 I915_PW("DC_off", &xehpd_pwdoms_dc_off, 1418 .id = SKL_DISP_DC_OFF), 1419 ), 1420 .ops = &gen9_dc_off_power_well_ops, 1421 } 1422 }; 1423 1424 static const struct i915_power_well_desc_list xehpd_power_wells[] = { 1425 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1426 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1427 I915_PW_DESCRIPTORS(xehpd_power_wells_dc_off), 1428 I915_PW_DESCRIPTORS(xelpd_power_wells_main), 1429 }; 1430 1431 /* 1432 * MTL is based on XELPD power domains with the exception of power gating for: 1433 * - DDI_IO (moved to PLL logic) 1434 * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA always-on) 1435 */ 1436 #define XELPDP_PW_2_POWER_DOMAINS \ 1437 XELPD_PW_B_POWER_DOMAINS, \ 1438 XELPD_PW_C_POWER_DOMAINS, \ 1439 XELPD_PW_D_POWER_DOMAINS, \ 1440 POWER_DOMAIN_AUDIO_PLAYBACK, \ 1441 POWER_DOMAIN_VGA, \ 1442 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1443 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1444 POWER_DOMAIN_PORT_DDI_LANES_TC3, \ 1445 POWER_DOMAIN_PORT_DDI_LANES_TC4 1446 1447 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2, 1448 XELPDP_PW_2_POWER_DOMAINS, 1449 POWER_DOMAIN_INIT); 1450 1451 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1, 1452 POWER_DOMAIN_AUX_USBC1, 1453 POWER_DOMAIN_AUX_TBT1); 1454 1455 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2, 1456 POWER_DOMAIN_AUX_USBC2, 1457 POWER_DOMAIN_AUX_TBT2); 1458 1459 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3, 1460 POWER_DOMAIN_AUX_USBC3, 1461 POWER_DOMAIN_AUX_TBT3); 1462 1463 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4, 1464 POWER_DOMAIN_AUX_USBC4, 1465 POWER_DOMAIN_AUX_TBT4); 1466 1467 static const struct i915_power_well_desc xelpdp_power_wells_main[] = { 1468 { 1469 .instances = &I915_PW_INSTANCES( 1470 I915_PW("PW_2", &xelpdp_pwdoms_pw_2, 1471 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 1472 .id = SKL_DISP_PW_2), 1473 ), 1474 .ops = &hsw_power_well_ops, 1475 .has_fuses = true, 1476 }, { 1477 .instances = &I915_PW_INSTANCES( 1478 I915_PW("PW_A", &xelpd_pwdoms_pw_a, 1479 .hsw.idx = XELPD_PW_CTL_IDX_PW_A), 1480 ), 1481 .ops = &hsw_power_well_ops, 1482 .irq_pipe_mask = BIT(PIPE_A), 1483 .has_fuses = true, 1484 }, { 1485 .instances = &I915_PW_INSTANCES( 1486 I915_PW("PW_B", &xelpd_pwdoms_pw_b, 1487 .hsw.idx = XELPD_PW_CTL_IDX_PW_B), 1488 ), 1489 .ops = &hsw_power_well_ops, 1490 .irq_pipe_mask = BIT(PIPE_B), 1491 .has_fuses = true, 1492 }, { 1493 .instances = &I915_PW_INSTANCES( 1494 I915_PW("PW_C", &xelpd_pwdoms_pw_c, 1495 .hsw.idx = XELPD_PW_CTL_IDX_PW_C), 1496 ), 1497 .ops = &hsw_power_well_ops, 1498 .irq_pipe_mask = BIT(PIPE_C), 1499 .has_fuses = true, 1500 }, { 1501 .instances = &I915_PW_INSTANCES( 1502 I915_PW("PW_D", &xelpd_pwdoms_pw_d, 1503 .hsw.idx = XELPD_PW_CTL_IDX_PW_D), 1504 ), 1505 .ops = &hsw_power_well_ops, 1506 .irq_pipe_mask = BIT(PIPE_D), 1507 .has_fuses = true, 1508 }, 1509 }; 1510 1511 static const struct i915_power_well_desc xelpdp_power_wells_aux[] = { 1512 { 1513 .instances = &I915_PW_INSTANCES( 1514 I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A), 1515 I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B), 1516 I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1), 1517 I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2), 1518 I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3), 1519 I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4), 1520 ), 1521 .ops = &xelpdp_aux_power_well_ops, 1522 }, 1523 }; 1524 1525 static const struct i915_power_well_desc_list xelpdp_power_wells[] = { 1526 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1527 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1528 I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off), 1529 I915_PW_DESCRIPTORS(xelpdp_power_wells_main), 1530 I915_PW_DESCRIPTORS(xelpdp_power_wells_aux), 1531 }; 1532 1533 I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc, 1534 POWER_DOMAIN_PORT_DDI_LANES_TC1, 1535 POWER_DOMAIN_PORT_DDI_LANES_TC2, 1536 POWER_DOMAIN_PORT_DDI_LANES_TC3, 1537 POWER_DOMAIN_PORT_DDI_LANES_TC4, 1538 POWER_DOMAIN_AUX_USBC1, 1539 POWER_DOMAIN_AUX_USBC2, 1540 POWER_DOMAIN_AUX_USBC3, 1541 POWER_DOMAIN_AUX_USBC4, 1542 POWER_DOMAIN_AUX_TBT1, 1543 POWER_DOMAIN_AUX_TBT2, 1544 POWER_DOMAIN_AUX_TBT3, 1545 POWER_DOMAIN_AUX_TBT4, 1546 POWER_DOMAIN_INIT); 1547 1548 static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = { 1549 { 1550 .instances = &I915_PW_INSTANCES(I915_PW("PICA_TC", 1551 &xe2lpd_pwdoms_pica_tc, 1552 .id = DISP_PW_ID_NONE), 1553 ), 1554 .ops = &xe2lpd_pica_power_well_ops, 1555 }, 1556 }; 1557 1558 I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off, 1559 POWER_DOMAIN_DC_OFF, 1560 XELPD_PW_C_POWER_DOMAINS, 1561 XELPD_PW_D_POWER_DOMAINS, 1562 POWER_DOMAIN_AUDIO_MMIO, 1563 POWER_DOMAIN_INIT); 1564 1565 static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = { 1566 { 1567 .instances = &I915_PW_INSTANCES( 1568 I915_PW("DC_off", &xe2lpd_pwdoms_dc_off, 1569 .id = SKL_DISP_DC_OFF), 1570 ), 1571 .ops = &gen9_dc_off_power_well_ops, 1572 }, 1573 }; 1574 1575 static const struct i915_power_well_desc_list xe2lpd_power_wells[] = { 1576 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1577 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1578 I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff), 1579 I915_PW_DESCRIPTORS(xelpdp_power_wells_main), 1580 I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), 1581 I915_PW_DESCRIPTORS(xelpdp_power_wells_aux), 1582 }; 1583 1584 /* 1585 * Xe3 changes the power well hierarchy slightly from Xe_LPD+; PGB now 1586 * depends on PG1 instead of PG2: 1587 * 1588 * PG0 1589 * | 1590 * --PG1-- 1591 * / | \ 1592 * PGA PGB PG2 1593 * / \ 1594 * PGC PGD 1595 */ 1596 1597 #define XE3LPD_PW_C_POWER_DOMAINS \ 1598 POWER_DOMAIN_PIPE_C, \ 1599 POWER_DOMAIN_PIPE_PANEL_FITTER_C 1600 1601 #define XE3LPD_PW_D_POWER_DOMAINS \ 1602 POWER_DOMAIN_PIPE_D, \ 1603 POWER_DOMAIN_PIPE_PANEL_FITTER_D 1604 1605 #define XE3LPD_PW_2_POWER_DOMAINS \ 1606 XE3LPD_PW_C_POWER_DOMAINS, \ 1607 XE3LPD_PW_D_POWER_DOMAINS, \ 1608 POWER_DOMAIN_TRANSCODER_C, \ 1609 POWER_DOMAIN_TRANSCODER_D, \ 1610 POWER_DOMAIN_VGA, \ 1611 POWER_DOMAIN_PORT_DDI_LANES_TC1, \ 1612 POWER_DOMAIN_PORT_DDI_LANES_TC2, \ 1613 POWER_DOMAIN_PORT_DDI_LANES_TC3, \ 1614 POWER_DOMAIN_PORT_DDI_LANES_TC4 1615 1616 I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_2, 1617 XE3LPD_PW_2_POWER_DOMAINS, 1618 POWER_DOMAIN_INIT); 1619 1620 I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_b, 1621 POWER_DOMAIN_PIPE_B, 1622 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 1623 POWER_DOMAIN_INIT); 1624 1625 I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_c, 1626 XE3LPD_PW_C_POWER_DOMAINS, 1627 POWER_DOMAIN_INIT); 1628 1629 I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_d, 1630 XE3LPD_PW_D_POWER_DOMAINS, 1631 POWER_DOMAIN_INIT); 1632 1633 static const struct i915_power_well_desc xe3lpd_power_wells_main[] = { 1634 { 1635 .instances = &I915_PW_INSTANCES( 1636 I915_PW("PW_2", &xe3lpd_pwdoms_pw_2, 1637 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 1638 .id = SKL_DISP_PW_2), 1639 ), 1640 .ops = &hsw_power_well_ops, 1641 .has_fuses = true, 1642 }, { 1643 .instances = &I915_PW_INSTANCES( 1644 I915_PW("PW_A", &xelpd_pwdoms_pw_a, 1645 .hsw.idx = XELPD_PW_CTL_IDX_PW_A), 1646 ), 1647 .ops = &hsw_power_well_ops, 1648 .irq_pipe_mask = BIT(PIPE_A), 1649 .has_fuses = true, 1650 }, { 1651 .instances = &I915_PW_INSTANCES( 1652 I915_PW("PW_B", &xe3lpd_pwdoms_pw_b, 1653 .hsw.idx = XELPD_PW_CTL_IDX_PW_B), 1654 ), 1655 .ops = &hsw_power_well_ops, 1656 .irq_pipe_mask = BIT(PIPE_B), 1657 .has_fuses = true, 1658 }, { 1659 .instances = &I915_PW_INSTANCES( 1660 I915_PW("PW_C", &xe3lpd_pwdoms_pw_c, 1661 .hsw.idx = XELPD_PW_CTL_IDX_PW_C), 1662 ), 1663 .ops = &hsw_power_well_ops, 1664 .irq_pipe_mask = BIT(PIPE_C), 1665 .has_fuses = true, 1666 }, { 1667 .instances = &I915_PW_INSTANCES( 1668 I915_PW("PW_D", &xe3lpd_pwdoms_pw_d, 1669 .hsw.idx = XELPD_PW_CTL_IDX_PW_D), 1670 ), 1671 .ops = &hsw_power_well_ops, 1672 .irq_pipe_mask = BIT(PIPE_D), 1673 .has_fuses = true, 1674 }, 1675 }; 1676 1677 I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_dc_off, 1678 POWER_DOMAIN_DC_OFF, 1679 XE3LPD_PW_2_POWER_DOMAINS, 1680 XE3LPD_PW_C_POWER_DOMAINS, 1681 XE3LPD_PW_D_POWER_DOMAINS, 1682 POWER_DOMAIN_AUDIO_MMIO, 1683 POWER_DOMAIN_AUDIO_PLAYBACK, 1684 POWER_DOMAIN_INIT); 1685 1686 static const struct i915_power_well_desc xe3lpd_power_wells_dcoff[] = { 1687 { 1688 .instances = &I915_PW_INSTANCES( 1689 I915_PW("DC_off", &xe3lpd_pwdoms_dc_off, 1690 .id = SKL_DISP_DC_OFF), 1691 ), 1692 .ops = &gen9_dc_off_power_well_ops, 1693 }, 1694 }; 1695 1696 static const struct i915_power_well_desc_list xe3lpd_power_wells[] = { 1697 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1698 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1699 I915_PW_DESCRIPTORS(xe3lpd_power_wells_dcoff), 1700 I915_PW_DESCRIPTORS(xe3lpd_power_wells_main), 1701 I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), 1702 I915_PW_DESCRIPTORS(xelpdp_power_wells_aux), 1703 }; 1704 1705 static const struct i915_power_well_desc wcl_power_wells_main[] = { 1706 { 1707 .instances = &I915_PW_INSTANCES( 1708 I915_PW("PW_2", &xe3lpd_pwdoms_pw_2, 1709 .hsw.idx = ICL_PW_CTL_IDX_PW_2, 1710 .id = SKL_DISP_PW_2), 1711 ), 1712 .ops = &hsw_power_well_ops, 1713 .has_fuses = true, 1714 }, { 1715 .instances = &I915_PW_INSTANCES( 1716 I915_PW("PW_A", &xelpd_pwdoms_pw_a, 1717 .hsw.idx = XELPD_PW_CTL_IDX_PW_A), 1718 ), 1719 .ops = &hsw_power_well_ops, 1720 .irq_pipe_mask = BIT(PIPE_A), 1721 .has_fuses = true, 1722 }, { 1723 .instances = &I915_PW_INSTANCES( 1724 I915_PW("PW_B", &xe3lpd_pwdoms_pw_b, 1725 .hsw.idx = XELPD_PW_CTL_IDX_PW_B), 1726 ), 1727 .ops = &hsw_power_well_ops, 1728 .irq_pipe_mask = BIT(PIPE_B), 1729 .has_fuses = true, 1730 }, { 1731 .instances = &I915_PW_INSTANCES( 1732 I915_PW("PW_C", &xe3lpd_pwdoms_pw_c, 1733 .hsw.idx = XELPD_PW_CTL_IDX_PW_C), 1734 ), 1735 .ops = &hsw_power_well_ops, 1736 .irq_pipe_mask = BIT(PIPE_C), 1737 .has_fuses = true, 1738 }, 1739 }; 1740 1741 static const struct i915_power_well_desc wcl_power_wells_aux[] = { 1742 { 1743 .instances = &I915_PW_INSTANCES( 1744 I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A), 1745 I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B), 1746 I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1), 1747 I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2), 1748 ), 1749 .ops = &xelpdp_aux_power_well_ops, 1750 }, 1751 }; 1752 1753 static const struct i915_power_well_desc_list wcl_power_wells[] = { 1754 I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), 1755 I915_PW_DESCRIPTORS(icl_power_wells_pw_1), 1756 I915_PW_DESCRIPTORS(xe3lpd_power_wells_dcoff), 1757 I915_PW_DESCRIPTORS(wcl_power_wells_main), 1758 I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), 1759 I915_PW_DESCRIPTORS(wcl_power_wells_aux), 1760 }; 1761 1762 static void init_power_well_domains(const struct i915_power_well_instance *inst, 1763 struct i915_power_well *power_well) 1764 { 1765 int j; 1766 1767 if (!inst->domain_list) 1768 return; 1769 1770 if (inst->domain_list->count == 0) { 1771 bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM); 1772 1773 return; 1774 } 1775 1776 for (j = 0; j < inst->domain_list->count; j++) 1777 set_bit(inst->domain_list->list[j], power_well->domains.bits); 1778 } 1779 1780 #define for_each_power_well_instance_in_desc_list(_desc_list, _desc_count, _desc, _inst) \ 1781 for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \ 1782 for ((_inst) = (_desc)->instances->list; \ 1783 (_inst) - (_desc)->instances->list < (_desc)->instances->count; \ 1784 (_inst)++) 1785 1786 #define for_each_power_well_instance(_desc_list, _desc_count, _descs, _desc, _inst) \ 1787 for ((_descs) = (_desc_list); \ 1788 (_descs) - (_desc_list) < (_desc_count); \ 1789 (_descs)++) \ 1790 for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ 1791 (_desc), (_inst)) 1792 1793 static int 1794 __set_power_wells(struct i915_power_domains *power_domains, 1795 const struct i915_power_well_desc_list *power_well_descs, 1796 int power_well_descs_sz) 1797 { 1798 struct intel_display *display = container_of(power_domains, 1799 struct intel_display, 1800 power.domains); 1801 u64 power_well_ids = 0; 1802 const struct i915_power_well_desc_list *desc_list; 1803 const struct i915_power_well_desc *desc; 1804 const struct i915_power_well_instance *inst; 1805 int power_well_count = 0; 1806 int plt_idx = 0; 1807 1808 for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) 1809 power_well_count++; 1810 1811 power_domains->power_well_count = power_well_count; 1812 power_domains->power_wells = 1813 kzalloc_objs(*power_domains->power_wells, 1814 power_well_count); 1815 if (!power_domains->power_wells) 1816 return -ENOMEM; 1817 1818 for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { 1819 struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; 1820 enum i915_power_well_id id = inst->id; 1821 1822 pw->desc = desc; 1823 drm_WARN_ON(display->drm, 1824 overflows_type(inst - desc->instances->list, pw->instance_idx)); 1825 pw->instance_idx = inst - desc->instances->list; 1826 1827 init_power_well_domains(inst, pw); 1828 1829 plt_idx++; 1830 1831 if (id == DISP_PW_ID_NONE) 1832 continue; 1833 1834 drm_WARN_ON(display->drm, id >= sizeof(power_well_ids) * 8); 1835 drm_WARN_ON(display->drm, power_well_ids & BIT_ULL(id)); 1836 power_well_ids |= BIT_ULL(id); 1837 } 1838 1839 return 0; 1840 } 1841 1842 #define set_power_wells(power_domains, __power_well_descs) \ 1843 __set_power_wells(power_domains, __power_well_descs, \ 1844 ARRAY_SIZE(__power_well_descs)) 1845 1846 /** 1847 * intel_display_power_map_init - initialize power domain -> power well mappings 1848 * @power_domains: power domain state 1849 * 1850 * Creates all the power wells for the current platform, initializes the 1851 * dynamic state for them and initializes the mapping of each power well to 1852 * all the power domains the power well belongs to. 1853 */ 1854 int intel_display_power_map_init(struct i915_power_domains *power_domains) 1855 { 1856 struct intel_display *display = container_of(power_domains, 1857 struct intel_display, 1858 power.domains); 1859 /* 1860 * The enabling order will be from lower to higher indexed wells, 1861 * the disabling order is reversed. 1862 */ 1863 if (!HAS_DISPLAY(display)) { 1864 power_domains->power_well_count = 0; 1865 return 0; 1866 } 1867 1868 if (DISPLAY_VERx100(display) == 3002) 1869 return set_power_wells(power_domains, wcl_power_wells); 1870 else if (DISPLAY_VER(display) >= 30) 1871 return set_power_wells(power_domains, xe3lpd_power_wells); 1872 else if (DISPLAY_VER(display) >= 20) 1873 return set_power_wells(power_domains, xe2lpd_power_wells); 1874 else if (DISPLAY_VER(display) >= 14) 1875 return set_power_wells(power_domains, xelpdp_power_wells); 1876 else if (display->platform.dg2) 1877 return set_power_wells(power_domains, xehpd_power_wells); 1878 else if (DISPLAY_VER(display) >= 13) 1879 return set_power_wells(power_domains, xelpd_power_wells); 1880 else if (display->platform.dg1) 1881 return set_power_wells(power_domains, dg1_power_wells); 1882 else if (display->platform.alderlake_s) 1883 return set_power_wells(power_domains, adls_power_wells); 1884 else if (display->platform.rocketlake) 1885 return set_power_wells(power_domains, rkl_power_wells); 1886 else if (DISPLAY_VER(display) == 12) 1887 return set_power_wells(power_domains, tgl_power_wells); 1888 else if (DISPLAY_VER(display) == 11) 1889 return set_power_wells(power_domains, icl_power_wells); 1890 else if (display->platform.geminilake) 1891 return set_power_wells(power_domains, glk_power_wells); 1892 else if (display->platform.broxton) 1893 return set_power_wells(power_domains, bxt_power_wells); 1894 else if (DISPLAY_VER(display) == 9) 1895 return set_power_wells(power_domains, skl_power_wells); 1896 else if (display->platform.cherryview) 1897 return set_power_wells(power_domains, chv_power_wells); 1898 else if (display->platform.broadwell) 1899 return set_power_wells(power_domains, bdw_power_wells); 1900 else if (display->platform.haswell) 1901 return set_power_wells(power_domains, hsw_power_wells); 1902 else if (display->platform.valleyview) 1903 return set_power_wells(power_domains, vlv_power_wells); 1904 else if (display->platform.i830) 1905 return set_power_wells(power_domains, i830_power_wells); 1906 else 1907 return set_power_wells(power_domains, i9xx_power_wells); 1908 } 1909 1910 /** 1911 * intel_display_power_map_cleanup - clean up power domain -> power well mappings 1912 * @power_domains: power domain state 1913 * 1914 * Cleans up all the state that was initialized by intel_display_power_map_init(). 1915 */ 1916 void intel_display_power_map_cleanup(struct i915_power_domains *power_domains) 1917 { 1918 kfree(power_domains->power_wells); 1919 } 1920