1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_POWER_H__ 7 #define __INTEL_DISPLAY_POWER_H__ 8 9 #include <linux/mutex.h> 10 #include <linux/workqueue.h> 11 12 enum aux_ch; 13 enum port; 14 struct i915_power_well; 15 struct intel_display; 16 struct intel_encoder; 17 struct ref_tracker; 18 struct seq_file; 19 20 /* -ENOENT means we got the ref, but there's no tracking */ 21 #define INTEL_WAKEREF_DEF ERR_PTR(-ENOENT) 22 23 /* 24 * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances 25 * consecutive, so that the pipe,transcoder,port -> power domain macros 26 * work correctly. 27 */ 28 enum intel_display_power_domain { 29 POWER_DOMAIN_DISPLAY_CORE, 30 POWER_DOMAIN_PIPE_A, 31 POWER_DOMAIN_PIPE_B, 32 POWER_DOMAIN_PIPE_C, 33 POWER_DOMAIN_PIPE_D, 34 POWER_DOMAIN_PIPE_PANEL_FITTER_A, 35 POWER_DOMAIN_PIPE_PANEL_FITTER_B, 36 POWER_DOMAIN_PIPE_PANEL_FITTER_C, 37 POWER_DOMAIN_PIPE_PANEL_FITTER_D, 38 POWER_DOMAIN_TRANSCODER_A, 39 POWER_DOMAIN_TRANSCODER_B, 40 POWER_DOMAIN_TRANSCODER_C, 41 POWER_DOMAIN_TRANSCODER_D, 42 POWER_DOMAIN_TRANSCODER_EDP, 43 POWER_DOMAIN_TRANSCODER_DSI_A, 44 POWER_DOMAIN_TRANSCODER_DSI_C, 45 46 /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */ 47 POWER_DOMAIN_TRANSCODER_VDSC_PW2, 48 49 POWER_DOMAIN_PORT_DDI_LANES_A, 50 POWER_DOMAIN_PORT_DDI_LANES_B, 51 POWER_DOMAIN_PORT_DDI_LANES_C, 52 POWER_DOMAIN_PORT_DDI_LANES_D, 53 POWER_DOMAIN_PORT_DDI_LANES_E, 54 POWER_DOMAIN_PORT_DDI_LANES_F, 55 56 POWER_DOMAIN_PORT_DDI_LANES_TC1, 57 POWER_DOMAIN_PORT_DDI_LANES_TC2, 58 POWER_DOMAIN_PORT_DDI_LANES_TC3, 59 POWER_DOMAIN_PORT_DDI_LANES_TC4, 60 POWER_DOMAIN_PORT_DDI_LANES_TC5, 61 POWER_DOMAIN_PORT_DDI_LANES_TC6, 62 63 POWER_DOMAIN_PORT_DDI_IO_A, 64 POWER_DOMAIN_PORT_DDI_IO_B, 65 POWER_DOMAIN_PORT_DDI_IO_C, 66 POWER_DOMAIN_PORT_DDI_IO_D, 67 POWER_DOMAIN_PORT_DDI_IO_E, 68 POWER_DOMAIN_PORT_DDI_IO_F, 69 70 POWER_DOMAIN_PORT_DDI_IO_TC1, 71 POWER_DOMAIN_PORT_DDI_IO_TC2, 72 POWER_DOMAIN_PORT_DDI_IO_TC3, 73 POWER_DOMAIN_PORT_DDI_IO_TC4, 74 POWER_DOMAIN_PORT_DDI_IO_TC5, 75 POWER_DOMAIN_PORT_DDI_IO_TC6, 76 77 POWER_DOMAIN_PORT_DSI, 78 POWER_DOMAIN_PORT_CRT, 79 POWER_DOMAIN_PORT_OTHER, 80 POWER_DOMAIN_VGA, 81 POWER_DOMAIN_AUDIO_MMIO, 82 POWER_DOMAIN_AUDIO_PLAYBACK, 83 84 POWER_DOMAIN_AUX_IO_A, 85 POWER_DOMAIN_AUX_IO_B, 86 POWER_DOMAIN_AUX_IO_C, 87 POWER_DOMAIN_AUX_IO_D, 88 POWER_DOMAIN_AUX_IO_E, 89 POWER_DOMAIN_AUX_IO_F, 90 91 POWER_DOMAIN_AUX_A, 92 POWER_DOMAIN_AUX_B, 93 POWER_DOMAIN_AUX_C, 94 POWER_DOMAIN_AUX_D, 95 POWER_DOMAIN_AUX_E, 96 POWER_DOMAIN_AUX_F, 97 98 POWER_DOMAIN_AUX_USBC1, 99 POWER_DOMAIN_AUX_USBC2, 100 POWER_DOMAIN_AUX_USBC3, 101 POWER_DOMAIN_AUX_USBC4, 102 POWER_DOMAIN_AUX_USBC5, 103 POWER_DOMAIN_AUX_USBC6, 104 105 POWER_DOMAIN_AUX_TBT1, 106 POWER_DOMAIN_AUX_TBT2, 107 POWER_DOMAIN_AUX_TBT3, 108 POWER_DOMAIN_AUX_TBT4, 109 POWER_DOMAIN_AUX_TBT5, 110 POWER_DOMAIN_AUX_TBT6, 111 112 POWER_DOMAIN_GMBUS, 113 POWER_DOMAIN_GT_IRQ, 114 POWER_DOMAIN_DC_OFF, 115 POWER_DOMAIN_TC_COLD_OFF, 116 POWER_DOMAIN_INIT, 117 118 POWER_DOMAIN_NUM, 119 POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM, 120 }; 121 122 #define POWER_DOMAIN_PIPE(pipe) \ 123 ((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_A)) 124 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 125 ((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_PANEL_FITTER_A)) 126 #define POWER_DOMAIN_TRANSCODER(tran) \ 127 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 128 (enum intel_display_power_domain)((tran) - TRANSCODER_A + POWER_DOMAIN_TRANSCODER_A)) 129 130 struct intel_power_domain_mask { 131 DECLARE_BITMAP(bits, POWER_DOMAIN_NUM); 132 }; 133 134 struct i915_power_domains { 135 /* 136 * Power wells needed for initialization at driver init and suspend 137 * time are on. They are kept on until after the first modeset. 138 */ 139 bool initializing; 140 bool display_core_suspended; 141 int power_well_count; 142 143 u32 dc_state; 144 u32 target_dc_state; 145 u32 allowed_dc_mask; 146 147 struct ref_tracker *init_wakeref; 148 struct ref_tracker *disable_wakeref; 149 150 struct mutex lock; 151 int domain_use_count[POWER_DOMAIN_NUM]; 152 153 struct delayed_work async_put_work; 154 struct ref_tracker *async_put_wakeref; 155 struct intel_power_domain_mask async_put_domains[2]; 156 int async_put_next_delay; 157 158 struct i915_power_well *power_wells; 159 }; 160 161 struct intel_display_power_domain_set { 162 struct intel_power_domain_mask mask; 163 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM 164 struct ref_tracker *wakerefs[POWER_DOMAIN_NUM]; 165 #endif 166 }; 167 168 #define for_each_power_domain(__domain, __mask) \ 169 for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \ 170 for_each_if(test_bit((__domain), (__mask)->bits)) 171 172 int intel_display_power_init(struct intel_display *display); 173 void intel_display_power_cleanup(struct intel_display *display); 174 void intel_display_power_init_hw(struct intel_display *display); 175 void intel_display_power_driver_remove(struct intel_display *display); 176 void intel_display_power_enable(struct intel_display *display); 177 void intel_display_power_disable(struct intel_display *display); 178 void intel_display_power_sanitize_state(struct intel_display *display); 179 180 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle); 181 void intel_display_power_resume_early(struct intel_display *display); 182 void intel_display_power_set_target_dc_state(struct intel_display *display, 183 u32 state); 184 u32 intel_display_power_get_current_dc_state(struct intel_display *display); 185 186 void intel_display_power_runtime_suspend(struct intel_display *display); 187 void intel_display_power_runtime_resume(struct intel_display *display); 188 189 bool intel_display_power_is_enabled(struct intel_display *display, 190 enum intel_display_power_domain domain); 191 struct ref_tracker *intel_display_power_get(struct intel_display *display, 192 enum intel_display_power_domain domain); 193 struct ref_tracker * 194 intel_display_power_get_if_enabled(struct intel_display *display, 195 enum intel_display_power_domain domain); 196 void __intel_display_power_put_async(struct intel_display *display, 197 enum intel_display_power_domain domain, 198 struct ref_tracker *wakeref, 199 int delay_ms); 200 void intel_display_power_flush_work(struct intel_display *display); 201 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 202 void intel_display_power_put(struct intel_display *display, 203 enum intel_display_power_domain domain, 204 struct ref_tracker *wakeref); 205 static inline void 206 intel_display_power_put_async(struct intel_display *display, 207 enum intel_display_power_domain domain, 208 struct ref_tracker *wakeref) 209 { 210 __intel_display_power_put_async(display, domain, wakeref, -1); 211 } 212 213 static inline void 214 intel_display_power_put_async_delay(struct intel_display *display, 215 enum intel_display_power_domain domain, 216 struct ref_tracker *wakeref, 217 int delay_ms) 218 { 219 __intel_display_power_put_async(display, domain, wakeref, delay_ms); 220 } 221 #else 222 void intel_display_power_put_unchecked(struct intel_display *display, 223 enum intel_display_power_domain domain); 224 225 static inline void 226 intel_display_power_put(struct intel_display *display, 227 enum intel_display_power_domain domain, 228 struct ref_tracker *wakeref) 229 { 230 intel_display_power_put_unchecked(display, domain); 231 } 232 233 static inline void 234 intel_display_power_put_async(struct intel_display *display, 235 enum intel_display_power_domain domain, 236 struct ref_tracker *wakeref) 237 { 238 __intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, -1); 239 } 240 241 static inline void 242 intel_display_power_put_async_delay(struct intel_display *display, 243 enum intel_display_power_domain domain, 244 struct ref_tracker *wakeref, 245 int delay_ms) 246 { 247 __intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, delay_ms); 248 } 249 #endif 250 251 void 252 intel_display_power_get_in_set(struct intel_display *display, 253 struct intel_display_power_domain_set *power_domain_set, 254 enum intel_display_power_domain domain); 255 256 bool 257 intel_display_power_get_in_set_if_enabled(struct intel_display *display, 258 struct intel_display_power_domain_set *power_domain_set, 259 enum intel_display_power_domain domain); 260 261 void 262 intel_display_power_put_mask_in_set(struct intel_display *display, 263 struct intel_display_power_domain_set *power_domain_set, 264 struct intel_power_domain_mask *mask); 265 266 static inline void 267 intel_display_power_put_all_in_set(struct intel_display *display, 268 struct intel_display_power_domain_set *power_domain_set) 269 { 270 intel_display_power_put_mask_in_set(display, power_domain_set, &power_domain_set->mask); 271 } 272 273 void intel_display_power_debug(struct intel_display *display, struct seq_file *m); 274 275 enum intel_display_power_domain 276 intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port); 277 enum intel_display_power_domain 278 intel_display_power_ddi_io_domain(struct intel_display *display, enum port port); 279 enum intel_display_power_domain 280 intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch); 281 enum intel_display_power_domain 282 intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch); 283 enum intel_display_power_domain 284 intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch); 285 286 /* 287 * FIXME: We should probably switch this to a 0-based scheme to be consistent 288 * with how we now name/number DBUF_CTL instances. 289 */ 290 enum dbuf_slice { 291 DBUF_S1, 292 DBUF_S2, 293 DBUF_S3, 294 DBUF_S4, 295 I915_MAX_DBUF_SLICES 296 }; 297 298 void gen9_dbuf_slices_update(struct intel_display *display, 299 u8 req_slices); 300 301 #define __with_intel_display_power(display, domain, wf) \ 302 for (struct ref_tracker *(wf) = intel_display_power_get((display), (domain)); (wf); \ 303 intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL) 304 305 #define with_intel_display_power(display, domain) \ 306 __with_intel_display_power(display, domain, __UNIQUE_ID(wakeref)) 307 308 #define __with_intel_display_power_if_enabled(display, domain, wf) \ 309 for (struct ref_tracker *(wf) = intel_display_power_get_if_enabled((display), (domain)); (wf); \ 310 intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL) 311 312 #define with_intel_display_power_if_enabled(display, domain) \ 313 __with_intel_display_power_if_enabled(display, domain, __UNIQUE_ID(wakeref)) 314 315 #endif /* __INTEL_DISPLAY_POWER_H__ */ 316